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REJ09B0256-0100
32
SH7763
Hardware Manual
Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series R5S77630
Rev.1.00 Revision Date: Oct. 01, 2007
Rev. 1.00 Oct. 01, 2007 Page ii of lxvi
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. 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With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
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General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. 5. Reading from/Writing to Reserved Bit of Each Register Note: Treat the reserved bit of register used in each module as follows except in cases where the specifications for values which are read from or written to the bit are provided in the description. The bit is always read as 0. The write value should be 0 or one, which has been read immediately before writing. Writing the value, which has been read immediately before writing has the advantage of preventing the bit from being affected on its extended function when the function is assigned.
Rev. 1.00 Oct. 01, 2007 Page iv of lxvi
Configuration of This Manual
This manual comprises the following items: General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. Electrical Characteristics 8. Appendix 9. Index 1. 2. 3. 4. 5. 6.
Rev. 1.00 Oct. 01, 2007 Page v of lxvi
Preface
This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users.
Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. Rules: Bit order: Number notation: Signal notation: The MSB is on the left and the LSB is on the right. Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. An overbar is added to a low-active signal: xxxx
Rev. 1.00 Oct. 01, 2007 Page vi of lxvi
Abbreviations ALU ASID BGA CMT CPG CPU DDR DDRIF DMA DMAC FIFO FPU HAC H-UDI INTC JTAG LBSC LRAM LRU LSB MMCIF MMU Arithmetic Logic Unit Address Space Identifier Ball Grid Array Timer/Counter (Compare Match Timer) Clock Pulse Generator Central Processing Unit Double Data Rate DDR-SDRAM Interface Direct Memory Access Direct Memory Access Controller First-In First-Out Floating-point Unit Audio Codec User Debugging Interface Interrupt Controller Joint Test Action Group Local Bus State Controller L Memory Least Recently Used Least Significant Bit Multimedia Card Interface Memory Management Unit
Rev. 1.00 Oct. 01, 2007 Page vii of lxvi
MSB PC PCI PCIC PFC RISC RTC SCIF SIOF SSI TAP TLB TMU UART UBC WDT
Most Significant Bit Program Counter Peripheral Component Interconnect PCI (local bus) Controller Pin Function Controller Reduced Instruction Set Computer Realtime Clock Serial Communication Interface with FIFO Serial Interface with FIFO Serial Sound Interface Test Access Port Translation Lookaside Buffer Timer Unit Universal Asynchronous Receiver/Transmitter User Break Controller Watchdog Timer
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Rev. 1.00 Oct. 01, 2007 Page viii of lxvi
Contents
Section 1 Overview......................................................................................................................... 1 1.1 Features of the SH7763.......................................................................................................... 1 1.2 Block Diagram ..................................................................................................................... 13 1.3 Pin Arrangement .................................................................................................................. 14
Section 2 Programming Model ............................................................................37
2.1 2.2 Data Formats........................................................................................................................ 37 Register Descriptions ........................................................................................................... 38 2.2.1 Privileged Mode and Banks .................................................................................... 38 2.2.2 General Registers.................................................................................................... 42 2.2.3 Floating-Point Registers.......................................................................................... 43 2.2.4 Control Registers .................................................................................................... 45 2.2.5 System Registers..................................................................................................... 47 Memory-Mapped Registers.................................................................................................. 51 Data Formats in Registers .................................................................................................... 52 Data Formats in Memory ..................................................................................................... 52 Processing States.................................................................................................................. 53 Usage Note........................................................................................................................... 55 2.7.1 Notes on Self-Modified Codes................................................................................ 55
2.3 2.4 2.5 2.6 2.7
Section 3 Instruction Set ......................................................................................57
3.1 3.2 3.3 Execution Environment ....................................................................................................... 57 Addressing Modes ............................................................................................................... 59 Instruction Set ...................................................................................................................... 64
Section 4 Pipelining .............................................................................................79
4.1 4.2 4.3 Pipelines............................................................................................................................... 79 Parallel-Executability........................................................................................................... 90 Issue Rates and Execution Cycles........................................................................................ 94
Section 5 Exception Handling ...........................................................................105
5.1 5.2 Summary of Exception Handling....................................................................................... 105 Register Descriptions ......................................................................................................... 105 5.2.1 TRAPA Exception Register (TRA) ...................................................................... 106 5.2.2 Exception Event Register (EXPEVT)................................................................... 107 5.2.3 Interrupt Event Register (INTEVT)...................................................................... 108 Exception Handling Functions........................................................................................... 109
5.3
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5.4 5.5
5.6
5.7
5.3.1 Exception Handling Flow ..................................................................................... 109 5.3.2 Exception Handling Vector Addresses ................................................................. 109 Exception Types and Priorities .......................................................................................... 110 Exception Flow .................................................................................................................. 112 5.5.1 Exception Flow..................................................................................................... 112 5.5.2 Exception Source Acceptance............................................................................... 114 5.5.3 Exception Requests and BL Bit ............................................................................ 115 5.5.4 Return from Exception Handling.......................................................................... 115 Description of Exceptions.................................................................................................. 116 5.6.1 Resets.................................................................................................................... 116 5.6.2 General Exceptions............................................................................................... 118 5.6.3 Interrupts............................................................................................................... 132 5.6.4 Priority Order with Multiple Exceptions .............................................................. 133 Usage Notes ....................................................................................................................... 135
Section 6 Memory Management Unit (MMU).................................................. 137
6.1 6.2 Overview of MMU ............................................................................................................ 137 6.1.1 Address Spaces ..................................................................................................... 140 Register Descriptions......................................................................................................... 146 6.2.1 Page Table Entry High Register (PTEH).............................................................. 147 6.2.2 Page Table Entry Low Register (PTEL) ............................................................... 148 6.2.3 Translation Table Base Register (TTB) ................................................................ 149 6.2.4 TLB Exception Address Register (TEA) .............................................................. 149 6.2.5 MMU Control Register (MMUCR) ...................................................................... 149 6.2.6 Physical Address Space Control Register (PASCR)............................................. 152 6.2.7 Instruction Re-Fetch Inhibit Control Register (IRMCR) ...................................... 153 TLB Functions ................................................................................................................... 156 6.3.1 Unified TLB (UTLB) Configuration .................................................................... 156 6.3.2 Instruction TLB (ITLB) Configuration................................................................. 159 6.3.3 Address Translation Method................................................................................. 160 MMU Functions................................................................................................................. 162 6.4.1 MMU Hardware Management.............................................................................. 162 6.4.2 MMU Software Management ............................................................................... 162 6.4.3 MMU Instruction (LDTLB).................................................................................. 163 6.4.4 Hardware ITLB Miss Handling ............................................................................ 164 6.4.5 Avoiding Synonym Problems............................................................................... 165 MMU Exceptions............................................................................................................... 166 6.5.1 Instruction TLB Multiple Hit Exception............................................................... 166 6.5.2 Instruction TLB Miss Exception........................................................................... 167 6.5.3 Instruction TLB Protection Violation Exception .................................................. 168
6.3
6.4
6.5
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6.6
6.7
6.8
6.5.4 Data TLB Multiple Hit Exception ........................................................................ 169 6.5.5 Data TLB Miss Exception .................................................................................... 169 6.5.6 Data TLB Protection Violation Exception............................................................ 170 6.5.7 Initial Page Write Exception................................................................................. 171 Memory-Mapped TLB Configuration................................................................................ 172 6.6.1 ITLB Address Array ............................................................................................. 173 6.6.2 ITLB Data Array................................................................................................... 174 6.6.3 UTLB Address Array............................................................................................ 175 6.6.4 UTLB Data Array ................................................................................................. 176 32-Bit Address Extended Mode ......................................................................................... 177 6.7.1 Overview of 32-Bit Address Extended Mode....................................................... 178 6.7.2 Transition to 32-Bit Address Extended Mode ...................................................... 178 6.7.3 Privileged Space Mapping Buffer (PMB) Configuration ..................................... 179 6.7.4 PMB Function....................................................................................................... 181 6.7.5 Memory-Mapped PMB Configuration.................................................................. 182 6.7.6 Notes on Using 32-Bit Address Extended Mode .................................................. 184 Usage Notes ....................................................................................................................... 186
Section 7 Caches ................................................................................................187
7.1 7.2 Features.............................................................................................................................. 187 Register Descriptions ......................................................................................................... 190 7.2.1 Cache Control Register (CCR) ............................................................................. 191 7.2.2 Queue Address Control Register 0 (QACR0)....................................................... 193 7.2.3 Queue Address Control Register 1 (QACR1)....................................................... 194 7.2.4 On-Chip Memory Control Register (RAMCR) .................................................... 195 Operand Cache Operation.................................................................................................. 197 7.3.1 Read Operation ..................................................................................................... 197 7.3.2 Prefetch Operation ................................................................................................ 198 7.3.3 Write Operation .................................................................................................... 199 7.3.4 Write-Back Buffer ................................................................................................ 201 7.3.5 Write-Through Buffer........................................................................................... 201 7.3.6 OC Two-Way Mode ............................................................................................. 201 Instruction Cache Operation .............................................................................................. 202 7.4.1 Read Operation ..................................................................................................... 202 7.4.2 Prefetch Operation ................................................................................................ 203 7.4.3 IC Two-Way Mode............................................................................................... 203 Cache Operation Instruction .............................................................................................. 204 7.5.1 Coherency between Cache and External Memory ................................................ 204 7.5.2 Prefetch Operation ................................................................................................ 205 Memory-Mapped Cache Configuration ............................................................................. 206
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7.3
7.4
7.5
7.6
7.7
7.8
7.6.1 IC Address Array.................................................................................................. 206 7.6.2 IC Data Array ....................................................................................................... 208 7.6.3 OC Address Array ................................................................................................ 209 7.6.4 OC Data Array...................................................................................................... 210 Store Queues ...................................................................................................................... 212 7.7.1 SQ Configuration.................................................................................................. 212 7.7.2 Writing to SQ........................................................................................................ 212 7.7.3 Transfer to External Memory ............................................................................... 213 7.7.4 Determination of SQ Access Exception................................................................ 214 7.7.5 Reading from SQ .................................................................................................. 214 Notes on Using 32-Bit Address Extended Mode ............................................................... 215
Section 8 L Memory.......................................................................................... 217
8.1 8.2 Features.............................................................................................................................. 217 Register Descriptions......................................................................................................... 218 8.2.1 On-Chip Memory Control Register (RAMCR) .................................................... 220 8.2.2 L Memory Transfer Source Address Register 0 (LSA0) ...................................... 221 8.2.3 L Memory Transfer Source Address Register 1 (LSA1) ...................................... 223 8.2.4 L Memory Transfer Destination Address Register 0 (LDA0) .............................. 225 8.2.5 L Memory Transfer Destination Address Register 1 (LDA1) .............................. 227 Operation ........................................................................................................................... 229 8.3.1 Access from the CPU and FPU............................................................................. 229 8.3.2 Access from the SuperHyway Bus Master Module .............................................. 229 8.3.3 Block Transfer ...................................................................................................... 229 L Memory Protective Functions ........................................................................................ 231 Usage Notes ....................................................................................................................... 232 8.5.1 Page Conflict ........................................................................................................ 232 8.5.2 L Memory Coherency........................................................................................... 232 8.5.3 Sleep Mode ........................................................................................................... 232 Note on Using 32-Bit Address Extended Mode................................................................. 232
8.3
8.4 8.5
8.6
Section 9 Interrupt Controller (INTC)............................................................... 233
9.1 Features.............................................................................................................................. 233 9.1.1 Interrupt Method................................................................................................... 235 9.1.2 Interrupt Types in INTC ....................................................................................... 236 Input/Output Pins............................................................................................................... 240 Register Descriptions......................................................................................................... 241 9.3.1 Interrupt Control Register 0 (ICR0)...................................................................... 246 9.3.2 Interrupt Control Register 1 (ICR1)...................................................................... 248 9.3.3 Interrupt Priority Register (INTPRI) .................................................................... 249
9.2 9.3
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9.4
9.5
9.6 9.7
Interrupt Source Register (INTREQ).................................................................... 250 Interrupt Mask Register 0 (INTMSK0) ................................................................ 251 Interrupt mask register 1 (INTMSK1) .................................................................. 253 Interrupt mask register 2 (INTMSK2) .................................................................. 254 Interrupt Mask Clear Register 0 (INTMSKCLR0) ............................................... 257 Interrupt mask clear register 1 (INTMSKCLR1).................................................. 259 Interrupt mask clear register 2 (INTMSKCLR2).................................................. 260 NMI Flag Control Register (NMIFCR) ................................................................ 263 User Interrupt Mask Level Register (USERIMASK) ........................................... 264 On-chip module Interrupt Priority Registers (INT2PRI0 to INT2PRI13) ............ 266 Interrupt Source Register 0 (Mask State is not affected) (INT2A0) ..................... 268 Interrupt Source Register 01 (Mask State is not affected) (INT2A01) ................. 269 Interrupt Source Register (Mask State is affected) (INT2A1) .............................. 272 Interrupt Source Register 11 (Mask State is affected) (INT2A11) ....................... 274 Interrupt Mask Register (INT2MSKR)................................................................. 276 Interrupt Mask Register 1 (INT2MSKR1)............................................................ 277 Interrupt Mask Clear Register (INT2MSKCR)..................................................... 279 Interrupt Mask Clear Register 1 (INT2MSKCR1)................................................ 281 On-chip Module Interrupt Source Registers (INT2B0 to INT2B7 and INT2B9 to INT2B11) ........................................................................................... 283 9.3.23 GPIO Interrupt Set Register (INT2GPIC) .............................................................. 289 Interrupt Sources................................................................................................................ 292 9.4.1 NMI Interrupt........................................................................................................ 292 9.4.2 IRQ Interrupts ....................................................................................................... 292 9.4.3 IRL Interrupts ....................................................................................................... 293 9.4.4 On-chip Module Interrupts ................................................................................... 295 9.4.5 Interrupt Priority Level of On-chip Module Interrupts ......................................... 295 9.4.6 Interrupt Exception Handling and Priority............................................................ 296 Operation ........................................................................................................................... 305 9.5.1 Interrupt Sequence ................................................................................................ 305 9.5.2 Multiple Interrupts ................................................................................................ 307 9.5.3 Interrupt Masking by MAI Bit .............................................................................. 307 Interrupt Response Time.................................................................................................... 308 Usage Notes ....................................................................................................................... 309 9.7.1 Example of Interrupt Handling Routine for Level-Encoded IRL and Level-Sensed IRQ................................................................................................. 309 9.7.2 Notes on Setting IRQ7/IRL7 to IRQ0/IRL0 Pin Function.................................... 310 9.7.3 To Clear IRQ and IRL Interrupt Requests ............................................................ 310
9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 9.3.10 9.3.11 9.3.12 9.3.13 9.3.14 9.3.15 9.3.16 9.3.17 9.3.18 9.3.19 9.3.20 9.3.21 9.3.22
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Section 10 SuperHyway Bus Bridge (SBR)...................................................... 313
10.1 Features.............................................................................................................................. 313 10.2 Register Descriptions......................................................................................................... 314 10.2.1 Bus Arbitration Priority Level Setting Register (SBRIVCLV) ............................ 315 10.2.2 SuperHyway Bus Priority Control Resister (PRPRICR) ...................................... 316 10.3 Operation ........................................................................................................................... 317 10.3.1 SuperHyway Bus Interface ................................................................................... 317 10.3.2 Bus Arbitration ..................................................................................................... 317
Section 11 Local Bus State Controller (LBSC)................................................. 319
11.1 Features.............................................................................................................................. 319 11.2 Input/Output Pins............................................................................................................... 322 11.3 Area Overview................................................................................................................... 324 11.3.1 Space Divisions .................................................................................................... 324 11.3.2 Memory Bus Width .............................................................................................. 328 11.3.3 Data Alignment..................................................................................................... 329 11.3.4 PCMCIA Support ................................................................................................. 329 11.4 Register Descriptions......................................................................................................... 333 11.4.1 Memory Address Map Select Register (MMSELR)............................................. 334 11.4.2 Bus Control Register (BCR) ................................................................................. 336 11.4.3 CSn Bus Control Register (CSnBCR) .................................................................. 340 11.4.4 CSn Wait Control Register (CSnWCR)................................................................ 346 11.4.5 CSn PCMCIA Control Register (CSnPCR).......................................................... 351 11.5 Operation ........................................................................................................................... 356 11.5.1 Endian/Access Size and Data Alignment.............................................................. 356 11.5.2 Areas..................................................................................................................... 361 11.5.3 SRAM interface .................................................................................................... 365 11.5.4 Burst ROM Interface ............................................................................................ 373 11.5.5 PCMCIA Interface................................................................................................ 375 11.5.6 MPX Interface ...................................................................................................... 386 11.5.7 Byte Control SRAM Interface .............................................................................. 399 11.5.8 Wait Cycles between Accesses............................................................................. 403 11.5.9 Bus Arbitration ..................................................................................................... 405 11.5.10 Master Mode......................................................................................................... 407 11.5.11 Cooperation between Master and Slave................................................................ 408
Section 12 DDR-SDRAM Interface (DDRIF) .................................................. 409
12.1 Features.............................................................................................................................. 409 12.2 Input/Output Pins............................................................................................................... 411
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12.3 Data Conversion................................................................................................................. 412 12.3.1 Data Alignment..................................................................................................... 412 12.3.2 Data Alignment in Peripheral Modules ................................................................ 414 12.4 Register Descriptions ......................................................................................................... 415 12.4.1 Memory Interface Mode Register (MIM) ............................................................. 417 12.4.2 DDR-SDRAM Control Register (SCR)................................................................ 421 12.4.3 DDR-SDRAM Timing Register (STR)................................................................. 423 12.4.4 DDR-SDRAM Row Attribute Register (SDR) ..................................................... 426 12.4.5 DDR-SDRAM Mode Register (SDMR) ............................................................... 427 12.4.6 DDR-SDRAM Back-up Register (DBK).............................................................. 429 12.5 Operation ........................................................................................................................... 430 12.5.1 DDR-SDRAM Access .......................................................................................... 430 12.5.2 DDR-SDRAM Initialization Sequence................................................................. 430 12.5.3 Supported DDR-SDRAM Commands .................................................................. 432 12.5.4 DDR-SDRAM Access Mode................................................................................ 433 12.5.5 Power-Down Modes ............................................................................................. 433 12.5.6 Registers that Set DDR-SDRAM Timing Restrictions ......................................... 434 12.5.7 Operating Frequency............................................................................................. 435 12.5.8 Note on Clock Stop............................................................................................... 435 12.5.9 Using SCR to Issue REFA Commands (Outside the Initialization Sequence)...... 435 12.5.10 Note on Timing of Connected DDR-SDRAM...................................................... 435 12.5.11 Note on Setting Auto-Refresh Interval ................................................................. 436 12.5.12 Address Multiplexing ........................................................................................... 436 12.5.13 DDR-SDRAM Access Arbitration........................................................................ 436 12.5.14 Coherency When Accessing DDR-SDRAM ........................................................ 437 12.6 DDRIF Basic Timing......................................................................................................... 438
Section 13 PCI Controller (PCIC) .....................................................................449
13.1 Features.............................................................................................................................. 449 13.2 Input/Output Pins ............................................................................................................... 452 13.3 Register Descriptions ......................................................................................................... 455 13.3.1 PCIC Enable Control Register (PCIECR) ............................................................ 460 13.3.2 Configuration Registers ........................................................................................ 461 13.3.3 Local Register ....................................................................................................... 486 13.4 Operation ........................................................................................................................... 527 13.4.1 Supported PCI Commands.................................................................................... 527 13.4.2 PCIC Initialization ................................................................................................ 528 13.4.3 Master Access ....................................................................................................... 529 13.4.4 Target Access........................................................................................................ 537 13.4.5 Host Bus Bridge Mode ......................................................................................... 546
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13.4.6 Normal mode ........................................................................................................ 549 13.4.7 Power Management .............................................................................................. 549 13.4.8 PCI Local Bus Basic Interface.............................................................................. 550 13.5 Usage Notes ....................................................................................................................... 562 13.5.1 Notes on PCIC Target Reading............................................................................. 562 13.5.2 Notes on Host Mode ............................................................................................. 562
Section 14 Direct Memory Access Controller (DMAC)................................... 565
14.1 Features.............................................................................................................................. 565 14.2 Input/Output Pins............................................................................................................... 567 14.3 Register Descriptions......................................................................................................... 569 14.3.1 DMA Source Address Registers (SAR0 to SAR5) ............................................... 572 14.3.2 DMA Source Address Registers (SARB0 to SARB3).......................................... 573 14.3.3 DMA Destination Address Registers (DAR0 to DAR5) ...................................... 573 14.3.4 DMA Destination Address Registers (DARB0 to DARB3) ................................. 574 14.3.5 DMA Transfer Count Registers (TCR0 to TCR5)................................................ 574 14.3.6 DMA Transfer Count Registers (TCRB0 to TCRB3)........................................... 575 14.3.7 DMA Channel Control Registers (CHCR0 to CHCR5) ....................................... 576 14.3.8 DMA Operation Register (DMAOR) ................................................................... 584 14.3.9 DMA Extended Resource Selectors (DMARS0 to DMARS2)............................. 587 14.4 Operation ........................................................................................................................... 591 14.4.1 DMA Transfer Requests ....................................................................................... 591 14.4.2 Channel Priority.................................................................................................... 595 14.4.3 DMA Transfer Types............................................................................................ 598 14.4.4 DMA Transfer Flow ............................................................................................. 606 14.4.5 Repeat Mode Transfer .......................................................................................... 608 14.4.6 Reload Mode Transfer .......................................................................................... 609 14.4.7 DREQ Pin Sampling Timing ................................................................................ 610 14.5 Usage Notes ....................................................................................................................... 614 14.5.1 Module Stop ......................................................................................................... 614 14.5.2 Address Error........................................................................................................ 614 14.5.3 Notes on Burst Mode Transfer.............................................................................. 614 14.5.4 DACK and TEND Output Divisions .................................................................... 615 14.5.5 CS Output Settings and Transfer Size Larger than External Bus Width............... 615 14.5.6 DACK and TEND Assertion and DREQ Sampling.............................................. 615 14.5.7 DMA Transfer to DMAC Prohibited.................................................................... 619 14.5.8 NMI Interrupt........................................................................................................ 619
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Section 15 External CPU Interface (EXCPU) ...................................................621
15.1 Features.............................................................................................................................. 621 15.2 Input/Output Pins ............................................................................................................... 622 15.3 Register Descriptions ......................................................................................................... 623 15.3.1 External CPU Control Register (EXCCTRL) ....................................................... 624 15.3.2 External CPU Memory Space Select Register (EXCMSETR) ............................. 625 15.3.3 External CPU Interrupt Output Control Register (EXCINOR)............................. 626 15.4 Operation ........................................................................................................................... 627
Section 16 Clock Pulse Generator (CPG)..........................................................633
Features.............................................................................................................................. 633 Input/Output Pins ............................................................................................................... 636 Clock Operating Mode....................................................................................................... 637 Register Descriptions ......................................................................................................... 638 16.4.1 Frequency Control Register (FRQCR) ................................................................. 639 16.4.2 PLL Control Register (PLLCR)............................................................................ 641 16.5 Notes on Board Design ...................................................................................................... 642 16.1 16.2 16.3 16.4
Section 17 Watchdog Timer and Reset (WDT).................................................645
17.1 Features.............................................................................................................................. 645 17.2 Input/Output Pins ............................................................................................................... 647 17.3 Register Descriptions ......................................................................................................... 648 17.3.1 Watchdog Timer Stop Time Register (WDTST) .................................................. 649 17.3.2 Watchdog Timer Control/Status Register (WDTCSR)......................................... 650 17.3.3 Watchdog timer Base Stop Time Register (WDTBST) ........................................ 652 17.3.4 Watchdog Timer Counter (WDTCNT)................................................................. 653 17.3.5 Watchdog Timer Base Counter (WDTBCNT) ..................................................... 653 17.4 Operation ........................................................................................................................... 654 17.4.1 Reset request......................................................................................................... 654 17.4.2 Using watchdog timer mode ................................................................................. 655 17.4.3 Using Interval timer mode .................................................................................... 656 17.4.4 Time for WDT Overflow ...................................................................................... 656 17.4.5 Clearing WDT Counter......................................................................................... 658 17.5 Status Pin Change Timing during Reset ............................................................................ 659 17.5.1 Power-On Reset by PRESET................................................................................ 659 17.5.2 Power-On Reset by Watchdog Timer Overflow................................................... 662 17.5.3 Manual Reset by Watchdog Timer Overflow ....................................................... 664
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Section 18 Power-Down Mode ......................................................................... 667
18.1 Features.............................................................................................................................. 667 18.1.1 Types of Power-Down Modes .............................................................................. 667 18.2 Input/Output Pins............................................................................................................... 669 18.3 Register Descriptions......................................................................................................... 670 18.3.1 Standby Control Register (STBCR)...................................................................... 671 18.3.2 Module Stop Register 0 (MSTPCR0) ................................................................... 672 18.3.3 Module Stop Register 1 (MSTPCR1) ................................................................... 673 18.4 Sleep Mode ........................................................................................................................ 678 18.4.1 Transition to Sleep Mode...................................................................................... 678 18.4.2 Canceling Sleep Mode .......................................................................................... 678 18.5 Software Standby Mode..................................................................................................... 679 18.5.1 Transition to Software Standby Mode .................................................................. 679 18.5.2 Canceling Software Standby Mode ...................................................................... 679 18.6 Module Standby Mode....................................................................................................... 680 18.6.1 Transition to Module Standby Mode .................................................................... 680 18.6.2 Canceling Module Standby Mode ........................................................................ 680 18.7 DDR-SDRAM Power Supply Backup............................................................................... 681 18.7.1 Control of Self-Refresh and Initialization............................................................. 681 18.7.2 DDR-SDRAM Backup Sequence when Turning Off System Power Supply ....... 682 18.8 RTC Power Supply Backup ............................................................................................... 684 18.8.1 Transition to RTC Power Supply Backup Mode .................................................. 684 18.8.2 Canceling RTC Power Supply Backup Mode....................................................... 684 18.9 STATUS Pin Signal Change Timing ................................................................................. 685 18.9.1 Timing at Reset..................................................................................................... 685 18.9.2 Timing at Sleep Mode Cancellation ..................................................................... 685
Section 19 Timer Unit (TMU)........................................................................... 687
19.1 Features.............................................................................................................................. 687 19.2 Input/Output Pins............................................................................................................... 689 19.3 Register Descriptions......................................................................................................... 690 19.3.1 Timer Output Control Register (TOCR)............................................................... 692 19.3.2 Timer Start Register (TSTR) ................................................................................ 693 19.3.3 Timer Constant Register (TCORn) (n = 0 to 5) .................................................... 695 19.3.4 Timer Counter (TCNTn) (n = 0 to 5).................................................................... 695 19.3.5 Timer Control Registers (TCRn) (n = 0 to 5) ....................................................... 696 19.3.6 Input Capture Register 2 (TCPR2) ....................................................................... 698 19.4 Operation ........................................................................................................................... 699 19.4.1 Counter Operation ................................................................................................ 699
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19.4.2 Input Capture Function ......................................................................................... 703 19.5 Interrupts............................................................................................................................ 704 19.6 Usage Notes ....................................................................................................................... 705 19.6.1 Register Writes ..................................................................................................... 705 19.6.2 Reading from TCNT............................................................................................. 705 19.6.3 External Clock Frequency..................................................................................... 705
Section 20 16-Bit Timer Pulse Unit (TPU) .......................................................707
20.1 Features.............................................................................................................................. 707 20.2 Input/Output Pins ............................................................................................................... 710 20.3 Register Descriptions ......................................................................................................... 711 20.3.1 Timer Control Registers (TCR) ............................................................................ 715 20.3.2 Timer Mode Registers (TMDR) ........................................................................... 719 20.3.3 Timer I/O Control Registers (TIOR) .................................................................... 721 20.3.4 Timer Interrupt Enable Registers (TIER) ............................................................. 723 20.3.5 Timer Status Registers (TSR) ............................................................................... 725 20.3.6 Timer Counters (TCNT) ....................................................................................... 727 20.3.7 Timer General Registers (TGR)............................................................................ 727 20.3.8 Timer Start Register (TSTR) ................................................................................ 728 20.4 Operation ........................................................................................................................... 729 20.4.1 Overview............................................................................................................... 729 20.4.2 Basic Functions..................................................................................................... 730 20.4.3 Buffer Operation ................................................................................................... 734 20.4.4 PWM Modes ......................................................................................................... 737 20.4.5 Phase Counting Mode........................................................................................... 740 20.5 Usage Notes ....................................................................................................................... 746
Section 21 Compare Match Timer (CMT) ........................................................747
21.1 Features.............................................................................................................................. 747 21.2 Register Descriptions ......................................................................................................... 749 21.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 751 21.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 752 21.2.3 Compare Match Timer Counter (CMCNT) .......................................................... 754 21.2.4 Compare Match Timer Constant Register (CMCOR)........................................... 754 21.3 Operation ........................................................................................................................... 755 21.3.1 Counter Operation................................................................................................. 755 21.3.2 Counter Size.......................................................................................................... 756 21.3.3 Timing for Counting by CMCNT ......................................................................... 756 21.3.4 DMA Transfer Requests and Internal Interrupt Requests to CPU ........................ 757 21.3.5 Compare Match Flag Set Timing (All Channels) ................................................. 757
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Section 22 Realtime Clock (RTC)..................................................................... 759
22.1 Features.............................................................................................................................. 759 22.1.1 Block Diagram...................................................................................................... 760 22.2 Input/Output Pins............................................................................................................... 761 22.3 Register Descriptions......................................................................................................... 762 22.4 Register Descriptions......................................................................................................... 764 22.4.1 64 Hz Counter (R64CNT)..................................................................................... 764 22.4.2 Second Counter (RSECCNT) ............................................................................... 764 22.4.3 Minute Counter (RMINCNT)............................................................................... 765 22.4.4 Hour Counter (RHRCNT) .................................................................................... 765 22.4.5 Day-of-Week Counter (RWKCNT)...................................................................... 766 22.4.6 Day Counter (RDAYCNT)................................................................................... 767 22.4.7 Month Counter (RMONCNT) .............................................................................. 768 22.4.8 Year Counter (RYRCNT)..................................................................................... 768 22.4.9 Second Alarm Register (RSECAR) ...................................................................... 769 22.4.10 Minute Alarm Register (RMINAR)...................................................................... 769 22.4.11 Hour Alarm Register (RHRAR) ........................................................................... 770 22.4.12 Day-of-Week Alarm Register (RWKAR)............................................................. 770 22.4.13 Day Alarm Register (RDAYAR).......................................................................... 771 22.4.14 Month Alarm Register (RMONAR) ..................................................................... 772 22.4.15 RTC Control Register 1 (RCR1)........................................................................... 772 22.4.16 RTC Control Register 2 (RCR2)........................................................................... 774 22.4.17 RTC Control Register (RCR3) and Year-Alarm Register (RYRAR) ................... 777 22.5 Operation ........................................................................................................................... 778 22.5.1 Time Setting Procedures....................................................................................... 778 22.5.2 Time Reading Procedures..................................................................................... 779 22.5.3 Alarm Function..................................................................................................... 780 22.6 Interrupts............................................................................................................................ 781 22.7 Usage Notes ....................................................................................................................... 781 22.7.1 Register Initialization............................................................................................ 781 22.7.2 Crystal Oscillator Circuit ...................................................................................... 781 22.7.3 Interrupt source and request generating order....................................................... 782
Section 23 Gigabit Ethernet Controller (GETHER).......................................... 783
23.1 Features.............................................................................................................................. 783 23.2 Input/Output Pins............................................................................................................... 785 23.3 Register Descriptions......................................................................................................... 790 23.3.1 Software Reset Register (ARSTR) ....................................................................... 807 23.3.2 E-MAC Mode Register (ECMR) .......................................................................... 808 23.3.3 E-MAC Status Register (ECSR)........................................................................... 814
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23.3.4 E-MAC Interrupt Permission Register (ECSIPR)................................................. 816 23.3.5 PHY Interface Register (PIR) ............................................................................... 817 23.3.6 MAC Address High Register (MAHR) ................................................................ 818 23.3.7 MAC Address Low Register (MALR).................................................................. 819 23.3.8 Receive Frame Length Register (RFLR) .............................................................. 820 23.3.9 PHY Status Register (PSR)................................................................................... 821 23.3.10 PHY_INT Polarity Register (PIPR)...................................................................... 822 23.3.11 Transmit Retry Over Counter Register (TROCR) ................................................ 823 23.3.12 Delayed Collision Detect Counter Register (CDCR)............................................ 824 23.3.13 Lost Carrier Counter Register (LCCR)................................................................. 825 23.3.14 CRC Error Frame Receive Counter Register (CEFCR)........................................ 826 23.3.15 Frame Receive Error Counter Register (FRECR)................................................. 827 23.3.16 Too-Short Frame Receive Counter Register (TSFRCR)....................................... 828 23.3.17 Too-Long Frame Receive Counter Register (TLFRCR)....................................... 829 23.3.18 Residual-Bit Frame Receive Counter Register (RFCR) ....................................... 830 23.3.19 Carrier Extension Loss Counter Register (CERCR) ............................................. 831 23.3.20 Carrier Extension Error Counter Register (CEECR) ............................................ 832 23.3.21 Multicast Address Frame Receive Counter Register (MAFCR)........................... 833 23.3.22 Automatic PAUSE Frame Register (APR) ........................................................... 834 23.3.23 Manual PAUSE Frame Register (MPR) ............................................................... 835 23.3.24 Automatic PAUSE Frame Retransmit Count Register (TPAUSER) .................... 836 23.3.25 PAUSE Frame Transmit Counter Register (PFTCR) ........................................... 837 23.3.26 PAUSE Frame Receive Counter Register (PFRCR)............................................. 838 23.3.27 GETHER Mode Register (GECMR) .................................................................... 839 23.3.28 Burst Cycle Count Upper-Limit Register (BCULR)............................................. 840 23.3.29 TSU Counter Reset Register (TSU_CTRST) ....................................................... 841 23.3.30 Relay Enable Register (Port 0 to 1) (TSU_FWEN0) ............................................ 842 23.3.31 Relay Enable Register (Port 1 to 0) (TSU_FWEN1) ............................................ 843 23.3.32 Relay FIFO Size Select Register (TSU_FCM) ..................................................... 844 23.3.33 Relay FIFO Overflow Alert Set Register (Port 0) (TSU_BSYSL0) ..................... 845 23.3.34 Relay FIFO Overflow Alert Set Register (Port 1) (TSU_BSYSL1) ..................... 847 23.3.35 Transmit/Relay Priority Control Mode Register (Port 0) (TSU_PRISL0)............ 849 23.3.36 Transmit/Relay Priority Control Mode Register (Port 1) (TSU_PRISL1)............ 851 23.3.37 Receive/Relay Function Set Register (Port 0 to 1) (TSU_FWSL0)...................... 853 23.3.38 Receive/Relay Function Set Register (Port 1 to 0) (TSU_FWSL1)...................... 855 23.3.39 Relay Function Set Register (Common) (TSU_FWSLC)..................................... 857 23.3.40 Qtag Addition/Deletion Set Register (Port 0 to 1) (TSU_QTAG0) ...................... 859 23.3.41 Qtag Addition/Deletion Set Register (Port 1 to 0) (TSU_QTAG1) ...................... 860 23.3.42 Relay Status Register (TSU_FWSR) .................................................................... 861 23.3.43 Relay Status Interrupt Mask Register (TSU_FWINMK)...................................... 864
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23.3.44 Added Qtag Value Set Register (Port 0 to 1) (TSU_ADQT0).............................. 867 23.3.45 Added Qtag Value Set Register (Port 1 to 0) (TSU_ADQT1).............................. 868 23.3.46 VLANtag Set Register (Port 0) (TSU_VTAG0)................................................... 869 23.3.47 VLANtag Set Register (Port 1) (TSU_VTAG1)................................................... 870 23.3.48 CAM Entry Table Busy Register (TSU_ADSBSY) ............................................. 871 23.3.49 CAM Entry Table Enable Register (TSU_TEN) .................................................. 872 23.3.50 CAM Entry Table POST1 Register (TSU_POST1).............................................. 877 23.3.51 CAM Entry Table POST2 Register (TSU_POST2).............................................. 880 23.3.52 CAM Entry Table POST3 Register (TSU_POST3).............................................. 883 23.3.53 CAM Entry Table POST4 Register (TSU_POST4).............................................. 886 23.3.54 CAM Entry Table 0H to 31H Registers (TSU_ADRH0 to TSU_ADRH31)........ 889 23.3.55 CAM Entry Table 0L to 31L Registers (TSU_ADRL0 to TSU_ADRL31) ......... 890 23.3.56 Transmit Frame Counter Register (Port 0) (Normal Transmission Only) (TXNLCR0).......................................................................................................... 891 23.3.57 Transmit Frame Counter Register (Port 0) (Normal and Erroneous Transmission) (TXALCR0) ........................................... 892 23.3.58 Receive Frame Counter Register (Port 0) (Normal Reception Only) (RXNLCR0) ......................................................................................................... 893 23.3.59 Receive Frame Counter Register (Port 0) (Normal and Erroneous Reception) (RXALCR0) ......................................................................................................... 894 23.3.60 Relay Frame Counter Register (Port 1 to 0) (Normal Relay Only) (FWNLCR0) ......................................................................................................... 895 23.3.61 Relay Frame Counter Register (Port 1 to 0) (Normal and Erroneous Transmission) (FWALCR0)........................................... 896 23.3.62 Transmit Frame Counter Register (Port 1) (Normal Transmission Only) (TXNLCR1)........................................................... 897 23.3.63 Transmit Frame Counter Register (Port 1) (Normal and Erroneous Transmission) (TXALCR1) ........................................... 898 23.3.64 Receive Frame Counter Register (Port 1) (Normal Reception Only) (RXNLCR1) ......................................................................................................... 899 23.3.65 Receive Frame Counter Register (Port 1) (Normal and Erroneous Reception) (RXALCR1)................................................. 900 23.3.66 Relay Frame Counter Register (Port 0 to 1) (Normal Relay Only) (FWNLCR1) ......................................................................................................... 901 23.3.67 Relay Frame Counter Register (Port 0 to 1) (Normal and Erroneous Transmission) (FWALCR1)........................................... 902 23.3.68 E-DMAC Start Register (EDSR) .......................................................................... 903 23.3.69 E-DMAC Mode Register (EDMR)....................................................................... 904 23.3.70 E-DMAC Transmit Request Register (EDTRR) .................................................. 906 23.3.71 E-DMAC Receive Request Register (EDRRR).................................................... 907
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23.3.72 Transmit Descriptor List Start Address Register (TDLAR) ................................. 908 23.3.73 Receive Descriptor List Start Address Register (RDLAR)................................... 909 23.3.74 E-MAC/E-DMAC Status Register (EESR) .......................................................... 910 23.3.75 E-MAC/E-DMAC Status Interrupt Permission Register (EESIPR) ..................... 916 23.3.76 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 920 23.3.77 Receive Missed-Frame Counter Register (RMFCR) ............................................ 923 23.3.78 Transmit FIFO Threshold Register (TFTR).......................................................... 924 23.3.79 FIFO Depth Register (FDR) ................................................................................. 925 23.3.80 Receiving Method Control Register (RMCR) ...................................................... 926 23.3.81 Receive Descriptor Fetch Address Register (RDFAR)......................................... 927 23.3.82 Receive Descriptor Finished Address Register (RDFXR) .................................... 928 23.3.83 Receive Descriptor Final Flag Register (RDFFR) ................................................ 929 23.3.84 Transmit Descriptor Fetch Address Register (TDFAR) ....................................... 930 23.3.85 Transmit Descriptor Finished Address Register (TDFXR)................................... 931 23.3.86 Transmit Descriptor Final Flag Register (TDFFR)............................................... 932 23.3.87 Overflow Alert FIFO Threshold Register (FCFTR) ............................................. 933 23.3.88 Receive Data Padding Insert Register (RPADIR)................................................. 935 23.4 Operation ........................................................................................................................... 936 23.4.1 Descriptors and Descriptor List ............................................................................ 939 23.4.2 Transmission......................................................................................................... 956 23.4.3 Reception .............................................................................................................. 962 23.4.4 Relay ..................................................................................................................... 968 23.4.5 CAM Function ...................................................................................................... 969 23.4.6 Transmit/Receive Processing of Multi-Buffer Frame (Single-Frame/Multi-Descriptor) .......................................................................... 971 23.4.7 Padding Insertion in Receive Data........................................................................ 973 23.4.8 Interrupt Processing .............................................................................................. 974 23.4.9 Activation Procedure ............................................................................................ 978 23.4.10 Flow Control......................................................................................................... 980 23.4.11 Magic Packet Detection ........................................................................................ 981 23.4.12 Direction for IEEE802.1Q Qtag............................................................................ 982 23.5 Connection to PHY-LSI..................................................................................................... 984 23.5.1 MII Frame Transmission/Reception Timing......................................................... 984 23.5.2 GMII/MII Frame Reception Timing ..................................................................... 986 23.5.3 RMII Frame Transmission/Reception Timing ...................................................... 988 23.5.4 Accessing MII Registers ....................................................................................... 989 23.5.5 Mll-RMII Interface Conversion ............................................................................ 991 23.6 Usage Notes ....................................................................................................................... 993 23.6.1 Checksum Calculation of Ethernet Frames........................................................... 993 23.6.2 Notes on TSU Use ................................................................................................ 993
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Section 24 IP Security Accelerator (SECURITY) ........................................... 995 Section 25 Stream Interface (STIF)................................................................... 997
25.1 Features.............................................................................................................................. 997 25.2 Input/Output Pins............................................................................................................... 999 25.3 Register Descriptions....................................................................................................... 1000 25.3.1 Mode Registers 0, 1 (STIMDR0, STIMDR1)..................................................... 1002 25.3.2 Control Registers 0, 1 (STICR0, STICR1) ......................................................... 1006 25.3.3 Interrupt Status Registers 0, 1 (STIISR0, STIISR1) ........................................... 1007 25.3.4 Interrupt Enable Registers 0, 1 (STIIER0, STIIER1) ......................................... 1009 25.3.5 Time Stamp Counter Registers 0, 1 (STITSC0, STITSC1) ................................ 1011 25.3.6 Transmit/Receive Packet Count Registers 0, 1 (STIPNR0, STIPNR1) .............. 1012 25.3.7 Transmit/Receive Packet Counter Registers 0, 1 (STIPCR0, STIPCR1) ........... 1013 25.3.8 Transmit/Receive FIFO Data Registers 0, 1 (STIFIFO0, STIFIFO1) ................ 1014 25.3.9 Operation ............................................................................................................ 1015 25.3.10 External Memory Configuration for Stream Data Transmission/Reception....... 1015 25.3.11 Stream Data Receive Operation.......................................................................... 1016 25.3.12 Stream Data Transmit Operation ........................................................................ 1020
Section 26 I2C Bus Interface (IIC)................................................................... 1025
26.1 Features............................................................................................................................ 1025 26.2 Input/Output Pins............................................................................................................. 1026 26.3 Register Descriptions....................................................................................................... 1026 26.3.1 Slave Control Register (ICSCR)......................................................................... 1029 26.3.2 Slave Status Register (ICSSR)............................................................................ 1031 26.3.3 Slave Interrupt Enable Register (ICSIER) .......................................................... 1034 26.3.4 Slave Address Register (ICSAR)........................................................................ 1035 26.3.5 Master Control Register (ICMCR) ..................................................................... 1036 26.3.6 Master Status Register (ICMSR) ........................................................................ 1038 26.3.7 Master Interrupt Enable Register (ICMIER) ...................................................... 1040 26.3.8 Master Address Register (ICMAR) .................................................................... 1041 26.3.9 Clock Control Register (ICCCR)........................................................................ 1041 26.3.10 Receive and Transmit Data Registers (ICRXD and ICTXD) ............................. 1043 26.4 Operations........................................................................................................................ 1044 26.4.1 Data and Clock Filters ........................................................................................ 1044 26.4.2 Clock Generator.................................................................................................. 1044 26.4.3 Master/Slave Interfaces....................................................................................... 1044 26.4.4 Software Status Interlocking............................................................................... 1044 26.4.5 I2C Bus Data Format ........................................................................................... 1046 26.4.6 7-Bit Address Format.......................................................................................... 1047
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26.4.7 10-Bit Address Format........................................................................................ 1048 26.4.8 Master Transmit Operation ................................................................................. 1050 26.4.9 Master Receive Operation................................................................................... 1052 26.5 Programming Examples................................................................................................... 1054 26.5.1 Master Transmitter.............................................................................................. 1054 26.5.2 Master Receiver .................................................................................................. 1055 26.5.3 Master Transmitter--Restart--Master Receiver ................................................ 1056
Section 27 Serial Communication Interface with FIFO (SCIF) ......................1059
27.1 Features............................................................................................................................ 1059 27.2 Input/Output Pins ............................................................................................................. 1065 27.3 Register Descriptions ....................................................................................................... 1066 27.3.1 Receive Shift Register (SCRSR)......................................................................... 1068 27.3.2 Receive FIFO Data Register (SCFRDR) ............................................................ 1068 27.3.3 Transmit Shift Register (SCTSR) ....................................................................... 1069 27.3.4 Transmit FIFO Data Register (SCFTDR) ........................................................... 1069 27.3.5 Serial Mode Register (SCSMR).......................................................................... 1070 27.3.6 Serial Control Register (SCSCR)........................................................................ 1073 27.3.7 Serial Status Register (SCFSR) .......................................................................... 1077 27.3.8 Bit Rate Register (SCBRR) ................................................................................ 1083 27.3.9 FIFO Control Register (SCFCR) ........................................................................ 1084 27.3.10 Transmit FIFO Data Count Register (SCTFDR) ................................................ 1086 27.3.11 Receive FIFO Data Count Register (SCRFDR).................................................. 1086 27.3.12 Serial Port Register (SCSPTR) ........................................................................... 1087 27.3.13 Line Status Register (SCLSR) ............................................................................ 1090 27.3.14 Serial Error Register (SCRER) ........................................................................... 1091 27.4 Operation ......................................................................................................................... 1092 27.4.1 Overview............................................................................................................. 1092 27.4.2 Operation in Asynchronous Mode ...................................................................... 1094 27.4.3 Operation in Clocked Synchronous Mode .......................................................... 1104 27.5 SCIF Interrupt Sources and the DMAC ........................................................................... 1113 27.6 Usage Notes ..................................................................................................................... 1115
Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)...................................................................................1119
28.1 Features............................................................................................................................ 1119 28.2 Input/Output Pins ............................................................................................................. 1123 28.3 Register Descriptions ....................................................................................................... 1124 28.3.1 Receive Shift Register (SCRSR)......................................................................... 1126 28.3.2 Receive FIFO Data Register (SCFRDR) ............................................................ 1126
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28.3.3 Transmit Shift Register (SCTSR) ....................................................................... 1127 28.3.4 Transmit FIFO Data Register (SCFTDR)........................................................... 1127 28.3.5 Serial Mode Register (SCSMR).......................................................................... 1128 28.3.6 Serial Control Register (SCSCR)........................................................................ 1131 28.3.7 Serial Status Register (SCFSR) .......................................................................... 1135 28.3.8 Bit Rate Register (SCBRR) ................................................................................ 1141 28.3.9 FIFO Control Register (SCFCR) ........................................................................ 1142 28.3.10 FIFO Data Count Register (SCFDR).................................................................. 1144 28.3.11 Serial Port Register (SCSPTR) ........................................................................... 1145 28.3.12 Line Status Register (SCLSR) ............................................................................ 1147 28.3.13 BRG Frequency Division Register (BRGDL2) .................................................. 1148 28.3.14 BRG Clock Select Register (BRGCKS2) ........................................................... 1149 28.3.15 IrDA Serial Mode Register (SCSMRIR) ............................................................ 1150 28.4 Operation ......................................................................................................................... 1151 28.4.1 Overview ............................................................................................................ 1151 28.4.2 Operation in Asynchronous Mode ...................................................................... 1155 28.4.3 Operation in Clocked Synchronous Mode .......................................................... 1165 28.4.4 SCIF Interrupt Sources and the DMAC.............................................................. 1174 28.4.5 Usage Notes ........................................................................................................ 1176 28.5 Infrared Data Communication Interface .......................................................................... 1179 28.5.1 Infrared Data Communication Format................................................................ 1179 28.5.2 Operation of Infrared Data Communication Interface ........................................ 1180 28.6 Baud Rate Generator for External Clock (BRG) ............................................................. 1181 28.6.1 BRG Block Diagram........................................................................................... 1181 28.6.2 Restrictions on the BRG ..................................................................................... 1182
Section 29 Serial I/O with FIFO (SIOF) ......................................................... 1185
29.1 Features............................................................................................................................ 1185 29.2 Input/Output Pins............................................................................................................. 1187 29.3 Register Descriptions....................................................................................................... 1188 29.3.1 Mode Register (SIMDR) .................................................................................... 1192 29.3.2 Clock Select Register (SISCR) ........................................................................... 1194 29.3.3 Control Register (SICTR)................................................................................... 1196 29.3.4 Transmit Data Register (SITDR) ........................................................................ 1199 29.3.5 Receive Data Register (SIRDR) ......................................................................... 1200 29.3.6 Transmit Control Data Register (SITCR) ........................................................... 1201 29.3.7 Receive Control Data Register (SIRCR) ............................................................ 1202 29.3.8 Status Register (SISTR)...................................................................................... 1203 29.3.9 Interrupt Enable Register (SIIER) ...................................................................... 1209 29.3.10 FIFO Control Register (SIFCTR) ....................................................................... 1211
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29.3.11 Transmit Data Assign Register (SITDAR) ......................................................... 1213 29.3.12 Receive Data Assign Register (SIRDAR)........................................................... 1214 29.3.13 Control Data Assign Register (SICDAR) ........................................................... 1215 29.4 Operation ......................................................................................................................... 1217 29.4.1 Serial Clocks ....................................................................................................... 1217 29.4.2 Serial Timing ...................................................................................................... 1218 29.4.3 Transfer Data Format.......................................................................................... 1220 29.4.4 Register Allocation of Transfer Data .................................................................. 1222 29.4.5 Control Data Interface ........................................................................................ 1225 29.4.6 FIFO.................................................................................................................... 1227 29.4.7 Transmit and Receive Procedures....................................................................... 1229 29.4.8 Interrupts............................................................................................................. 1234 29.4.9 Transmit and Receive Timing............................................................................. 1236
Section 30 SIM Card Module (SIM) ...............................................................1241
30.1 Features............................................................................................................................ 1241 30.2 Input/Output Pins ............................................................................................................. 1243 30.3 Register Descriptions ....................................................................................................... 1244 30.3.1 Serial Mode Register (SCSMR).......................................................................... 1246 30.3.2 Bit Rate Register (SCBRR) ................................................................................ 1247 30.3.3 Serial Control Register (SCSCR)........................................................................ 1248 30.3.4 Transmit Shift Register (SCTSR) ....................................................................... 1250 30.3.5 Transmit Data Register (SCTDR)....................................................................... 1251 30.3.6 Serial Status Register (SCSSR) .......................................................................... 1252 30.3.7 Receive Shift Register (SCRSR)......................................................................... 1258 30.3.8 Receive Data Register (SCRDR) ........................................................................ 1258 30.3.9 Smart Card Mode Register (SCSCMR) .............................................................. 1259 30.3.10 Serial Control 2 Register (SCSC2R)................................................................... 1261 30.3.11 Guard Extension Register (SCGRD) .................................................................. 1262 30.3.12 Wait Time Register (SCWAIT) .......................................................................... 1263 30.3.13 Sampling Register (SCSMPL) ............................................................................ 1264 30.4 Operation ......................................................................................................................... 1265 30.4.1 Overview............................................................................................................. 1265 30.4.2 Data Format ........................................................................................................ 1266 30.4.3 Register Settings ................................................................................................. 1267 30.4.4 Clocks ................................................................................................................. 1269 30.4.5 Data Transmit/Receive Operation....................................................................... 1270 30.5 Usage Notes ..................................................................................................................... 1278
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Section 31 Multimedia Card Interface (MMCIF) ........................................... 1285
31.1 Features............................................................................................................................ 1285 31.2 Input/Output Pins............................................................................................................. 1287 31.3 Register Descriptions....................................................................................................... 1288 31.3.1 Command Type Register (CMDTYR)................................................................ 1292 31.3.2 Response Type Register (RSPTYR)................................................................... 1293 31.3.3 Transfer Byte Number Count Register (TBCR) ................................................. 1297 31.3.4 Transfer Block Number Counter (TBNCR)........................................................ 1298 31.3.5 Command Registers 0 to 5 (CMDR0 to CMDR5).............................................. 1298 31.3.6 Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD)............................ 1300 31.3.7 Command Start Register (CMDSTRT) .............................................................. 1302 31.3.8 Operation Control Register (OPCR)................................................................... 1304 31.3.9 Command Timeout Control Register (CTOCR) ................................................. 1306 31.3.10 Data Timeout Register (DTOUTR) .................................................................... 1307 31.3.11 Card Status Register (CSTR).............................................................................. 1308 31.3.12 Interrupt Control Registers 0 and 1 (INTCR0, INTCR1) ................................... 1310 31.3.13 Interrupt Status Registers 0 and 1 (INTSTR0, INTSTR1).................................. 1312 31.3.14 Transfer Clock Control Register (CLKON)........................................................ 1316 31.3.15 VDD/Open-Drain Control Register (VDCNT)................................................... 1317 31.3.16 Data Register (DR) ............................................................................................. 1318 31.3.17 FIFO Pointer Clear Register (FIFOCLR) ........................................................... 1318 31.3.18 DMA Control Register (DMACR) ..................................................................... 1319 31.3.19 Interrupt Control Register 2 (INTCR2) .............................................................. 1320 31.3.20 Interrupt Status Register 2 (INTSTR2)............................................................... 1321 31.3.21 Card Switch Register (CSWR) ........................................................................... 1322 31.3.22 Switch Status Register (SWSR).......................................................................... 1323 31.3.23 Chattering Elimination Pulse Setting Register (CHATR) .................................. 1324 31.4 Operation ......................................................................................................................... 1326 31.4.1 Operations in MMC Mode.................................................................................. 1326 31.5 Operations when Using DMAC....................................................................................... 1351 31.5.1 Operation in Read Sequence............................................................................... 1351 31.5.2 Operation in Write Sequence .............................................................................. 1354 31.6 MMCIF Interrupt Sources................................................................................................ 1357 31.7 Procedure to Apply the Card Detection Function ............................................................ 1358
Section 32 PC Card Controller (PCC)............................................................. 1359
32.1 Features............................................................................................................................ 1359 32.1.1 PCMCIA Support ............................................................................................... 1360 32.2 Input/Output Pins............................................................................................................. 1364
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32.3 Register Descriptions ....................................................................................................... 1365 32.3.1 Area 6 Interface Status Register (PCC0ISR) ...................................................... 1366 32.3.2 Area 6 General Control Register (PCC0GCR) ................................................... 1369 32.3.3 Area 6 Card Status Change Register (PCC0CSCR)............................................ 1372 32.3.4 Area 6 Card Status Change Interrupt Enable Register (PCC0CSCIER)............. 1376 32.4 Operation ......................................................................................................................... 1380 32.4.1 PC card Connection Specification (Interface Diagram, Pin Correspondence)........................................................... 1380 32.4.2 PC Card Interface Timing................................................................................... 1384 32.5 Usage Notes ..................................................................................................................... 1389
Section 33 Audio Codec Interface (HAC) .......................................................1391
33.1 Features............................................................................................................................ 1391 33.2 Input/Output Pins ............................................................................................................. 1392 33.3 Register Descriptions ....................................................................................................... 1393 33.3.1 Control and Status Register (HACCR) ............................................................... 1394 33.3.2 Command/Status Address Register (HACCSAR) .............................................. 1396 33.3.3 Command/Status Data Register (HACCSDR).................................................... 1398 33.3.4 PCM Left Channel Register (HACPCML) ......................................................... 1399 33.3.5 PCM Right Channel Register (HACPCMR)....................................................... 1401 33.3.6 TX Interrupt Enable Register (HACTIER) ......................................................... 1402 33.3.7 TX Status Register (HACTSR)........................................................................... 1403 33.3.8 RX Interrupt Enable Register (HACRIER)......................................................... 1405 33.3.9 RX Status Register (HACRSR) .......................................................................... 1406 33.3.10 HAC Control Register (HACACR) .................................................................... 1407 33.4 AC 97 Frame Slot Structure............................................................................................. 1409 33.5 Operation ......................................................................................................................... 1410 33.5.1 Receiver .............................................................................................................. 1410 33.5.2 Transmitter.......................................................................................................... 1411 33.5.3 DMA ................................................................................................................... 1411 33.5.4 Interrupts............................................................................................................. 1411 33.5.5 Initialization Sequence........................................................................................ 1412 33.5.6 Notes ................................................................................................................... 1417 33.5.7 Reference ............................................................................................................ 1417
Section 34 Serial Sound Interface (SSI) ..........................................................1419
34.1 Features............................................................................................................................ 1419 34.2 Input/Output Pins ............................................................................................................. 1421 34.3 Register Descriptions ....................................................................................................... 1422 34.3.1 Control Register (SSICR) ................................................................................... 1424
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34.3.2 Status Register (SSISR) ...................................................................................... 1431 34.3.3 Transmit Data Register (SSITDR)...................................................................... 1436 34.3.4 Receive Data Register (SSIRDR) ....................................................................... 1436 34.4 Operation ......................................................................................................................... 1437 34.4.1 Bus Format ......................................................................................................... 1437 34.4.2 Non-Compressed Modes..................................................................................... 1438 34.4.3 Operation Modes ................................................................................................ 1448 34.4.4 Transmit Operation............................................................................................. 1449 34.4.5 Receive Operation .............................................................................................. 1452 34.4.6 Serial Clock Control ........................................................................................... 1455 34.5 Usage Note....................................................................................................................... 1456 34.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation .......... 1456 34.5.2 Restrictions for Operation in Slave Mode........................................................... 1456
Section 35 USB Host Controller (USBH) ....................................................... 1457
35.1 Features............................................................................................................................ 1457 35.2 Pin Description ................................................................................................................ 1459 35.3 Register Description ........................................................................................................ 1460 35.3.1 HcRevision Register (USBHR) .......................................................................... 1462 35.3.2 HcControl Register (USBHC) ............................................................................ 1463 35.3.3 HcCommandStatus Register (USBHCS) ............................................................ 1465 35.3.4 HcInterruptStatus Register (USBHIS) ................................................................ 1466 35.3.5 HcInterruptEnable Register (USBHIE) .............................................................. 1468 35.3.6 HcInterruptDisable Register (USBHID)............................................................. 1469 35.3.7 HcHCCA Register (USBHHCCA) ..................................................................... 1471 35.3.8 HcPeriodCurrentED Register (USBHPCED) ..................................................... 1471 35.3.9 HcControlHeadED Register (USBHCHED) ...................................................... 1472 35.3.10 HcControlCurrentED Register (USBHCCED) ................................................... 1472 35.3.11 HcBulkHeadED Register (USBHBHED)........................................................... 1473 35.3.12 HcBulkCurrentED Register (USBHBCED) ....................................................... 1473 35.3.13 HcDoneHead Register (USBHDHED) ............................................................... 1474 35.3.14 HcFmInterval Register (USBHFI)...................................................................... 1475 35.3.15 HcFrameRemaining Register (USBHFR)........................................................... 1476 35.3.16 HcFmNumber Register (USBHFN).................................................................... 1477 35.3.17 HcPeriodicStart Register (USBHPS).................................................................. 1478 35.3.18 HcLSThreshold Register (USBHLST) (Not supporting LowSpeed mode) ........ 1479 35.3.19 HcRhDescriptorA Register (USBHRDA) (Only one port is supported by this LSI.)............................................................ 1480 35.3.20 HcRhDescriptorB Register (USBHRDB) (Only one port is supported by this LSI.)............................................................ 1482
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35.3.21 HcRhStatus Register (USBHRS) ........................................................................ 1484 35.3.22 HcRhPortStatus[2] Register (USBHRPS2)......................................................... 1486 35.3.23 ConfigurationControl Register (USBHSC)......................................................... 1489 35.4 Functional Description..................................................................................................... 1491 35.4.1 General Functionality ......................................................................................... 1491 35.5 Connection Example of an External Circuit .................................................................... 1493 35.6 Usage Notes ..................................................................................................................... 1493 35.6.1 External memory that USBH accesses................................................................ 1493 35.6.2 Issuing USB Bus Reset ....................................................................................... 1493
Section 36 USB Function Controller (USBF) .................................................1495
36.1 Features............................................................................................................................ 1495 36.2 Input/Output Pins ............................................................................................................. 1497 36.3 Register Descriptions ....................................................................................................... 1498 36.3.1 Interrupt Flag Register 0 (IFR0) ......................................................................... 1504 36.3.2 Interrupt Flag Register 1 (IFR1) ......................................................................... 1507 36.3.3 Interrupt Flag Register 2 (IFR2) ......................................................................... 1509 36.3.4 Interrupt Flag Register 3 (IFR3) ......................................................................... 1511 36.3.5 Interrupt Flag Register 4 (IFR4) ......................................................................... 1514 36.3.6 Interrupt Select Register 0 (ISR0)....................................................................... 1515 36.3.7 Interrupt Select Register 1 (ISR1)....................................................................... 1516 36.3.8 Interrupt Select Register 2 (ISR2)....................................................................... 1517 36.3.9 Interrupt Select Register 3 (ISR3)....................................................................... 1518 36.3.10 Interrupt Select Register 4 (ISR4)....................................................................... 1519 36.3.11 Interrupt Enable Register 0 (IER0) ..................................................................... 1520 36.3.12 Interrupt Enable Register 1 (IER1) ..................................................................... 1521 36.3.13 Interrupt Enable Register 2 (IER2) ..................................................................... 1522 36.3.14 Interrupt Enable Register 3 (IER3) ..................................................................... 1523 36.3.15 Interrupt Enable Register 4 (IER4) ..................................................................... 1524 36.3.16 EP0i Data Register (EPDR0i)............................................................................. 1525 36.3.17 EP0o Data Register (EPDR0o) ........................................................................... 1526 36.3.18 EP0s Data Register (EPDR0s) ............................................................................ 1527 36.3.19 EP1 Data Register (EPDR1) ............................................................................... 1528 36.3.20 EP2 Data Register (EPDR2) ............................................................................... 1529 36.3.21 EP3 Data Register (EPDR3) ............................................................................... 1530 36.3.22 EP4 Data Register (EPDR4) ............................................................................... 1531 36.3.23 EP5 Data Register (EPDR5) ............................................................................... 1532 36.3.24 EP0o Receive Data Size Register (EPSZ0o) ...................................................... 1533 36.3.25 EP1 Receive Data Size Register (EPSZ1) .......................................................... 1534 36.3.26 EP4 Receive Data Size Register (EPSZ4) .......................................................... 1535
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36.4
36.5 36.6 36.7 36.8
36.9 36.10
36.3.27 Trigger Register (TRG) ...................................................................................... 1536 36.3.28 Data Status Register (DASTS)............................................................................ 1537 36.3.29 FIFO Clear Register 0 (FCLR0) ......................................................................... 1538 36.3.30 FIFO Clear Register 1 (FCLR1) ......................................................................... 1539 36.3.31 DMA Transfer Setting Register (DMA) ............................................................. 1540 36.3.32 Endpoint Stall Register 0 (EPSTL0)................................................................... 1541 36.3.33 Endpoint Stall Register 1 (EPSTL1)................................................................... 1542 36.3.34 Configuration Value Register (CVR) ................................................................. 1543 36.3.35 Time Stamp Register (TSRH/TSRL).................................................................. 1544 36.3.36 Control Register 0 (CTLR0) ............................................................................... 1546 36.3.37 Control Register 1 (CTLR1) ............................................................................... 1548 36.3.38 Endpoint Information Register (EPIR) ............................................................... 1549 36.3.39 Timer Register (TMRH/TMRL) ......................................................................... 1555 36.3.40 Set Time Out Register (STOH/STOL) ............................................................... 1557 Operation ......................................................................................................................... 1559 36.4.1 Cable Connection................................................................................................ 1559 36.4.2 Cable Disconnection ........................................................................................... 1560 36.4.3 EP1 Bulk-Out Transfer (Dual FIFOs)................................................................. 1566 36.4.4 EP2 Bulk-In Transfer (Dual FIFOs) ................................................................... 1567 36.4.5 EP3 Interrupt-In Transfer.................................................................................... 1569 EP4 Isochronous-Out Transfer......................................................................................... 1570 EP5 Isochronous-In Transfer ........................................................................................... 1573 Processing of USB Standard Commands and Class/Vendor Commands ........................ 1576 36.7.1 Processing of Commands Transmitted by Control Transfer............................... 1576 Stall Operations................................................................................................................ 1577 36.8.1 Overview ............................................................................................................ 1577 36.8.2 Forcible Stall by Application .............................................................................. 1577 36.8.3 Automatic Stall by USB Function Controller ..................................................... 1579 Examples of External Circuit........................................................................................... 1581 36.9.1 Example of the Connection between USB Function Controller ......................... 1581 Usage Notes ..................................................................................................................... 1582 36.10.1 Setup Data Reception ......................................................................................... 1582 36.10.2 FIFO Clear.......................................................................................................... 1582 36.10.3 Overreading/Overwriting of Data Register......................................................... 1582 36.10.4 Assigning EP0 Interrupt Sources ........................................................................ 1583 36.10.5 FIFO Clear when DMA Transfer is Set .............................................................. 1583 36.10.6 Note on Using TR Interrupt ................................................................................ 1583
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Section 37 LCD Controller (LCDC)................................................................1585
37.1 Features............................................................................................................................ 1585 37.2 Input/Output Pins ............................................................................................................. 1587 37.3 Register Configuration..................................................................................................... 1588 37.3.1 LCDC Input Clock Register (LDICKR) ............................................................. 1591 37.3.2 LCDC Module Type Register (LDMTR) ........................................................... 1593 37.3.3 LCDC Data Format Register (LDDFR).............................................................. 1596 37.3.4 LCDC Scan Mode Register (LDSMR) ............................................................... 1598 37.3.5 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ......... 1599 37.3.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) ......... 1601 37.3.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ......... 1602 37.3.8 LCDC Palette Control Register (LDPALCR)..................................................... 1603 37.3.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ..................................... 1604 37.3.10 LCDC Horizontal Character Number Register (LDHCNR) ............................... 1605 37.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ....................................... 1606 37.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) ........................... 1607 37.3.13 LCDC Vertical Total Line Number Register (LDVTLNR)................................ 1608 37.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) ........................................... 1609 37.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ..... 1610 37.3.16 LCDC Interrupt Control Register (LDINTR) ..................................................... 1611 37.3.17 LCDC Power Management Mode Register (LDPMMR) ................................... 1614 37.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR) .............................. 1616 37.3.19 LCDC Control Register (LDCNTR)................................................................... 1618 37.3.20 LCDC User Specified Interrupt Control Register (LDUINTR).......................... 1619 37.3.21 LCDC User Specified Interrupt Line Number Register (LDUINTLNR) ........... 1621 37.3.22 LCDC Memory Access Interval Number Register (LDLIRNR) ........................ 1622 37.4 Operation ......................................................................................................................... 1623 37.4.1 LCD Module Sizes which can be Displayed in this LCDC ................................ 1623 37.4.2 Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (SDRAM)............................................................................................. 1625 37.4.3 Color Palette Specification ................................................................................. 1628 37.4.4 Data Format ........................................................................................................ 1629 37.4.5 Setting the Display Resolution............................................................................ 1633 37.4.6 Power-Supply Control Sequence ........................................................................ 1633 37.4.7 Operation for Hardware Rotation ....................................................................... 1638 37.5 Clock and LCD Data Signal Examples............................................................................ 1641 37.6 Usage Notes ..................................................................................................................... 1653 37.6.1 Procedure for Halting Access to Display Data Storage VRAM (DDR-SDRAM in Area 3) .................................................................................. 1653
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37.6.2 Notes on Using NMI Interrupt............................................................................ 1653
Section 38 A/D Converter ............................................................................... 1655
38.1 Features............................................................................................................................ 1655 38.2 Input Pins ......................................................................................................................... 1657 38.3 Register Descriptions....................................................................................................... 1658 38.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................ 1658 38.3.2 A/D Control/Status Registers (ADCSR)............................................................. 1660 38.4 Operation ......................................................................................................................... 1663 38.4.1 Single Mode (MDS1 = 0, MDS0 = 0)................................................................. 1663 38.4.2 Multi Mode (MDS[1:0] = 10)............................................................................. 1664 38.4.3 Scan Mode (MDS1 = 1, MDS0 = 1) ................................................................... 1666 38.4.4 A/D Conversion Time......................................................................................... 1668 38.5 Interrupts.......................................................................................................................... 1668 38.6 Definitions of A/D Conversion Accuracy........................................................................ 1669 38.7 Usage Notes ..................................................................................................................... 1671 38.7.1 Setting Analog Input Voltage ............................................................................. 1671 38.7.2 Processing of Analog Input Pins......................................................................... 1671 38.7.3 Pck0 Clock and Clock Division Ratio Settings .................................................. 1672 38.7.4 A/D Conversion Stop.......................................................................................... 1672
Section 39 D/A Converter (DAC) ................................................................... 1673
39.1 Features............................................................................................................................ 1673 39.2 Input/Output Pins............................................................................................................. 1674 39.3 Register Descriptions....................................................................................................... 1674 39.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................ 1675 39.3.2 D/A Control Register (DACR) ........................................................................... 1676 39.4 Operation ......................................................................................................................... 1677 39.5 Usage Notes ..................................................................................................................... 1678
Section 40 General Purpose I/O (GPIO) ......................................................... 1679
40.1 Features............................................................................................................................ 1679 40.2 Register Descriptions....................................................................................................... 1690 40.2.1 Port A Control Register (PACR) ........................................................................ 1693 40.2.2 Port B Control Register (PBCR)......................................................................... 1695 40.2.3 Port C Control Register (PCCR)......................................................................... 1696 40.2.4 Port D Control Register (PDCR) ........................................................................ 1698 40.2.5 Port E Control Register (PECR) ......................................................................... 1700 40.2.6 Port F Control Register (PFCR).......................................................................... 1701 40.2.7 Port G Control Register (PGCR) ........................................................................ 1703
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40.2.8 Port H Control Register (PHCR) ........................................................................ 1705 40.2.9 Port I Control Register (PICR) ........................................................................... 1707 40.2.10 Port J Control Register (PJCR) ........................................................................... 1709 40.2.11 Port K Control Register (PKCR) ........................................................................ 1711 40.2.12 Port L Control Register (PLCR) ......................................................................... 1713 40.2.13 Port M Control Register (PMCR) ....................................................................... 1715 40.2.14 Port N Control Register (PNCR) ........................................................................ 1717 40.2.15 Port O Control Register (POCR) ........................................................................ 1719 40.2.16 Port A Data Register (PADR)............................................................................. 1721 40.2.17 Port B Data Register (PBDR) ............................................................................. 1722 40.2.18 Port C Data Register (PCDR) ............................................................................. 1723 40.2.19 Port D Data Register (PDDR)............................................................................. 1724 40.2.20 Port E Data Register (PEDR).............................................................................. 1725 40.2.21 Port F Data Register (PFDR) .............................................................................. 1726 40.2.22 Port G Data Register (PGDR)............................................................................. 1727 40.2.23 Port H Data Register (PHDR)............................................................................. 1728 40.2.24 Port I Data Register (PIDR)................................................................................ 1729 40.2.25 Port J Data Register (PJDR) ............................................................................... 1730 40.2.26 Port K Data Register (PKDR)............................................................................. 1731 40.2.27 Port L Data Register (PLDR).............................................................................. 1732 40.2.28 Port M Data Register (PMDR) ........................................................................... 1733 40.2.29 Port N Data Register (PNDR)............................................................................. 1734 40.2.30 Port O Data Register (PODR)............................................................................. 1735 40.2.31 Port I Pull-Up Control Register (PIPUPR) ......................................................... 1736 40.2.32 Port J Pull-Up Control Register (PJPUPR)......................................................... 1737 40.2.33 Port K Pull-Up Control Register (PKPUPR) ...................................................... 1738 40.2.34 Port L Pull-Up Control Register (PLPUPR) ....................................................... 1739 40.2.35 Port M Pull-Up Control Register (PMPUPR)..................................................... 1740 40.2.36 Port N Pull-Up Control Register (PNPUPR) ...................................................... 1742 40.2.37 Port O Pull-Up Control Register (POPUPR) ...................................................... 1743 40.2.38 Input-Pin Pull-Up Control Register (PPUPR)..................................................... 1744 40.2.39 Pin Select Register 0 (PSEL0) ............................................................................ 1745 40.2.40 Pin Select Register 1 (PSEL1) ............................................................................ 1746 40.2.41 Pin Select Register 2 (PSEL2) ............................................................................ 1749 40.2.42 Pin Select Register 3 (PSEL3) ............................................................................ 1752 40.2.43 Pin Select Register 4 (PSEL4) ............................................................................ 1755 40.3 Usage Examples............................................................................................................... 1758 40.3.1 Port Output Function .......................................................................................... 1758 40.3.2 Port Input Function ............................................................................................. 1758 40.3.3 Peripheral Module Function ............................................................................... 1758
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Section 41 User Break Controller (UBC)........................................................ 1759
41.1 Features............................................................................................................................ 1759 41.2 Register Descriptions....................................................................................................... 1761 41.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1) ......................... 1763 41.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1) ......................... 1770 41.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1)............................ 1772 41.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)........... 1774 41.2.5 Match Data Setting Register 1 (CDR1) .............................................................. 1776 41.2.6 Match Data Mask Setting Register 1 (CDMR1) ................................................. 1777 41.2.7 Execution Count Break Register 1 (CETR1)...................................................... 1778 41.2.8 Channel Match Flag Register (CCMFR) ............................................................ 1779 41.2.9 Break Control Register (CBCR) ......................................................................... 1780 41.3 Operation Description...................................................................................................... 1781 41.3.1 Definition of Words Related to Accesses ........................................................... 1781 41.3.2 User Break Operation Sequence ......................................................................... 1782 41.3.3 Instruction Fetch Cycle Break ............................................................................ 1784 41.3.4 Operand Access Cycle Break ............................................................................. 1785 41.3.5 Sequential Break................................................................................................. 1787 41.3.6 Program Counter Value to be Saved................................................................... 1788 41.4 User Break Debugging Support Function ........................................................................ 1789 41.5 User Break Examples....................................................................................................... 1791 41.6 Usage Notes ..................................................................................................................... 1795
Section 42 User Debugging Interface (H-UDI)............................................... 1797
42.1 Features............................................................................................................................ 1797 42.2 Input/Output Pins............................................................................................................. 1799 42.3 Boundary Scan TAP Controllers (IDCODE, EXTEST, SAMPLE/PRELOAD, and BYPASS)......................................................................................................................... 1800 42.4 Register Descriptions....................................................................................................... 1802 42.4.1 Instruction Register (SDIR) ................................................................................ 1803 42.4.2 Interrupt Source Register (SDINT)..................................................................... 1804 42.4.3 Bypass Register (SDBPR) .................................................................................. 1805 42.4.4 Boundary Scan Register (SDBSR) ..................................................................... 1805 42.5 Operation ......................................................................................................................... 1823 42.5.1 TAP Control ....................................................................................................... 1823 42.5.2 H-UDI Reset ....................................................................................................... 1824 42.5.3 H-UDI Interrupt .................................................................................................. 1824 42.6 Usage Notes ..................................................................................................................... 1824
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Section 43 Electrical Characteristics ...............................................................1825
43.1 Absolute Maximum Ratings ............................................................................................ 1825 43.2 Power-On and Power-Off Order ...................................................................................... 1826 43.2.1 Power-On Order.................................................................................................. 1826 43.2.2 Power-Off Order ................................................................................................. 1826 43.2.3 Power-Off and Power-On Order in RTC Power-Supply Backup Mode (Hardware Standby)............................................................................................ 1828 43.2.4 Power-Off and Power-On Order in DDR-SDRAM Power-Supply Backup Mode...................................................................................................... 1828 43.3 DC Characteristics ........................................................................................................... 1829 43.4 AC Characteristics ........................................................................................................... 1833 43.4.1 Clock and Control Signal Timing ....................................................................... 1834 43.4.2 Control Signal Timing ........................................................................................ 1838 43.4.3 Bus Timing ......................................................................................................... 1840 43.4.4 DDRIF Signal Timing ........................................................................................ 1858 43.4.5 INTC Module Signal Timing.............................................................................. 1861 43.4.6 External CPU Interface Read/Write Access Timing........................................... 1863 43.4.7 PCIC Module Signal Timing .............................................................................. 1865 43.4.8 DMAC Module Signal Timing ........................................................................... 1867 43.4.9 TMU Module Signal Timing .............................................................................. 1868 43.4.10 16-bit Timer Pulse Unit (TPU) Timing............................................................... 1869 43.4.11 GETHER Module Signal Timing ....................................................................... 1870 43.4.12 Stream Interface Module Timing........................................................................ 1876 43.4.13 I2C Bus Interface Timing .................................................................................... 1880 43.4.14 SCIF Module Signal Timing............................................................................... 1882 43.4.15 SIOF Module Signal Timing .............................................................................. 1884 43.4.16 SIM Module Signal Timing ................................................................................ 1888 43.4.17 MMCIF Module Signal Timing.......................................................................... 1889 43.4.18 HAC Interface Module Signal Timing................................................................ 1891 43.4.19 SSI Interface Module Signal Timing .................................................................. 1893 43.4.20 USB Module Signal Timing ............................................................................... 1895 43.4.21 LCDC Module Signal Timing ............................................................................ 1896 43.4.22 GPIO Signal Timing ........................................................................................... 1897 43.4.23 H-UDI Module Signal Timing............................................................................ 1898 43.5 A/D, D/A Converter Characteristics ................................................................................ 1900 43.5.1 A/D Converter Characteristics ............................................................................ 1900 43.5.2 D/A Converter Characteristics ............................................................................ 1900 43.6 AC Characteristic Test Conditions................................................................................... 1901 43.7 Change in Delay Time Based on Load Capacitance ........................................................ 1902
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Appendix
A. B. C. D. E. F. G. H. I. J.
....................................................................................................... 1903
CPU Operation Mode Register (CPUOPM) .................................................................... 1903 Instruction Prefetching and Its Side Effects..................................................................... 1905 Speculative Execution for Subroutine Return.................................................................. 1906 List of Mode Control Pins and Schematic Diagram of External Cicuits ......................... 1907 Notes on Board Design .................................................................................................... 1909 Package Dimensions ........................................................................................................ 1912 Pin States ......................................................................................................................... 1913 Handling of Unused Pins ................................................................................................. 1931 Version Registers............................................................................................................. 1943 Heat Radiation ................................................................................................................. 1944 J.1 Heat Resistance Simulation Conditions.............................................................. 1944 J.2 Analysis Results of Heat Resistance Simulation ................................................ 1945
Index
....................................................................................................... 1947
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Figures
Section 1 Overview Figure 1.1 SH7763 Block Diagram .............................................................................................. 13 Figure 1.2 Pin Arrangement.......................................................................................................... 15 Section 2 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Section 4 Figure 4.1 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Programming Model Data Formats ............................................................................................................... 37 CPU Register Configuration in Each Processing Mode .............................................. 41 General Registers ........................................................................................................ 42 Floating-Point Registers .............................................................................................. 44 Relationship between SZ bit and Endian..................................................................... 50 Formats of Byte Data and Word Data in Register ....................................................... 52 Data Formats in Memory............................................................................................. 53 Processing State Transitions........................................................................................ 54 Pipelining Basic Pipelines ............................................................................................................ 79 Instruction Execution Patterns (1) ............................................................................... 81 Instruction Execution Patterns (2) ............................................................................... 82 Instruction Execution Patterns (3) ............................................................................... 83 Instruction Execution Patterns (4) ............................................................................... 84 Instruction Execution Patterns (5) ............................................................................... 85 Instruction Execution Patterns (6) ............................................................................... 86 Instruction Execution Patterns (7) ............................................................................... 87 Instruction Execution Patterns (8) ............................................................................... 88 Instruction Execution Patterns (9) ............................................................................... 89
Section 5 Exception Handling Figure 5.1 Instruction Execution and Exception Handling......................................................... 113 Figure 5.2 Example of General Exception Acceptance Order .................................................... 114 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.7 Figure 6.8 Memory Management Unit (MMU) Role of MMU ............................................................................................................ 139 Virtual Address Space (AT in MMUCR = 0)............................................................ 140 Virtual Address Space (AT in MMUCR = 1)............................................................ 141 P4 Area...................................................................................................................... 143 Physical Address Space............................................................................................. 144 UTLB Configuration ................................................................................................. 156 Relationship between Page Size and Address Format............................................... 158 ITLB Configuration................................................................................................... 159
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Figure 6.9 Flowchart of Memory Access Using UTLB.............................................................. 160 Figure 6.10 Flowchart of Memory Access Using ITLB ............................................................. 161 Figure 6.11 Operation of LDTLB Instruction............................................................................. 164 Figure 6.12 Memory-Mapped ITLB Address Array................................................................... 173 Figure 6.13 Memory-Mapped ITLB Data Array ........................................................................ 174 Figure 6.14 Memory-Mapped UTLB Address Array ................................................................. 176 Figure 6.15 Memory-Mapped UTLB Data Array....................................................................... 177 Figure 6.16 Physical Address Space (32-Bit Address Extended Mode)..................................... 177 Figure 6.17 PMB Configuration ................................................................................................. 179 Figure 6.18 Memory-Mapped PMB Address Array ................................................................... 183 Figure 6.19 Memory-Mapped PMB Data Array......................................................................... 183 Section 7 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Figure 7.6 Figure 7.7 Figure 7.8 Figure 7.9 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Caches Configuration of Operand Cache (OC) ..................................................................... 188 Configuration of Instruction Cache (IC) ................................................................... 189 Configuration of Write-Back Buffer ......................................................................... 201 Configuration of Write-Through Buffer.................................................................... 201 Memory-Mapped IC Address Array ......................................................................... 207 Memory-Mapped IC Data Array ............................................................................... 208 Memory-Mapped OC Address Array........................................................................ 210 Memory-Mapped OC Data Array ............................................................................. 211 Store Queue Configuration........................................................................................ 212 Interrupt Controller (INTC) Block Diagram of INTC............................................................................................ 234 Example of IRL Interrupt Connection....................................................................... 293 On-chip Module Interrupt Priority ............................................................................ 296 Interrupt Operation Flowchart................................................................................... 306 Example of Interrupt Handling Routine .................................................................... 309
Section 10 SuperHyway Bus Bridge (SBR) Figure 10.1 SBR Block Diagram................................................................................................ 313 Figure 10.2 Bus Arbitration by the SBR..................................................................................... 317 Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Local Bus State Controller (LBSC) LBSC Block Diagram ............................................................................................. 321 Correspondence between Virtual Address Space and External Memory Space...... 325 External Memory Space Allocation ........................................................................ 327 Basic Timing of SRAM Interface............................................................................ 366 Example of 32-Bit Data-Width SRAM Connection................................................ 367 Example of 16-Bit Data-Width SRAM Connection................................................ 368 Example of 8-Bit Data-Width SRAM Connection.................................................. 368
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Figure 11.8 SRAM Interface Wait Timing (Software Wait Only) ............................................. 369 Figure 11.9 SRAM Interface Wait Cycle Timing (Wait Cycle Insertion by RDY Signal)......... 370 Figure 11.10 SRAM Interface Wait State Timing (Read-Strobe Negate Timing Setting).......... 372 Figure 11.11 Burst ROM Basic Access Timing ......................................................................... 374 Figure 11.12 Burst ROM Wait Access Timing........................................................................... 374 Figure 11.13 Burst ROM Wait Access Timing........................................................................... 375 Figure 11.14 CExx and DACK Output of ATA Complete Mode in DMA Transfer.................. 377 Figure 11.15 Example of PCMCIA Interface ............................................................................. 380 Figure 11.16 Basic Timing for PCMCIA Memory Card Interface ............................................. 381 Figure 11.17 Wait Timing for PCMCIA Memory Card Interface .............................................. 382 Figure 11.18 Basic Timing for PCMCIA I/O Card Interface ..................................................... 383 Figure 11.19 Wait Timing for PCMCIA I/O Card Interface ...................................................... 384 Figure 11.20 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ............................. 385 Figure 11.21 Example of 32-Bit Data Width MPX Connection ................................................. 387 Figure 11.22 MPX Interface Timing 1 (Single Read Cycle, IW = 0, No External Wait) ........... 387 Figure 11.23 MPX Interface Timing 2 (Single Read, IW = 0, One External Wait Inserted)...... 388 Figure 11.24 MPX Interface Timing 3 (Single Write Cycle, IW = 0, No External Wait) .......... 389 Figure 11.25 MPX Interface Timing 4 (Single Write Cycle, IW = 1, One External Wait Inserted)................................... 390 Figure 11.26 MPX Interface Timing 5 (Burst Read Cycle, IW = 0, No External Wait)............. 391 Figure 11.27 MPX Interface Timing 6 (Burst Read Cycle, IW = 0, External Wait Control) ..... 392 Figure 11.28 MPX Interface Timing 7 (Burst Write Cycle, IW = 0, No External Wait)............ 393 Figure 11.29 MPX Interface Timing 8 (Burst Write Cycle, IW = 1, External Wait Control) .... 394 Figure 11.30 MPX Interface Timing 9 (Burst Read Cycle, IW = 0, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer) ............................. 395 Figure 11.31 MPX Interface Timing 10 (Burst Read Cycle, IW = 0, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)...................... 396 Figure 11.32 MPX Interface Timing 11 (Burst Write Cycle, IW = 0, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer) ............................. 397 Figure 11.33 MPX Interface Timing 12 (Burst Write Cycle, IW = 1, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)...................... 398 Figure 11.34 Example of 32-Bit Data-Width Byte-Control SRAM ........................................... 399 Figure 11.35 Byte-Control SRAM Basic Read Cycle (No Wait) ............................................... 400 Figure 11.36 Byte-Control SRAM Basic Read Cycle (One Internal Wait Cycle)...................... 401 Figure 11.37 Byte-Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) ............................................................. 402 Figure 11.38 Wait Cycles between Access Cycles ..................................................................... 404 Figure 11.39 Arbitration Sequence............................................................................................. 406
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Section 12 Figure 12.1 Figure 12.2 Figure 12.3
DDR-SDRAM Interface (DDRIF) DDRIF Block Diagram ........................................................................................... 410 Data Alignment in DDR-SDRAM and DDRIF....................................................... 414 Relationship between Write Values in SDMR and Output Signals to Memory Pins ........................................................................................................... 428 Figure 12.4 DDR-SDRAM Access............................................................................................. 430 Figure 12.5 Basic DDRIF Timing (1 Burst Read: 1, 2, 4, or 8 Bytes; Without Auto-Precharge) ........................................................................................ 438 Figure 12.6 Basic DDRIF Timing (1 Burst Write: 1, 2, 4, or 8 Bytes; Without Auto-Precharge) ........................................................................................ 439 Figure 12.7 Basic DDRIF Timing (1 Burst Read: 1, 2, 4, or 8 Bytes; With Auto-Precharge)....................................... 440 Figure 12.8 Basic DDRIF Timing (1 Burst Write: 1, 2, 4, or 8 Bytes; With Auto-Precharge)...................................... 441 Figure 12.9 Basic DDRIF Timing (4 Burst Read: 32 Bytes; Without Auto-Precharge)............. 442 Figure 12.10 Basic DDRIF Timing (4 Burst Write: 32 Bytes; Without Auto-Precharge).......... 443 Figure 12.11 Basic DDRIF Timing (Precharge all Banks (PREALL) to Bank Activate (ACT)).................................. 444 Figure 12.12 Basic DDRIF Timing (Mode Register Set (MRS)) ............................................... 445 Figure 12.13 Basic DDRIF Timing (Auto-Refresh (REFA) Enter/Exit to Bank Activate (ACT)) ............................... 446 Figure 12.14 Basic DDRIF Timing (Self-Refresh Entry from IDLE (REFS)/ Self-Refresh Exit (REFSX) to Any Command Input)........................................... 447 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Figure 13.9 PCI Controller (PCIC) PCIC Block Diagram .............................................................................................. 451 SuperHyway Bus to PCI Local Bus Access ............................................................ 530 SuperHyway Bus to PCI Local Bus Address Translation (PCI Memory Space 0)............................................................................................ 531 SuperHyway Bus to PCI Local Bus Address Translation (PCI Memory Space 1)............................................................................................ 532 SuperHyway Bus to PCI Local Bus Address Translation (PCI Memory Space 2)............................................................................................ 532 SuperHyway Bus to PCI Local Bus Address Translation (PCI I/O) ....................... 533 Endian Conversion from SuperHyway Bus to PCI Local bus (Non-Byte Swapping: TBS = 0).............................................................................. 535 Endian Conversion from SuperHyway Bus to PCI Local bus (Byte Swapping: TBS = 1) ...................................................................................... 536 PCI local bus to SuperHyway bus Memory Map .................................................... 537
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Figure 13.10 PCI Local Bus to SuperHyway Bus Address Translation (Local Address Space 0/1) .................................................................................... 539 Figure 13.11 PCI Local Bus to SuperHyway Bus Address Translation (PCIC I/O Space) ........ 540 Figure 13.12 Endian Conversion from PCI Local Bus to SuperHyway bus (Non-Byte Swapping: TBS = 0)............................................................................ 542 Figure 13.13 Endian Conversion from PCI Local Bus to SuperHyway bus (Non-Byte Swapping: TBS = 1)............................................................................ 543 Figure 13.14 Cache Flush/Purge Execution Flow for PCI local Bus to SuperHyway Bus......... 545 Figure 13.15 Address Generation for Type 0 Configuration Access.......................................... 547 Figure 13.16 PCI Local Bus Power Down State Transition ....................................................... 550 Figure 13.17 Master Write Cycle in Host Bus Bridge Mode (Single)........................................ 551 Figure 13.18 Master Read Cycle in Host Bus Bridge Mode (Single)......................................... 552 Figure 13.19 Master Write Cycle in Normal Mode (Burst)........................................................ 553 Figure 13.20 Master Read Cycle in Normal Mode (Burst)......................................................... 554 Figure 13.21 Target Read Cycle in Normal Mode (Single)........................................................ 556 Figure 13.22 Target Write Cycle in Normal Mode (Single)....................................................... 557 Figure 13.23 Target Memory Read Cycle in Host Bus Bridge Mode (Burst) ............................ 558 Figure 13.24 Target Memory Write Cycle in Host Bus Bridge Mode (Burst) ........................... 559 Figure 13.25 Master Write Cycle in Host Bus Bridge Mode (Burst, with stepping) .................. 560 Figure 13.26 Target Memory Read Cycle in Host Bus Bridge Mode (Burst, with stepping)..... 561 Figure 13.27 Timing Example of Device (REQm) Not Executing REQ Negation and FRAME Assertion Simultaneously....................................................................... 562 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Direct Memory Access Controller (DMAC) Block Diagram of DMAC ....................................................................................... 566 Round-Robin Mode................................................................................................. 596 Changes in Channel Priority in Round-Robin Mode............................................... 597 Data Flow of Dual Address Mode........................................................................... 598 Example of DMA Transfer Timing in Dual Address Mode (Source: Ordinary Memory, Destination: Ordinary Memory)................................. 599 Figure 14.6 DMA Transfer Timing Example in Cycle-Steal Normal Mode 1 (DREQ Low Level Detection) ................................................................................ 600 Figure 14.7 DMA Transfer Timing Example in Cycle-Steal Normal Mode 2 (DREQ Low Level Detection) ................................................................................ 601 Figure 14.8 Example of DMA Transfer Timing in Cycle Steal Intermittent Mode (DREQ Low Level Detection) ................................................................................ 601 Figure 14.9 DMA Transfer Timing Example in Burst Mode (DREQ Low Level Detection) .... 602 Figure 14.10 Bus State when Multiple Channels are Operating ................................................. 606 Figure 14.11 DMA Transfer Flowchart ...................................................................................... 607 Figure 14.12 Reload Mode Transfer........................................................................................... 609 Figure 14.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 610
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Figure 14.14 Figure 14.15 Figure 14.16 Figure 14.17 Figure 14.18 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Figure 17.6
Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 610 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 611 Example of DREQ Input Detection in Burst Mode Level Detection .................... 611 DMA Transfer End Signal (Cycle Steal Mode Level Detection) .......................... 612 Example of BSC Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)............................... 613 External CPU Interface (EXCPU) EXCPU Block Diagram .......................................................................................... 621 External CPU Access (Single Access) .................................................................... 630 External CPU Access (Burst Access)...................................................................... 631 Configuration of Connection with External CPU.................................................... 632
Clock Pulse Generator (CPG) Block Diagram of CPG ........................................................................................... 634 Notes on Using Crystal Resonator .......................................................................... 642 Notes on Using PLL or DLL Oscillator Circuit ...................................................... 643
Watchdog Timer and Reset (WDT) System Block Diagram............................................................................................ 646 WDT Counting Up Operation ................................................................................. 657 STATUS Output during Power-on.......................................................................... 660 STATUS Output by Reset input during Normal Operation .................................... 661 STATUS Output by Reset input during Sleep Mode .............................................. 661 STATUS Output by Watchdog timer overflow Power-On Reset during Normal Operation.................................................................................................... 662 Figure 17.7 STATUS Output by Watchdog timer overflow Power-On Reset during Sleep Mode .................................................................................................. 663 Figure 17.8 STATUS Output by Watchdog timer overflow Manual Reset during Normal Operation................................................................................................................. 664 Figure 17.9 STATUS Output by Watchdog timer overflow Manual Reset during Sleep Mode ....................................................................................................................... 665 Section 18 Power-Down Mode Figure 18.1 DDR-SDRAM Interface Operation when Turning System Power Supply On/Off ..................................................................................................................... 682 Figure 18.2 Sequence for Turning Off System Power Supply after Entering Self-Refresh Mode ....................................................................................................................... 683 Figure 18.3 Sequence for Turning VDD Power Supply (1.2 V) On/Off .................................... 685 Figure 18.4 STATUS Output when an Interrupt Occurs in Sleep Mode .................................... 685
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Section 19 Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Figure 19.5 Figure 19.6 Figure 19.7
Timer Unit (TMU) Block Diagram of TMU .......................................................................................... 688 Example of Count Operation Setting Procedure ..................................................... 700 TCNT Auto-Reload Operation ................................................................................ 701 Count Timing when Operating on Internal Clock ................................................... 701 Count Timing when Operating on External Clock .................................................. 702 Count Timing when Operating on on-chip RTC output Clock................................ 702 Operation Timing when Using Input Capture Function .......................................... 703
Section 20 16-Bit Timer Pulse Unit (TPU) Figure 20.1 Block Diagram of TPU............................................................................................ 709 Figure 20.2 Example of Counter Operation Setting Procedure .................................................. 730 Figure 20.3 Free-Running Counter Operation ............................................................................ 731 Figure 20.4 Periodic Counter Operation..................................................................................... 732 Figure 20.5 Example of Setting Procedure for Waveform Output by Compare Match.............. 732 Figure 20.6 Example of 0 Output/1 Output Operation ............................................................... 733 Figure 20.7 Example of Toggle Output Operation ..................................................................... 733 Figure 20.8 Compare Match Buffer Operation........................................................................... 734 Figure 20.9 Example of Buffer Operation Setting Procedure..................................................... 735 Figure 20.10 Example of Buffer Operation ................................................................................ 736 Figure 20.11 Example of PWM Mode Setting Procedure .......................................................... 738 Figure 20.12 Example of PWM Mode Operation (1) ................................................................. 739 Figure 20.13 Examples of PWM Mode Operation (2)................................................................ 739 Figure 20.14 Example of Phase Counting Mode Setting Procedure........................................... 741 Figure 20.15 Example of Phase Counting Mode 1 Operation .................................................... 742 Figure 20.16 Example of Phase Counting Mode 2 Operation .................................................... 743 Figure 20.17 Example of Phase Counting Mode 3 Operation .................................................... 744 Figure 20.18 Example of Phase Counting Mode 4 Operation .................................................... 745 Figure 20.19 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 746 Section 21 Figure 21.1 Figure 21.2 Figure 21.3 Figure 21.4 Section 22 Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Figure 22.5 Compare Match Timer (CMT) Block Diagram of CMT .......................................................................................... 748 Counter Operation (One-Shot Operation) ............................................................... 755 Counter Operation (Free-Running Operation)......................................................... 756 CMF Set Timing...................................................................................................... 757 Realtime Clock (RTC) Block Diagram of RTC ........................................................................................... 760 Examples of Time Setting Procedures..................................................................... 778 Examples of Time Reading Procedures................................................................... 779 Example of Use of Alarm Function......................................................................... 780 Example of Crystal Oscillator Circuit Connection .................................................. 782
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Section 23 Figure 23.1 Figure 23.2 Figure 23.3 Figure 23.4 Figure 23.5 Figure 23.6 Figure 23.7
Gigabit Ethernet Controller (GETHER) Configuration of GETHER ..................................................................................... 784 GETHER Data Path and Various Settings .............................................................. 938 Relationship between Transmit Descriptor and Transmit Buffer............................ 940 Relationship between Receive Descriptor and Receive Buffer ............................... 946 Relationship between Transmit Descriptor and Transmit Buffer............................ 952 Relationship between Receive Descriptor and Receive Buffer ............................... 953 Relationship between Transmit/Receive Descriptor and Descriptor Pointing Registers.................................................................................................................. 955 Figure 23.8 Sample Transmission Flowchart (Single-Frame/Two-Description)........................ 958 Figure 23.9 E-MAC Transmitter State Transitions..................................................................... 960 Figure 23.10 E-MAC Receiver State Transitions ....................................................................... 963 Figure 23.11 Sample Reception Flowchart (Single-Frame/Two-Descriptor)............................. 965 Figure 23.12 E-DMAC Operation after Transmit Error ............................................................. 971 Figure 23.13 E-DMAC Operation after Receive Error............................................................... 972 Figure 23.14 Padding Insertion in Receive Data ........................................................................ 973 Figure 23.15 Outlines of Qtag Additional Functions.................................................................. 982 Figure 23.16 Comparison of Normal Ethernet Frame and IEEE802.1Q Frame (with Qtag)...... 983 Figure 23.17 MII Frame Transmit Timing (Normal Transmission) ........................................... 984 Figure 23.18 MII Frame Transmit Timing (Collision) ............................................................... 984 Figure 23.19 MII Frame Transmit Timing (Transmit Error) ...................................................... 985 Figure 23.20 MII Frame Receive Timing (Normal Reception) .................................................. 985 Figure 23.21 MII Frame Receive Timing (Reception Error (1)) ................................................ 985 Figure 23.22 MII Fame Receive Timing (Reception Error (2)).................................................. 985 Figure 23.23 GMII/MII Fame Receive Timing (Normal Reception) ......................................... 986 Figure 23.24 GMII/MII Fame Receive Timing (with Carrier Extension) .................................. 986 Figure 23.25 GMII/MII Fame Receive Timing (Burst Reception)............................................. 986 Figure 23.26 GMII/MII Fame Receive Timing (Reception Error) ............................................. 987 Figure 23.27 GMII/MII Fame Receive Timing (Error with Carrier Extension) ......................... 987 Figure 23.28 GMII/MII Fame Receive Timing (False Carrier Indication)................................. 987 Figure 23.29 RMII Fame Receive Timing (Normal 100-Mbps Reception) ............................... 988 Figure 23.30 RMII Fame Receive Timing (100-Mbps Reception with Illegal Carrier Detected)............................................ 988 Figure 23.31 RMII Fame Transmit Timing (Normal 100-Mbps Transmission)......................... 988 Figure 23.32 MII Management Frame Format ........................................................................... 989 Figure 23.33 1-Bit Data Write Flowchart................................................................................... 990 Figure 23.34 Bus Release Flowchart (TA in Read in Figure 23.33)........................................... 990 Figure 23.35 1-Bit Data Read Flowchart.................................................................................... 991 Figure 23.36 Independent Bus Release Flowchart (IDLE in Write in Figure 23.33) ................. 991 Figure 23.37 MII-RMll Conversion Circuit ............................................................................... 992
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Figure 23.38 Data Subject to Checksum Calculation ................................................................. 993 Section 25 Stream Interface (STIF) Figure 25.1 Block Diagram of STIF ........................................................................................... 998 Figure 25.2 Transmit/Receive Data Structure in External Memory (with 16-Byte Work Area) .................................................................................... 1015 Figure 25.3 Clock Valid Reception Timing.............................................................................. 1017 Figure 25.4 Strobe Reception Timing....................................................................................... 1019 Figure 25.5 Clock Valid Transmission Timing ........................................................................ 1021 Figure 25.6 Strobe Transmission Timing ................................................................................. 1023 Section 26 I2C Bus Interface (IIC) Figure 26.1 Block Diagram for I2C Bus Interface .................................................................... 1025 Figure 26.2 I2C Bus Timing...................................................................................................... 1046 Figure 26.3 Master Data Transmit Format ............................................................................... 1047 Figure 26.4 Master Data Receive Format ................................................................................. 1047 Figure 26.5 Combination Transfer Format of Master Transfer ................................................ 1048 Figure 26.6 10-Bit Address Data Transmit Format .................................................................. 1048 Figure 26.7 10-Bit Address Data Receive Format.................................................................... 1049 Figure 26.8 10-Bit Address Transmit/Receive Combined Format ........................................... 1049 Figure 26.9 Data Transmit Mode Operation Timing ................................................................ 1051 Figure 26.10 Data Receive Mode Operation Timing................................................................ 1053 Section 27 Figure 27.1 Figure 27.2 Figure 27.3 Figure 27.4 Figure 27.5 Figure 27.6 Figure 27.7 Serial Communication Interface with FIFO (SCIF) Block Diagram of SCIF......................................................................................... 1061 SCIFn_RTS Pin (n = 0, 1) ..................................................................................... 1062 SCIFn_CTS Pin (n = 0, 1) ..................................................................................... 1063 SCIFn_SCK Pin (n = 0, 1)..................................................................................... 1064 SCIFn_TXD Pin (n = 0, 1) .................................................................................... 1064 SCIFn_RXD Pin (n = 0, 1).................................................................................... 1065 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, and Two Stop Bits) ......................................... 1094 Figure 27.8 Sample SCIF Initialization Flowchart ................................................................... 1097 Figure 27.9 Sample Serial Transmission Flowchart ................................................................. 1098 Figure 27.10 Sample SCIF Transmission Operation (Example with 8-Bit Data, Parity, One Stop Bit)................................................ 1100 Figure 27.11 Sample Operation Using Modem Control (SCIF_CTS)...................................... 1100 Figure 27.12 Sample Serial Reception Flowchart (1)............................................................... 1101 Figure 27.12 Sample Serial Reception Flowchart (2)............................................................... 1102 Figure 27.13 Sample SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit)................................................ 1103
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Figure 27.14 Sample Operation Using Modem Control (SCIF0_RTS) (Only in Channel 0) ............................................................................................ 1104 Figure 27.15 Data Format in Clocked Synchronous Communication ...................................... 1104 Figure 27.16 Sample SCIF Initialization Flowchart ................................................................. 1106 Figure 27.17 Sample Serial Transmission Flowchart ............................................................... 1107 Figure 27.18 Sample SCIF Transmission Operation in Clocked Synchronous Mode.............. 1108 Figure 27.19 Sample Serial Reception Flowchart (1)............................................................... 1109 Figure 27.19 Sample Serial Reception Flowchart (2)............................................................... 1110 Figure 27.20 Sample SCIF Reception Operation in Clocked Synchronous Mode ................... 1111 Figure 27.21 Sample Simultaneous Serial Transmission and Reception Flowchart................. 1112 Figure 27.22 Receive Data Sampling Timing in Asynchronous Mode .................................... 1116 Figure 27.23 Example of Synchronization Clock Transfer by DMAC .................................... 1117 Section 28 Figure 28.1 Figure 28.2 Figure 28.3 Figure 28.4 Figure 28.5 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA) Block Diagram of SCIF/IrDA ............................................................................... 1121 SCIF2_SCK Pin .................................................................................................... 1122 SCIF2_TXD Pin.................................................................................................... 1122 SCIF2_RXD Pin.................................................................................................... 1123 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, and Two Stop Bits) ......................................... 1155 Figure 28.6 Sample SCIF Initialization Flowchart ................................................................... 1158 Figure 28.7 Sample Serial Transmission Flowchart ................................................................. 1159 Figure 28.8 Sample SCIF Transmission Operation (Example with 8-Bit Data, Parity, One Stop Bit) .................................................. 1161 Figure 28.9 Sample Serial Reception Flowchart (1)................................................................. 1162 Figure 28.10 Sample Serial Reception Flowchart (2)............................................................... 1163 Figure 28.11 Sample SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit)................................................ 1165 Figure 28.12 Data Format in Clocked Synchronous Communication ...................................... 1165 Figure 28.13 Sample SCIF Initialization Flowchart ................................................................. 1167 Figure 28.14 Sample Serial Transmission Flowchart ............................................................... 1168 Figure 28.15 Sample SCIF Transmission Operation in Clocked Synchronous Mode.............. 1169 Figure 28.16 Sample Serial Reception Flowchart (1)............................................................... 1170 Figure 28.17 Sample Serial Reception Flowchart (2)............................................................... 1171 Figure 28.18 Sample SCIF Reception Operation in Clocked Synchronous Mode ................... 1172 Figure 28.19 Sample Simultaneous Serial Transmission and Reception Flowchart................. 1173 Figure 28.20 Receive Data Sampling Timing in Asynchronous Mode .................................... 1177 Figure 28.21 Infrared Communication Data Format ................................................................ 1179 Figure 28.22 Block Diagram of Infrared Data Communication Interface ................................ 1180 Figure 28.23 BRG Block Diagram ........................................................................................... 1181
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Section 29 Serial I/O with FIFO (SIOF) Figure 29.1 Block Diagram of SIOF ........................................................................................ 1186 Figure 29.2 Serial Clock Supply............................................................................................... 1217 Figure 29.3 Serial Data Synchronization Timing ..................................................................... 1219 Figure 29.4 SIOF Transmit/Receive Timing ............................................................................ 1220 Figure 29.5 Transmit/Receive Data Bit Alignment .................................................................. 1223 Figure 29.6 Control Data Bit Alignment .................................................................................. 1224 Figure 29.7 Control Data Interface (Slot Position) ................................................................... 1226 Figure 29.8 Control Data Interface (Secondary FS) ................................................................. 1227 Figure 29.9 Example of Transmit Operation in Master Mode.................................................. 1229 Figure 29.10 Example of Receive Operation in Master Mode ................................................. 1230 Figure 29.11 Example of Transmit Operation in Slave Mode .................................................. 1231 Figure 29.12 Example of Receive Operation in Slave Mode.................................................... 1232 Figure 29.13 Transmit and Receive Timing (8-Bit Monaural Data (1))................................... 1236 Figure 29.14 Transmit and Receive Timing (8-Bit Monaural Data (2))................................... 1237 Figure 29.15 Transmit and Receive Timing (16-Bit Monaural Data)....................................... 1237 Figure 29.16 Transmit and Receive Timing (16-Bit Stereo Data (1)) ...................................... 1238 Figure 29.17 Transmit and Receive Timing (16-Bit Stereo Data (2)) ...................................... 1238 Figure 29.18 Transmit and Receive Timing (16-Bit Stereo Data (3)) ...................................... 1239 Figure 29.19 Transmit and Receive Timing (16-Bit Stereo Data (4)) ...................................... 1239 Figure 29.20 Transmit and Receive Timing (16-Bit Stereo Data)............................................ 1240 Section 30 Figure 30.1 Figure 30.2 Figure 30.3 Figure 30.4 Figure 30.5 Figure 30.6 Figure 30.7 Figure 30.8 Figure 30.9 SIM Card Module (SIM) Smart Card Interface ............................................................................................. 1242 Data Format Used by Smart Card Interface .......................................................... 1266 Examples of Start Character Waveforms .............................................................. 1269 Example of Initialization Flow .............................................................................. 1271 Example of Transmit Processing........................................................................... 1273 Example of Receive Processing ............................................................................ 1275 Receive Data Sampling Timing in Smart Card Mode ........................................... 1278 Retransmission when Smart Card Interface is in Receive Mode........................... 1279 Retransmit Standby Mode (Clock Stopped) when Smart Card Interface is in Transmit Mode ...................................................................................................... 1280 Figure 30.10 Procedure for Stopping Clock and Restarting ..................................................... 1281 Figure 30.11 Example of Pin Connections in Smart Card Interface......................................... 1282 Figure 30.12 TEIE Set Timing ................................................................................................. 1283 Section 31 Multimedia Card Interface (MMCIF) Figure 31.1 MMCIF Block Diagram ........................................................................................ 1286 Figure 31.2 Example of Command Sequence for Commands Not Requiring Command Response ............................................................................................................... 1328
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Figure 31.3 Example of Operational Flow for Commands Not Requiring Command Response.............................................................................................. 1329 Figure 31.4 Example of Command Sequence for Commands without Data Transfer (No Data Busy State) ............................................................................................ 1330 Figure 31.5 Example of Command Sequence for Commands without Data Transfer (with Data Busy State) .......................................................................................... 1331 Figure 31.6 Example of Operational Flow for Commands without Data Transfer................... 1332 Figure 31.7 Example of Command Sequence for Commands with Read Data (Block Size FIFO Size) ...................................................................................... 1334 Figure 31.8 Example of Command Sequence for Commands with Read Data (Block Size > FIFO Size) ...................................................................................... 1335 Figure 31.9 Example of Command Sequence for Commands with Read Data (Multiblock Transfer)............................................................................................ 1336 Figure 31.10 Example of Operational Flow for Commands with Read Data (Single Block Transfer)....................................................................................... 1337 Figure 31.11 (1) Example of Operational Flow for Commands with Read Data (Open-ended Multiblock Transfer)................................................................ 1338 Figure 31.11 (2) Example of Operational Flow for Commands with Read Data (Open-ended Multiblock Transfer)................................................................ 1339 Figure 31.12 (1) Example of Operational Flow for Commands with Read Data (Pre-defined Multiblock Transfer) ................................................................ 1340 Figure 31.12 (2) Example of Operational Flow for Commands with Read Data (Pre-defined Multiblock Transfer) ................................................................ 1341 Figure 31.13 Example of Command Sequence for Commands with Write Data (Block Size FIFO Size).................................................................................... 1343 Figure 31.14 Example of Command Sequence for Commands with Write Data (Block Size > FIFO Size).................................................................................... 1344 Figure 31.15 Example of Command Sequence for Commands with Write Data (Multiblock Transfer).......................................................................................... 1345 Figure 31.16 Example of Operational Flow for Commands with Write Data (Single Block Transfer)....................................................................................... 1346 Figure 31.17 (1) Example of Operational Flow for Commands with Write Data (Open-ended Multiblock Transfer)................................................................ 1347 Figure 31.17 (2) Example of Operational Flow for Commands with Write Data (Open-ended Multiblock Transfer)................................................................ 1348 Figure 31.18 (1) Example of Operational Flow for Commands with Write Data (Pre-defined Multiblock Transfer) ................................................................ 1349 Figure 31.18 (2) Example of Operational Flow for Commands with Write Data (Pre-defined Multiblock Transfer) ................................................................ 1350
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Figure 31.19 (1) Example of Operational Flow for Auto-mode Pre-defined Multiblock Read Transfer ................................................................................................ 1352 Figure 31.19 (2) Example of Operational Flow for Auto-mode Pre-defined Multiblock Read Transfer ................................................................................................ 1353 Figure 31.20 (1) Example of Operational Flow for Auto-mode Pre-defined Multiblock Write Transfer ............................................................................................... 1355 Figure 31.20 (2) Example of Operational Flow for Auto-mode Pre-defined Multiblock Write Transfer ............................................................................................... 1356 Figure 31.21 Operation Flow to Apply the Card Identification Function................................. 1358 Section 32 Figure 32.1 Figure 32.2 Figure 32.3 Figure 32.4 Figure 32.5 Figure 32.6 Figure 32.7 Figure 32.8 Figure 32.9 Section 33 Figure 33.1 Figure 33.2 Figure 33.3 Figure 33.4 Figure 33.5 Figure 33.6 Figure 33.7 Section 34 Figure 34.1 Figure 34.2 Figure 34.3 Figure 34.4 Figure 34.5 Figure 34.6 Figure 34.7 Figure 34.8 PC Card Controller (PCC) PC Card Controller Block Diagram....................................................................... 1360 Continuous 32-Mbyte Area Mode......................................................................... 1362 Continuous 16-Mbyte Area Mode (Area 6)........................................................... 1363 SH7763 Interface................................................................................................... 1380 PCMCIA Memory Card Interface Basic Timing................................................... 1384 PCMCIA Memory Card Interface Wait Timing.................................................... 1385 PCMCIA I/O Card Interface Basic Timing ........................................................... 1386 PCMCIA I/O Card Interface Wait Timing ............................................................ 1387 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ............................. 1388 Audio Codec Interface (HAC) Block Diagram ...................................................................................................... 1392 AC97 Frame Slot Structure ................................................................................... 1409 Initialization Sequence .......................................................................................... 1412 Sample Flowchart for Off-Chip Codec Register Write ......................................... 1413 Sample Flowchart for Off-Chip Codec Register Read (1) .................................... 1414 Sample Flowchart for Off-Chip Codec Register Read (2) .................................... 1415 Sample Flowchart for Off-Chip Codec Register Read (3) .................................... 1416
Serial Sound Interface (SSI) Block Diagram of SSI Module .............................................................................. 1420 Philips Format (with no Padding).......................................................................... 1439 Philips Format (with Padding)............................................................................... 1439 Sony Format (with Serial Data First, Followed by Padding Bits) ......................... 1440 Matsushita Format (with Padding Bits First, Followed by Serial Data)................ 1440 Multichannel Format (2 Channels, No Padding)................................................... 1442 Multichannel Format (3 Channels with High Padding)......................................... 1442 Multichannel Format (4 Channels, with Padding Bits First, Followed by Serial Data, with Padding)..................................................................................... 1443 Figure 34.9 Basic Sample Format (Transmit Mode with Example System/ Data Word Length)................................................................................................ 1444
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Figure 34.10 Figure 34.11 Figure 34.12 Figure 34.13 Figure 34.14 Figure 34.15 Figure 34.16 Figure 34.17 Figure 34.18 Figure 34.19 Figure 34.20 Figure 34.21 Figure 34.22
Inverted Clock ..................................................................................................... 1445 Inverted Word Select........................................................................................... 1445 Inverted Padding Polarity.................................................................................... 1445 Padding Bits First, Followed by Serial Data, with Delay.................................... 1446 Padding Bits First, Followed by Serial Data, without Delay............................... 1446 Serial Data First, Followed by Padding Bits, without Delay............................... 1446 Parallel Right Aligned with Delay ...................................................................... 1447 Mute Enabled ...................................................................................................... 1447 Transition Diagram between Operation Modes................................................... 1448 Transmission Using DMA Controller ................................................................. 1450 Transmission using Interrupt Data Flow Control ................................................ 1451 Reception using DMA Controller ....................................................................... 1453 Reception using Interrupt Data Flow Control ..................................................... 1454
Section 35 USB Host Controller (USBH) Figure 35.1 Block Diagram of USBH ...................................................................................... 1458 Figure 35.2 Connection Example of External Circuit .............................................................. 1493 Section 36 USB Function Controller (USBF) Figure 36.1 Block Diagram of USBF ....................................................................................... 1496 Figure 36.2 Example of Endpoint Configuration ..................................................................... 1554 Figure 36.3 Cable Connection Operation ................................................................................. 1559 Figure 36.4 Cable Disconnection Operation............................................................................. 1560 Figure 36.5 Setup Stage Operation ........................................................................................... 1561 Figure 36.6 Data Stage (Control-In) Operation ........................................................................ 1562 Figure 36.7 Data Stage (Control-Out) Operation ..................................................................... 1563 Figure 36.8 Status Stage (Control-In) Operation...................................................................... 1564 Figure 36.9 Status Stage (Control-Out) Operation ................................................................... 1565 Figure 36.10 EP1 Bulk-Out Transfer Operation....................................................................... 1566 Figure 36.11 EP2 Bulk-In Transfer Operation ......................................................................... 1567 Figure 36.12 EP3 Interrupt-In Transfer Operation ................................................................... 1569 Figure 36.13 EP4 Isochronous-Out Transfer Operation (SOF is Normal) ............................... 1570 Figure 36.14 EP4 Isochronous-Out Transfer Operation (SOF is Broken)................................ 1571 Figure 36.15 EP5 Isochronous-In Transfer Operation (SOF is Normal) .................................. 1573 Figure 36.16 EP5 Isochronous-In Transfer Operation (SOF in Broken) .................................. 1574 Figure 36.17 Forcible Stall by Application .............................................................................. 1578 Figure 36.18 Automatic Stall by USB Function Controller...................................................... 1580 Figure 36.19 Example of Transceiver Connection for USB function Controller ..................... 1581 Figure 36.20 Set Timing of TR Interrupt Flag.......................................................................... 1584
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Section 37 LCD Controller (LCDC) Figure 37.1 LCDC Block Diagram........................................................................................... 1586 Figure 37.2 Valid Display and the Retrace Period.................................................................... 1624 Figure 37.3 Color-Palette Data Format..................................................................................... 1628 Figure 37.4 Power-Supply Control Sequence and States of the LCD Module ......................... 1634 Figure 37.5 Power-Supply Control Sequence and States of the LCD Module ......................... 1634 Figure 37.6 Power-Supply Control Sequence and States of the LCD Module ......................... 1635 Figure 37.7 Power-Supply Control Sequence and States of the LCD Module ......................... 1635 Figure 37.8 Operation for Hardware Rotation (Normal Mode) ................................................ 1639 Figure 37.9 Operation for Hardware Rotation (Rotation Mode) .............................................. 1640 Figure 37.10 Clock and LCD Data Signal Example ................................................................. 1641 Figure 37.11 Clock and LCD Data Signal Example (STN Monochrome 8-Bit Data Bus Module)...................................................... 1641 Figure 37.12 Clock and LCD Data Signal Example (STN Color 4-Bit Data Bus Module)...... 1642 Figure 37.13 Clock and LCD Data Signal Example (STN Color 8-Bit Data Bus Module)...... 1642 Figure 37.14 Clock and LCD Data Signal Example (STN Color 12-Bit Data Bus Module).... 1643 Figure 37.15 Clock and LCD Data Signal Example (STN Color 16-Bit Data Bus Module).... 1644 Figure 37.16 Clock and LCD Data Signal Example (DSTN Monochrome 8-Bit Data Bus Module)................................................... 1645 Figure 37.17 Clock and LCD Data Signal Example (DSTN Monochrome 16-Bit Data Bus Module)................................................. 1646 Figure 37.18 Clock and LCD Data Signal Example (DSTN Color 8-Bit Data Bus Module) ............................................................... 1647 Figure 37.19 Clock and LCD Data Signal Example (DSTN Color 12-Bit Data Bus Module) ............................................................. 1648 Figure 37.20 Clock and LCD Data Signal Example (DSTN Color 16-Bit Data Bus Module) ............................................................. 1649 Figure 37.21 Clock and LCD Data Signal Example (TFT Color 16-Bit Data Bus Module) .... 1650 Figure 37.22 Clock and LCD Data Signal Example (8-Bit Interface Color 640 x 480) ........... 1651 Figure 37.23 Clock and LCD Data Signal Example (16-Bit Interface Color 640 x 480) ......... 1652 Section 38 Figure 38.1 Figure 38.2 Figure 38.3 A/D Converter Block Diagram of A/D Converter ......................................................................... 1656 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) .......... 1664 Example of A/D Converter Operation (Multi Mode, Three Channels AN0 to AN2 Selected) ......................................... 1665 Figure 38.4 Example of A/D Converter Operation (Scan Mode, Three Channels AN0 to AN2 Selected) ....................................................................................................... 1667 Figure 38.5 Definitions of A/D Conversion Accuracy ............................................................. 1670 Figure 38.6 Example of Analog Input Pin Protection Circuit................................................... 1671
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Section 39 D/A Converter (DAC) Figure 39.1 Block Diagram of D/A Converter ......................................................................... 1673 Figure 39.2 D/A Converter Operation Example ....................................................................... 1677 Section 41 User Break Controller (UBC) Figure 41.1 Block Diagram of UBC......................................................................................... 1760 Figure 41.2 Flowchart of User Break Debugging Support Function ........................................ 1790 Section 42 Figure 42.1 Figure 42.2 Figure 42.3 Figure 42.4 User Debugging Interface (H-UDI) H-UDI Block Diagram .......................................................................................... 1798 Sequence for switching from Boundary-Scan TAP Controller to H-UDI............. 1801 TAP Controller State Transitions .......................................................................... 1823 H-UDI Reset.......................................................................................................... 1824
Section 43 Electrical Characteristics Figure 43.1 Power-On and Power-Off Timing ......................................................................... 1827 Figure 43.2 EXTAL Clock Input Timing ................................................................................. 1835 Figure 43.3 CLKOUT Clock Output Timing (1)...................................................................... 1835 Figure 43.4 CLKOUT Clock Output Timing (2)...................................................................... 1836 Figure 43.5 Power-On Oscillation Settling Time ..................................................................... 1836 Figure 43.6 PLL Synchronization Settling Time ...................................................................... 1837 Figure 43.7 Oscillation Settling Time on Return from Standby NMI or IRQ .......................... 1837 Figure 43.8 Reset Input Timing................................................................................................ 1837 Figure 43.9 Control Signal Timing........................................................................................... 1838 Figure 43.10 Pin Drive Timing in Standby Mode .................................................................... 1839 Figure 43.11 SRAM Bus Cycle: Basic Bus Cycle (No Wait) .................................................. 1841 Figure 43.12 SRAM Bus Cycle: Basic Bus Cycle (One Wait only by Software) .................... 1842 Figure 43.13 SRAM Bus Cycle: Basic Bus Cycle (One Wait by Software + One Wait by RDY, RDY Signal is Synchronous Input) ..................................... 1843 Figure 43.14 SRAM Bus Cycle: Basic Bus Cycle (No Wait, No Address Setup/ Hold Time Insertion, RDS = 1, RDH = 0, WTS = 1, WTH = 1) ........................ 1844 Figure 43.15 Burst ROM Bus Cycle (No Wait) ....................................................................... 1845 Figure 43.16 Burst ROM Bus Cycle (1st Data: One Wait by Software + One Wait by RDY; 2nd/3rd/4th Data: One Wait only by software) .................. 1846 Figure 43.17 Burst ROM Bus Cycle (No Wait, No Address Setup/Hold Time Insertion, RDS = 1, RDH = 0) ............................................................................................ 1847 Figure 43.18 Burst ROM Bus Cycle (One Wait by Software + One Wait by RDY) ............... 1848 Figure 43.19 PCMCIA Memory Bus Cycle ............................................................................. 1849 Figure 43.20 PCMCIA I/O Bus Cycle...................................................................................... 1850 Figure 43.21 PCMCIA I/O Bus Cycle (TEDA/TEDB = 1, TEHA/TEHB = 1, IW/PCIW = 1, Dynamic Bus Sizing).................................................................. 1851 Figure 43.22 MPX Basic Bus Cycle: Read............................................................................... 1852
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Figure 43.23 Figure 43.24 Figure 43.25 Figure 43.26 Figure 43.27 Figure 43.28 Figure 43.29 Figure 43.30 Figure 43.31 Figure 43.32 Figure 43.33 Figure 43.34 Figure 46.35 Figure 43.36 Figure 43.37 Figure 43.38 Figure 43.39 Figure 43.40 Figure 43.41 Figure 43.42 Figure 43.43 Figure 43.44 Figure 43.45 Figure 43.46 Figure 43.47 Figure 43.48 Figure 43.49 Figure 43.50 Figure 43.51 Figure 43.52 Figure 43.53 Figure 43.54 Figure 43.55 Figure 43.56 Figure 43.57 Figure 43.58 Figure 43.59 Figure 43.60
MPX Basic Bus Cycle: Write.............................................................................. 1853 MPX Bus Cycle: Burst Read............................................................................... 1854 MPX Bus Cycle: Burst Write .............................................................................. 1855 Byte Control SRAM Bus Cycle .......................................................................... 1856 Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, No Address Setup/Hold Time Insertion, RDS = 1, RDH = 0) ................................................ 1857 DDRIF MCLK Output Timing............................................................................ 1859 Read Timing of DDR-SDRAM (2 Burst Read) .................................................. 1859 Write Timing of DDR-SDRAM (2 Burst Write)................................................. 1860 NMI Input Timing ............................................................................................... 1861 IRQ/IRL, PINT Input and IRQOUT Output Timing........................................... 1862 External CPU Interface Read/Write Access Timing ........................................... 1864 PCI Clock Input Timing ...................................................................................... 1866 Output Signal Timing .......................................................................................... 1866 Input Signal Timing............................................................................................. 1866 DREQ, TEND, and DACK Timing..................................................................... 1867 TCLK Input Timing ............................................................................................ 1868 TPU Output Timing............................................................................................. 1869 TPU Clock Input Timing..................................................................................... 1869 MII Transmit Timing (normal operation)............................................................ 1871 MII Receive Timing (normal operation) ............................................................. 1871 MII Receive Timing (When an Error is Detected) .............................................. 1872 WOL Output Timing ........................................................................................... 1872 GMII Transmit Timing (normal operation)......................................................... 1873 GMII Receive Timing (normal operation) .......................................................... 1873 GMII Receive Timing (When an Error is Detected) ........................................... 1874 WOL Output Timing ........................................................................................... 1874 RMII Transmit Timing ........................................................................................ 1875 RMII Receive Timing (normal operation)........................................................... 1875 RMII Receive Timing (When an Error is Detected)............................................ 1876 STIF Clock Valid Receive Timing...................................................................... 1877 STIF Clock Valid Transmit Timing .................................................................... 1878 STIF Strobe Receive Timing............................................................................... 1878 STIF Strobe Transmit Timing ............................................................................. 1879 I2C Bus Interface Input/Output Timing ............................................................... 1881 AC Characteristic Load Condition ...................................................................... 1881 SCIFn_SCK Input Clock Timing ........................................................................ 1882 SCIFn I/O Synchronous Mode Clock Timing ..................................................... 1883 SIOF_MCLK Input Timing................................................................................. 1884
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Figure 43.61 SIOF Transmission/Reception Timing (Master Mode 1, Sampling at the Falling Edge) ................................................. 1885 Figure 43.62 SIOF Transmission/Reception Timing (Master Mode 1, Sampling at the Rising Edge) .................................................. 1885 Figure 43.63 SIOF Transmission/Reception Timing (Master Mode 2, Sampling at the Falling Edge) ................................................. 1886 Figure 43.64 SIOF Transmission/Reception Timing (Master Mode 2, Sampling at the Rising Edge) .................................................. 1886 Figure 43.65 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2) .............. 1887 Figure 43.66 SIM Module Signal Timing ................................................................................ 1888 Figure 43.67 MMCIF Transmit Timing ................................................................................... 1889 Figure 43.68 MMCIF Receive Timing (Sampling at the Rising Edge) .................................... 1890 Figure 43.69 HAC Cold Reset Timing ..................................................................................... 1891 Figure 43.70 HAC SYNC Output Timing ................................................................................ 1891 Figure 43.71 HAC Clock Input Timing.................................................................................... 1892 Figure 43.72 HAC Interface Module Signal Timing ................................................................ 1892 Figure 43.73 SSI Clock Input/Output Timing .......................................................................... 1893 Figure 43.74 SSI Transmit Timing (1) ..................................................................................... 1893 Figure 43.75 SSI Transmit Timing (2) ..................................................................................... 1894 Figure 43.76 SSI Receive Timing (1)....................................................................................... 1894 Figure 43.77 SSI Receive Timing (2)....................................................................................... 1894 Figure 43.78 USB Clock Timing.............................................................................................. 1895 Figure 43.79 LCDC Module Signal Timing ............................................................................. 1897 Figure 43.80 GPIO Timing....................................................................................................... 1897 Figure 43.81 TCK Input Timing............................................................................................... 1898 Figure 43.82 PRESET Hold Timing......................................................................................... 1899 Figure 43.83 H-UDI Data Transfer Timing.............................................................................. 1899 Figure 43.84 ASEBRK Pin Break Timing................................................................................ 1899 Figure 43.85 Output Load Circuit ............................................................................................ 1901 Figure 43.86 Load Capacitance - Delay Time .......................................................................... 1902 Appendix Figure B.1 Figure D.1 Figure E.1 Figure F.1 Figure J.1 Figure J.2 Instruction Prefetch................................................................................................. 1905 Schematic Diagram of External Circuits ................................................................ 1908 Connection Example of Bypass Capacitors for Analog Power Supply .................. 1911 Package Dimensions (449-Pin) ............................................................................... 1912 Overall View of Simulation Model (with heat sink)................................................ 1945 Heat Sink Model ...................................................................................................... 1946
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Tables
Section 1 Overview Table 1.1 Features of the SH7763........................................................................................... 80 Table 1.2 Pin Configuration.................................................................................................... 94 Section 2 Programming Model Table 2.1 Initial Register Values............................................................................................. 40 Table 2.2 Bit Allocation for FPU Exception Handling........................................................... 50 Section 3 Instruction Set Table 3.1 Execution Order of Delayed Branch Instructions ................................................... 57 Table 3.2 Addressing Modes and Effective Addresses........................................................... 59 Table 3.3 Notation Used in Instruction List............................................................................ 64 Table 3.4 Fixed-Point Transfer Instructions ........................................................................... 66 Table 3.5 Arithmetic Operation Instructions .......................................................................... 68 Table 3.6 Logic Operation Instructions .................................................................................. 70 Table 3.7 Shift Instructions..................................................................................................... 71 Table 3.8 Branch Instructions ................................................................................................. 72 Table 3.9 System Control Instructions.................................................................................... 72 Table 3.10 Floating-Point Single-Precision Instructions .......................................................... 75 Table 3.11 Floating-Point Double-Precision Instructions......................................................... 76 Table 3.12 Floating-Point Control Instructions ........................................................................ 76 Table 3.13 Floating-Point Graphics Acceleration Instructions ................................................. 77 Section 4 Pipelining Table 4.1 Representations of Instruction Execution Patterns.................................................. 80 Table 4.2 Instruction Groups .................................................................................................. 90 Table 4.3 Combination of Preceding and Following Instructions........................................... 93 Table 4.4 Issue Rates and Execution Cycles........................................................................... 95 Section 5 Exception Handling Table 5.1 Register Configuration.......................................................................................... 105 Table 5.2 States of Register in Each Operating Mode .......................................................... 105 Table 5.3 Exceptions............................................................................................................. 110 Section 6 Memory Management Unit (MMU) Table 6.1 Register Configuration.......................................................................................... 146 Table 6.2 Register States in Each Processing State .............................................................. 146
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Section 7 Caches Table 7.1 Cache Features...................................................................................................... 187 Table 7.2 Store Queue Features ............................................................................................ 187 Table 7.3 Register Configuration.......................................................................................... 190 Table 7.4 Register States in Each Processing State .............................................................. 190 Section 8 L Memory Table 8.1 L Memory Addresses............................................................................................ 217 Table 8.2 Register Configuration.......................................................................................... 218 Table 8.3 Register Status in Each Processing State .............................................................. 219 Table 8.4 Protective Function Exceptions to Access L Memory.......................................... 231 Section 9 Interrupt Controller (INTC) Table 9.1 Interrupt Types........................................................................................................ 82 Table 9.2 INTC Pin Configuration ......................................................................................... 86 Table 9.3 INTC Register Configuration ................................................................................. 87 Table 9.4 Register States in Each Operating Mode ................................................................ 90 Table 9.5 Interrupt Request Sources and INT2PRI0 to INT2PRI13..................................... 113 Table 9.6 RL[3:0], IRL[7:4] Pins and Interrupt Levels ........................................................ 140 Table 9.7 Interrupt Exception Handling and Priority............................................................ 143 Table 9.8 Interrupt Response Time....................................................................................... 154 Table 9.9 Switching Sequence of IRQ7/IRL7 to IRQ0/IRL0 Pin Function ......................... 156 Section 10 SuperHyway Bus Bridge (SBR) Table 10.1 Register Configuration.......................................................................................... 316 Table 10.2 Register State in Each Operating Mode................................................................ 316 Section 11 Local Bus State Controller (LBSC) Table 11.1 Pin Configuration.................................................................................................. 324 Table 11.2 LBSC External Memory Space Map .................................................................... 327 Table 11.3 Setting of bus width for area 0.............................................................................. 330 Table 11.4 Correspondence between External Pin (MD5) and Endian .................................. 331 Table 11.5 PCMCIA Interface Features ................................................................................. 331 Table 11.6 PCMCIA Support Interface .................................................................................. 332 Table 11.7 Register Configuration.......................................................................................... 335 Table 11.8 Register State in Each Operating Made. ............................................................... 335 Table 11.9 32-Bit External Device/Big-Endian Access and Data Alignment......................... 359 Table 11.10 16-Bit External Device/Big-Endian Access and Data Alignment..................... 359 Table 11.11 8-Bit External Device/Big-Endian Access and Data Alignment ...................... 360 Table 11.12 32-Bit External Device/Little-Endian Access and Data Alignment.................. 361 Table 11.13 16-Bit External Device/Little-Endian Access and Data Alignment.................. 361 Table 11.14 8-Bit External Device/Little-Endian Access and Data Alignment.................... 362
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Table 11.15
Relationship between Address and CE When Using PCMCIA Interface ......... 380
Section 12 DDR-SDRAM Interface (DDRIF) Table 12.1 Pin Configuration.................................................................................................... 81 Table 12.2 Access and Data Alignment in Little Endian Mode (External Bus Width is 32 Bits) .............................................................................. 82 Table 12.3 Access and Data Alignment in Big Endian Mode (External Bus Width is 32 Bits) .............................................................................. 83 Table 12.4 Register Configuration............................................................................................ 85 Table 12.5 Register State in Each Operating Mode .................................................................. 86 Table 12.6 DDR-SDRAM Commands Issued by DDRIF ...................................................... 102 Table 12.7 DDR-SDRAM Address Multiplexing (32-Bit Data Bus) ..................................... 106 Section 13 PCI Controller (PCIC) Input/Output Pins.................................................................................................... 82 Table 13.1 Table 13.2 List of PCIC Registers ............................................................................................ 85 Table 13.3 Register States in Each Operating Mode ................................................................ 88 Table 13.4 Supported Bus Commands.................................................................................... 157 Table 13.5 PCIC Address Map ............................................................................................... 159 Table 13.6 Interrupt Priority ................................................................................................... 178 Section 14 Direct Memory Access Controller (DMAC) Table 14.1 Pin Configuration.................................................................................................... 81 Table 14.2 Register Configuration of DMAC........................................................................... 83 Table 14.3 State of Registers in Each Operating Mode ............................................................ 85 Table 14.4 Transfer Request Sources ..................................................................................... 103 Table 14.5 Setting External Request Mode with RS bit ......................................................... 105 Table 14.6 Selecting External Request Detection with DL, DS Bits ...................................... 106 Table 14.7 Selecting External Request Detection with DO Bit .............................................. 106 Table 14.8 Selecting On-Chip Peripheral Module Request Modes with Bits RS[3:0] ........... 107 Table 14.9 DMA Transfer Matrix in Auto-Request Mode (all channels)............................... 117 Table 14.10 DMA Transfer Matrix in External Request Mode (only channels 0 to 3)......... 118 Table 14.11 DMA Transfer Matrix in On-Chip Peripheral module Request Mode.............. 119 Table 14.12 Register Setting for SRAM, Burst ROM, Byte Control SRAM Interface. ....... 131 Table 14.13 Register Setting for PCMCIA Interface............................................................ 132 Table 14.14 Register Setting for MPX Interface (Read Access) .......................................... 132 Table 14 15 Register Settings for MPX Interface (Write Access) ........................................ 132 Section 15 External CPU Interface (EXCPU) Table 15.1 Pin Configuration.................................................................................................. 612 Table 15.2 Register Configuration.......................................................................................... 613 Table 15.3 Register States in Each Operating Mode .............................................................. 613
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Table 15.4 Table 15.5
Access and Data Alignment for Little Endian ...................................................... 618 Access and Data Alignment for Big Endian ......................................................... 619
Section 16 Clock Pulse Generator (CPG) Table 16.1 Pin Configuration and Functions of CPG ............................................................... 82 Table 16.2 Clock Operating Modes .......................................................................................... 83 Table 16.3 Register Configuration............................................................................................ 84 Table 16.4 Register States in Each Operating Mode ................................................................ 84 Section 17 Watchdog Timer and Reset (WDT) Table 17.1 Pin Configuration.................................................................................................... 81 Table 17.2 Register Configuration............................................................................................ 82 Table 17.3 Register State in Each Operating Mode.................................................................. 82 Section 18 Power-Down Mode States in Power-Down Modes............................................................................... 654 Table 18.1 Table 18.2 Pin Configuration.................................................................................................. 655 Table 18.3 Register Configuration.......................................................................................... 656 Table 18.4 Register States in Each Operating Mode .............................................................. 656 Table 18.5 Pin Configuration.................................................................................................. 670 Section 19 Timer Unit (TMU) Table 19.1 Pin Configuration.................................................................................................. 675 Table 19.2 Register Configuration.......................................................................................... 676 Table 19.3 Register States in Each Operating Mode .............................................................. 677 Table 19.4 TMU Interrupt Sources......................................................................................... 690 Section 20 16-Bit Timer Pulse Unit (TPU) Table 20.1 TPU Functions ...................................................................................................... 694 Table 20.2 TPU Pin Configurations........................................................................................ 696 Table 20.3 Register Configuration.......................................................................................... 697 Table 20.4 Register State in Each Operating Mode................................................................ 699 Table 20.5 TPU Clock Sources............................................................................................... 702 Table 20.6 TPSC[2:0] (1) ....................................................................................................... 703 Table 20.6 TPSC[2:0] (2) ....................................................................................................... 703 Table 20.6 TPSC[2:0] (3) ....................................................................................................... 703 Table 20.6 TPSC[2:0] (4) ....................................................................................................... 704 Table 20.7 IOA[2:0] ............................................................................................................... 708 Table 20.8 Register Combinations in Buffer Operation ......................................................... 720 Table 20.9 Phase Counting Mode Clock Input Pins ............................................................... 726 Table 20.10 Up/Down-Count Conditions in Phase Counting Mode 1.................................. 728 Table 20.11 Up/Down-Count Conditions in Phase Counting Mode 2.................................. 729 Table 20.12 Up/Down-Count Conditions in Phase Counting Mode 3.................................. 730
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Table 20.13
Up/Down-Count Conditions in Phase Counting Mode 4.................................. 731
Section 21 Compare Match Timer (CMT) Table 21.1 Register Configuration.......................................................................................... 735 Table 21.2 Register State in Each Operating Mode ................................................................ 736 Section 22 Realtime Clock (RTC) Table 22.1 RTC Pins............................................................................................................... 747 Table 22.2 Register Configuration.......................................................................................... 748 Table 22.3 Register State in Each Operating Mode ................................................................ 749 Table 22.4 Crystal Oscillator Circuit Constants (Recommended Values) .............................. 767 Table 22.5 Interrupt source and request generating order....................................................... 768 Section 23 Gigabit Ethernet Controller (GETHER) Table 23.1 Pin Configuration.................................................................................................... 81 Table 23.2 Register Configuration............................................................................................ 86 Table 23.3 Register States in Each Operating Mode ................................................................ 94 Table 23.4 Relay Frame Process (Without CAM) .................................................................. 264 Table 23.5 Receive Frame Processing .................................................................................... 266 Table 23.6 Relay Frame Process (With CAM) ....................................................................... 266 Table 23.7 List of GETHER Interrupts................................................................................... 271 Section 25 Stream Interface (STIF) Table 25.1 Pin Configuration.................................................................................................. 985 Table 25.2 Register Configuration.......................................................................................... 986 Table 25.3 Register States in Each Operating Mode .............................................................. 987 Section 26 I2C Bus Interface (IIC) Table 26.1 Pin Configuration.................................................................................................... 80 Table 26.2 Register Configuration............................................................................................ 80 Table 26.3 Register State in Each Operating Mode .................................................................. 82 Table 26.4 Suggested Settings for CDF and SCGD ................................................................. 97 Table 26.5 Description on Symbols of I2C Bus Data Format ................................................. 100 Section 27 Serial Communication Interface with FIFO (SCIF) Table 27.1 Pin Configuration................................................................................................ 1051 Table 27.2 Register Configuration (1) .................................................................................. 1052 Table 27.3 Register State in Each Operating Mode .............................................................. 1053 Table 27.4 SCSMR Settings ................................................................................................. 1069 Table 27.5 SCSMR Settings for Serial Transfer Format Selection....................................... 1079 Table 27.6 SCSMR and SCSCR Settings for SCIF Clock Source Selection........................ 1079 Table 27.7 Serial Transfer Formats (Asynchronous Mode).................................................. 1081 Table 27.8 SCIF Interrupt Sources ....................................................................................... 1100
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA) Table 28.1 Pin Configuration................................................................................................ 1109 Table 28.2 Register Configuration........................................................................................ 1110 Table 28.3 Register States in each Operation Mode ............................................................. 1111 Table 28.4 SCSMR Settings ................................................................................................. 1127 Table 28.5 Baud Rate (3.6864 MHz Clock) ......................................................................... 1134 Table 28.6 SCSMR Settings for Serial Transfer Format Selection....................................... 1138 Table 28.7 SCSMR and SCSCR Settings for SCIF Clock Source Selection........................ 1139 Table 28.8 Serial Transfer Formats (Asynchronous Mode).................................................. 1142 Table 28.9 SCIF Interrupt Sources ....................................................................................... 1161 Section 29 Serial I/O with FIFO (SIOF) Table 29.1 Pin Configuration................................................................................................ 1173 Table 29.2 Register Configuration........................................................................................ 1174 Table 29.3 Register State in Each Operating Mode.............................................................. 1176 Table 29.4 Operation in Each Transfer Mode....................................................................... 1180 Table 29.5 SIOF Serial Clock Frequency ............................................................................. 1204 Table 29.6 Serial Transfer Modes......................................................................................... 1207 Table 29.7 Frame Length...................................................................................................... 1207 Table 29.8 Audio Mode Specification for Transmit Data..................................................... 1209 Table 29.9 Audio Mode Specification for Receive Data ...................................................... 1210 Table 29.10 Setting Number of Channels in Control Data ................................................. 1211 Table 29.11 Conditions to Issue Transmit Request ............................................................ 1214 Table 29.12 Conditions to Issue Receive Request .............................................................. 1214 Table 29.13 Transmit and Receive Reset ........................................................................... 1219 Table 29.14 SIOF Interrupt Sources ................................................................................... 1220 Section 30 SIM Card Module (SIM) Table 30.1 Pin Configuration................................................................................................ 1229 Table 30.2 Register Configuration........................................................................................ 1230 Table 30.3 Register State in Each Operating Mode.............................................................. 1231 Table 30.4 Register Settings for Smart Card Interface ......................................................... 1254 Table 30.5 Example of Bit Rates (bits/s) for SCBRR Settings (Pck0 = 66.6 MHz, SCSMPL = 371).................................................................. 1256 Table 30.6 Interrupt Sources of Smart Card Interface .......................................................... 1262 Section 31 Multimedia Card Interface (MMCIF) Table 31.1 Pin Configuration................................................................................................ 1273 Table 31.2 Register Configuration........................................................................................ 1274 Table 31.3 Register States in Each Processing Mode ........................................................... 1276 Table 31.4 Correspondence between Commands and CMDTYR and RSPTYR Settings.... 1281 Table 31.5 CMDR Configuration ......................................................................................... 1284
Rev. 1.00 Oct. 01, 2007 Page lxii of lxvi
Table 31.6 Table 31.7 Table 31.8
Correspondence between Command Response Byte Number and RSPR........... 1286 List of Chattering Elimination Pulse Cycles....................................................... 1311 MMCIF Interrupt Sources................................................................................... 1343
Section 32 PC Card Controller (PCC) Table 32.1 Features of the PCMCIA Interface ..................................................................... 1347 Table 32.2 PCC Pin Configuration ....................................................................................... 1350 Table 32.3 Register Configuration........................................................................................ 1351 Table 32.4 Register State in Each Operating Mode .............................................................. 1351 Table 32.5 PCMCIA Support Interface ................................................................................ 1367 Section 33 Audio Codec Interface (HAC) Table 33.1 Pin Configuration................................................................................................ 1378 Table 33.2 Register Configuration........................................................................................ 1379 Table 33.3 Register State in Each Operating Mode .............................................................. 1379 Table 33.4 AC97 Transmit Frame Structure......................................................................... 1395 Table 33.5 AC97 Receive Frame Structure .......................................................................... 1396 Section 34 Serial Sound Interface (SSI) Table 34.1 Pin Configuration.................................................................................................... 81 Table 34.2 Register Configuration............................................................................................ 82 Table 34.3 Register State in Each Operating Mode .................................................................. 83 Table 34.4 Bus Formats of SSI Module.................................................................................... 97 Table 34.5 Number of Padding Bits for Each Valid Configuration........................................ 101 Section 35 USB Host Controller (USBH) Table 35.1 USB Host Pin Assignment.................................................................................. 1445 Table 35.2 Register Configuration........................................................................................ 1446 Table 35.3 Register State in Each Operating Mode .............................................................. 1447 Section 36 USB Function Controller (USBF) Table 36.1 Pin Configuration and Functions ............................................................................ 81 Table 36.2 (1) Register Configuration (Access Size = 8 bits) ................................................ 82 Table 36.2 (2) Register Configuration (Access Size = 32 bits) .............................................. 84 Table 36.3 Register State in Each Operating Mode .................................................................. 86 Table 36.4 Restrictions of Settable Values ............................................................................. 137 Table 36.5 Example of Endpoint Configuration ..................................................................... 137 Table 36.6 Example of Setting of Endpoint Configuration Information................................. 138 Table 36.7 Command Decoding on Application Side............................................................. 160 Section 37 LCD Controller (LCDC) Table 37.1 Pin Configuration.................................................................................................... 81 Table 37.2 Register Configuration............................................................................................ 82
Rev. 1.00 Oct. 01, 2007 Page lxiii of lxvi
Table 37.3 Table 37.4 Table 37.5 Table 37.6 Table 37.7 Table 37.8
Register State in Each Operating Mode.................................................................. 83 I/O Clock Frequency and Clock Division Ratio ..................................................... 86 Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (32-bit SDRAM) .................................................................................... 119 Available Power-Supply Control-Sequence Periods at Typical Frame Rates....... 130 LCDC Operating Modes....................................................................................... 131 LCD Module Power-Supply States....................................................................... 131
Section 38 A/D Converter Table 38.1 Pin Configuration................................................................................................ 1643 Table 38.2 Register Configuration........................................................................................ 1644 Table 38.3 Register State in Each Operating Mode.............................................................. 1644 Table 38.4 Analog Input Channels and A/D Data Registers................................................. 1645 Table 38.5 A/D Conversion Time......................................................................................... 1654 Table 38.6 Relationship between Clock Division Ratio and Usable Pck0 Clock Frequency1658 Section 39 D/A Converter (DAC) Table 39.1 Pin Configuration................................................................................................ 1660 Table 39.2 Register Configuration........................................................................................ 1660 Table 39.3 Register State in Each Operating Mode.............................................................. 1660 Section 40 General Purpose I/O (GPIO) Table 40.1 Multiplexed Pins Controlled by Port Control Registers ......................................... 80 Table 40.2 Register Configuration (1) ...................................................................................... 90 Table 40.3 Register States in Each Operating Mode ................................................................ 92 Section 41 User Break Controller (UBC) Table 41.1 Register Configuration........................................................................................ 1747 Table 41.2 Register Status in Each Processing State ............................................................ 1748 Table 41.3 Settings for Match Data Setting Register............................................................ 1762 Table 41.4 Relation between Operand Sizes and Address Bits to be Compared .................. 1771 Section 42 User Debugging Interface (H-UDI) Table 42.1 Pin Configuration................................................................................................ 1785 Table 42.2 Commands Supported by Boundary-Scan TAP Controller ................................ 1787 Table 42.3 Register Configuration (1) .................................................................................. 1788 Table 42.4 Register Configuration (2) .................................................................................. 1788 Table 42.5 Register Status in Each Processing State ............................................................ 1788 Table 42.6 SDBSR Configuration ........................................................................................ 1792 Section 43 Electrical Characteristics Table 43.1 Absolute Maximum Ratings ................................................................................... 79 Table 43.2 Power-On and Power-Off Timing .......................................................................... 81
Rev. 1.00 Oct. 01, 2007 Page lxiv of lxvi
Table 43.3 Table 43.4 Table 43.5 Table 43.6 Table 43.7 Table 43.8 Table 43.9 Table 43.10 Table 43.11 Table 43.12 Table 43.13 Table 43.14 Table 43.15 Table 43.16 Table 43.17 Table 43.18 Table 43.19 Table 43.20 Table 43.21 Table 43.22 Table 43.23 Table 43.24 Table 43.25 Table 43.26 Table 43.27 Table 43.28 Table 43.29 Table 43.30 Table 43.31 Table 43.32 Table 43.33 Table 43.34 Table 43.35 Table 43.36 Table 43.37 Table 43.38 Table 43.39 Table 43.40
DC Characteristics (1) [common] ........................................................................... 83 DC Characteristics (2-a) [Except of USB Transceiver and I2C Related Pins] ........ 84 DC Characteristics (2-b) [I2C Related Pins] ........................................................... 85 DC Characteristics (2-c) [USB Transceiver Related Pins] ..................................... 86 Permissible Output Currents ................................................................................... 86 Maximum Operating Frequency ............................................................................. 87 Clock and Control Signal Timing ........................................................................... 88 Control Signal Timing ........................................................................................ 92 Bus Timing ......................................................................................................... 94 DDRIF Signal Timing....................................................................................... 112 INTC Module Signal Timing............................................................................ 115 External CPU Interface Access Timing ............................................................ 117 PCIC Signal Timing.......................................................................................... 119 DMAC Module Signal Timing ......................................................................... 121 TMU Module Signal Timing ............................................................................ 122 16-bit Timer Pulse Unit .................................................................................... 123 Ethernet Controller Signal Timing (MII).......................................................... 124 Ethernet Controller Signal Timing (GMII) ....................................................... 126 Ethernet Controller Signal Timing (RMII) ....................................................... 128 STIF Clock Valid Reception Signal Timing..................................................... 130 STIF Clock Valid Transmission Signal Timing................................................ 131 STIF Strobe Reception Signal Timing.............................................................. 132 STIF Strobe Transmission Signal Timing......................................................... 133 I2C Bus Interface Timing .................................................................................. 134 SCIF Module Signal Timing............................................................................. 136 SIOF Module Signal Timing ............................................................................ 138 SIM Module Signal Timing .............................................................................. 142 MMCIF Module Signal Timing........................................................................ 143 HAC Interface Module Signal Timing.............................................................. 145 SSI Interface Module Signal Timing ................................................................ 147 USB Module Clock Timing .............................................................................. 149 USB Electrical Characteristics (Full-Speed)..................................................... 149 USB Electrical Characteristics (Low-Speed).................................................... 150 LCDC Module Signal Timing .......................................................................... 150 GPIO Signal Timing ......................................................................................... 151 H-UDI Module Signal Timing.......................................................................... 152 A/D Converter Characteristics .......................................................................... 154 D/A Converter Characteristics .......................................................................... 154
Appendix Table D.1 Mode Control Pins ......................................................................................................... 83
Rev. 1.00 Oct. 01, 2007 Page lxv of lxvi
Table G.1 Table H.1 Table I.1 Table J.1
Pin States ................................................................................................................ 89 Handling of Unused Pins ...................................................................................... 107 Register Configuration.......................................................................................... 119 Heat Resistance Simulation Results...................................................................... 121
Rev. 1.00 Oct. 01, 2007 Page lxvi of lxvi
Section 1 Overview
Section 1 Overview
1.1 Features of the SH7763
This LSI is a single-chip multifunction CMOS microcomputer that integrates the Renesas Technology original RISC (reduced instruction set computer) CPU core with the peripheral functions required for a wide range of application systems such as high-speed Ethernet, display, and digital AV systems. The SH-4A is upwardly compatible with the SH-1, SH-2, SH-3, and SH-4 microcompututers at the instruction set level. This microprocessor core integrates a cache memory and the MMU. The CPU of this LSI has a RISC instruction set and basically operates on a one-cycle-perinstruction basis, which dramatically reduces the instruction execution time. The internal 32-bit configuration enhances the data processing capability. The CPU of this LSI allows highperformance, highly-functional systems to be built at lower cost even for applications that require high speeds which cannot be implemented with conventional microcomputers. With this LSI, the on-chip DMAC (direct memory access controller) permits high-speed data transfer and the external memory access support function permits direct connection to various types of memory device. Furthermore, the LSI also incorporates powerful peripheral functions which are optimal for system configuration, such as the LCD controller, USB full-speed host controller, function controller, PCI controller, high-speed asynchronous serial communication interface, serial interface for a voice/audio codec, A/D converter, and D/A converter. The LSI has a two-channel gigabit Ethernet controller that includes an IEEE802.3z-compliant media access controller (MAC) and a gigabit media-independent interface (GMII) standard unit, which allows implementation of 10/100/1000-Mbps LAN connections. In addition, the inclusion of the security accelerator allows efficient security control for the data on the network. The external memory access support function permits direct connection to normal memory, DDRSDRAM, and PCMCIA. Because of the various built-in functions that can be applied to a wide range of fields, use of this LSI not only enables dramatic cost reduction of user-developed systems, but also enables downsizing and low power consumption.
Rev. 1.00 Oct. 01, 2007 Page 1 of 1956 REJ09B0256-0100
Section 1 Overview
Table 1.1
Item
Features of the SH7763
Features 266 MHz 478 MIPS (266 MHz), 1862 MFLOPS (266 MHz) Renesas Technology original architecture 32-bit internal data bus General-register files: Sixteen 32-bit general registers (eight 32-bit shadow registers) Seven 32-bit control registers Four 32-bit system registers * RISC-type instruction set (upward compatible with the SH-1, SH-2, SH-3 and SH-4 microcomputers) Instruction length: 16-bit fixed length for improved code efficiency Load/store architecture Delayed branch instructions Instructions executed with conditions Instruction set based on the C language * * * * * * Super scalar which executes two instructions simultaneously including the FPU Instruction execution time: Two instruction per cycle (max) Virtual address apace: 4 Gbytes Space identifier ASID: 8 bits, 256 virtual address spaces On-chip multiplier Seven-stage pipeline
Maximum operating * frequency Performance CPU * * * *
Rev. 1.00 Oct. 01, 2007 Page 2 of 1956 REJ09B0256-0100
Section 1 Overview
Item FPU
Features * * * * * * * * * * * On-chip floating-point coprocessor Supports single-precision (32 bits) and double-precision (64 bits) Supports IEEE754-compliant data types and exceptions Two rounding modes: Round to Nearest and Round to Zero Handling of denormalized numbers: Truncation to zero or interrupt generation for IEEE754 compliance Floating-point registers: 32 bits x 16 words x 2 banks (single-precision x 16 words or double-precision x 8 words) x 2 banks 32-bit CPU-FPU floating-point communication register (FPUL) Supports FMAC (multiply-and-accumulate) instruction Supports FDIV (divide) and FSQRT (square root) instructions Supports FLDI0/FLDI1 (load constant 0/1) instructions Instruction execution times Latency (FADD/FSUB): 3 cycles (single-precision), 5 cycles (doubleprecision) Latency (FMAC/ FMUL): 5 cycles (single-precision), 7 cycles (doubleprecision) Pitch (FADD/FSUB): 1 cycle (single-precision/double-precision) Pitch (FMAC/FMUL): 1 cycle (single-precision), 3 cycles (doubleprecision) Note: * FMAC is supported for single-precision only. 3-D graphics instructions (single-precision only): 4-dimensional vector conversion and matrix operations (FTRV): 4 cycles (pitch), 8 cycles (latency) 4-dimensional vector (FIPR) inner product: 1 cycle (pitch), 5 cycles (latency) * Ten-stage pipeline
Rev. 1.00 Oct. 01, 2007 Page 3 of 1956 REJ09B0256-0100
Section 1 Overview
Item Memory management unit (MMU)
Features * * * * * * * 4 Gbytes of physical address space, 256 address spaces (identified by an 8-bit ASID (address space identifier)) Supports single virtual memory mode and multiple virtual memory mode Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, or 1 Mbytes 4-entry full associative TLB for instructions 64-entry full associative TLB for instructions and operands Supports software-controlled replacement and random-counter replacement algorithms Contents of TLB are directly accessible through address mapping Instruction cache (IC) 32-Kbyte 4-way set associative 32-byte block length * Operand cache (OC) 32-Kbyte 4-way set associative 32-byte block length Selectable write method (copy-back or write-through) * Storage queue (32 bytes x 2 entries) High-speed memory (16 Kbytes) Two independent read/write ports 8-/16-/32-/64-bit access from the CPU/FPU 8-/16-/32-/64-bit access from the DMAC * Supports memory protective mechanism Supports debugging by means of user break interrupts Two break channels Address, data value, access type, and data size are available as break condition settings Supports sequential break functions
Cache memory
*
LRAM
* *
User break controller (UBC)
* * * *
Rev. 1.00 Oct. 01, 2007 Page 4 of 1956 REJ09B0256-0100
Section 1 Overview
Item Clock pulse generator (CPG)
Features * * Selectable CPU clock: 8 times EXTAL Clock modes: CPU frequency: Local bus frequency: 266 MHz (max.) 1/4 times the CPU clock 66 MHz (max.)
DDR-SDRAM I/F frequency: 1/2 times the CPU clock 133 MHz (max.) Peripheral bus 0 frequency: Peripheral bus 1 frequency: * Support of power-down modes: Sleep mode Software standby mode Module standby mode RTC power supply backup mode DDR-SDRAM power supply backup mode * Interrupt controller (INTC) * * * Single-channel watchdog timer Direct jump mode (SH4 compatible) External interrupt pins: NMI, IRL7 to IRL0, IRQ7 to IRQ0, and PINT15 to PINT0 On-chip peripheral module interrupts: Priority level can be set for each module 1/4 times the CPU clock 66 MHz (max.) 1/8 times the CPU clock 33 MHz (max.)
Rev. 1.00 Oct. 01, 2007 Page 5 of 1956 REJ09B0256-0100
Section 1 Overview
Item Local bus state controller (LBSC)
Features * Physical address space divided into seven areas (areas 0 to 6), each comprising up to 64 Mbytes I/F configuration, bus width, and wait cycle insertion are settable for each area * SRAM interface Wait cycle insertion by register setting Wait cycle insertion by the RDY pin Supported bus width: 8, 16, or 32 bits Supported space: Areas 0 to 2 and areas 4 to 6 * Burst ROM interface Wait cycle insertion by register setting Number of bursts is specified by register setting Supported bus width: 8, 16, or 32 bits Supported space: Areas 0, 5, and 6 * Interface for SRAM with byte selection Supports direct connection to SRAM with byte selection Supported space: Areas 1 and 4 * PCMCIA interface (only supported in little endian mode) Wait cycle insertion by register setting Supports ATAPI interface (multi-word DMA supported) Supports I/O bus-width sizing Supported space: Areas 5 and 6
Rev. 1.00 Oct. 01, 2007 Page 6 of 1956 REJ09B0256-0100
Section 1 Overview
Item DDR-SDRAM controller (DDRIF)
Features * * * DDR-SDRAM interface: 32-bit data bus width Supports the DDR266 or DDR200 SDRAM DDR-SDRAM refreshing Programmable refreshing intervals (auto-refresh mode) Self-refresh mode * * * Supports a burst length of 2 Switching of big/little endian for external memory access is possible at power-on reset Capacity and bit width (bits) of connectable memory devices 128-Mbit DDR-SDRAM (x16), two chips in parallel connection 256-Mbit DDR-SDRAM (x16), two chips in parallel connection 512-Mbit DDR-SDRAM (x16), two chips in parallel connection 1-Gbit DDR-SDRAM (x16), two chips in parallel connection
PCI controller (PCIC)
*
PCI controller (Rev.2.2-compatible) 32-bit bus 33 MHz/66 MHz
* * * * Direct memory access controller (DMAC) * * * * * * *
Supports PCI master/slave Supports the PCI host function Built-in bus arbiter External input pin for clock exclusively used by the PCI bus Interrupt requests can be sent to CPU Six channels (four channels support external requests) Transfer data size: Byte, word (2 bytes), longword (4 bytes), 16 or 32 bytes Maximum number of transfers: 16,777,216 Address mode: Dual address mode Bus modes: Selectable from cycle-steal and burst modes Transfer requests: Selectable from external request (channels 0 to 3 only), on-chip peripheral module request, and auto-request mode Priority: Selectable from fixed channel priority mode and round-robin mode
Rev. 1.00 Oct. 01, 2007 Page 7 of 1956 REJ09B0256-0100
Section 1 Overview
Item Timer unit (TMU)
Features * * * 6-channel auto-reload 32-bit timer Input-capture function (channels 2 and 5 only) Choice of seven types of counter input clock for each channel External clock (TCLK), five peripheral clocks (Pck0/4, Pck0/16, Pck0/64, Pck0/256, Pck0/1024), and RTC clock
Compare match timer (CMT)
* * * * *
Includes 32-bit counters for four channels (16-bit/32-bit selectable) An interrupt or DMA transfer request can be generated on compare match or an overflow On-chip clock, calendar function and alarm function Built-in 32-kHz crystal oscillator with a maximum resolution of 1/256 seconds (interrupt cycle) Alarm, periodic, and carry interrupt requests Each channel includes 64-byte transmit/receive FIFOs Three channels (SCIF0, SCIF1, SCIF2) Full-duplex communication Modem control function (RTS/CTS) available in asynchronous mode (channels 0 and 1) Transmit/receive clock source is selectable as either the internal clock from the baud-rate generator or the clock externally input from the SCK pin Channel 2 includes an IrDA 1.0-compliant interface Each channel includes 64-byte transmit/receive FIFOs Three channels (SIOF0, SIOF1, SIOF2) Supports 8-/16-bit mono and 16-bit stereo audio input/output Sampling rate clock input selectable from Pck0 and external pin Includes a prescaler Supports MMC mode A maximum bit rate of 16.7 Mbps at 33 MHz of peripheral clock 1 Interface is through the MCCLK output pin for transfer clock output, MCCMD I/O pin for command output/response input, MCDAT I/O pin for data input/output Four interrupt sources
Realtime clock (RTC)
Serial communication interface (SCIF)
* * * * *
* Serial I/O with FIFO * (SIOF) * * * * Multimedia card interface (MMCIF) * * *
*
Rev. 1.00 Oct. 01, 2007 Page 8 of 1956 REJ09B0256-0100
Section 1 Overview
Item Serial sound interface (SSI)
Features * * * * * * Four channels (SSI0, SSI1, SSI2, SSI3) Supports various serial audio formats Supports master/slave functions Programmable word clock and bit clock generation Multi-channel format Supports 8/16/18/20/22/24/32-bit data formats H-UDI (User Debugging Interface) AUD (Advanced User Debugger) Data transfer rates of 1.5 Mbps and 12 Mbps OHCI version 1.0 Includes a USB device controller (UDC) supporting USB2.0 Automatic processing of standard USB commands (some commands are not included: Get Descriptor/Class/Vector commands are processed on the microcomputer's firmware) * Transfer rate: Full speed (12 Mbps only) Digital interface for audio codec (single channel) Supports transmission/reception for slot 1 to slot 4 Choice of 16- or 20-bit DMA transfer in transmission/reception Supports various sampling rates by adjusting slot data Generates data ready, data request, overflow, and underflow interrupts Supports the I2C bus interface protocol Two channels (IIC0, IIC1) Master/slave functions Multi-master function A maximum transfer rate of 400 Kbps Programmable clock generation from the system clock 10 bits 4LSB, four channels Conversion time: 8.5 s Three conversion modes: single mode, multi-mode, and scan mode Four data registers Sample-and-hold function Generates A/D conversion end interrupts Input range: 0 to Avcc (max. 3.6 V) * * * * *
Debug interface USB host interface (OHCI USBH) USB function interface Version 2.0 (USBF)
* * * * *
Audio codec interface (HAC)
I2C bus interface (IIC)
A/D converter (ADC)
* * * * * * * * * * * * *
Rev. 1.00 Oct. 01, 2007 Page 9 of 1956 REJ09B0256-0100
Section 1 Overview
Item D/A converter (DAC)
Features * * * * * * * * * * * * * 8 bits 4LSB, two channels Conversion time: 10 s Two data registers Output range: 0 to Avcc (max. 3.6 V) Display size: 16 x 1 pixels to 1024 x 1024 pixels Color display of 4, 8, 15, or 16 bpp (bits per pixel) Grayscale display of 1, 2, 4, or 6 bpp (bits per pixel) 8-bit frame controller Supported LCD panels: TFT, DSTN, and STN Signal polarity selection Hardware panel rotation Power control function Selectable clock source: Peripheral clock or external clock Supports control signals for one slot Compatible with the SH7709 when PCC operation is disabled (two slots) One channel. Conforms to the ISO 7816-3 data protocol. (T = 0, T = 1) Asynchronous half-duplex character transmission protocol Data length: 8 bits Parity bit generation and check Selectable output clock cycles per etu (elementary time unit) Selectable direct convention/inverse convention Built-in prescaler using Pck0 Changeable clock polarity (high or low) in idle state Interrupt request and DMAC request Up to four pulse outputs Up to four-phase PWM outputs Bidirectional port pins can be configured as input or output by setting the corresponding bits
LCD controller (LCDC)
PC card controller (PCC) SIM card interface (SIM)
* * * * * * * * * * * * * *
16-bit timer pulse unit (TPU) I/O ports (GPIO)
Rev. 1.00 Oct. 01, 2007 Page 10 of 1956 REJ09B0256-0100
Section 1 Overview
Item Stream interface (STIF)
Features * Parallel connection available when MPEG2 TS stream is input Parallel stream connection Stream input: Master mode with clock-valid operation Byte transfer mode with strobe operation Stream output: Master mode with clock-valid operation Byte transfer mode with strobe operation * Two channels (STIF0, STIF1) E-DMAC (DMAC dedicated for Ethernet) Four channels Transfer between GETHER and external/internal memory 32-byte burst transfer Supports the one-descriptor-for-one-frame and multi-descriptors-forone-frame (multi-buffer) transfer methods Transfer data width: 32 bits Includes FIFOs (2 Kbytes for transmission, 8 Kbytes for reception) * MAC (Media Access Control) Two channels (GETHER0, GETHER1) Data frame composition/decomposition (IEEE802.3, 2000 Editioncompliant frame format) Changeable transfer rate: 10, 100, or 1000 Mbps Full-duplex/half-duplex transmission/reception IEEE802.3x-compliant flow control available. Automatic/manual transmission of PAUSE frames for flow control Supports IEEE802.1Q (VLAN) Supports IEEE802.3-compliant PHY interface GMII (Gigabit Media Independent Interface), MII (Media Independent Interface), and RMII (Reduced Media Independent Interface) Support for higher-layer protocols (sum check) Includes a switching unit for inter-channel transfer (transfer FIFO: 6 Kbytes)
Gigabit Ethernet controller (GETHER)
*
Rev. 1.00 Oct. 01, 2007 Page 11 of 1956 REJ09B0256-0100
Section 1 Overview
Item Security accelerator*1 (SECURITY)
Features * * * * * * Encryption/decryption based on AES (Advanced Encryption Standard) (Key length: 128, 192, and 256 bits) DES/Triple-DES encryption/decryption based on DES (Data Encryption Standard) Hash function generation based on the MD5 (Message-Digest Algorithm) Hash function generation based on sha-1 of the Source Hash Standard Includes a dedicated DMAC for data transfer Interrupt requests to the CPU P-FBGA2121-449 (BGA - 449 pin (21 x 21 mm)) 3.3 V 0.3 V, 1.25 V 0.1 V, 2.5 V 0.2 V (for DDR-SDRAM) -20 to +75C*
2
Package Power-supply voltage
* *
Temperature range * Process Product lineup *
0.13-m CMOS, 5 metal layers
Operating Frequency 133 MHz
Abbrev. R5S77630 R5S77631
Power Supply 3.3 V 0.3 V 1.25 V 0.1 V 2.5 V 0.2 V
Product Type R5S77630Y266BGV R5S77631Y266BGV
Package BGA-499 pin
Notes: 1. The security accelerator is incorporated only in the R5S77630, not in the R5S77631. 2. Note that a heat radiation countermeasure, such as heat sinks, is required when the ambient temperature exceeds 60 degrees.
Rev. 1.00 Oct. 01, 2007 Page 12 of 1956 REJ09B0256-0100
Section 1 Overview
1.2
Block Diagram
CPU PCIC EXCPU LBSC PCC (External bus)
I-cache
MMU FPU
Instruction bus Operand bus
Internal bus for cache and RAM
(External bus) (External bus)
O-cache
SuperHyway bus
DDRIF
(External bus)
UBC
LCDC
Peripheral bus 1
AUD
LRAM MMCIF
Peripheral bus 0
HPB
RTC
SuperHyway bridge bus
SECURITY*
DMAC 6 channels SBR CPG
SIM SIOF 3 channels INTC SCIF 3 channels IIC 2 channels SSI 4 channels AD/DA
GETHER
USBH
USBF CMT
[Legend] AUD: Advanced user debugger CMT: Compare match timer CPG: Clock pulse generator CPU: Central processing unit DDRIF: DDR-SDRAM interface DMAC: Direct memory access controller FPU: Floating-point unit GPIO: General purpose I/O SBR: SuperHyway bridge HPB: Peripheral bus bridge I-Cache: Instruction cache INTC: Interrupt controller LBSC: Local bus state controller PCC: PC card controller LRAM: L memory MMCIF: Multimedia card interface MMU: Memory management unit O-Cache: Operand (data) cache PCIC: PCI controller EXCPU: External CPU interface RTC: Realtime clock UBC: User break controller H-UDI: User debugging interface GETHER: Gigabit Ethernet controller SECURITY*: Security accelerator USBH: USB host controller
TMU
TPU
HAC STIF 2 channels GPIO
WDT
H-UDI
USBF: SCIF: SIOF: SSI: STIF: HAC: AD/DA: TMU: IIC: WDT: SIM: TPU: LCDC:
USB function controller Serial communication interface with FIFO Serial I/O with FIFO Serial sound interface Stream interface Audio codec interface A/D converter, D/A converter Timer unit IIC bus interface Watchdog timer SIM card module 16-bit pulse unit LCD controller
Note: * SECURITY is incorporated only in the R5S77630, not in the R5S77631.
Figure 1.1 SH7763 Block Diagram
Rev. 1.00 Oct. 01, 2007 Page 13 of 1956 REJ09B0256-0100
Section 1 Overview
1.3
Pin Arrangement
Figure 1.2 shows the pin arrangement and table 1.2 lists the pin configuration of this LSI.
Rev. 1.00 Oct. 01, 2007 Page 14 of 1956 REJ09B0256-0100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A M_CLK0 M_WE M_RAS M_BA0 M_A10 M_A1 XTAL2 USBM M_A3 M_CLK1
VSSQ-DDR
VCCQ-DDR
M_VREF
PTI0/STATUS0/ ST1_CLK/ RMII0_MDC
PTK4/ST1_D4/ GET0_ERXD4/ SIOF2_TXD/ LCD_D6 PTI6/IRQ2/IRL2/ ST0M_D6I/ IIC1_SCL PTJ1/ST0M_CLKIO/ RMII1_RX_ER/ LCD_CLK CS5/CE1A PTJ5/ST0M_D3I/ ET0_ERXD3/ RMII1_RXD0/ LCD_DON
PTM6/D30/ PTM4/D28/EX_AD28/ EX_AD30/ST0_D6/ ST0_D4/ ET0_RX-CLK/ ET0_PHY-INT/ CS0 RMII0_TXD1/PINT6 RMII0_RXD0/PINT4
VSSQ
VSSQ
B M_CKE M_A13 M_CAS M_CS M_BA1 M_A0 M_A2 EXTAL2 USBP M_A4 CS2/EX_CS1 RDY/EX_RDY/ PCC_WAIT
VCCQ-DDR
VSSQ-DDR
M_BKPRST
PTI2/ST0M_STARTI/ IIC0_SCL/ SIOF1_RXD/ USB_OVRCRT/ USBF_VBUS PTI3/ST0M_VALIDI/ IIC0_SDA/ SIOF1_MCLK/ USB_CLK PTI5/MD10/ ST1_VALID/LCD_D1 PTI7/IRQ3/IRL3/ ST0M_D7I/ IIC1_SDA
PTM5/D29/EX_AD29/ PTM7/D31/ EX_AD31/ST0_D7/ ST0_D5/ ET0_RX-ER/ ET0_RX-DV/ RMII0_TXD0/PINT7 RMII0_TXD_EN/PINT5 VSSQ
PTM3/D27/EX_AD27/ ST0_D3/ ET0_LINKSTA/ RMII0_RXD1/PINT3
REF125CK/ SSI_CLK/ HAC_BITCLK
C VCCQ-DDR M_A12 M_A11 M_A9 M_A7 M_A6 VCCQ M_A8 M_A5 VCCQ XRTCSTBI CS1/EX_CS0 CS6/CE1B
M_D0
VCCQ-DDR
VSSQ-DDR
PTI1/STATUS1/ ST1_REQ/ RMII0_MDIO
PTK7/ST1_D7/ GET0_ERXD7/ SIOF2_MCLK/ LCD_VCPWC PTK6/ST1_D6/ GET0_ERXD6/ SIOF2_SCK/ LCD_VEPWC
PTI4/MD8/ST1_START/ ET1_PHY-INT/ RMII0M0_MDC/ USB_PWREN/USBF_UPLUP
PTJ4/ST0M_D2I/ ET0_ERXD2/ RMII1_RXD1/ LCD_CL2 PTJ7/INTB/ PTJ3/ST0M_D1I/ ST0M_D5I/IRQOUT/ ET0_ERXD1/ RMII1_TXD0/ RMII1_CRS_DV/ LCD_D0 LCD_CL1 VSSQ
BS/EX_BS
PTM1/D25/ PTM2/D26/EX_AD26/ EX_AD25/ST0_D1/ ST0_D2/ET0_WOL/ ET0_TX-CLK/ RMII0_CRS_DV/PINT2 RMII0_RX_ER/PINT1
D VSSQ-DDR VSSQ-DDR VSSQ-DDR VCCQ-DDR VSSQ-DDR VSSQ-DDR VCCQ VCCQ-DDR VDD-RTC VCCQ-DDR VSSQ VSSQ VDD
M_D1
M_D16
VCCQ-DDR
PTK5/ST1_D5/ GET0_ERXD5/ SIOF2_RXD/ LCD_D7
PTJ6/ST0M_D4I/ ET0_CRS/ RMII1_TXD_EN/ LCD_FLM PTJ2/ST0M_D0I/ ET0_ERXD0/ RMII1_TXD1/ CS4 LCD_M_DISP
VSSQ
VCCQ
PTL7/D23/ PTM0/D24/EX_AD24/ EX_AD23/ST0_VALID/ ST0_D0/ET0_TX-ER/ ET0_TX-EN/TEND1/ PINT0/RMII0M0_MDIO LCD_D15
E VCCQ-DDR VCCQ-DDR VCCQ-DDR VSSQ VDD VCCQ VSS VSSQ VSS VSSQ-DDR VSSQ-DDR VCCQ VDD Vss-RTC VCCQ-DDR VSS VSS VCCQ
M_D2
M_D17
M_D18
PTK3/ST1_D3/ GET0_ETXD7/ SIOF2_SYNC/ LCD_D5
RDWR/EX_RDWR PTK2/ST1_D2/ GET0_ETXD6/ SIOF1_SCK/ LCD_D4
PTL6/D22/EX_AD22/ ST0_START/ ET0_ETXD2/DACK1/ LCD_D14
PTL5/D21/ EX_AD21/ST0_CLK/ ET0_ETXD1/DREQ1/ LCD_D13
F VSSQ-DDR VSSQ-DDR VSS
M_D3
M_D19
M_D20
PTL4/D20/EX_AD20/ ST0_REQ/ ET0_ETXD0/INTD/ LCD_D12
PTJ0/ST0M_REQO/ GET0_GTX-CLK/ REF50CK
G VCCQ-DDR VCCQ-DDR VDD
M_D4
M_D21
M_D22
PTK1/ST1_D1/ GET0_ETXD5/ SIOF1_TXD/ LCD_D3 PTL3/D19/EX_AD19/ IRQ7/IRL7/ ET0_MDIO/INTC/ LCD_D11
PTK0/ST1_D0/ GET0_ETXD4/ SIOF1_SYNC/ LCD_D2 PTL2/D18/EX_AD18/ IRQ6/IRL6/ ET0_ETXD3/TEND0/ LCD_D10
WE3/IOWR
WE2/IORD
H VSSQ-DDR VSSQ-DDR VCCQ
M_D5
M_D23
M_DQS2
PTL0/D16/EX_AD16/ IRQ4/IRL4/ ET0_COL/DREQ0/ LCD_D8
PTL1/D17/EX_AD17/ IRQ5/IRL5/ ET0_MDC/DACK0/ LCD_D9
D15/EX_AD15
D14/EX_AD14
J VSSQ-DDR VSSQ-DDR VSS D7/EX_AD7 D6/EX_AD6 D13/EX_AD13 D12/EX_AD12
M_D7
M_D6
M_DQM2
K VCCQ-DDR VCCQ-DDR VSS VSS VSS VSS VSS VSS VSS VDD D5/EX_AD5 D4/EX_AD4 D11/EX_AD11 D10/EX_AD10
M_DQM0
M_DQS0
M_DQS3
L Vss-DLL1 Vss-DLL2 VSS VSS VSS VSS VSS VSS VSS VCCQ D3/EX_AD3 D2/EX_AD2 D9/EX_AD9 D8/EX_AD8
M_DQS1
M_DQM1
M_DQM3
M Vdd-DLL1 Vdd-DLL2 VSS VSS VSS VSS VSS VSS VSS VSS D1/EX_AD1 D0/EX_AD0 WE1/WE CLKOUT
M_D8
M_D24
M_D25
N VCCQ-DDR VCCQ-DDR VSS VSS VSS VSS VSS VSS
M_D9
M_D26
M_D27
VSS
VDD
RD/FRAME/ EX_FRAME
WE0/PCC_REG
A1
A0
P VSSQ-DDR VSSQ-DDR VSS VSS VSS VSS VSS
M_D10
M_D28
M_D29
VSS
VSS
VSSQ
A9
A8
A3
A2
R VCCQ-DDR VCCQ-DDR VSS VSS VSS VSS VSS
M_D11
M_D30
M_D31
VSS
VSS
VCCQ
A11
A10
A5
A4
T VSS VCCQ-DDR VCCQ-DDR VSS VSS VSS
VSS
VSS
AVss VSS A17 A16 A7 A6
M_D13
M_D12
VSSQ-DDR
U VSSQ-DDR VSSQ-DDR VDD A19 A18 A13 A12
M_D15
M_D14
VSSQ-DDR
V VDD VDD VSS A21 A20 A15 A14
Figure 1.2 Pin Arrangement
PTF0/GNT0/ GNTIN/SIM_D/ ET1_ETXD3/DREQ3 VDD PTD7/PCIRESET/ PCC_RESET/ GET1_ETXD7/ LCDM_VEPWC VSS PTG4/AD30/ ET1_LINKSTA VSSQ VSSQ VDD VDD VCCQ VCCQ VDD VCCQ VCCQ VSSQ VCCQ VSSQ VSSQ VCCQ VSSQ VCCQ PTE4/AD22/ SCIF2_RXD/ GET1_ERXD4/ SSI0_SDATA PTD4/STOP/ PTD5/AD18/PCC_CD2/ PTD3/PCIFRAME/ PCC_BVD2/ PCC_CD1/ GET1_ERXD6/ PTA3/AD15/ SIOF0_SCK/HAC_RES/ SIOF0_MCLK/ SSI1_SDATA/ LCDM_D12 SSI1_WS/LCDM_DON SCIF1_CTS LCDM_D14 PTB2/AD11/ PINT10/LCDM_D7 PTB6/CBE0/ PINT14/LCDM_D3 PTC1/AD4/ LCDM_D1 PTC2/AD2/ LCDM_D0 PTA4/AD13/ SCIF1_RTS PTB3/AD9/PINT11/ PTB7/AD6/PINT15/ LCDM_D6 LCDM_D2 VSSQ VCCQ MPMD PTO6/IRQ0/IRL0/ DACK1M//MD5 PTO2/AUDATA1/ RMII0M1_MDC VCCQ PTH1/IDSEL/ TPU_TI3B/ ET1_RX-ER/ RMII1M_CRS_DV PTE2/AD16/ PCC_IOIS16/ GET1_ERXD7/ TEND2 PTD2/TRDY/PCC_RDY/ SIOF0_RXD/ PTA0/PAR/ HAC_SYNC/ LCDM_D11 SCIF1_SCK PTE3/AD20/ SCIF2_SCK/ GET1_ERXD5/ SSI0_WS PTC5/AD0/ MMC_CD/ LCDM_FLM PTN2/SCIF0_TXD/ MD1 MRESET PTO7/IRQ1/IRL1/ TEND1M/ SSI3_SCK/MD6 PTO3/AUDATA2/ RMII0M1_MDIO/ SSI2_SCK PTH2/AD24/ TPU_TI2A/ ET1_ERXD0/ RMII1M_TXD1 PTH7/AD17/ TPU_TO3/ ET1_RX-DV PTD0/IRDY/PCC_VS1/ SIOF0_SYNC/ PTA2/LOCK/ HAC_SD_IN/ LCDM_D13 SCIF1_TXD PTH3/AD21/ TPU_TI2B/ ET1_ERXD2/ RMII1M_RXD1 PTB1/SERR/ PINT9/LCDM_D9 PTB5/AD14/ PINT13/ LCDM_M_DISP PTC0/AD10/ MMC_DAT/ LCDM_D5 PTC4/AD7/ MMC_CMD/ LCDM_CL2 PTC7/AD3/ MMC_CLK PTN0/ SCIF0_SCK/MD0 PTN3/ SCIF0_CTS/MD4 PTN5/NMI PTO0/AUDSYNC/ PTO4/AUDATA3/ RMII1_MDC/ EX_INT/SSI3_WS SSI2_WS PTH5/AD23/ TPU_TO1/ ET1_ERXD1/ RMII1M_TXD0 PTH4/AD19/ TPU_TO0/ ET1_ERXD3/ RMII1M_RXD0 PTD1/CBE2/PCC_VS2/ SIOF0_TXD/ PTA1/DEVSEL/ HAC_SD_OUT/ LCDM_D15 SCIF1_RXD PTB0/PERR/ PINT8/LCDM_D10 PTB4/CBE1/ PINT12/LCDM_D8 PTA5/AD12 PTC3/AD8/ MMC_ODMOD/ LCDM_D4 PTC6/AD5/ LCDM_CL1 PTA6/AD1/ MMC_VDDON PTN4/ PTN1/ SCIF0_RXD/MD3 SCIF0_RTS/MD2 PRESET PTO1/AUDATA0/ RMII1_MDIO/ SSI2_SDATA PTO5/AUDCK/ DREQ1M/ SSI3_SDATA
VDD
VDD
VDD
W
PTG1/GNT2/ ET1_ETXD0
PTG3/REQ3/ ET1_ETXD2
VDD
A25/EX_SIZE2
A24/EX_SIZE1
A23/EX_SIZE0
A22
Y
PTE1/PCICLK/ GET1_ETXD4/ DACK2
PTG2/REQ1/ ET1_ETXD1 PTD6/REQ2/ PCC_BVD1/ GET1_ETXD5/ SSI1_SCK/ LCDM_VCPWC
PTE0/INTA/ PCC_DRV/ GET1_ETXD6/ DREQ2
VCCQ
CE2A
CE2B
DA1
DA0
AA
PTF1/REQ0/REQOUT/ SIM_CLK/ET1_MDC/ PTF2/AD31/SIM_RST/ PTG0/GNT1/ ET1_WOL DACK3 ET1_MDIO/TEND3
VSSQ
VCCQ
VSSQ
VSSQ
IOIS16/TMU_TCLK
AVcc
AVcc
AB
PTE5/AD29/ SCIF2_TXD/ GET1_GTX-CLK/ SSI0_SCK
PTG7/AD28/ ET1_TX-EN
PTG6/AD26/ ET1_TX-ER
VSSQ
TDO
VSSQ
VSSQ
VCCQ
AN3
AN2
AC
PTH6/AD27/ TPU_TO2/ ET1_CRS/ RMII1M_TXD_EN
PTH0/AD25/ TPU_TI3A/ ET1_COL/ RMII1M_RX_ER
VSSQ
TRST
TDI
TMS
BACK
AVss
AN1
AN0
AD
PTF3/CBE3/ ET1_TX-CLK
VSSQ
VCCQ
ASEBRK/ BRKACK
Vss-PLL3
Vss-PLL2
BREQ
VCCQ
Vss-PLL1
AVcc
AE
Section 1 Overview
Rev. 1.00 Oct. 01, 2007 Page 15 of 1956
VSSQ
VCCQ
PTG5/GNT3/ ET1_RX-CLK
TCK
Vdd-PLL3
Vdd-PLL2
EXTAL
XTAL
Vdd-PLL1
VSSQ
REJ09B0256-0100
Section 1 Overview
Table 1.2
Pin Configuration
I/O I O O O O O O O O O IO Function DDR-SDRAM I/O GND DDR-SDRAM I/O VCC DDR-SDRAM VREF DDR-SDRAM clock DDR-SDRAM clock DDR-SDRAM write enable DDR-SDRAM RAS DDR-SDRAM bank active DDR-SDRAM address bus DDR-SDRAM address bus DDR-SDRAM address bus Crystal resonator for RTC DPort/ST data sync/IIC serial clock/SIOF receive data/USB overcurrent detection/USB cable connection monitor pin Port/status 0/ST data clock/ RMII management data clock Port/ST data/ETHER receive data/ SIOF transmit data/LCD data Port/external interrupt input/ST data (mirror pin)/IIC serial clock Port/ST data (mirror pin)/Ether receive data/RMII receive data/LCD display start Power Supply VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VDD_RTC VCCQ VCCQ
Pin No. Pin Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 VSSQ-DDR VCCQ-DDR M_VREF M_CLK0 M_CLK1 M_WE M_RAS M_BA0 M_A10 M_A1 M_A3 XTAL2 USBM
PTI2/ST0M_STARTI/IIC0_SCL/ I/I/IO/I/I/I SIOF1_RXD/USB_OVRCRT/ USBF_VBUS PTI0/STATUS0/ST1_CLK/ RMII0_MDC PTK4/ST1_D4/GET0_ERXD4/ SIOF2_TXD/LCD_D6 PTI6/IRQ2/IRL2/ST0M_D6I/ IIC1_SCL PTJ5/ST0M_D3I/ET0_ERXD3/ RMII1_RXD0/LCD_DON IO/O/IO/O IO/IO/I/O/O I/I/I/I/IO IO/I/I/I/O
A15 A16 A17 A18
VCCQ VCCQ VCCQ VCCQ
Rev. 1.00 Oct. 01, 2007 Page 16 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name A19 A20 A21 PTJ1/ST0M_CLKIO/ RMII1_RX_ER/LCD_CLK CS5/CE1A PTM6/D30/EX_AD30/ST0_D6/ ET0_RX-CLK/RMII0_TXD1/ PINT6 PTM4/D28/EX_AD28/ST0_D4/ ET0_PHY-INT/RMII0_RXD0/ PINT4 CS0 VSSQ VSSQ VCCQ-DDR VSSQ-DDR M_BKPRST M_CKE M_A13 M_CAS M_CS M_BA1 M_A0 M_A2 M_A4 EXTAL2 USBP
I/O IO/IO/I/I O/O
Function Port/ST data clock RMII receive error/LCD clock source Chip select/Card select
Power Supply VCCQ VCCQ
VCCQ IO/IO/IO/IO/I/O/I Port/data bus/address-and-data bus/ST data/ETHER receive clock/ RMII transmit data/port interrupt input IO/IO/IO/IO/I/I/I Port/data bus/address-and-data bus/ST data/ PHY interrupt/RMII receive data/port interrupt input Chip select I/O GND I/O GND DDR-SDRAM I/O VCC DDR-SDRAM I/O GND DDR-SDRAM power supply backup reset DDR-SDRAM clock enable DDR-SDRAM address bus DDR-SDRAM CAS DDR-SDRAM chip select DDR-SDRAM bank active DDR-SDRAM address bus DDR-SDRAM address bus DDR-SDRAM address bus Crystal resonator for RTC D+ VCCQ
A22
A23 A24 A25 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13
O I O O O O O O O O I IO
VCCQ VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VDD_RTC VCCQ
Rev. 1.00 Oct. 01, 2007 Page 17 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name B14 PTI3/ST0M_VALIDI/IIC0_SDA/ SIOF1_MCLK/USB_CLK PTK7/ST1_D7/GET0_ERXD7/ SIOF2_MCLK/LCD_VCPWC PTI5/MD10/ST1_VALID/ LCD_D1 PTI7/IRQ3/IRL3/ST0M_D7I/ IIC1_SDA PTJ4/ST0M_D2I/ET0_ERXD2/ RMII1_RXD1/LCD_CL2 RDY/EX_RDY/PCC_WAIT CS2/EX_CS1 PTM7/D31/EX_AD31/ST0_D7/ ET0_RX-DV/RMII0_TXD0/ PINT7 PTM5/D29/EX_AD29/ST0_D5/ ET0_RX-ER/RMII0_TXD_EN/ PINT5 VSSQ PTM3/D27/EX_AD27/ST0_D3/ ET0_LINKSTA/RMII0_RXD1/ PINT3 REF125CK/ SSI_CLK/HAC_BITCLK M_D0 VCCQ-DDR VSSQ-DDR VCCQ-DDR
I/O I/I/IO/I/I
Function Port/ST data valid (mirror pin)/IIC serial data/ SIOF master clock/USB clock input Port/ST data /ETHER receive data/SIOF master clock/LCD power supply control
Power Supply VCCQ
B15
IO/IO/I/I/O
VCCQ
B16
IO/I /IO/O
VCCQ Port/mode control (external CPU connection select)/ST data valid/LCD data Port/external interrupt input/ST data (mirror pin)/ IIC serial data Port/ST data (mirror pin)/ETHER receive data/RMII receive data/LCD shift clock Ready/external CPU ready/PCMCIA hardware wait request Chip select VCCQ
B17
I/I/I/I/IO
B18
IO/I/I/I/O
VCCQ
B19 B20 B21
I/O/I O/I
VCCQ VCCQ
VCCQ IO/IO/IO/IO/I/O/I Port/data bus/address-and-data bus/ST data/ETHER receive data valid/RMII transmit data/port interrupt input IO/IO/IO/IO/I/O/I Port/data bus/address-and-data bus/ST data/ETHER receive error/RMII transmit enable/port interrupt input IO/IO/IO/IO/I/I/I I/O GND Port/data bus/address-and-data bus/ST data/ETHER link status/RMII receive data/port interrupt input 125-MHz reference clock/SSI divider input clock/HAC clock DDR-SDRAM data bus DDR-SDRAM I/O VCC DDR-SDRAM I/O GND DDR-SDRAM I/O VCC VCCQ
B22
B23 B24
VCCQ
B25 C1 C2 C3 C4
I/I/I IO
VCCQ VCCQ_ DDR
Rev. 1.00 Oct. 01, 2007 Page 18 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 M_A12 M_A11 M_A9 M_A8 M_A7 M_A6 M_A5 XRTCSTBI VCCQ PTI1/STATUS1/ST1_REQ/ RMII0_MDIO PTK6/ST1_D6/GET0_ERXD6/ SIOF2_SCK/LCD_VEPWC
I/O O O O O O O O I IO/O/IO/IO
Function DDR-SDRAM address bus DDR-SDRAM address bus DDR-SDRAM address bus DDR-SDRAM address bus DDR-SDRAM address bus DDR-SDRAM address bus DDR-SDRAM address bus RTC standby I/O VCC Port/status 1/ST data receive preparation request/RMII management data IO Port/ST data/ETHER receive data/SIOF serial clock/LCD power supply control
Power Supply VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VDD_RTC VCCQ
C15
IO/IO/I/IO/O
VCCQ
C16
IO/I /IO/I/O/O/O PTI4/MD8/ST1_START/ ET1_PHY-INT/RMII0M0_MDC/ USB_PWREN/USBF_UPLUP
VCCQ Port/mode control (clock input mode)/ST data sync/PHY interrupt/RMII management data clock/USB power supply enable/USB Pull-up control output pin Port/PCI interrupt/ST data (mirror pin)/interrupt request output/RMII transmit data/LCD data Port/ST data (mirror pin)/ETHER receive data/RMII carrier detection/LCD shift clock Chip select/Card select Chip select I/O VCC VCCQ
C17
PTJ7/INTB/ST0M_D5I/ IO/I/I/O/O/O IRQOUT/RMII1_TXD0/LCD_D0 PTJ3/ST0M_D1I/ET0_ERXD1/ RMII1_CRS_DV/LCD_CL1 CS6/CE1B CS1/EX_CS0 VCCQ IO/I/I/I/O
C18
VCCQ
C19 C20 C21
O/O O/I
VCCQ VCCQ
Rev. 1.00 Oct. 01, 2007 Page 19 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name C22 C23 C24 VSSQ BS/EX_BS PTM2/D26/EX_AD26/ST0_D2/ ET0_WOL/RMII0_CRS_DV/ PINT2 PTM1/D25/EX_AD25/ST0_D1/ ET0_TX-CLK/RMII0_RX_ER/ PINT1 M_D1 M_D16 VCCQ-DDR VSSQ-DDR VSSQ-DDR VSSQ-DDR VCCQ-DDR VCCQ-DDR VSSQ-DDR VSSQ-DDR VCCQ-DDR VDD-RTC VSSQ VSSQ PTK5/ST1_D5/GET0_ERXD5/ SIOF2_RXD/LCD_D7 VCCQ PTJ6/ST0M_D4I/ET0_CRS/ RMII1_TXD_EN/LCD_FLM PTJ2/ST0M_D0I/ ET0_ERXD0/RMII1_TXD1/ LCD_M_DISP
I/O O/I
Function I/O GND Bus cycle start
Power Supply VCCQ VCCQ
IO/IO/IO/IO/O/I/I Port/data bus/address-and-data bus/ST data/ETHER wake on run/RMII carrier detection/port interrupt input IO/IO/IO/IO/I/I/I
C25
VCCQ Port/data bus/address-and-data bus/ST data/ETHER transmit clock/RMII receive error/port interrupt input DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM I/O VCC DDR-SDRAM I/O GND DDR-SDRAM I/O GND DDR-SDRAM I/O GND DDR-SDRAM I/O VCC DDR-SDRAM I/O VCC DDR-SDRAM I/O GND DDR-SDRAM I/O GND DDR-SDRAM I/O VCC RTC VDD I/O GND I/O GND Port/ST data/ETHER receive data/SIOF receive data/LCD data I/O VCC Port/ST data (mirror pin)/ETHER carrier detection/RMII transmit enable/LCD line marker Port/ST data (mirror pin)/ETHER receive data/RMII transmit data/LCD liquid crystal AC signal VCCQ_ DDR VCCQ_ DDR VCCQ VCCQ
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17
IO IO IO/IO/I/I/O IO/I/I/O/O
D18
IO/I/I/O/O
VCCQ
Rev. 1.00 Oct. 01, 2007 Page 20 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name D19 D20 D21 D22 D23 D24 CS4 VDD VSSQ VCCQ RDWR/EX_RDWR PTM0/D24/EX_AD24/ST0_D0/ ET0_TX-ER/PINT0/ RMII0M0_MDIO PTL7/D23/EX_AD23/ ST0_VALID/ET0_TX-EN/ TEND1/LCD_D15 M_D2 M_D17 M_D18 VCCQ-DDR VCCQ-DDR VSSQ-DDR VCCQ-DDR VDD VSS VSSQ-DDR VCCQ-DDR VSS-RTC VSS VCCQ VSSQ VDD VSS VCCQ
I/O O O/I
Function Chip select Internal VDD I/O GND I/O VCC Read/write
Power Supply VCCQ VCCQ VCCQ
IO/IO/IO/IO/O/I/I Port/data bus/address-and-data O bus/ST data/ETHER transmit error/port interrupt input/RMII management data IO IO/IO/IO/IO/O/O/ Port/data bus/address-and-data O bus/ST data valid/ETHER transmit enable/DMA transfer end/LCD data IO IO IO DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM I/O VCC DDR-SDRAM I/O VCC DDR-SDRAM I/O GND DDR-SDRAM I/O VCC Internal VDD Internal GND DDR-SDRAM I/O GND DDR-SDRAM I/O VCC RTC GND Internal GND I/O VCC I/O GND Internal VDD Internal GND I/O VCC
D25
VCCQ
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18
VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR
Rev. 1.00 Oct. 01, 2007 Page 21 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name E19 E20 E21 E22 E23 E24 VSSQ VSS VCCQ PTK3/ST1_D3/GET0_ETXD7/ SIOF2_SYNC/LCD_D5 PTK2/ST1_D2/GET0_ETXD6/ SIOF1_SCK/LCD_D4 PTL6/D22/EX_AD22/ ST0_START/ET0_ETXD2/ DACK1/LCD_D14
I/O IO/IO/O/IO/O IO/IO/O/IO/O
Function I/O GND Internal GND I/O VCC Port/ST data/ETHER transmit data/SIOF frame sync/LCD data Port/ST data/ETHER transmit data/SIOF serial clock/LCD data
Power Supply VCCQ VCCQ VCCQ
IO/IO/IO/IO/O/O/ Port/data bus/address-and-data O bus/ST data sync/ETHER transmit data/DMA transfer request acknowledge/LCD data Port/data bus/address-and-data bus/ST data clock/ETHER transmit data/DMA transfer request/LCD data DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM I/O GND DDR-SDRAM I/O GND Internal GND Port/ST data/ETHER transmit data/SIOF transmit data/LCD data Port/ST data/ETHER transmit data/SIOF frame sync/LCD data Port/data bus/address-and-data bus/ST data receive preparation request/ETHER transmit data/PCI interrupt/LCD data Port/ST data receive preparation request (mirror pin)/GMII transmit clock/50-MHz reference clock DDR-SDRAM data bus
E25
PTL5/D21/EX_AD21/ST0_CLK/ IO/IO/IO/IO/O/I/ ET0_ETXD1/DREQ1/LCD_D13 O M_D3 M_D19 M_D20 VSSQ-DDR VSSQ-DDR VSS PTK1/ST1_D1/GET0_ETXD5/ SIOF1_TXD/LCD_D3 PTK0/ST1_D0/GET0_ETXD4/ SIOF1_SYNC/LCD_D2 PTL4/D20/EX_AD20/ ST0_REQ/ET0_ETXD0/INTD/ LCD_D12 PTJ0/ST0M_REQO/ GET0_GTX-CLK/REF50CK M_D4 IO IO IO IO/IO/O/O/O IO/IO/O/IO/O IO/IO/IO/IO/O/I/ O
VCCQ
F1 F2 F3 F4 F5 F21 F22 F23 F24
VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ VCCQ VCCQ
F25
IO/O/O/I
VCCQ
G1
IO
VCCQ_ DDR
Rev. 1.00 Oct. 01, 2007 Page 22 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name G2 G3 G4 G5 G21 G22 M_D21 M_D22 VCCQ-DDR VCCQ-DDR VDD PTL3/D19/EX_AD19/IRQ7/ IRL7/ET0_MDIO/INTC/ LCD_D11 PTL2/D18/EX_AD18/IRQ6/ IRL6/ET0_ETXD3/TEND0/ LCD_D10 WE3/IOWR WE2/IORD M_D5 M_D23 M_DQS2 VSSQ-DDR VSSQ-DDR VCCQ PTL0/D16/EX_AD16/IRQ4/ IRL4/ET0_COL/DREQ0/ LCD_D8 PTL1/D17/EX_AD17/IRQ5/ IRL5/ET0_MDC/DACK0/ LCD_D9 D15/EX_AD15 D14/EX_AD14
I/O IO IO
Function DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM I/O VCC DDR-SDRAM I/O VCC Internal VDD
Power Supply VCCQ_ DDR VCCQ_ DDR VCCQ
IO/IO/IO/I/I/IO/I/ Port/data bus/address-and-data O bus/external interrupt input/ETHER management data IO/PCI interrupt/LCD data IO/IO/IO/I/I/O/O/ Port/data bus/address-and-data O bus/external interrupt input/ETHER transmit data/DMA transfer end/LCD data O/O O/O IO IO IO Data enable/PCMCIA IOWR Data enable/PCMCIA IORD DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM data strobe DDR-SDRAM I/O GND DDR-SDRAM I/O GND I/O VCC
G23
VCCQ
G24 G25 H1 H2 H3 H4 H5 H21 H22
VCCQ VCCQ VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ
IO/IO/IO/I/I/I/I/O Port/data bus/address-and-data bus/external interrupt input/ETHER collision detection/DMA transfer request/LCD data IO/IO/IO/I/I/O/O/ Port/data bus/address-and-data O bus/external interrupt input/ETHER management data clock/DMA transfer acknowledge/LCD data IO/IO IO/IO Data bus/address-and-data bus Data bus/address-and-data bus
H23
VCCQ
H24 H25
VCCQ VCCQ
Rev. 1.00 Oct. 01, 2007 Page 23 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name J1 J2 J3 J4 J5 J21 J22 J23 J24 J25 K1 K2 K3 K4 K5 K10 K11 K12 K13 K14 K15 K16 K21 K22 K23 K24 K25 M_D7 M_D6 M_DQM2 VSSQ-DDR VSSQ-DDR VSS D7/EX_AD7 D6/EX_AD6 D13/EX_AD13 D12/EX_AD12 M_DQM0 M_DQS0 M_DQS3 VCCQ-DDR VCCQ-DDR VSS VSS VSS VSS VSS VSS VSS VDD D5/EX_AD5 D4/EX_AD4 D11/EX_AD11 D10/EX_AD10
I/O IO IO O IO/IO IO/IO IO/IO IO/IO O IO IO IO/IO IO/IO IO/IO IO/IO
Function DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM data mask DDR-SDRAM I/O GND DDR-SDRAM I/O GND Internal GND Data bus/address-and-data bus Data bus/address-and-data bus Data bus/address-and-data bus Data bus/address-and-data bus DDR-SDRAM data mask DDR-SDRAM data strobe DDR-SDRAM data strobe DDR-SDRAM I/O VCC DDR-SDRAM I/O VCC Internal GND Internal GND Internal GND Internal GND Internal GND Internal GND Internal GND Internal VDD Data bus/address-and-data bus Data bus/address-and-data bus Data bus/address-and-data bus Data bus/address-and-data bus
Power Supply VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ VCCQ VCCQ VCCQ VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ VCCQ VCCQ VCCQ
Rev. 1.00 Oct. 01, 2007 Page 24 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name L1 L2 L3 L4 L5 L10 L11 L12 L13 L14 L15 L16 L21 L22 L23 L24 L25 M1 M2 M3 M4 M5 M10 M11 M12 M13 M14 M_DQS1 M_DQM1 M_DQM3 VSS-DLL1 VSS-DLL2 VSS VSS VSS VSS VSS VSS VSS VCCQ D3/EX_AD3 D2/EX_AD2 D9/EX_AD9 D8/EX_AD8 M_D8 M_D24 M_D25 VDD-DLL1 VDD-DLL2 VSS VSS VSS VSS VSS
I/O IO O O IO/IO IO/IO IO/IO IO/IO IO IO IO
Function DDR-SDRAM data strobe DDR-SDRAM data mask DDR-SDRAM data mask DLL1 GND DLL2 GND Internal GND Internal GND Internal GND Internal GND Internal GND Internal GND Internal GND I/O VCC Data bus/address-and-data bus Data bus/address-and-data bus Data bus/address-and-data bus Data bus/address-and-data bus DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM data bus DLL1 VDD DLL2 VDD Internal GND Internal GND Internal GND Internal GND Internal GND
Power Supply VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ VCCQ VCCQ VCCQ VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR
Rev. 1.00 Oct. 01, 2007 Page 25 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name M15 M16 M21 M22 M23 M24 M25 N1 N2 N3 N4 N5 N10 N11 N12 N13 N14 N15 N16 N21 N22 N23 N24 N25 P1 P2 P3 VSS VSS VSS D1/EX_AD1 D0/EX_AD0 WE1/WE CLKOUT M_D9 M_D26 M_D27 VCCQ-DDR VCCQ-DDR VSS VSS VSS VSS VSS VSS VSS VDD RD/FRAME/EX_FRAME WE0/PCC_REG A1 A0 M_D10 M_D28 M_D29
I/O IO/IO IO/IO O/O O IO IO IO O/O/I O/O O O IO IO IO
Function Internal GND Internal GND Internal GND Data bus/address-and-data bus Data bus/address-and-data bus Data enable/PCMCIA WE System clock output DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM I/O VCC DDR-SDRAM I/O VCC Internal GND Internal GND Internal GND Internal GND Internal GND Internal GND Internal GND Internal VDD Access cycle Data enable/PCMCIA REG Address bus Address bus DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM data bus
Power Supply VCCQ VCCQ VCCQ VCCQ VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ VCCQ VCCQ VCCQ VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR
Rev. 1.00 Oct. 01, 2007 Page 26 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name P4 P5 P10 P11 P12 P13 P14 P15 P16 P21 P22 P23 P24 P25 R1 R2 R3 R4 R5 R10 R11 R12 R13 R14 R15 R16 R21 R22 R23 VSSQ-DDR VSSQ-DDR VSS VSS VSS VSS VSS VSS VSS VSSQ A9 A8 A3 A2 M_D11 M_D30 M_D31 VCCQ-DDR VCCQ-DDR VSS VSS VSS VSS VSS VSS VSS VCCQ A11 A10
I/O O O O O IO IO IO O O
Function DDR-SDRAM I/O GND DDR-SDRAM I/O GND Internal GND Internal GND Internal GND Internal GND Internal GND Internal GND Internal GND I/O GND Address bus Address bus Address bus Address bus DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM I/O VCC DDR-SDRAM I/O VCC Internal GND Internal GND Internal GND Internal GND Internal GND Internal GND Internal GND I/O VCC Address bus Address bus
Power Supply VCCQ VCCQ VCCQ VCCQ VCCQ_ DDR VCCQ_ DDR VCCQ_ DDR VCCQ VCCQ
Rev. 1.00 Oct. 01, 2007 Page 27 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name R24 R25 T1 T2 T3 T4 T5 T10 T11 T12 T13 T14 T15 T16 T21 T22 T23 T24 T25 U1 U2 U3 U4 U5 U21 U22 U23 U24 A5 A4 M_D13 M_D12 VSSQ-DDR VCCQ-DDR VCCQ-DDR VSS VSS VSS VSS VSS VSS AVss VSS A17 A16 A7 A6 M_D15 M_D14 VSSQ-DDR VSSQ-DDR VSSQ-DDR VDD A19 A18 A13
I/O O O IO IO O O O O IO IO O O O
Function Address bus Address bus DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM I/O GND DDR-SDRAM I/O VCC DDR-SDRAM I/O VCC Internal GND Internal GND Internal GND Internal GND Internal GND Internal GND Analog GND Internal GND Address bus Address bus Address bus Address bus DDR-SDRAM data bus DDR-SDRAM data bus DDR-SDRAM I/O GND DDR-SDRAM I/O GND DDR-SDRAM I/O GND Internal VDD Address bus Address bus Address bus
Power Supply VCCQ VCCQ VCCQ_ DDR VCCQ_ DDR VCCQ VCCQ VCCQ VCCQ VCCQ_ DDR VCCQ_ DDR VCCQ VCCQ VCCQ
Rev. 1.00 Oct. 01, 2007 Page 28 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name U25 V1 V2 V3 V4 V5 V21 V22 V23 V24 V25 W1 W2 W3 W4 W5 W21 W22 W23 W24 W25 Y1 A12 VDD VDD VDD VDD VDD VSS A21 A20 A15 A14 PTG1/GNT2/ET1_ETXD0 PTG2/REQ1/ET1_ETXD1 PTG3/REQ3/ET1_ETXD2 PTF0/GNT0/GNTIN/SIM_D/ ET1_ETXD3/DREQ3 VDD VDD A25/EX_SIZE2 A24/EX_SIZE1 A23/EX_SIZE0 A22 PTE1/PCICLK/GET1_ETXD4/ DACK2 PTD6/REQ2/PCC_BVD1/ GET1_ETXD5/SSI1_SCK/ LCDM_VCPWC
I/O O O O O O IO/O/O IO/I/O IO/I/O IO/IO/I/IO/O/I O/I O/I O/I O IO/I/O/O
Function Address bus Internal VDD Internal VDD Internal VDD Internal VDD Internal VDD Internal GND Address bus Address bus Address bus Address bus Port/PCI bus grant/ETHER transmit data Port/PCI bus request/ETHER transmit data Port/PCI bus request/ETHER transmit data Port/PCI bus grant/SIM data/ETHER transmit data/DMA transfer request Internal VDD Internal VDD Address bus/access size Address bus/access size Address bus/access size Address bus Port/PCI input clock/GMII transmit data/DMA transfer request acknowledge Port/PCI bus mastership request (host)/PCMCIA BVD1/GMII transmit data/SSI serial bit clock/LCD power supply control (mirror pin)
Power Supply VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ
Y2
IO/I/I/O/IO/O
VCCQ
Rev. 1.00 Oct. 01, 2007 Page 29 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name Y3 PTE0/INTA/PCC_DRV/ GET1_ETXD6/DREQ2 PTD7/PCIRESET/ PCC_RESET/GET1_ETXD7/ LCDM_VEPWC VSS VCCQ CE2A CE2B DA1 DA0 PTF1/REQ0/REQOUT/ SIM_CLK/ET1_MDC/DACK3
I/O IO/IO/O/O/I
Function Port/PCI interrupt/PCMCIA buffer control/GMII transmit data/DMA transfer request Port/PCI reset/PCMCIA reset/GMII transmit data/LCD power supply control (mirror pin) Internal GND I/O VCC PCMCIA select PCMCIA select Analog output Analog output Port/PCI bus mastership request (host)/PCI bus mastership request output/SIM clock output/ETHER management data clock/DMA transfer request acknowledge Port/PCI address-and-data bus/SIM reset/ETHER management data IO/DMA transfer end Port/PCI bus GND/ETHER wake on LAN Port/PCI address-and-data bus/ ETHER link status I/O GND I/O VCC I/O GND I/O VCC Internal VDD Internal VDD Internal VDD I/O VCC I/O VCC I/O GND
Power Supply VCCQ
Y4
O/O/O/O/O
VCCQ
Y5 Y21 Y22 Y23 Y24 Y25 AA1
O O O O IO/IO/O/O/O/O
VCCQ VCCQ AVcc AVcc VCCQ
AA2
PTF2/AD31/SIM_RST/ ET1_MDIO/TEND3 PTG0/GNT1/ET1_WOL PTG4/AD30/ET1_LINKSTA VSSQ VCCQ VSSQ VCCQ VDD VDD VDD VCCQ VCCQ VSSQ
IO/IO/O/IO/O
VCCQ
AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14
IO/O/O IO/IO/I
VCCQ VCCQ
Rev. 1.00 Oct. 01, 2007 Page 30 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AB1 VCCQ VSSQ VSSQ VCCQ VSSQ VCCQ VSSQ VSSQ IOIS16/TMU_TCLK AVcc AVcc PTE5/AD29/SCIF2_TXD/ GET1_GTX-CLK/SSI0_SCK PTG7/AD28/ET1_TX-EN PTG6/AD26/ET1_TX-ER VSSQ VCCQ PTE4/AD22/SCIF2_RXD/ GET1_ERXD4/SSI0_SDATA PTD5/AD18/PCC_CD2/ GET1_ERXD6/SSI1_SDATA/ LCDM_D14
I/O I/I IO/IO/O/O/IO
Function I/O VCC I/O GND I/O GND I/O VCC I/O GND I/O VCC I/O GND I/O GND PCMCIA16-bit IO/TMU clock Analog VCC Analog VCC
Power Supply VCCQ
Port/PCI address-and-data bus/SCIF VCCQ transmit data/GMII transmit clock/SSI serial bit clock Port/PCI address-and-data bus/ ETHER transmit enable Port/PCI address-and-data bus/ ETHER transmit error I/O GND I/O VCC VCCQ VCCQ
AB2 AB3 AB4 AB5 AB6
IO/IO/O IO/IO/O IO/IO/I/I/IO
Port/PCI address-and-data bus/SCIF VCCQ receive data/GMII receive data/SSI serial data IO Port/PCI address-and-data bus/PCMCIA CD2/GMII receive data/SSI serial data IO/LCD data (mirror pin) Port/PCI cycle frame/PCMCIA BVD2/SIOF serial clock/HAC reset/LCD data (mirror pin) Port/PCI stop/PCMCIA CD1/SIOF master clock/SSI word select/LCD display start (mirror pin) VCCQ
AB7
IO/IO/I/I/IO/O
AB8
PTD3/PCIFRAME/PCC_BVD2/ IO/IO/I/IO/O/O SIOF0_SCK/HAC_RES/ LCDM_D12 PTD4/STOP/PCC_CD1/ SIOF0_MCLK/SSI1_WS/ LCDM_DON PTA3/AD15/SCIF1_CTS IO/IO/I/I/IO/O
VCCQ
AB9
VCCQ
AB10
IO/IO/IO
Port/PCI address-and-data bus/SCIF VCCQ modem control (CTS)
Rev. 1.00 Oct. 01, 2007 Page 31 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name AB11 AB12
I/O
Function Port/PCI address-and-data bus/port interrupt input/LCD data (mirror pin) Port/PCI command and byte enable/port interrupt input/LCD data (mirror pin) Port/PCI address-and-data bus/LCD data (mirror pin) I/O GND I/O VCC Chip mode specification
Power Supply VCCQ VCCQ
PTB2/AD11/PINT10/LCDM_D7 IO/IO/I/O PTB6/CBE0/PINT14/ LCDM_D3 PTC1/AD4/LCDM_D1 VSSQ VCCQ MPMD PTO6/IRQ0/IRL0/ DACK1M/MD5 PTO2/AUDATA1/ RMII0M1_MDC VSSQ TDO VSSQ VSSQ VCCQ AN3 AN2 PTH6/AD27/TPU_TO2/ ET1_CRS/RMII1M_TXD_EN IO/IO/I/O
AB13 AB14 AB15 AB16 AB17
IO/IO/O I IO/I/I/O/I
VCCQ VCCQ
VCCQ Port/external interrupt input/DMA transfer request acknowledge (mirror pin)/mode control (endian switching) Port/AUD data/RMII management data clock I/O GND H-UDI data output I/O GND I/O GND I/O VCC Analog input Analog input Port/PCI address-and-data bus/TPU clock output/ETHER carrier detection/RMII transmit enable (mirror pin) Port/PCI address-and-data bus/TPU clock input/ETHER collision detection/RMII receive error (mirror pin) I/O GND I/O VCC Port/PCI configuration device select/TPU clock input/ETHER receive error/RMII carrier detection (mirror pin) VCCQ VCCQ AVcc AVcc VCCQ
AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AC1
IO/O/O O I I IO/IO/O/I/O
AC2
PTH0/AD25/TPU_TI3A/ ET1_COL/RMII1M_RX_ER
IO/IO/I/I/I
VCCQ
AC3 AC4 AC5
VSSQ VCCQ

VCCQ
PTH1/IDSEL/TPU_TI3B/ IO/I/I/I/I ET1_RX-ER/RMII1M_CRS_DV
Rev. 1.00 Oct. 01, 2007 Page 32 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name AC6 PTE3/AD20/SCIF2_SCK/ GET1_ERXD5/SSI0_WS PTE2/AD16/PCC_IOIS16/ GET1_ERXD7/TEND2 PTD2/TRDY/PCC_RDY/ SIOF0_RXD/HAC_SYNC/ LCDM_D11 PTA0/PAR/SCIF1_SCK PTA4/AD13/SCIF1_RTS PTB3/AD9/PINT11/LCDM_D6 PTB7/AD6/PINT15/LCDM_D2 PTC2/AD2/LCDM_D0 PTC5/AD0/MMC_CD/ LCDM_FLM PTN2/SCIF0_TXD/MD1 MRESET PTO7/IRQ1/IRL1/TEND1M/ SSI3_SCK/MD6
I/O IO/IO/IO/I/IO
Function Port/PCI address-and-data bus/IrDA serial clock /GMII receive data/SSI word select Port/PCI address-and-data bus/PCMCIA 16-bit IO/GMII receive data/DMA transmit end Port/PCI target ready/PCMCIA ready/SIOF receive data/HAC frame sync/LCD data (mirror pin) Port/PCI parity signal/SCIF serial clock
Power Supply VCCQ
AC7
IO/IO/I/I/O
VCCQ
AC8
IO/IO/I/I/O/O
VCCQ
AC9 AC10 AC11 AC12 AC13 AC14
IO/IO/IO IO/IO/IO IO/IO/I/O IO/IO/I/O IO/IO/O IO/IO/I/O
VCCQ
Port/PCI address-and-data bus/SCIF VCCQ modem control (RTS) Port/PCI address-and-data bus/port interrupt input/LCD data (mirror pin) Port/PCI address-and-data bus/port interrupt input/LCD data (mirror pin) Port/PCI address-and-data bus/LCD data (mirror pin) VCCQ VCCQ VCCQ
Port/PCI address-and-data bus/MMC VCCQ card detection/LCD line marker (mirror pin) Port/SCIF transmit data/mode control VCCQ (clock operating mode) Manual rest input VCCQ
AC15 AC16 AC17
IO/O/I I IO/I/I/O/IO/I
Port/external interrupt input/DMA VCCQ transfer end (mirror pin)/SSI serial bit clock/mode control (PCI operating mode select) Port/AUD data/RMII management data IO/SSI serial bit clock H-UDI reset input H-UDI data input H-UDI mode input Bus usage permission Analog GND VCCQ VCCQ VCCQ VCCQ VCCQ
AC18 AC19 AC20 AC21 AC22 AC23
PTO3/AUDATA2/ RMII0M1_MDIO/SSI2_SCK TRST TDI TMS BACK AVss
IO/O/IO/IO I I I O
Rev. 1.00 Oct. 01, 2007 Page 33 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name AC24 AC25 AD1 AD2 AD3 AD4 AN1 AN0 PTF3/CBE3/ET1_TX-CLK VSSQ VCCQ PTH2/AD24/TPU_TI2A/ ET1_ERXD0/RMII1M_TXD1 PTH3/AD21/TPU_TI2B/ ET1_ERXD2/RMII1M_RXD1 PTH7/AD17/TPU_TO3/ ET1_RX-DV PTD0/IRDY/PCC_VS1/ SIOF0_SYNC/HAC_SD_IN/ LCDM_D13 PTA2/LOCK/SCIF1_TXD PTB1/SERR/PINT9/ LCDM_D9 PTB5/AD14/PINT13/ LCDM_M_DISP PTC0/AD10/MMC_DAT/ LCDM_D5 PTC4/AD7/MMC_CMD LCDM_CL2 PTC7/AD3/MMC_CLK PTN0/SCIF0_SCK/MD0 PTN3/SCIF0_CTS/MD4
I/O I I IO/IO/I IO/IO/I/I/O
Function Analog input Analog input Port/PCI command and byte enable/transmit clock I/O GND I/O VCC
Power Supply AVcc AVcc VCCQ
Port/PCI address-and-data bus/TPU VCCQ clock input/ETHER receive data/RMII transmit data (mirror pin) Port/PCI address-and-data bus/TPU VCCQ clock input/ETHER receive data/RMII receive data (mirror pin) Port/PCI address-and-data bus/TPU clock output/ETHER receive data valid Port/PCI initiator ready/PCMCIA VS1/SIOF frame sync/HAC serial data input/LCD data (mirror pin) Port/PCI lock/SCIF transmit data Port/PCI parity error/port interrupt input/ LCD data (mirror pin) Port/PCI address-and-data bus/port interrupt input/LCD liquid crystal AC signal (mirror pin) VCCQ
AD5
IO/IO/I/I/I
AD6
IO/IO/O/I
AD7
IO/IO/I/IO/I/O
VCCQ
AD8 AD9 AD10
IO/IO/O IO/IO/I/O IO/IO/I/O
VCCQ VCCQ VCCQ
AD11 AD12 AD13 AD14 AD15
IO/IO/IO/O IO/IO/IO/O IO/IO/O IO/IO/I IO/IO/I
Port/PCI address-and-data bus/MMC VCCQ DAT/LCD data (mirror pin) Port/PCI address-and-data bus/MMC VCCQ CMD/LCD shift clock (mirror pin) Port/PCI address-and-data bus/MMC VCCQ clock output Port/SCIF serial clock/mode control (clock operating mode) Port/SCIF modem control (CTS)/mode control (bus width for area 0) Port/non-maskable interrupt input VCCQ VCCQ
AD16
PTN5/NMI
IO/I
VCCQ
Rev. 1.00 Oct. 01, 2007 Page 34 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name AD17 PTO0/AUDSYNC/ RMII1_MDC/SSI2_WS PTO4/AUDATA3/EX_INT/ SSI3_WS ASEBRK/BRKACK VSS-PLL3 VSS-PLL2 BREQ VCCQ VSS-PLL1 AVcc VSSQ VCCQ PTG5/GNT3/ET1_RX-CLK PTH5/AD23/TPU_TO1/ ET1_ERXD1/RMII1M_TXD0 PTH4/AD19/TPU_TO0/ ET1_ERXD3/RMII1M_RXD0 PTD1/CBE2/PCC_VS2/ SIOF0_TXD/HAC_SD_OUT/ LCDM_D15 PTA1/DEVSEL/SCIF1_RXD PTB0/PERR/PINT8/ LCDM_D10 PTB4/CBE1/PINT12/ LCDM_D8 PTA5/AD12
I/O IO/O/O/IO
Function Port/AUD sync signal/RMII management data clock/SSI word select Port/AUD data/external CPU interrupt/SSI word select Break mode acknowledge PLL3 GND PLL2 GND Bus release request I/O VCC PLL1 GND Analog VCC I/O GND I/O VCC Port/PCI bus grant/ETHER receive clock Port/PCI address-and-data bus/TPU clock output/ETHER receive data/RMII transmit data (mirror pin) Port/PCI address-and-data bus/TPU clock output/ETHER receive data/RMII receive data (mirror pin) Port/PCI command-and-byte enable/PCMCIA VS2/SIOF transmit data/HAC serial data output/LCD data (mirror pin) Port/PCI device select/SCIF receive data Port/PCI system error/port interrupt input/LCD data (mirror pin) Port/PCI command-and-byte enable/port interrupt input/LCD data (mirror pin) Port/PCI address-and-data bus
Power Supply VCCQ
AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AE1 AE2 AE3 AE4
IO/O/O/IO IO I IO/O/I IO/IO/O/I/O
VCCQ VCCQ VCCQ VCCQ VCCQ
AE5
IO/IO/O/I/I
VCCQ
AE6
IO/IO/I/O/O/O
VCCQ
AE7 AE8 AE9
IO/IO/I IO/IO/I/O IO/IO/I/O
VCCQ VCCQ VCCQ
AE10
IO/IO
VCCQ
Rev. 1.00 Oct. 01, 2007 Page 35 of 1956 REJ09B0256-0100
Section 1 Overview
Pin No. Pin Name AE11 PTC3/AD8/MMC_ODMOD/ LCDM_D4 PTC6/AD5/LCDM_CL1 PTA6/AD1/MMC_VDDON PTN1/SCIF0_RXD/MD3 PTN4/SCIF0_RTS/MD2
I/O IO/IO/O/O
Function
Power Supply
Port/PCI address-and-data bus/MMC VCCQ open-drain control/LCD data (mirror pin) Port/PCI address-and-data bus/LCD shift clock (mirror pin) VCCQ
AE12 AE13 AE14 AE15
IO/IO/O IO/IO/O IO/I/I IO/IO/I
Port/PCI address-and-data bus/MMC VCCQ card power supply control Port/SCIF receive data/mode control (bus width for area 0) Port/SCIF modem control (RTS)/mode control (clock operating mode) Power-on reset Port/AUD data/RMII management data IO/SSI serial data IO VCCQ VCCQ
AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25
PRESET PTO1/AUDATA0/ RMII1_MDIO/SSI2_SDATA PTO5/AUDCK/DREQ1M/ SSI3_SDATA TCK VDD-PLL3 VDD-PLL2 EXTAL XTAL VDD-PLL1 VSSQ
I IO/O/IO/IO IO/O/I/IO I I O
VCCQ VCCQ
Port/AUD clock/DMA transfer request VCCQ (mirror pin)/SSI serial data IO H-UDI clock PLL3 VDD PLL2 VDD VCCQ
External clock input/crystal resonator VCCQ Crystal resonator PLL1 VDD I/O GND VCCQ
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Section 2 Programming Model
Section 2 Programming Model
The programming model of this LSI is explained in this section. This LSI has registers and data formats as shown below.
2.1
Data Formats
The data formats supported in this LSI are shown in figure 2.1.
7 Byte (8 bits) 0
15 Word (16 bits)
0
31 Longword (32 bits)
0
Single-precision floating-point (32 bits)
31 30 s e
22 f
0
Double-precision floating-point (64 bits)
[Legend] s: Sign field e: Exponent field f: Fraction field
63 62 s e
51 f
0
Figure 2.1 Data Formats
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Section 2 Programming Model
2.2
2.2.1 (1)
Register Descriptions
Privileged Mode and Banks Processing Modes
This LSI has two processing modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers--general registers, system registers, control registers, and floating-point registers--and the registers that can be accessed differ in the two processing modes. (2) General Registers
There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processing mode change. * Privileged mode In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC/STC instructions. When the RB bit is 0 (that is, when bank 0 is selected), the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are accessed by the LDC/STC instructions. * User mode In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. The eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed.
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Section 2 Programming Model
(3)
Control Registers
Control registers comprise the global base register (GBR) and status register (SR), which can be accessed in both processing modes, and the saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register (DBR), which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. (4) System Registers
System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register (PR), and the program counter (PC). Access to these registers does not depend on the processing mode. (5) Floating-Point Registers and System Registers Related to FPU
There are thirty-two floating-point registers, FR0-FR15 and XF0-XF15. FR0-FR15 and XF0- XF15 can be assigned to either of two banks (FPR0_BANK0-FPR15_BANK0 or FPR0_BANK1- FPR15_BANK1). FR0-FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floatingpoint registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0- XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX. System registers related to the FPU comprise the floating-point communication register (FPUL) and the floating-point status/control register (FPSCR). These registers are used for communication between the FPU and the CPU, and the exception handling setting. Register values after a reset are shown in table 2.1.
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Section 2 Programming Model
Table 2.1
Type
Initial Register Values
Registers Initial Value* Undefined
General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, R8 to R15 Control registers SR
MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, IMASK = B'1111, reserved bits = 0, others = undefined
GBR, SSR, SPC, SGR, DBR Undefined VBR System registers MACH, MACL, PR PC Floating-point registers Note: * FR0 to FR15, XF0 to XF15, FPUL FPSCR H'00000000 Undefined H'A0000000 Undefined H'00040001
Initialized by a power-on reset and manual reset.
The CPU register configuration in each processing mode is shown in figure 2.2. User mode and privileged mode are switched by the processing mode bit (MD) in the status register.
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Section 2 Programming Model
31 R0_BANK0*1,*2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 SR
0
31 R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC SGR DBR
0
31 R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC SGR DBR
0
GBR MACH MACL PR
PC
(a) Register configuration in user mode
R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 (b) Register configuration in privileged mode (RB = 1)
R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 (c) Register configuration in privileged mode (RB = 0)
Notes: 1. R0 is used as the index register in indexed register-indirect addressing mode and indexed GBR indirect addressing mode. 2. Banked registers 3. Banked registers Accessed as general registers when the RB bit is set to 1 in SR. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. 4. Banked registers Accessed as general registers when the RB bit is cleared to 0 in SR. Accessed only by LDC/STC instructions when the RB bit is set to 1.
Figure 2.2 CPU Register Configuration in Each Processing Mode
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Section 2 Programming Model
2.2.2
General Registers
Figure 2.3 shows the relationship between the processing modes and general registers. This LSI has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of these can be accessed as general registers R0 to R15 in one processing mode. This LSI has two processing modes, user mode and privileged mode. * R0_BANK0 to R7_BANK0 Allocated to R0 to R7 in user mode (SR.MD = 0) Allocated to R0 to R7 when SR.RB = 0 in privileged mode (SR.MD = 1). * R0_BANK1 to R7_BANK1 Cannot be accessed in user mode. Allocated to R0 to R7 when SR.RB = 1 in privileged mode.
SR.MD = 0 or (SR.MD = 1, SR.RB = 0) R0 R1 R2 R3 R4 R5 R6 R7 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15
(SR.MD = 1, SR.RB = 1) R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Figure 2.3 General Registers
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Section 2 Programming Model
Note on Programming:
As the user's R0 to R7 are assigned to R0_BANK0 to R7_BANK0, and after an exception or interrupt R0 to R7 are assigned to R0_BANK1 to R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0 to R7 (R0_BANK0 to R7_BANK0).
2.2.3
Floating-Point Registers
Figure 2.4 shows the floating-point register configuration. There are thirty-two 32-bit floatingpoint registers, FPR0_BANK0 to FPR15_BANK0, AND FPR0_BANK1 to FPR15_BANK1, comprising two banks. These registers are referenced as FR0 to FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0 to XF15, XD0/2/4/6/8/10/12/14, or XMTRX. Reference names of each register are defined depending on the state of the FR bit in FPSCR (see figure 2.4). 1. Floating-point registers, FPRn_BANKj (32 registers) FPR0_BANK0 to FPR15_BANK0 FPR0_BANK1 to FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0 to FR15 are assigned to FPR0_BANK0 to FPR15_BANK0; when FPSCR.FR = 1, FR0 to FR15 are assigned to FPR0_BANK1 to FPR15_BANK1. 3. Double-precision floating-point registers or single-precision floating-point registers, DRi (8 registers): A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} 4. Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises four FR registers. FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7}, FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15} 5. Single-precision floating-point extended registers, XFi (16 registers) When FPSCR.FR = 0, XF0 to XF15 are assigned to FPR0_BANK1 to FPR15_BANK1; when FPSCR.FR = 1, XF0 to XF15 are assigned to FPR0_BANK0 to FPR15_BANK0. 6. Double-precision floating-point extended registers, XDi (8 registers): An XD register comprises two XF registers. XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15}
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Section 2 Programming Model
7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15
FPSCR.FR=1
FPSCR.FR=0
FV0
DR0 DR2
FV4
DR4 DR6
FV8
DR8 DR10
FV12
DR12 DR14
FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15
FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 FPR11_BANK0 FPR12_BANK0 FPR13_BANK0 FPR14_BANK0 FPR15_BANK0 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1
XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15
XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14
XMTRX
XMTRX
XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14
DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14
FV0
FV4
FV8
FV12
Figure 2.4 Floating-Point Registers
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Section 2 Programming Model
2.2.4 (1)
Control Registers Status Register (SR)
BIt:
31
0 R 15
30
MD 1 R/W 14
0 R
29
RB 1 R/W 13
0 R
28
BL 1 R/W 12
0 R
27
0 R 11
0 R
26
0 R 10
0 R
25
0 R 9 M 0 R/W
24
0 R 8 Q 0 R/W
23
0 R 7
1 R/W
22
0 R 6
21
0 R 5
20
0 R 4
1 R/W
19
0 R 3
0 R
18
0 R 2
0 R
17
0 R 1 S 0 R/W
16 0 R
0
Initial value: R/W:
BIt:
FD Initial value: 0 R/W: R/W
IMASK 1 1 R/W R/W
T 0 R/W
Bit 31
Bit Name --
Initial Value 0
R/W R
Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
30
MD
1
R/W
Processing Mode Selects the processing mode. 0: User mode (Some instructions cannot be executed and some resources cannot be accessed.) 1: Privileged mode This bit is set to 1 by an exception or interrupt.
29
RB
1
R/W
Privileged Mode General Register Bank Specification Bit 0: R0_BANK0 to R7_BANK0 are accessed as general registers R0 to R7 and R0_BANK1 to R7_BANK1 can be accessed using LDC/STC instructions 1: R0_BANK1 to R7_BANK1 are accessed as general registers R0 to R7 and R0_BANK0-R7_BANK0 can be accessed using LDC/STC instructions This bit is set to 1 by an exception or interrupt.
28
BL
1
R/W
Exception/Interrupt Block Bit This bit is set to 1 by a reset, an exception, or an interrupt. While this bit is set to 1, an interrupt request is masked. In this case, this processor enters the reset state when a general exception other than a user break occurs.
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Section 2 Programming Model
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
27 to 16 --
15
FD
0
R/W
FPU Disable Bit When this bit is set to 1 and an FPU instruction is not in a delay slot, a general FPU disable exception occurs. When this bit is set to 1 and an FPU instruction is in a delay slot, a slot FPU disable exception occurs. (FPU instructions: H'F*** instructions and LDS (.L)/STS(.L) instructions using FPUL/FPSCR)
14 to 10 --
All 0
R
Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
9 8 7 to 4
M Q IMASK
0 0 All 1
R/W R/W R/W
M Bit Used by the DIV0S, DIV0U, and DIV1 instructions. Q Bit Used by the DIV0S, DIV0U, and DIV1 instructions. Interrupt Mask Level Bits An interrupt whose priority is equal to or less than the value of the IMASK bits is masked. It can be chosen by CPU operation mode register (CPUOPM) whether the level of IMASK is changed to accept an interrupt or not when an interrupt is occurred. For details, see appendix A, CPU Operation Mode Register (CPUOPM).
3, 2
--
All 0
R
Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
1 0
S T
0 0
R/W R/W
S Bit Used by the MAC instruction. T Bit Indicates true/false condition, carry/borrow, or overflow/underflow. For details, see section 3, Instruction Set.
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Section 2 Programming Model
(2)
Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined)
The contents of SR are saved to SSR in the event of an exception or interrupt. (3) Saved Program Counter (SPC) (32 bits, Privileged Mode, Initial Value = Undefined)
The address of an instruction at which an interrupt or exception occurs is saved to SPC. (4) Global Base Register (GBR) (32 bits, Initial Value = Undefined)
GBR is referenced as the base address of addressing @(disp,GBR) and @(R0,GBR). (5) Vector Base Register (VBR) (32 bits, Privileged Mode, Initial Value = H'00000000)
VBR is referenced as the branch destination base address in the event of an exception or interrupt. For details, see section 5, Exception Handling. (6) Saved General Register 15 (SGR) (32 bits, Privileged Mode, Initial Value = Undefined)
The contents of R15 are saved to SGR in the event of an exception or interrupt. (7) Debug Base Register (DBR) (32 bits, Privileged Mode, Initial Value = Undefined)
When the user break debugging function is enabled (CBCR.UBDE = 1), DBR is referenced as the branch destination address of the user break handler instead of VBR. 2.2.5 (1) System Registers Multiply-and-Accumulate Registers (MACH and MACL) (32 bits, Initial Value = Undefined)
MACH and MACL are used for the added value in a MAC instruction, and to store the operation result of a MAC or MUL instruction. (2) Procedure Register (PR) (32 bits, Initial Value = Undefined)
The return address is stored in PR in a subroutine call using a BSR, BSRF, or JSR instruction. PR is referenced by the subroutine return instruction (RTS). (3) Program Counter (PC) (32 bits, Initial Value = H'A0000000)
PC indicates the address of the instruction currently being executed.
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Section 2 Programming Model
(4)
Floating-Point Status/Control Register (FPSCR)
BIt:
31
0 R 15
0 R/W
30
0 R 14
0 R/W
29
0 R 13
0 R/W
28
0 R 12
0 R/W
27
0 R 11
0 R/W
26
0 R 10
0 R/W
25
0 R 9
24
0 R 8
0 R/W
23
0 R 7
0 R/W
22
0 R 6
0 R/W
21
FR
20
SZ
19
PR
18
DN
17
0 R/W 1
RM
16 0 R/W
0 1 R/W
Cause
Initial value: R/W: BIt: Initial value: R/W:
0 R/W 5
0 R/W
0 R/W 4
Flag
0 R/W 3
0 R/W
1 R/W 2
0 R/W
Cause
Enable (EN)
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
31 to 22 --
21
FR
0
R/W
Floating-Point Register Bank 0: FPR0_BANK0 to FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 are assigned to XF0 to XF15 1: FPR0_BANK0 to FPR15_BANK0 are assigned to XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1 are assigned to FR0 to FR15
20
SZ
0
R/W
Transfer Size Mode 0: Data size of FMOV instruction is 32-bits 1: Data size of FMOV instruction is a 32-bit register pair (64 bits) For relationship between the SZ bit, PR bit, and endian, see figure 2.5.
19
PR
0
R/W
Precision Mode 0: Floating-point instructions are executed as single-precision operations 1: Floating-point instructions are executed as double-precision operations (graphics support instructions are undefined) For relationship between the SZ bit, PR bit, and endian, see figure 2.5
18
DN
1
R/W
Denormalization Mode 0: Denormalized number is treated as such 1: Denormalized number is treated as zero
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Section 2 Programming Model
Bit
Bit Name
Initial Value All 0
R/W R/W R/W R/W
Description FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0. When an FPU exception occurs, the bits corresponding to FPU exception cause field and flag field are set to 1. The FPU exception flag field remains set to 1 until it is cleared to 0 by software. For bit allocations of each field, see table 2.2.
17 to 12 Cause 11 to 7 6 to 2
Enable (EN) All 0 Flag All 0
1, 0
RM
01
R/W
Rounding Mode These bits select the rounding mode. 00: Round to Nearest 01: Round to Zero 10: Reserved 11: Reserved
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Section 2 Programming Model

Floating-point register
63 DR (2i) 63 FR (2i) FR (2i+1)
0
0
63 Memory area 8n
32 31 8n+3 8n+4
0 8n+7

Floating-point register
63 DR (2i)
0
63 DR (2i)
0 *2
63 DR (2i)
0
*1, *2 63 FR (2i) FR (2i+1) 0 63 FR (2i)
0 FR (2i+1)
63 FR (2i) FR (2i+1)
0
63 Memory area 4n+3
32 31 4n 4m+3 (1) SZ = 0
0 4m
63 8n+3
32 31 8n 8n+7 (2) SZ = 1, PR = 0
0 8n+4
63 8n+7
32 31 8n+4 8n+3 (3) SZ = 1, PR = 1
0 8n
Notes: 1. In the case of SZ = 0 and PR = 0, DR register can not be used. 2. The bit-location of DR register is used for double precision format when PR = 1. (In the case of (2), it is used when PR is changed from 0 to 1.)
Figure 2.5 Relationship between SZ bit and Endian Table 2.2
Field Name Cause Enable Flag FPU exception cause field FPU exception enable field
Bit Allocation for FPU Exception Handling
FPU Error (E) Bit 17 None Invalid Division Operation (V) by Zero (Z) Bit 16 Bit 11 Bit 6 Bit 15 Bit 10 Bit 5 Overflow Underflow Inexact (O) (U) (I) Bit 14 Bit 9 Bit 4 Bit 13 Bit 8 Bit 3 Bit 12 Bit 7 Bit 2
FPU exception flag None field
(5)
Floating-Point Communication Register (FPUL) (32 bits, Initial Value = Undefined)
Information is transferred between the FPU and CPU via FPUL.
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Section 2 Programming Model
2.3
Memory-Mapped Registers
Some control registers are mapped to the following memory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are used as follows. * H'1C00 0000 to H'1FFF FFFF This area must be accessed using the address translation function of the MMU. Setting the page number of this area to the corresponding field of the TLB enables access to a memory-mapped register. The operation of an access to this area without using the address translation function of the MMU is not guaranteed. * H'FC00 0000 to H'FFFF FFFF Access to area H'FC00 0000 to H'FFFF FFFF in user mode will cause an address error. Memory-mapped registers can be referenced in user mode by means of access that involves address translation. Note: Do not access addresses to which registers are not mapped in either area. The operation of an access to an address with no register mapped is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined.
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Section 2 Programming Model
2.4
Data Formats in Registers
Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
76 S
0
31 S
76 S
0
15 14 S
0
31 S
15 14 S
0
Figure 2.6 Formats of Byte Data and Word Data in Register
2.5
Data Formats in Memory
Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in an 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being loaded into a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big endian or little endian byte order can be selected for the data format. The endian should be set with the external pin after a power-on reset. The endian cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. The data format in memory is shown in figure 2.7.
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Section 2 Programming Model
A
31 7 07
A+1
23 07
A+2
15 7 07
A+3
0 0
A + 11 A + 10 A + 9
31 7 23 07 15 07 7 07
A+8
0 0
Address A Byte 0 Byte 1 Byte 2 Byte 3 Address A + 4 Address A + 8
15 0 15
Byte 3 Byte 2 Byte 1 Byte 0 Address A + 8
0 15 0
0
15
Word 0
31
Word 1
0 31
Word 1
Word 0
0
Address A + 4 Address A
Longword
Longword
Big endian
Little endian
Figure 2.7 Data Formats in Memory For the 64-bit data format, see figure 2.5.
2.6
Processing States
This LSI has major three processing states: the reset state, instruction execution state, and powerdown state. (1) Reset State
In this state the CPU is reset. The reset state is divided into the power-on reset state and the manual reset. In the power-on reset state, the internal state of the CPU and the on-chip peripheral module registers are initialized. In the manual reset state, the internal state of the CPU and some registers of on-chip peripheral modules are initialized. For details, see register descriptions for each section. (2) Instruction Execution State
In this state, the CPU executes program instructions in sequence. The Instruction execution state has the normal program execution state and the exception handling state. (3) Power-Down State
In a power-down state, CPU halts operation and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are two modes in the power-down state: sleep mode and standby mode.
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Section 2 Programming Model
From any state when reset/manual reset input
Reset state
Reset/manual reset clearance
Reset/manual reset input
Reset/manual reset input
Instruction execution state
Sleep instruction execution
Interrupt occurence
Power-down state
Figure 2.8 Processing State Transitions
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Section 2 Programming Model
2.7
2.7.1
Usage Note
Notes on Self-Modified Codes*
This LSI prefetches instructions more drastically than conventional SH-4 to accelerate the processing speed. Therefore if the instruction in the memory is modified and it is executed immediately, then the pre-modified code that is prefetched are likely to be executed. In order to execute the modified code definitely, one of the following sequences should be executed between the execution of modifying codes and modified codes. (1) In case the modified codes are in non-cacheable area
SYNCO ICBI @Rn
The target for the ICBI instruction can be any address within the range where no address error exception occurs. (2) In case the modified codes are in cacheable area (write-through)
SYNCO ICBI @Rn
The all instruction cache area corresponding to the modified codes should be invalidated by the ICBI instruction. The ICBI instruction should be issued to each cache line. One cache line is 32 bytes. (3) In case the modified codes are in cacheable area (copy-back)
OCBP @Rm or OCBWB @Rm SYNCO ICBI @Rn
The all operand cache area corresponding to the modified codes should be written back to the main memory by the OCBP or OCBWB instruction. Then the all instruction cache area corresponding to the modified codes should be invalidated by the ICBI instruction. The OCBP, OCBWB and ICBI instruction should be issued to each cache line. One cache line is 32 bytes. Note: * Processes executed while changing the instructions on the memory dynamically.
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Section 2 Programming Model
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Section 3 Instruction Set
Section 3 Instruction Set
This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved to and from memory using longword or quadword size. Double-precision floating-point data (64 bits) can be moved to and from memory using longword size. When this LSI moves byte-size or word-size data from memory to a register, the data is sign-extended.
3.1
Execution Environment
PC: At the start of instruction execution, the PC indicates the address of the instruction itself. Load-Store Architecture: This LSI has a load-store architecture in which operations are basically executed using registers. Except for bit-manipulation operations such as logical AND that are executed directly in memory, operands in an operation that requires memory access are loaded into registers and the operation is executed between the registers. Delayed Branches: Except for the two branch instructions BF and BT, this LSI's branch instructions and RTE are delayed branches. In a delayed branch, the instruction following the branch is executed before the branch destination instruction. Delay Slot: This execution slot following a delayed branch is called a delay slot. For example, the BRA execution sequence is as follows: Table 3.1 Execution Order of Delayed Branch Instructions
Instructions BRA ADD : : TARGET target-inst (Branch destination instruction) TARGET (Delayed branch instruction) (Delay slot) Execution Order BRA ADD target-inst
A slot illegal instruction exception may occur when a specific instruction is executed in a delay slot. For details, see section 5, Exception Handling. The instruction following BF/S or BT/S for which the branch is not taken is also a delay slot instruction.
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Section 3 Instruction Set
T Bit: The T bit in SR is used to show the result of a compare operation, and is referenced by a conditional branch instruction. An example of the use of a conditional branch instruction is shown below. ADD #1, R0 CMP/EQ R1, R0 BT TARGET ; T bit is not changed by ADD operation ; If R0 = R1, T bit is set to 1 ; Branches to TARGET if T bit = 1 (R0 = R1)
In an RTE delay slot, the SR bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits--S, T, M, Q, FD, BL, and RB--after modification are used for delay slot instruction execution. The STC and STC.L SR instructions access all SR bits after modification. Constant Values: An 8-bit constant value can be specified by the instruction code and an immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in memory, and can be referenced by a PC-relative load instruction. MOV.W @(disp, PC), Rn MOV.L @(disp, PC), Rn There are no PC-relative load instructions for floating-point operations. However, it is possible to set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point register.
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Section 3 Instruction Set
3.2
Addressing Modes
Addressing modes and effective address calculation methods are shown in table 3.2. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (SV in MMUCR = 0), the least significant bit of PTEH is also referenced as the access ASID. For details, see section 6, Memory Management Unit (MMU). Table 3.2 Addressing Modes and Effective Addresses
Effective Address Calculation Method Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents.
Rn Rn
Addressing Instruction Mode Format Register direct Register indirect Register indirect with postincrement Rn @Rn
Calculation Formula -- Rn EA (EA: effective address)
Rn EA After instruction execution Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Quadword: Rn + 8 Rn
@Rn+
Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand.
Rn
Rn + 1/2/4/8
Rn
+
1/2/4/8
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Section 3 Instruction Set
Addressing Instruction Mode Format Register indirect with predecrement @-Rn
Effective Address Calculation Method Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand.
Rn
Rn - 1/2/4/8
Calculation Formula
Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn Quadword: Rn - 8 Rn Rn EA (Instruction executed with Rn after calculation) Byte: Rn + disp EA Word: Rn + disp x 2 EA Longword: Rn + disp x 4 EA
-
Rn - 1/2/4/8
1/2/4/8
Register @(disp:4, Rn) Effective address is register Rn contents with indirect with 4-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size.
Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4
Indexed register indirect
@(R0, Rn)
Effective address is sum of register Rn and R0 contents.
Rn
+
Rn + R0 EA
Rn + R0
R0
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Section 3 Instruction Set
Addressing Instruction Mode Format GBR indirect @(disp:8, with GBR) displacement
Effective Address Calculation Method Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size.
GBR
disp (zero-extended)
Calculation Formula
Byte: GBR + disp EA Word: GBR + disp x 2 EA Longword: GBR + disp x 4 EA
+ x
GBR + disp x 1/2/4
1/2/4
Indexed GBR @(R0, GBR) indirect
Effective address is sum of register GBR and R0 contents.
GBR
+
GBR + R0 EA
GBR + R0
R0
PC-relative @(disp:8, PC) Effective address is PC + 4 with 8-bit with displacement disp added. After disp is zerodisplacement extended, it is multiplied by 2 (word), or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked.
PC &* H'FFFF FFFC 4 + disp (zero-extended) x 2/4 * With longword operand +
PC + 4 + disp x2 or PC & H'FFFF FFFC + 4 + disp x 4
Word: PC + 4 + disp x 2 EA Longword: PC & H'FFFF FFFC + 4 + disp x 4 EA
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Section 3 Instruction Set
Addressing Instruction Mode Format PC-relative disp:8
Effective Address Calculation Method Effective address is PC + 4 with 8-bit displacement disp added after being sign-extended and multiplied by 2.
PC + 4
PC + 4 + disp x 2
Calculation Formula
PC + 4 + disp x 2 BranchTarget
+ disp (sign-extended) x
2
PC-relative
disp:12
Effective address is PC + 4 with 12-bit displacement disp added after being sign-extended and multiplied by 2.
PC + 4
PC + 4 + disp x 2
PC + 4 + disp x 2 BranchTarget
+ disp (sign-extended) x
2
Rn
Effective address is sum of PC + 4 and Rn.
PC
+
PC + 4 + Rn Branch-Target
4
Rn
+
PC + 4 + Rn
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Section 3 Instruction Set
Addressing Instruction Mode Format Immediate #imm:8 #imm:8 #imm:8
Effective Address Calculation Method 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended.
Calculation Formula -- --
8-bit immediate data imm of TRAPA instruction is -- zero-extended and multiplied by 4.
Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (x1, x2, or x4) is performed according to the operand size. This is done to clarify the operation of the LSI. Refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, GBR) ; GBR indirect with displacement @ (disp:8, PC) ; PC-relative with displacement disp:8, disp:12 ; PC-relative
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Section 3 Instruction Set
3.3
Instruction Set
Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13. Table 3.3
Item Instruction mnemonic
Notation Used in Instruction List
Format OP.Sz SRC, DEST Description OP: Sz: SRC: DEST: Rm: Rn: imm: disp: , (xx) M/Q/T & | Operation code Size Source operand Source and/or destination operand Source register Destination register Immediate data Displacement
Operation notation
Transfer direction Memory operand SR flag bits Logical AND of individual bits Logical OR of individual bits Logical exclusive-OR of individual bits ~ Logical NOT of individual bits <>n n-bit shift MSB LSB mmmm: nnnn: 0000: 0001: : 1111: mmm: nnn: 000: 001: : 111: mm: nn: 00: 01: 10: 11: iiii: dddd: Register number (Rm, FRm) Register number (Rn, FRn) R0, FR0 R1, FR1 R15, FR15 Register number (DRm, XDm, Rm_BANK) Register number (DRn, XDn, Rn_BANK) DR0, XD0, R0_BANK DR2, XD2, R1_BANK DR14, XD14, R7_BANK Register number (FVm) Register number (FVn) FV0 FV4 FV8 FV12 Immediate data Displacement
Instruction code
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Section 3 Instruction Set
Item Privileged mode T bit New
Format
Description "Privileged" means the instruction can only be executed in privileged mode.
Value of T bit after --: No change instruction execution "New" means the instruction which is newly added in this LSI.
Note: Scaling (x1, x2, x4, or x8) is executed according to the size of the instruction operand.
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Section 3 Instruction Set
Table 3.4
Instruction MOV MOV.W MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B
Fixed-Point Transfer Instructions
Operation imm sign extension Rn (disp x 2 + PC + 4) sign extension Rn Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd Privileged T Bit New -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
#imm,Rn
@(disp*,PC),Rn
@(disp*,PC),Rn
(disp x 4 + PC & H'FFFF FFFC 1101nnnndddddddd + 4) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) sign extension Rn (Rm) sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) (Rm) sign extension Rn, Rm + 1 Rm (Rm) sign extension Rn, Rm + 2 Rm (Rm) Rn, Rm + 4 Rm R0 (disp + Rn) R0 (disp x 2 + Rn) Rm (disp x 4 + Rn) (disp + Rm) sign extension R0 (disp x 2 + Rm) sign extension R0 (disp x 4 + Rm) Rn Rm (R0 + Rn) Rm (R0 + Rn) Rm (R0 + Rn) (R0 + Rm) sign extension Rn 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100
Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn
R0,@(disp*,Rn) R0,@(disp*,Rn) Rm,@(disp*,Rn) @(disp*,Rm),R0
@(disp*,Rm),R0
@(disp*,Rm),Rn
Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn
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Section 3 Instruction Set Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA @(R0,Rm),Rn @(R0,Rm),Rn Operation (R0 + Rm) sign extension Rn (R0 + Rm) Rn Instruction Code 0000nnnnmmmm1101 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd Privileged T Bit New -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
R0,@(disp*,GBR) R0 (disp + GBR) R0,@(disp*,GBR) R0 (disp x 2 + GBR) R0,@(disp*,GBR) R0 (disp x 4 + GBR) @(disp*,GBR),R0 (disp + GBR)
sign extension R0 sign extension R0
@(disp*,GBR),R0 (disp x 2 + GBR)
@(disp*,GBR),R0 (disp x 4 + GBR) R0
@(disp*,PC),R disp x 4 + 0 PC & H'FFFF FFFC + 4 R0 LDST T If (T == 1) R0 (Rn) 0 LDST 1 LDST (Rm) R0 When interrupt/exception occurred 0 LDST (Rm) R0 Load non-boundary alignment data
MOVCO. R0,@Rn L MOVLI.L @Rm,R0
0000nnnn01110011
LDST New
0000mmmm01100011
New
MOVUA.L @Rm,R0
0100mmmm10101001
New
MOVUA.L @Rm+,R0 MOVT SWAP.B Rn Rm,Rn
(Rm) R0, Rm + 4 Rm 0100mmmm11101001 Load non-boundary alignment data
-- -- -- --
-- -- -- --
New -- -- -- --
T Rn Rm swap lower 2 bytes Rn Rm swap upper/lower words Rn Rm:Rn middle 32 bits Rn
0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101
SWAP.W Rm,Rn XTRCT Rm,Rn
Note:
*
The assembler of Renesas uses the value after scaling (x1, x2, or x4) as the displacement (disp).
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Section 3 Instruction Set
Table 3.5
Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS
Arithmetic Operation Instructions
Operation Rn + Rm Rn Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 Privileged T Bit -- -- -- -- -- -- -- -- -- Carry Overflow New -- -- -- --
Rm,Rn
#imm,Rn Rn + imm Rn Rm,Rn Rm,Rn Rn + Rm + T Rn, carry T Rn + Rm Rn, overflow T
#imm,R0 When R0 = imm, 1 T Otherwise, 0 T Rm,Rn Rm,Rn When Rn = Rm, 1 T Otherwise, 0 T When Rn Rm (unsigned), 1T Otherwise, 0 T When Rn Rm (signed), 1T Otherwise, 0 T When Rn > Rm (unsigned), 1T Otherwise, 0 T When Rn > Rm (signed), 1T Otherwise, 0 T When Rn 0, 1 T Otherwise, 0 T When Rn > 0, 1 T Otherwise, 0 T When any bytes are equal, 1T Otherwise, 0 T 1-step division (Rn / Rm) MSB of Rn Q, MSB of Rm M, M^Q T 0 M/Q/T Signed, Rn x Rm MAC, 32 x 32 64 bits
Comparison -- result Comparison -- result Comparison -- result Comparison -- result Comparison -- result Comparison -- result Comparison -- result Comparison -- result Comparison -- result Calculation result Calculation result 0 -- -- -- -- --
CMP/GE
Rm,Rn
0011nnnnmmmm0011
--
CMP/HI
Rm,Rn
0011nnnnmmmm0110
--
CMP/GT
Rm,Rn
0011nnnnmmmm0111
--
CMP/PZ CMP/PL
CMP/STR
Rn Rn Rm,Rn
0100nnnn00010001 0100nnnn00010101 0010nnnnmmmm1100
-- -- --
DIV1 DIV0S DIV0U
Rm,Rn Rm,Rn
0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 0011nnnnmmmm1101
-- -- -- --
DMULS.L Rm,Rn
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Section 3 Instruction Set Instruction DMULU.L Rm,Rn Operation Unsigned, Rn x Rm MAC, 32 x 32 64 bits Rn - 1 Rn; when Rn = 0, 1T When Rn 0, 0 T Rm sign-extended from byte Rn Rm sign-extended from word Rn Rm zero-extended from byte Rn Rm zero-extended from word Rn (Rn) x (Rm) + MAC MAC Rn + 4 Rn, Rm + 4 Rm 32 x 32 + 64 64 bits MAC.W
@Rm+,@Rn+ Signed,
Instruction Code 0011nnnnmmmm0101
Privileged T Bit -- --
New --
DT
Rn
0100nnnn00010000
--
Comparison -- result
EXTS.B
Rm,Rn
0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
EXTS.W Rm,Rn EXTU.B Rm,Rn
EXTU.W Rm,Rn MAC.L
@Rm+,@Rn+ Signed,
0100nnnnmmmm1111
--
--
--
(Rn) x (Rm) + MAC MAC Rn + 2 Rn, Rm + 2 Rm 16 x 16 + 64 64 bits MUL.L Rm,Rn Rn x Rm MACL 32 x 32 32 bits Signed, Rn x Rm MACL 16 x 16 32 bits Unsigned, Rn x Rm MACL 16 x 16 32 bits 0 - Rm Rn 0 - Rm - T Rn, borrow T Rn - Rm Rn Rn - Rm - T Rn, borrow T Rn - Rm Rn, underflow T 0000nnnnmmmm0111 0010nnnnmmmm1111 -- -- -- -- -- --
MULS.W Rm,Rn
MULU.W Rm,Rn
0010nnnnmmmm1110
--
--
--
NEG NEGC SUB SUBC SUBV
Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn
0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011
-- -- -- -- --
-- Borrow -- Borrow Underflow
-- -- -- -- --
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Section 3 Instruction Set
Table 3.6
Instruction AND AND
Logic Operation Instructions
Operation Rn & Rm Rn R0 & imm R0 Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 Privileged T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Test result New -- -- -- -- -- -- -- --
Rm,Rn #imm,R0
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm (R0 + GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0
#imm,@(R0,GBR)
~Rm Rn Rn | Rm Rn R0 | imm R0 (R0 + GBR) | imm (R0 + GBR) When (Rn) = 0, 1 T Otherwise, 0 T In both cases, 1 MSB of (Rn) Rn & Rm; when result = 0, 1 T Otherwise, 0 T R0 & imm; when result = 0, 1 T Otherwise, 0 T
TAS.B @Rn
TST
Rm,Rn
0010nnnnmmmm1000
--
Test result Test result Test result -- -- --
--
TST
#imm,R0
11001000iiiiiiii
--
--
TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; when result = 0, 1 T Otherwise, 0 T XOR XOR Rm,Rn #imm,R0 Rn Rm Rn R0 imm R0
11001100iiiiiiii
--
--
0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii
-- -- --
-- -- --
XOR.B #imm,@(R0,GBR) (R0 + GBR) imm (R0 + GBR)
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Section 3 Instruction Set
Table 3.7
Instruction ROTL ROTR ROTCL ROTCR SHAD Rn Rn Rn Rn
Shift Instructions
Operation T Rn MSB LSB Rn T T Rn T T Rn T Instruction Code Privileged T Bit MSB LSB MSB LSB -- New -- -- -- -- --
0100nnnn00000100 -- 0100nnnn00000101 -- 0100nnnn00100100 -- 0100nnnn00100101 --
Rm,Rn
When Rm 0, Rn << Rm Rn 0100nnnnmmmm1100 -- When Rm < 0, Rn >> Rm [MSB Rn] T Rn 0 MSB Rn T 0100nnnn00100000 -- 0100nnnn00100001 --
SHAL SHAR SHLD
Rn Rn Rm,Rn
MSB LSB --
-- -- --
When Rm 0, Rn << Rm Rn 0100nnnnmmmm1101 -- When Rm < 0, Rn >> Rm [0 Rn] T Rn 0 0 Rn T Rn << 2 Rn Rn >> 2 Rn Rn << 8 Rn Rn >> 8 Rn Rn << 16 Rn Rn >> 16 Rn 0100nnnn00000000 -- 0100nnnn00000001 -- 0100nnnn00001000 -- 0100nnnn00001001 -- 0100nnnn00011000 -- 0100nnnn00011001 -- 0100nnnn00101000 -- 0100nnnn00101001 --
SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16
Rn Rn Rn Rn Rn Rn Rn Rn
MSB LSB -- -- -- -- -- --
-- -- -- -- -- -- -- --
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Section 3 Instruction Set
Table 3.8
Instruction BF
Branch Instructions
Operation label When T = 0, disp x 2 + PC + 4 PC When T = 1, nop Delayed branch; when T = 0, disp x 2 + PC + 4 PC When T = 1, nop When T = 1, disp x 2 + PC + 4 PC When T = 0, nop Delayed branch; when T = 1, disp x 2 + PC + 4 PC When T = 0, nop Delayed branch, disp x 2 + PC + 4 PC Instruction Code Privileged T Bit -- New --
10001011dddddddd --
BF/S
label
10001111dddddddd --
--
--
BT
label
10001001dddddddd --
--
--
BT/S
label
10001101dddddddd --
--
--
BRA BRAF BSR BSRF JMP JSR RTS
label Rn label Rn @Rn @Rn
1010dddddddddddd --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
Delayed branch, Rn + PC + 4 0000nnnn00100011 -- PC Delayed branch, PC + 4 PR, 1011dddddddddddd -- disp x 2 + PC + 4 PC Delayed branch, PC + 4 PR, 0000nnnn00000011 -- Rn + PC + 4 PC Delayed branch, Rn PC 0100nnnn00101011 -- Delayed branch, PC + 4 PR, 0100nnnn00001011 -- Rn PC Delayed branch, PR PC 0000000000001011 --
Table 3.9
Instruction CLRMAC CLRS CLRT ICBI
System Control Instructions
Operation 0 MACH, MACL 0S 0T @Rn Invalidates instruction cache block indicated by virtual address Rm SR Instruction Code 0000000000101000 0000000001001000 0000000000001000 0000nnnn11100011 Privileged T Bit -- -- -- -- -- 0 New -- -- -- New
LDC LDC LDC
Rm,SR
0100mmmm00001110 0100mmmm00011110 0100mmmm00101110
Privileged -- Privileged
LSB -- --
-- -- --
Rm,GBR Rm GBR Rm,VBR Rm VBR
Rev. 1.00 Oct. 01, 2007 Page 72 of 1956 REJ09B0256-0100
Section 3 Instruction Set Instruction LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L LDTLB MOVCA.L R0,@Rn NOP OCBI OCBP OCBWB PREF PREFI RTE SETS @Rn @Rn @Rn @Rn @Rn Rm,SGR Rm,SSR Rm,SPC Rm,DBR Rm,Rn_BANK @Rm+,SR @Rm+,GBR @Rm+,VBR @Rm+,SGR @Rm+,SSR @Rm+,SPC @Rm+,DBR Operation Rm SGR Rm SSR Rm SPC Rm DBR Rm Rn_BANK (n = 0 to 7) (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm (Rm) SGR, Rm + 4 Rm (Rm) SSR, Rm + 4 Rm (Rm) SPC, Rm + 4 Rm (Rm) DBR, Rm + 4 Rm Instruction Code Privileged T Bit New -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- New -- --
0100mmmm00111010 Privileged -- 0100mmmm00111110 Privileged -- 0100mmmm01001110 Privileged -- 0100mmmm11111010 Privileged -- 0100mmmm1nnn1110 Privileged -- 0100mmmm00000111 Privileged LSB 0100mmmm00010111 -- --
0100mmmm00100111 Privileged -- 0100mmmm00110110 Privileged -- 0100mmmm00110111 Privileged -- 0100mmmm01000111 Privileged -- 0100mmmm11110110 Privileged -- 0100mmmm1nnn0111 Privileged -- 0100mmmm00001010 -- 0100mmmm00011010 -- 0100mmmm00101010 -- -- -- -- -- -- --
@Rm+,Rn_BANK (Rm) Rn_BANK, Rm + 4 Rm Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR Rm MACH Rm MACL Rm PR
(Rm) MACH, Rm + 4 Rm 0100mmmm00000110 -- (Rm) MACL, Rm + 4 Rm 0100mmmm00010110 -- (Rm) PR, Rm + 4 Rm PTEH/PTEL TLB R0 (Rn) (without fetching cache block) No operation Invalidates operand cache block Writes back and invalidates operand cache block Writes back operand cache block (Rn) operand cache Reads 32-byte instruction block into instruction cache Delayed branch, SSR/SPC SR/PC 1S 0100mmmm00100110 --
0000000000111000 Privileged -- 0000nnnn11000011 -- 0000000000001001 -- 0000nnnn10010011 -- 0000nnnn10100011 -- 0000nnnn10110011 -- 0000nnnn10000011 -- 0000nnnn11010011 -- -- -- -- -- --
0000000000101011 Privileged -- 0000000001011000 -- --
Rev. 1.00 Oct. 01, 2007 Page 73 of 1956 REJ09B0256-0100
Section 3 Instruction Set Instruction SETT SLEEP STC STC STC STC STC STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L SR,Rn GBR,Rn VBR,Rn SSR,Rn SPC,Rn SGR,Rn DBR,Rn Rm_BANK,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn SSR,@-Rn SPC,@-Rn SGR,@-Rn DBR,@-Rn
Rm_BANK,@-Rn
Operation 1T Sleep or standby SR Rn GBR Rn VBR Rn SSR Rn SPC Rn SGR Rn DBR Rn Rm_BANK Rn (m = 0 to 7) Rn - 4 Rn, SR (Rn) Rn - 4 Rn, GBR (Rn) Rn - 4 Rn, VBR (Rn) Rn - 4 Rn, SSR (Rn) Rn - 4 Rn, SPC (Rn) Rn - 4 Rn, SGR (Rn) Rn - 4 Rn, DBR (Rn) Rn - 4 Rn, Rm_BANK (Rn) (m = 0 to 7) MACH Rn MACL Rn PR Rn Rn - 4 Rn, MACH (Rn) Rn - 4 Rn, MACL (Rn) Rn - 4 Rn, PR (Rn) Prevents the next instruction from being issued until instructions issued before this instruction have been completed.
Instruction Code
Privileged T Bit 1
New -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
0000000000011000 --
0000000000011011 Privileged -- 0000nnnn00000010 Privileged -- 0000nnnn00010010 -- --
0000nnnn00100010 Privileged -- 0000nnnn00110010 Privileged -- 0000nnnn01000010 Privileged -- 0000nnnn00111010 Privileged -- 0000nnnn11111010 Privileged -- 0000nnnn1mmm0010 Privileged -- 0100nnnn00000011 Privileged -- 0100nnnn00010011 -- --
0100nnnn00100011 Privileged -- 0100nnnn00110011 Privileged -- 0100nnnn01000011 Privileged -- 0100nnnn00110010 Privileged -- 0100nnnn11110010 Privileged -- 0100nnnn1mmm0011 Privileged --
STS STS STS STS.L STS.L STS.L SYNCO
MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn
0000nnnn00001010 -- 0000nnnn00011010 -- 0000nnnn00101010 -- 0100nnnn00000010 -- 0100nnnn00010010 -- 0100nnnn00100010 -- 0000000010101011
-- -- -- -- -- --
-- -- -- -- -- -- New
TRAPA
#imm
PC + 2 SPC, SR SSR, #imm << 2 TRA, H'160 EXPEVT, VBR + H'0100 PC
11000011iiiiiiii --
--
--
Rev. 1.00 Oct. 01, 2007 Page 74 of 1956 REJ09B0256-0100
Section 3 Instruction Set
Table 3.10 Floating-Point Single-Precision Instructions
Instruction FLDI0 FLDI1 FMOV FMOV.S FMOV.S FMOV.S FMOV.S FMOV.S FMOV.S FMOV FMOV FMOV FMOV FMOV FMOV FMOV FLDS FSTS FABS FADD FCMP/EQ FCMP/GT FDIV FLOAT FMAC FMUL FNEG FSQRT FSUB FTRC FRn FRn FRm,FRn @Rm,FRn Operation H'0000 0000 FRn H'3F80 0000 FRn FRm FRn (Rm) FRn Instruction Code Privileged T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- New -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1111nnnn10001101 -- 1111nnnn10011101 -- 1111nnnnmmmm1100 -- 1111nnnnmmmm1000 -- 1111nnnnmmmm0110 --
@(R0,Rm),FRn (R0 + Rm) FRn @Rm+,FRn FRm,@Rn FRm,@-Rn
(Rm) FRn, Rm + 4 Rm 1111nnnnmmmm1001 -- FRm (Rn) Rn-4 Rn, FRm (Rn) 1111nnnnmmmm1010 -- 1111nnnnmmmm1011 -- 1111nnnnmmmm0111 -- 1111nnn0mmm01100 -- 1111nnn0mmmm1000 -- 1111nnn0mmmm0110 --
FRm,@(R0,Rn) FRm (R0 + Rn) DRm,DRn @Rm,DRn DRm DRn (Rm) DRn
@(R0,Rm),DRn (R0 + Rm) DRn @Rm+,DRn DRm,@Rn DRm,@-Rn
(Rm) DRn, Rm + 8 Rm 1111nnn0mmmm1001 -- DRm (Rn) Rn-8 Rn, DRm (Rn) 1111nnnnmmm01010 -- 1111nnnnmmm01011 -- 1111nnnnmmm00111 -- 1111mmmm00011101 -- 1111nnnn00001101 --
DRm,@(R0,Rn) DRm (R0 + Rn) FRm,FPUL FPUL,FRn FRn FRm,FRn FRm,FRn FRm,FRn FRm,FRn FPUL,FRn FR0,FRm,FRn FRm,FRn FRn FRn FRm,FRn FRm,FPUL FRm FPUL FPUL FRn
FRn & H'7FFF FFFF FRn 1111nnnn01011101 -- FRn + FRm FRn When FRn = FRm, 1 T Otherwise, 0 T When FRn > FRm, 1 T Otherwise, 0 T FRn/FRm FRn (float) FPUL FRn FR0*FRm + FRn FRn FRn*FRm FRn FRn H'8000 0000 FRn FRn FRn FRn - FRm FRn (long) FRm FPUL 1111nnnnmmmm0000 -- 1111nnnnmmmm0100 -- 1111nnnnmmmm0101 -- 1111nnnnmmmm0011 -- 1111nnnn00101101 -- 1111nnnnmmmm1110 -- 1111nnnnmmmm0010 -- 1111nnnn01001101 -- 1111nnnn01101101 -- 1111nnnnmmmm0001 -- 1111mmmm00111101 --
Comparis -- on result Comparis -- on result
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
Rev. 1.00 Oct. 01, 2007 Page 75 of 1956 REJ09B0256-0100
Section 3 Instruction Set
Table 3.11 Floating-Point Double-Precision Instructions
Instruction FABS FADD FCMP/EQ DRn DRm,DRn DRm,DRn Operation DRn & H'7FFF FFFF FFFF FFFF DRn DRn + DRm DRn When DRn = DRm, 1 T Otherwise, 0 T When DRn > DRm, 1 T Otherwise, 0 T DRn /DRm DRn Instruction Code 1111nnn001011101 1111nnn0mmm00000 1111nnn0mmm00100 Privileged T Bit -- -- -- -- -- New -- --
Compari -- son result Compari -- son result -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
FCMP/GT
DRm,DRn
1111nnn0mmm00101
--
FDIV FCNVDS FCNVSD FLOAT FMUL FNEG FSQRT FSUB FTRC
DRm,DRn
1111nnn0mmm00011 1111mmm010111101 1111nnn010101101 1111nnn000101101 1111nnn0mmm00010 1111nnn001001101 1111nnn001101101 1111nnn0mmm00001 1111mmm000111101
-- -- -- -- -- -- -- -- --
DRm,FPUL double_to_ float(DRm) FPUL FPUL,DRn float_to_ double (FPUL) DRn FPUL,DRn (float)FPUL DRn DRm,DRn DRn DRn DRm,DRn DRn *DRm DRn DRn ^ H'8000 0000 0000 0000 DRn DRn DRn DRn - DRm DRn
DRm,FPUL (long) DRm FPUL
Table 3.12 Floating-Point Control Instructions
Instruction LDS LDS Rm,FPSCR Rm,FPUL Operation Rm FPSCR Rm FPUL Instruction Code 0100mmmm01101010 0100mmmm01011010 Privileged T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- New -- -- -- -- -- -- -- --
LDS.L @Rm+,FPSCR (Rm) FPSCR, Rm+4 Rm 0100mmmm01100110 LDS.L @Rm+,FPUL STS STS FPSCR,Rn FPUL,Rn (Rm) FPUL, Rm+4 Rm FPSCR Rn FPUL Rn Rn - 4 Rn, FPSCR (Rn) Rn - 4 Rn, FPUL (Rn) 0100mmmm01010110 0000nnnn01101010 0000nnnn01011010 0100nnnn01100010 0100nnnn01010010
STS.L FPSCR,@-Rn STS.L FPUL,@-Rn
Rev. 1.00 Oct. 01, 2007 Page 76 of 1956 REJ09B0256-0100
Section 3 Instruction Set
Table 3.13 Floating-Point Graphics Acceleration Instructions
Instruction FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FIPR FTRV FRCHG FSCHG FPCHG FSRRA FRn FSCA FPUL,DRn DRm,XDn XDm,DRn XDm,XDn @Rm,XDn @Rm+,XDn Operation DRm XDn XDm DRn XDm XDn (Rm) XDn (Rm) XDn, Rm + 8 Rm Instruction Code 1111nnn1mmm01100 1111nnn0mmm11100 1111nnn1mmm11100 1111nnn1mmmm1000 1111nnn1mmmm1001 1111nnn1mmmm0110 1111nnnnmmm11010 1111nnnnmmm11011 1111nnnnmmm10111 1111nnmm11101101 1111nn0111111101 1111101111111101 1111001111111101 1111011111111101 1111nnnn01111101 1111nnn011111101 Privileged T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- New -- -- -- -- -- -- -- -- -- -- -- -- -- New New New
@(R0,Rm),XDn (R0 + Rm) XDn XDm,@Rn XDm,@-Rn XDm (Rn) Rn - 8 Rn, XDm (Rn)
XDm,@(R0,Rn) XDm (R0 + Rn) FVm,FVn XMTRX,FVn inner_product (FVm, FVn) FR[n+3] transform_vector (XMTRX, FVn) FVn ~FPSCR.FR FPSCR.FR ~FPSCR.SZ FPSCR.SZ ~FPSCR.PR FPSCR.PR 1/sqrt (FRn)* FRn sin(FPUL) FRn cos(FPUL) FR[n + 1]
Note:
*
sqrt (FRn) is the square root of FRn.
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Section 3 Instruction Set
Rev. 1.00 Oct. 01, 2007 Page 78 of 1956 REJ09B0256-0100
Section 4 Pipelining
Section 4 Pipelining
This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel.
4.1
Pipelines
Figure 4.1 shows the basic pipelines. Normally, a pipeline consists of seven stages: instruction fetch (I1/I2), decode and register read (ID), execution (E1/E2/E3), and write-back (WB). An instruction is executed as a combination of basic pipelines.
1. General Pipeline I1 -Instruction fetch I2 ID E1 E2 -Operation E3 WB -Write-back
-Instruction decode -Forwarding -Issue -Register read
2. General Load/Store Pipeline I1 -Instruction fetch I2 ID E1 E2 E3 WB -Write-back
-Instruction decode -Address calculation -Memory data access -Issue -Register read
3. Special Pipeline I1 -Instruction fetch I2 ID E1 E2 -Operation E3 WB -Write-back
-Instruction decode -Forwarding -Issue -Register read
4. Special Load/Store Pipeline I1 -Instruction fetch I2 ID -Instruction decode -Issue -Register read E1 E2 E3 WB
5. Floating-Point Pipeline I1 -Instruction fetch I2 ID FS1 FS2 -Operation FS3 -Operation FS4 -Operation FS -Operation -Write-back
-Instruction decode -Register read -Issue -Forwarding
6.
Floating-Point Extended Pipeline I1 -Instruction fetch I2 ID -Instruction decode -Issue FE1 FE2 FE3 -Operation FE4 -Operation FE5 -Operation FE6 -Operation FS -Operation -Write-back
-Register read -Operation -Forwarding
Figure 4.1 Basic Pipelines
Rev. 1.00 Oct. 01, 2007 Page 79 of 1956 REJ09B0256-0100
Section 4 Pipelining
Figure 4.2 shows the instruction execution patterns. Representations in figure 4.2 and their descriptions are listed in table 4.1. Table 4.1 Representations of Instruction Execution Patterns
Description CPU EX pipe is occupied CPU LS pipe is occupied (with memory access) CPU LS pipe is occupied (without memory access) Either CPU EX pipe or CPU LS pipe is occupied
Representation
E1 S1 s1 E1/S1
E1S1
E2 S2 s2
E3 S3 s3
WB WB WB
,
E1s1
Both CPU EX pipe and CPU LS pipe are occupied CPU MULT operation unit is occupied
FS
M2
M3
MS
FE1 FE2 FE3 FE4 FE5 FE6 FS1 FS2 FS3 FS4 FS
ID
FPU-EX pipe is occupied FPU-LS pipe is occupied ID stage is locked Both CPU and FPU pipes are occupied
Rev. 1.00 Oct. 01, 2007 Page 80 of 1956 REJ09B0256-0100
Section 4 Pipelining
(1-1) BF, BF/S, BT, BT/S, BRA, BSR:1 issue cycle + 0 to 2 branch cycles I1 I2 ID E1/S1 E2/s2 E3/s3
WB
Note: In branch instructions that are categorized as (1-1), the number of branch cycles may be reduced by prefetching.
(I1)
(I2)
(ID)
(Branch destination instruction)
(1-2) JSR, JMP, BRAF, BSRF: 1 issue cycle + 3 branch cycles I1 I2 ID E1/S1 E2/S2 E3/S3
WB
(I1)
(I2)
(ID)
(Branch destination instruction)
(1-3) RTS: 1 issue cycle + 0 to 3 branch cycles I1 I2 ID E1/S1 E2/S2 E3/S3
WB
Note: The number of branch cycles may be 0 by prefetching instruction.
(I1)
(I2)
(ID)
(Branch destination instruction)
(1-4) RTE: 4 issue cycles + 1 branch cycles
I1 I2 ID s1 ID s2 E1s1 ID s3 E2s2
ID (I1)
(I2)
WB E3s3
WB
(ID)
(Branch destination instruction)
(1-5) TRAPA: 8 issue cycles + 5 cycles + 1 branch cycle
I1 I2 ID S1 ID S2 S3 WB E1s1 E2s2 E3s3
Note: It is 14 cycles to the ID stage in the first instruction of exception handler.
WB
ID
E1s1 E2s2 E3s3 ID E1s1 E2s2 ID E1s1 ID
WB E3s3 E2s2 E1s1 ID
WB E3s3 E2s2 E1s1 ID
(I1)
WB E3s3 WB E2s2 E3s3 WB E1s1 E2s2 E3s3 WB
(I2) (ID)
(1-6) SLEEP: 2 issue cycles
I1 I2 ID S1 ID S2 E1s1 S3 E2s2 WB E3s3
WB
Note: It is not constant cycles to the clock halted period.
Figure 4.2 Instruction Execution Patterns (1)
Rev. 1.00 Oct. 01, 2007 Page 81 of 1956 REJ09B0256-0100
Section 4 Pipelining
(2-1) 1-step operation (EX type): 1 issue cycle EXT[SU].[BW], MOVT, SWAP, XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, CLRS, CLRT, SETS, SETT Note: Except for AND#, OR#, TST#, and XOR# instructions using GBR relative addressing mode I1 I2 ID E1 E2 E3 WB
(2-2) 1-step operation (LS type): 1 issue cycle MOVA I1 I2 ID s1 s2 s3 WB
(2-3) 1-step operation (MT type): 1 issue cycle MOV#, NOP I1 I2 ID E1/S1 E2/s2 E3/s3 WB
(2-4) MOV (MT type): 1 issue cycle MOV I1 I2 ID E1/s1 E2/s2 E3/S3 WB
Figure 4.2 Instruction Execution Patterns (2)
Rev. 1.00 Oct. 01, 2007 Page 82 of 1956 REJ09B0256-0100
Section 4 Pipelining
(3-1) Load/store: 1 issue cycle MOV.[BWL], MOV.[BWL] @(d,GBR) I1 I2 ID S1 S2 S3
WB
(3-2) AND.B, OR.B, XOR.B, TST.B: 3 issue cycles I1 I2 ID S1 ID S2
ID
S3
E1S1
WB
E2S2 E3S3 WB
(3-3) TAS.B: 4 issue cycles
I1 I2 ID S1 ID S2 E1S1 ID S3 E2S2
ID
WB E3S3
E1S1
WB
E2S2
E3S3
WB
(3-4) PREF, OCBI, OCBP, OCBWB, MOVCA.L, SYNCO: 1 issue cycle
I1
I2
ID
S1
S2
S3
WB
(3-5) LDTLB: 1 issue cycle I1 I2 ID E1s1 E2s2 E3s3
WB
(3-6) ICBI: 8 issue cycles + 5 cycles + 3 branch cycle
I1 I2 ID s1 ID s2
ID
ID
ID
s3
WB
ID
5 cycles (min.)
E1s1 E2s2 E3s3 WB ID E1s1 E2s2 E3s3 WB ID E1s1 E2s2 E3s3
(I1)
WB
(3-7) PREFI: 5 issue cycles + 5 cycles + 3 branch cycle
I1 I2 ID s1 ID s2 E1s1 s3 E2s2 WB E3s3 WB
(I2) (ID)
(Branch to the next instruction of ICBI.)
ID 5 cycles (min.)
E1s1
ID
E2s2 E1s1
ID
E3s3 E2s2 E1s1
WB E3s3 E2s2
(I1)
WB E3s3
(I2)
WB (ID)
(3-8) MOVLI.L: 1 issue cycle I1 I2 ID S1 S2 S3
WB
(Branch to the next instruction of PREFI.)
(3-9) MOVCO.L: 1 issue cycle I1 I2 ID S1 S2 S3
WB
(3-10) MOVUA.L: 2 issue cycles I1 I2 ID S1 S2 S1 S3 S2 WB S3 WB
Figure 4.2 Instruction Execution Patterns (3)
Rev. 1.00 Oct. 01, 2007 Page 83 of 1956 REJ09B0256-0100
Section 4 Pipelining
(4-1) LDC to Rp_BANK/SSR/SPC/VBR: 1 issue cycle I1 I2 ID s1 s2 s3
WB
(4-2) LDC to DBR/SGR: 4 issue cycles I1 I2 ID s1 ID s2
ID
ID
s3
WB
(4-3) LDC to GBR: 1 issue cycle
I1 I2 ID s1 s2 s3
WB
(4-4) LDC to SR: 4 issue cycles + 3 branch cycles
I1 I2 ID E1s1 ID E2s2 ID
ID
E3s3
WB
(I1)
(I2)
(ID)
(Branch to the next instruction.)
(4-5) LDC.L to Rp_BANK/SSR/SPC/VBR: 1 issue cycle
I1
I2
ID
S1
S2
S3
WB
(4-6) LDC.L to DBR/SGR: 4 issue cycles I1 I2 ID S1 ID S2 ID
ID
S3
WB
(4-7) LDC.L to GBR: 1 issue cycle
I1 I2 ID S1 S2 S3
WB
(4-8) LDC.L to SR: 6 issue cycles + 3 branch cycles
I1
I2
ID
E1S1 ID
E2S2 ID
E3S3
WB
ID ID
ID
(I1)
(I2)
(ID)
(Branch to the next instruction.)
Figure 4.2 Instruction Execution Patterns (4)
Rev. 1.00 Oct. 01, 2007 Page 84 of 1956 REJ09B0256-0100
Section 4 Pipelining
(4-9) STC from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle I1 I2 ID s1 s2 s3
WB
(4-10) STC from SR: 1 issue cycle I1 I2 ID
E1s1 E2s2 E3s3 WB
(4-11) STC.L from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle
I1 I2 ID S1 S2 S3
WB
(4-12) STC.L from SR: 1 issue cycle I1 I2 ID
E1S1 E2S2 E3S3 WB
(4-13) LDS to PR: 1 issue cycle
I1 I2 ID s1 s2 s3
WB
(4-14) LDS.L to PR: 1 issue cycle
I1
I2
ID
S1
S2
S3
WB
(4-15) STS from PR: 1 issue cycle
I1
I2
ID
s1
s2
s3
WB
(4-16) STS.L from PR: 1 issue cycle
I1
I2
ID
S1
S2
S3
WB
(4-17) BSRF, BSR, JSR delay slot instructions (PR set): 0 issue cycle
(I1)
(I2)
(ID)
(??1)
(??2)
(??3)
(WB)
Notes: The value of PR is changed in the E3 stage of delay slot instruction. When the STS and STS.L instructions from PR are used as delay slot instructions, changed PR value is used.
Figure 4.2 Instruction Execution Patterns (5)
Rev. 1.00 Oct. 01, 2007 Page 85 of 1956 REJ09B0256-0100
Section 4 Pipelining
(5-1) LDS to MACH/L: 1 issue cycle I1 I2 ID s1 s2 s3 WB MS
(5-2) LDS.L to MACH/L: 1 issue cycle
I1 I2 ID S1 S2 S3 WB MS
(5-3) STS from MACH/L: 1 issue cycle
I1 I2 ID s1 s2 s3 WB MS
(5-4) STS.L from MACH/L: 1 issue cycle
I1 I2 ID S1 S2 S3 WB MS
(5-5) MULS.W, MULU.W: 1 issue cycle
I1
I2
ID
E1
M2
M3
MS
(5-6) DMULS.L, DMULU.L, MUL.L: 1 issue cycle I1 I2
ID
E1
M2
M3 M2
M3
MS
(5-7) CLRMAC: 1 issue cycle
I1 I2
ID
E1
M2
M3
MS
(5-8) MAC.W: 2 issue cycle
I1
I2
ID
S1 ID
S2 S1
S3 S2
WB S3
WB M2
M3
MS
(5-9) MAC.L: 2 issue cycle
I1 I2 ID S1 ID S2 S1 S3 S2 WB S3 WB M2
M3 M2
M3
MS
Figure 4.2 Instruction Execution Patterns (6)
Rev. 1.00 Oct. 01, 2007 Page 86 of 1956 REJ09B0256-0100
Section 4 Pipelining
(6-1) LDS to FPUL: 1 issue cycle I1 I2 ID s1 FS1 s2 FS2 s3 FS3 FS4 FS
(6-2) STS from FPUL: 1 issue cycle I1 I2 ID
FS1 s1
FS2 s2
FS3 s3
FS4 WB
(6-3) LDS.L to FPUL: 1 issue cycle I1 I2 ID S1 FS1 S2 FS2 S3 FS3 WB FS4
FS
(6-4) STS.L from FPUL: 1 issue cycle
I1 I2
ID
FS1 S1
FS2 S2
FS3 S3
FS4 WB
(6-5) LDS to FPSCR: 1 issue cycle I1 I2 ID s1 FS1 s2 FS2 s3 FS3
FS4
FS
(6-6) STS from FPSCR: 1 issue cycle I1 I2
ID
FS1 s1
FS2 s2
FS3 s3
FS4 WB
(6-7) LDS.L to FPSCR: 1 issue cycle I1 I2 ID S1 FS1 S2 FS2 S3 FS3 WB FS4
FS
(6-8) STS.L from FPSCR: 1 issue cycle
I1 I2
ID
FS1 S1
FS2 S2
FS3 S3
FS4 WB
(6-9) FPU load/store instruction FMOV: 1 issue cycle I1 I2 ID S1 FS1 S2 FS2 S3 FS3 WB FS4 FS
(6-10) FLDS: 1 issue cycle I1 I2 ID s1 FS1 s2 FS2 s3 FS3 WB FS4 FS
(6-11) FSTS: 1 issue cycle I1 I2 ID
s1 FS1 s2 FS2 s3 FS3 FS4 FS
Figure 4.2 Instruction Execution Patterns (7)
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Section 4 Pipelining
(6-12) Single-precision FABS, FNEG/double-precision FABS, FNEG: 1 issue cycle I1 I2 ID s1 FS1 s2 FS2 s3 FS3 FS4
FS
(6-13) FLDI0, FLDI1: 1 issue cycle
I1 I2 ID s1 FS1 s2 FS2 s3 FS3 FS4
FS
(6-14) Single-precision floating-point computation: 1 issue cycle
FCMP/EQ, FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, FSCHG, FPCHG I1 I2
ID FE1 FE2 FE3 FE4 FE5
FE6 FS
(6-15) Single-precision FDIV/FSQRT: 1 issue cycle
I1 I2
ID FE1 FE2 FS FE3 FE4 FE5 FE6 FEDS (Divider occupied cycle)
FE3
FE4
FE5
FE6
FS
(6-16) Double-precision floating-point computation: 1 issue cycle FCMP/EQ, FCMP/GT, FADD, FLOAT, FSUB, FTRC, FCNVSD, FCNVDS
I1 I2
ID FE1 FE2 FE3 FE4 FE5 FE6
FS
(6-17) Double-precision floating-point computation: 1 issue cycle FMUL
I1 I2
ID
FE1
FE2 FE1
FE3 FE2 FE1
FE4 FE3 FE2
FE5 FE4 FE3
FE6 FE5 FE4
FS FE6 FE5
FS FE6
FS
(6-18) Double-precision FDIV/FSQRT: 1 issue cycle
I1 I2
ID
FE1
FE2
FE3
FS FE4 FE5 FE6 FEDS (Divider occupied cycle)
FE3
FE4 FE3
FE5 FE4
FE6 FE5
FS FE6
FS
Figure 4.2 Instruction Execution Patterns (8)
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Section 4 Pipelining
(6-19) FIPR: 1 issue cycle I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS
(6-20) FTRV: 1 issue cycle I1 I2 ID FE1 FE2 FE1 FE3 FE2 FE1 FE4 FE3 FE2 FE1 FE5 FE4 FE3 FE2 FE6 FE5 FE4 FE3 FS FE6 FE5 FE4 FS FE6 FE5
FS FE6
FS
(6-21) FSRRA: 1 issue cycle I1 I2 ID FE1 FE2 FE3 FEPL FE4 FE5 FE6 FS
Function computing unit occupied cycle (6-22) FSCA: 1 issue cycle I1 I2 ID FE1 FE4 FE5 FE6 FE3 FE4 FE5 FE2 FE3 FE4 FEPL Function computing unit occupied cycle FE2 FE1 FE3 FE2 FE1 FS FE6 FE5 FS FE6
FS
Figure 4.2 Instruction Execution Patterns (9)
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Section 4 Pipelining
4.2
Parallel-Executability
Instructions are categorized into six groups according to the internal function blocks used, as shown in table 4.2. Table 4.3 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 4.2
Instruction Group
EX ADD ADDC ADDV AND #imm,R0 AND Rm,Rn CLRMAC CLRS CLRT CMP DIV0S DIV0U DIV1 DMUS.L DMULU.L MT BR MOV #imm,Rn BF BF/S BRA DT EXTS EXTU MOVT MUL.L MULS.W MULU.W NEG NEGC NOT OR #imm,R0 OR Rm,Rn ROTCL ROTCR MOV Rm,Rn BRAF BSR BSRF
Instruction Groups
Instruction
ROTL ROTR SETS SETT SHAD SHAL SHAR SHLD SHLL SHLL2 SHLL8 SHLL16 SHLR SHLR2 NOP BT BT/S JMP JSR RTS SHLR8 SHLR16 SUB SUBC SUBV SWAP TST #imm,R0 TST Rm,Rn XOR #imm,R0 XOR Rm,Rn XTRCT
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Section 4 Pipelining
Instruction Group
LS FABS FNEG FLDI0 FLDI1 FLDS FMOV @adr,FR FMOV FR,@adr FMOV FR,FR FMOV.S @adr,FR FE FADD FSUB FCMP (S/D) FCNVDS FCNVSD CO AND.B #imm,@(R0,GBR) ICBI LDC Rm,DBR LDC Rm, SGR LDC Rm,SR LDC.L @Rm+,DBR LDC.L @Rm+,SGR
Instruction
FMOV.S FR,@adr FSTS LDC Rm,CR1 LDC.L @Rm+,CR1 LDS Rm,SR1 LDS Rm,SR2 LDS.L @adr,SR2 LDS.L @Rm+,SR1 LDS.L @Rm+,SR2 FDIV FIPR FLOAT FMAC FMUL LDC.L @Rm+,SR LDTLB MAC.L MAC.W MOVCO MOVLI
OR.B #imm,@(R0,GBR)
MOV.[BWL] @adr,R MOV.[BWL] R,@adr MOVA MOVCA.L MOVUA OCBI OCBP OCBWB PREF FRCHG FSCHG FSQRT FTRC FTRV PREFI RTE SLEEP STC SR,Rn STC.L SR,@-Rn SYNCO TAS.B
STC CR2,Rn STC.L CR2,@-Rn STS SR2,Rn STS.L SR2,@-Rn STS SR1,Rn STS.L SR1,@-Rn
FSCA FSRRA FPCHG
TRAPA TST.B #imm,@(R0,GBR) XOR.B #imm,@(R0,GBR)
[Legend] R: Rm/Rn @adr: Address SR1: MACH/MACL/PR SR2: FPUL/FPSCR CR1: GBR/Rp_BANK/SPC/SSR/VBR CR2: CR1/DBR/SGR FR: FRm/FRn/DRm/DRn/XDm/XDn
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Section 4 Pipelining
The parallel execution of two instructions can be carried out under following conditions. 1. Both addr (preceding instruction) and addr+2 (following instruction) are specified within the minimum page size (1 Kbyte). 2. The execution of these two instructions is supported in table 4.3, Combination of Preceding and Following Instructions. 3. Data used by an instruction of addr does not conflict with data used by a previous instruction 4. Data used by an instruction of addr+2 does not conflict with data used by a previous instruction 5. Both instructions are valid
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Section 4 Pipelining
Table 4.3
Combination of Preceding and Following Instructions
Preceding Instruction (addr) EX MT Yes Yes Yes Yes Yes No BR Yes Yes No Yes Yes No LS Yes Yes Yes No Yes No FE Yes Yes Yes Yes No No CO No No No No No No
Following Instruction (addr+2)
EX MT BR LS FE CO
No Yes Yes Yes Yes No
Note: The following table shows the parallel-executability of pairs of instructions in this LSI. It is different from table 4.3. Preceding Instruction (addr) EX Following EX Instruction MT (addr+2) BR LS No Yes Yes Yes MT Yes Yes Yes Yes Yes Yes Yes No BR Yes Yes No Yes Yes Yes Yes No LS Yes Yes Yes No Yes No Yes No FLSR Yes Yes Yes Yes No No* No No FLSM Yes Yes Yes No No* No Yes No FE Yes Yes Yes Yes No Yes No No CO No No No No No No No No
FLSR Yes FLSM Yes FE CO Yes No
[Legend] FLSR: FABS, FNEG, FLDI0, FLDI1, FLDS, FSTS, FMOV FR,FR FLSM: FMOV[.S] @adr,FR, FMOV[.S] FR,@adr, LDS Rm,SR2, LDS.L @Rm+,SR2, STS SR2,Rn, STS.L SR2,@-Rn LS: Original LS instructions except FLSR and FLSM Note: * The CPU can issue these two instructions simultaneously, but they are stalled in the FPU.
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Section 4 Pipelining
4.3
Issue Rates and Execution Cycles
Instruction execution cycles are summarized in table 4.4. Instruction Group in the table 4.4 corresponds to the category in the table 4.2. Penalty cycles due to a pipeline stall are not considered in the issue rates and execution cycles in this section.
1. Issue Rate
Issue rates indicates the issue period between one instruction and next instruction. E.g. AND.B instruction
I1 I2 ID S1 ID S2
ID
S3
E1S1
WB E2S2 E3S3 WB
Issue rate: 3
Next instruction
E.g. MAC.W instruction
I1 I2 ID S1 ID
(I1)
(I2)
(ID)
S2 S1
S3 S2
WB S3
Issue rate: 2
Next instruction
(I1)
(I2)
WB M2
M3
MS
(ID)
2. Execution Cycles
Execution cycles indicates the cycle counts an instruction occupied the pipeline based on the next rules. CPU instruction E.g. AND.B instruction
I1 I2 ID S1 ID S2
ID
Execution Cycles: 3
S3
E1S1
WB E2S2 E3S3
WB
E.g. MAC.W instruction
I1 I2 ID S1 ID S2 S1 S3 S2
WB S3
Execution Cycles: 4
WB M2
M3
MS
FPU instruction E.g. FMUL instruction
I1 I2 ID FE1 FE2 FE1 FE3 FE2 FE1 FE4 FE3 FE2 FE5 FE4 FE3 FE6 FE5 FE4
Execution Cycles: 3
FS FE6 FE5 FS FE6
FS
E.g. FDIV instruction
I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS Divider occupation cycle
Execution Cycles: 14
FE3 FE4 FE5 FE6
FS
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Section 4 Pipelining
Table 4.4
Functional Category
Issue Rates and Execution Cycles
Instruction Group Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,Rn @(disp,PC),R0 @(disp,PC),Rn @(disp,PC),Rn @Rm,Rn @Rm,Rn @Rm,Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn @(disp,GBR),R0 @(disp, GBR),R0 @(disp, GBR),R0 Rm,@Rn Rm,@Rn Rm,@Rn Rm,@-Rn Rm,@-Rn EX EX EX EX MT MT LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS Execution Execution Pattern Issue Rate Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2-1 2-1 2-1 2-1 2-4 2-3 2-2 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1
No. Instruction EXTS.B EXTS.W EXTU.B EXTU.W MOV MOV MOVA MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W
Data transfer 1 instructions 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
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Section 4 Pipelining
Functional Category
No. Instruction MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVCA.L MOVCO.L MOVLI.L MOVUA.L MOVUA.L MOVT OCBI OCBP OCBWB PREF SWAP.B SWAP.W XTRCT ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/GE Rm,@-Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) R0,@Rn R0,@Rn @Rm,R0 @Rm,R0 @Rm+,R0 Rn @Rn @Rn @Rn @Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn
Instruction Group LS LS LS LS LS LS LS LS LS LS LS CO CO LS LS EX LS LS LS LS EX EX EX EX EX EX EX EX EX EX
Execution Execution Pattern Issue Rate Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-4 3-9 3-8 3-10 3-10 2-1 3-4 3-4 3-4 3-4 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1
Data transfer 30 instructions 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Fixed-point arithmetic instructions 53 54 55 56 57 58 59
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Section 4 Pipelining
Functional Category Fixed-point arithmetic instructions
No. Instruction 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 CMP/GT CMP/HI CMP/HS CMP/PL CMP/PZ CMP/STR DIV0S DIV0U DIV1 DMULS.L DMULU.L DT MAC.L MAC.W MUL.L MULS.W MULU.W NEG NEGC SUB SUBC SUBV AND AND AND.B NOT OR OR OR.B TAS.B TST Rm,Rn Rm,Rn Rm,Rn Rn @Rm+,@Rn+ @Rm+,@Rn+ Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) @Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn Rm,Rn Rm,Rn
Instruction Group EX EX EX EX EX EX EX EX EX EX EX EX CO CO EX EX EX EX EX EX EX EX EX EX CO EX EX EX CO CO EX
Execution Execution Pattern Issue Rate Cycles 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 3 1 1 1 3 4 1 1 1 1 1 1 1 1 1 1 2 2 1 5 4 2 1 1 1 1 1 1 1 1 1 3 1 1 1 3 4 1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 5-6 5-6 2-1 5-9 5-8 5-6 5-5 5-5 2-1 2-1 2-1 2-1 2-1 2-1 2-1 3-2 2-1 2-1 2-1 3-2 3-3 2-1
Logical instructions
82 83 84 85 86 87 88 89 90
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Section 4 Pipelining
Functional Category Logical instructions
No. Instruction 91 92 93 94 95 TST TST.B XOR XOR XOR.B ROTL ROTR ROTCL ROTCR #imm,R0 #imm,@(R0,GBR) Rm,Rn #imm,R0 #imm,@(R0,GBR) Rn Rn Rn Rn Rm,Rn Rn Rn Rm,Rn Rn Rn Rn Rn Rn Rn Rn Rn disp disp disp disp disp Rm disp Rm @Rn
Instruction Group EX CO EX EX CO EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX BR BR BR BR BR BR BR BR BR
Execution Execution Pattern Issue Rate Cycles 1 3 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1+0 to 2 1+0 to 2 1+0 to 2 1+0 to 2 1+0 to 2 1+3 1+0 to 2 1+3 1+3 1 3 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2-1 3-2 2-1 2-1 3-2 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 1-1 1-1 1-1 1-1 1-1 1-2 1-1 1-2 1-2
Shift instructions
96 97 98 99
100 SHAD 101 SHAL 102 SHAR 103 SHLD 104 SHLL 105 SHLL2 106 SHLL8 107 SHLL16 108 SHLR 109 SHLR2 110 SHLR8 111 SHLR16 Branch instructions 112 BF 113 BF/S 114 BT 115 BT/S 116 BRA 117 BRAF 118 BSR 119 BSRF 120 JMP
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Section 4 Pipelining
Functional Category Branch instructions System control instructions
No. Instruction 121 JSR 122 RTS 123 NOP 124 CLRMAC 125 CLRS 126 CLRT 127 ICBI 128 SETS 129 SETT 130 PREFI 131 SYNCO 132 TRAPA 133 RTE 134 SLEEP 135 LDTLB 136 LDC 137 LDC 138 LDC 139 LDC 140 LDC 141 LDC 142 LDC 143 LDC 144 LDC.L 145 LDC.L 146 LDC.L 147 LDC.L 148 LDC.L 149 LDC.L 150 LDC.L Rm,DBR Rm,SGR Rm,GBR Rm,Rp_BANK Rm,SR Rm,SSR Rm,SPC Rm,VBR @Rm+,DBR @Rm+,SGR @Rm+,GBR @Rm+,Rp_BANK @Rm+,SR @Rm+,SSR @Rm+,SPC @Rn #imm @Rn @Rn
Instruction Group BR BR MT EX EX EX CO EX EX CO CO CO CO CO CO CO CO LS LS CO LS LS LS CO CO LS LS CO LS LS
Execution Execution Pattern Issue Rate Cycles 1+3 1+0 to 3 1 1 1 1 8+5+3 1 1 5+5+3 Undefined 8+5+1 4+1 Undefined 1 4 4 1 1 4+3 1 1 1 4 4 1 1 6+3 1 1 1 1 1 1 1 1 13 1 1 10 Undefined 13 4 Undefined 1 4 4 1 1 4 1 1 1 4 4 1 1 4 1 1 1-2 1-3 2-3 5-7 2-1 2-1 3-6 2-1 2-1 3-7 3-4 1-5 1-4 1-6 3-5 4-2 4-2 4-3 4-1 4-4 4-1 4-1 4-1 4-6 4-6 4-7 4-5 4-8 4-5 4-5
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Section 4 Pipelining
Functional Category System control instructions
No. Instruction 151 LDC.L 152 LDS 153 LDS 154 LDS 155 LDS.L 156 LDS.L 157 LDS.L 158 STC 159 STC 160 STC 161 STC 162 STC 163 STC 164 STC 165 STC 166 STC.L 167 STC.L 168 STC.L 169 STC.L 170 STC.L 171 STC.L 172 STC.L 173 STC.L 174 STS 175 STS 176 STS 177 STS.L 178 STS.L 179 STS.L @Rm+,VBR Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR DBR,Rn SGR,Rn GBR,Rn Rp_BANK,Rn SR,Rn SSR,Rn SPC,Rn VBR,Rn DBR,@-Rn SGR,@-Rn GBR,@-Rn Rp_BANK,@-Rn SR,@-Rn SSR,@-Rn SPC,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn
Instruction Group LS LS LS LS LS LS LS LS LS LS LS CO LS LS LS LS LS LS LS CO LS LS LS LS LS LS LS LS LS
Execution Execution Pattern Issue Rate Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4-5 5-1 5-1 4-13 5-2 5-2 4-14 4-9 4-9 4-9 4-9 4-10 4-9 4-9 4-9 4-11 4-11 4-11 4-11 4-12 4-11 4-11 4-11 5-3 5-3 4-15 5-4 5-4 4-16
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Section 4 Pipelining
Functional Category
No. Instruction FRn FRn FRm,FRn @Rm,FRn @Rm+,FRn @(R0,Rm),FRn FRm,@Rn FRm,@-Rn FRm,@(R0,Rn) FRm,FPUL FPUL,FRn FRn FRm,FRn FRm,FRn FRm,FRn FRm,FRn FPUL,FRn FR0,FRm,FRn FRm,FRn FRn FRn FRm,FRn FRm,FPUL DRm,DRn @Rm,DRn @Rm+,DRn @(R0,Rm),DRn DRm,@Rn DRm,@-Rn DRm,@(R0,Rn)
Instruction Group LS LS LS LS LS LS LS LS LS LS LS LS FE FE FE FE FE FE FE LS FE FE FE LS LS LS LS LS LS LS
Execution Execution Pattern Issue Rate Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 14 1 1 1 1 30 1 1 1 1 1 1 1 1 1 6-13 6-13 6-9 6-9 6-9 6-9 6-9 6-9 6-9 6-10 6-11 6-12 6-14 6-14 6-14 6-15 6-14 6-14 6-14 6-12 6-15 6-14 6-14 6-9 6-9 6-9 6-9 6-9 6-9 6-9
180 FLDI0 Singleprecision 181 FLDI1 floating-point instructions 182 FMOV 183 FMOV.S 184 FMOV.S 185 FMOV.S 186 FMOV.S 187 FMOV.S 188 FMOV.S 189 FLDS 190 FSTS 191 FABS 192 FADD 193 FCMP/EQ 194 FCMP/GT 195 FDIV 196 FLOAT 197 FMAC 198 FMUL 199 FNEG 200 FSQRT 201 FSUB 202 FTRC 203 FMOV 204 FMOV 205 FMOV 206 FMOV 207 FMOV 208 FMOV 209 FMOV
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Section 4 Pipelining
Functional Category
No. Instruction DRn DRm,DRn DRm,DRn DRm,DRn DRm,FPUL FPUL,DRn DRm,DRn FPUL,DRn DRm,DRn DRn DRn DRm,DRn DRm,FPUL Rm,FPUL Rm,FPSCR @Rm+,FPUL @Rm+,FPSCR FPUL,Rn FPSCR,Rn FPUL,@-Rn FPSCR,@-Rn DRm,XDn XDm,DRn XDm,XDn @Rm,XDn @Rm+,XDn @(R0,Rm),XDn XDm,@Rn XDm,@-Rn XDm,@(R0,Rn) FVm,FVn
Instruction Group LS FE FE FE FE FE FE FE FE LS FE FE FE LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS FE
Execution Execution Pattern Issue Rate Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 14 1 3 1 30 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6-12 6-16 6-16 6-16 6-16 6-16 6-18 6-16 6-17 6-12 6-18 6-16 6-16 6-1 6-5 6-3 6-7 6-2 6-6 6-4 6-8 6-9 6-9 6-9 6-9 6-9 6-9 6-9 6-9 6-9 6-19
210 FABS Doubleprecision 211 FADD floating-point instructions 212 FCMP/EQ 213 FCMP/GT 214 FCNVDS 215 FCNVSD 216 FDIV 217 FLOAT 218 FMUL 219 FNEG 220 FSQRT 221 FSUB 222 FTRC FPU system 223 LDS control 224 LDS instructions 225 LDS.L 226 LDS.L 227 STS 228 STS 229 STS.L 230 STS.L Graphics 231 FMOV acceleration 232 FMOV instructions 233 FMOV 234 FMOV 235 FMOV 236 FMOV 237 FMOV 238 FMOV 239 FMOV 240 FIPR
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Section 4 Pipelining
Functional Category
No. Instruction
Instruction Group FE FE FE FRn FPUL,DRn XMTRX,FVn FE FE FE
Execution Execution Pattern Issue Rate Cycles 1 1 1 1 1 1 1 1 1 1 3 4 6-14 6-14 6-14 6-21 6-22 6-20
241 FRCHG Graphics acceleration 242 FSCHG instructions 243 FPCHG 244 FSRRA 245 FSCA 246 FTRV
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Section 4 Pipelining
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Section 5 Exception Handling
Section 5 Exception Handling
5.1 Summary of Exception Handling
Exception handling processing is handled by a special routine which is executed by a reset, general exception handling, or interrupt. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing. The process of generating an exception handling request in response to abnormal termination, and passing control to a userwritten exception handling routine, in order to support such functions, is given the generic name of exception handling. The exception handling in this LSI is of three kinds: resets, general exceptions, and interrupts.
5.2
Register Descriptions
Table 5.1 lists the configuration of registers related exception handling. Table 5.1 Register Configuration
Abbr. TRA EXPEVT INTEVT R/W R/W R/W R/W P4 Address* H'FF00 0020 H'FF00 0024 H'FF00 0028 Area 7 Address* H'1F00 0020 H'1F00 0024 H'1F00 0028 Access Size 32 32 32
Register Name TRAPA exception register Exception event register Interrupt event register
Note:
*
P4 is the address when virtual address space P4 area is used. Area 7 is the address when physical address space area 7 is accessed by using the TLB.
Table 5.2
States of Register in Each Operating Mode
Power-on Reset Undefined
Register Name TRAPA exception register Exception event register Interrupt event register
Abbr. TRA EXPEVT INTEVT
Manual Reset Sleep Undefined Retained Retained Retained
Standby Retained Retained Retained
H'0000 0000 H'0000 0020 Undefined Undefined
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Section 5 Exception Handling
5.2.1
TRAPA Exception Register (TRA)
The TRAPA exception register (TRA) consists of 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software.
Bit: Initial value: R/W: Bit: Initial value: R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
TRACODE 0 R 0 R 0 R 0 R 0 R 0 R R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 R
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
31 to 10
9 to 2 1, 0
TRACODE
Undefined R/W All 0 R
TRAPA Code 8-bit immediate data of TRAPA instruction is set Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
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Section 5 Exception Handling
5.2.2
Exception Event Register (EXPEVT)
The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs. EXPEVT can also be modified by software.
Bit: Initial value: R/W: Bit: Initial value: R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6 EXPCODE
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0/1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
31 to 12
11 to 0
EXPCODE
H'000 or H'020
R/W
Exception Code The exception code for a reset or general exception is set. For details, see table 5.3.
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Section 5 Exception Handling
5.2.3
Interrupt Event Register (INTEVT)
The interrupt event register (INTEVT) consists of a 14-bit exception code. The exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software.
Bit: Initial value: R/W: Bit: Initial value: R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7 INTCODE
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
0 R
0 R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
31 to 14
13 to 0
INTCODE
Undefined R/W
Exception Code The exception code for an interrupt is set. For details, see table 5.3.
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Section 5 Exception Handling
5.3
5.3.1
Exception Handling Functions
Exception Handling Flow
In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address. An exception handling routine is a program written by the user to handle a specific exception. The exception handling routine is terminated and control returned to the original program by executing a return-from-exception instruction (RTE). This instruction restores the PC and SR contents and returns control to the normal processing routine at the point at which the exception occurred. The SGR contents are not written back to R15 with an RTE instruction. The basic processing flow is as follows. For the meaning of the SR bits, see section 2, Programming Model. The PC, SR, and R15 contents are saved in SPC, SSR, and SGR, respectively. The block bit (BL) in SR is set to 1. The mode bit (MD) in SR is set to 1. The register bank bit (RB) in SR is set to 1. In a reset, the FPU disable bit (FD) in SR is cleared to 0. The exception code is written to bits 11 to 0 of the exception event register (EXPEVT) or interrupt event register (INTEVT). 7. The CPU branches to the determined exception handling vector address, and the exception handling routine begins. 5.3.2 Exception Handling Vector Addresses 1. 2. 3. 4. 5. 6.
The reset vector address is fixed at H'A0000000. Exception and interrupt vector addresses are determined by adding the offset for the specific event to the vector base address, which is set by software in the vector base register (VBR). In the case of the TLB miss exception, for example, the offset is H'00000400, so if H'9C080000 is set in VBR, the exception handling vector address will be H'9C080400. If a further exception occurs at the exception handling vector address, a duplicate exception will result, and recovery will be difficult; therefore, addresses that are not to be converted (in P1 and P2 areas) should be specified for vector addresses.
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Section 5 Exception Handling
5.4
Exception Types and Priorities
Table 5.3 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.3 Exceptions
Exception Transition 3 Direction* Exception Execution Category Mode Exception Reset Abort type Power-on reset Manual reset H-UDI reset Instruction TLB multiple-hit exception Priority Priority Vector 2 2 Level* Order* Address 1 1 1 1 1 2 1 3 4 0 1 2 3 4 4 4 4 5 5 6 6 7 7 8 9 Offset Exception 4 Code* H'000 H'020 H'000 H'140 H'140
H'A000 0000 -- H'A000 0000 -- H'A000 0000 -- H'A000 0000 -- H'A000 0000 -- (VBR/DBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR)
Data TLB multiple-hit exception 1 General exception Reexecution type User break before instruction 1 execution* Instruction address error Instruction TLB miss exception Instruction TLB protection violation exception General illegal instruction exception 2 2 2 2 2
H'100/-- H'1E0 H'100 H'400 H'100 H'100 H'100 H'100 H'100 H'100 H'100 H'400 H'400 H'100 H'100 H'100 H'100 H'0E0 H'040 H'0A0 H'180 H'1A0 H'800 H'820 H'0E0 H'100 H'040 H'060 H'0A0 H'0C0 H'120 H'080
Slot illegal instruction exception 2 General FPU disable exception 2 Slot FPU disable exception Data address error (read) Data address error (write) 2 2 2
Data TLB miss exception (read) 2 Data TLB miss exception (write) 2 Data TLB protection violation exception (read) Data TLB protection violation exception (write) FPU exception Initial page write exception 2 2 2 2
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Section 5 Exception Handling Exception Transition 3 Direction* Exception Execution Category Mode Exception General exception Completion Unconditional trap (TRAPA) type User break after instruction 1 execution* Completion Nonmaskable interrupt type General interrupt request Priority Priority Vector 2 2 Level* Order* Address 2 2 3 4 4 10 -- -- (VBR) (VBR/DBR) (VBR) (VBR) Offset H'100 Exception 4 Code* H'160
H'100/-- H'1E0 H'600 H'600 H'1C0 --
Interrupt
Notes: 1. When UBDE in CBCR = 1, PC = DBR. In other cases, PC = VBR + H'100. 2. Priority is first assigned by priority level, then by priority order within each level (the lowest number represents the highest priority). 3. Control passes to H'A000 0000 in a reset, and to [VBR + offset] in other cases. 4. Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt.
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Section 5 Exception Handling
5.5
5.5.1
Exception Flow
Exception Flow
Figure 5.1 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.1 shows the relative priority order of the different kinds of exceptions (reset, general exception, and interrupt). Register settings in the event of an exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC. However, other registers may be set automatically by hardware, depending on the exception. For details, see section 5.6, Description of Exceptions. Also, see section 5.6.4, Priority Order with Multiple Exceptions, for exception handling during execution of a delayed branch instruction and a delay slot instruction, or in the case of instructions in which two data accesses are performed.
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Section 5 Exception Handling
Reset requested?
Yes
No
Execute next instruction
General exception requested? No Interrupt requested? No
Yes
Is highestYes priority exception re-exception type? Cancel instruction execution No result
Yes
SSR SR SPC PC SGR R15 EXPEVT/INTEVT exception code SR.{MD,RB,BL} 111 SR.IMASK received interuupt level (*) PC (CBCR.UBDE=1 && User_Break? DBR: (VBR + Offset))
EXPEVT exception code SR. {MD, RB, BL, FD, IMASK} 11101111 PC H'A000 0000
Note: * When the exception of the highest priority is an interrupt. Whether IMASK is updated or not can be set by software.
Figure 5.1 Instruction Execution and Exception Handling
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Section 5 Exception Handling
5.5.2
Exception Source Acceptance
A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions--general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception--are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline. These exceptions therefore all have the same priority. General exceptions are detected in the order of instruction execution. However, exception handling is performed in the order of instruction flow (program order). Thus, an exception for an earlier instruction is accepted before that for a later instruction. An example of the order of acceptance for general exceptions is shown in figure 5.2.
Pipeline flow: Instruction n Instruction n + 1 TLB miss (data access) ID E1 E2 E3 WB ID E1 E2 E3 WB General illegal instruction exception TLB miss (instruction access) I2 ID E1 E2 E3 WB [Legend] I1, I2 : Instruction fetch ID : Instruction decode E1, E2, E3 : Instruction execution (E2, E3: Memory access) WB : Write-back
I1 I1
I2 I2
Instruction n + 2
I1
Instruction n + 3
I1
I2
ID
E1
E2
E3
WB
Order of detection: General illegal instruction exception (instruction n + 1) and TLB miss (instruction n + 2) are detected simultaneously TLB miss (instruction n) Order of exception handling: TLB miss (instruction n) Re-execution of instruction n General illegal instruction exception (instruction n + 1) Re-execution of instruction n + 1 TLB miss (instruction n + 2) 3 Re-execution of instruction n + 2 Execution of instruction n + 3 4 Program order 1
2
Figure 5.2 Example of General Exception Acceptance Order
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Section 5 Exception Handling
5.5.3
Exception Requests and BL Bit
When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A0000000). For the operation in the event of a user break, see section 41, User Break Controller (UBC). If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL bit has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or accepted according to the setting made by software. Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable multiple exception state acceptance. 5.5.4 Return from Exception Handling
The RTE instruction is used to return from exception handling. When the RTE instruction is executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns from the exception handling routine by branching to the SPC address. If SPC and SSR were saved to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and issuing the RTE instruction.
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Section 5 Exception Handling
5.6
Description of Exceptions
The various exception handling operations explained here are exception sources, transition address on the occurrence of exception, and processor operation when a transition is made. 5.6.1 (1) Resets Power-On Reset
* Condition: Power-on reset request * Operations: Exception code H'000 is set in EXPEVT, initialization of the CPU and on-chip peripheral module is carried out, and then a branch is made to the reset vector (H'A0000000). For details, see the register descriptions in the relevant sections. A power-on reset should be executed when power is supplied. (2) Manual Reset
* Condition: Manual reset request * Operations: Exception code H'020 is set in EXPEVT, initialization of the CPU and on-chip peripheral module is carried out, and then a branch is made to the branch vector (H'A0000000). The registers initialized by a power-on reset and manual reset are different. For details, see the register descriptions in the relevant sections. (3) H-UDI Reset
* Source: SDIR.TI[7:4] = B'0110 (negation) or B'0111 (assertion) * Transition address: H'A0000000 * Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A0000000. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections.
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Section 5 Exception Handling
(4)
Instruction TLB Multiple-Hit Exception
* Source: Multiple ITLB address matches * Transition address: H'A0000000 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A0000000. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections. (5) Data TLB Multiple-Hit Exception
* Source: Multiple UTLB address matches * Transition address: H'A0000000 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A0000000. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections.
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Section 5 Exception Handling
5.6.2 (1)
General Exceptions Data TLB Miss Exception
* Source: Address mismatch in UTLB address comparison * Transition address: VBR + H'00000400 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'040 (for a read access) or H'060 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions.
Data_TLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'0000 0040 : H'0000 0060; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0400; }
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Section 5 Exception Handling
(2)
Instruction TLB Miss Exception
* Source: Address mismatch in ITLB address comparison * Transition address: VBR + H'00000400 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'40 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions.
ITLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 0040; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0400; }
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Section 5 Exception Handling
(3)
Initial Page Write Exception
* Source: TLB is hit in a store access, but dirty bit D = 0 * Transition address: VBR + H'00000100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'080 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
Initial_write_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 0080; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
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Section 5 Exception Handling
(4)
Data TLB Protection Violation Exception
* Source: The access does not accord with the UTLB protection information (PR bits) shown below.
PR 00 01 10 11 Privileged Mode Only read access possible Read/write access possible Only read access possible Read/write access possible User Mode Access not possible Access not possible Only read access possible Read/write access possible
* Transition address: VBR + H'00000100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
Data_TLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'0000 00A0 : H'0000 00C0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
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Section 5 Exception Handling
(5)
Instruction TLB Protection Violation Exception
* Source: The access does not accord with the ITLB protection information (PR bits) shown below.
PR 0 1 Privileged Mode Access possible Access possible User Mode Access not possible Access possible
* Transition address: VBR + H'00000100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
ITLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 00A0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
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Section 5 Exception Handling
(6)
Data Address Error
* Sources: Word data access from other than a word boundary (2n +1) Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3) Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) Access to area H'80000000 to H'FFFFFFFF in user mode Areas H'E0000000 to H'E3FFFFFF and H'E5000000 to H'E5FFFFFF can be accessed in user mode. For details, see section 6, Memory Management Unit (MMU) and section 8, L Memory. * Transition address: VBR + H'0000100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0E0 (for a read access) or H'100 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 6, Memory Management Unit (MMU).
Data_address_error() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access? H'0000 00E0: H'0000 0100; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
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Section 5 Exception Handling
(7)
Instruction Address Error
* Sources: Instruction fetch from other than a word boundary (2n +1) Instruction fetch from area H'80000000 to H'FFFFFFFF in user mode Area H'E5000000 to H'E5FFFFFF can be accessed in user mode. For details, see section 8, L Memory. * Transition address: VBR + H'00000100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in the SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 6, Memory Management Unit (MMU).
Instruction_address_error() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 00E0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
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Section 5 Exception Handling
(8)
Unconditional Trap
* Source: Execution of TRAPA instruction * Transition address: VBR + H'00000100 * Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR. The 8-bit immediate value in the TRAPA instruction is multiplied by 4, and the result is set in TRA [9:0]. Exception code H'160 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
TRAPA_exception() { SPC = PC + 2; SSR = SR; SGR = R15; TRA = imm << 2; EXPEVT = H'0000 0160; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
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Section 5 Exception Handling
(9)
General Illegal Instruction Exception
* Sources: Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR * Transition address: VBR + H'00000100 * Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'180 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other than H'FFFD is decoded.
General_illegal_instruction_exception() { SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 0180; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
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Section 5 Exception Handling
(10) Slot Illegal Instruction Exception * Sources: Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.L @Rm+,SR, ICBI, PREFI Decoding in user mode of a privileged instruction in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR Decoding of a PC-relative MOV instruction or MOVA instruction in a delay slot * Transition address: VBR + H'000 0100 * Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR. Exception code H'1A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other than H'FFFD is decoded.
Slot_illegal_instruction_exception() { SPC = PC - 2; SSR = SR; SGR = R15; EXPEVT = H'0000 01A0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
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Section 5 Exception Handling
(11) General FPU Disable Exception * Source: Decoding of an FPU instruction* not in a delay slot with SR.FD = 1 * Transition address: VBR + H'00000100 * Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'800 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Note: * FPU instructions are instructions in which the first 4 bits of the instruction code are F (but excluding undefined instruction H'FFFD), and the LDS, STS, LDS.L, and STS.L instructions corresponding to FPUL and FPSCR.
General_fpu_disable_exception() { SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 0800; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
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Section 5 Exception Handling
(12) Slot FPU Disable Exception * Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 * Transition address: VBR + H'00000100 * Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR. Exception code H'820 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
Slot_fpu_disable_exception() { SPC = PC - 2; SSR = SR; SGR = R15; EXPEVT = H'0000 0820; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
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Section 5 Exception Handling
(13) Pre-Execution User Break/Post-Execution User Break * Source: Fulfilling of a break condition set in the user break controller * Transition address: VBR + H'00000100, or DBR * Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC. In the case of a pre-execution break, the PC contents for the instruction at which the breakpoint is set are set in SPC. The SR and R15 contents when the break occurred are saved in SSR and SGR. Exception code H'1E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. It is also possible to branch to PC = DBR. For details of PC, etc., when a data break is set, see section 41, User Break Controller (UBC).
User_break_exception() { SPC = (pre_execution break? PC : PC + 2); SSR = SR; SGR = R15; EXPEVT = H'0000 01E0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = (BRCR.UBDE==1 ? DBR : VBR + H'0000 0100); }
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Section 5 Exception Handling
(14) FPU Exception * Source: Exception due to execution of a floating-point operation * Transition address: VBR + H'00000100 * Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR . The R15 contents at this time are saved in SGR. Exception code H'120 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
FPU_exception() { SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 0120; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
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Section 5 Exception Handling
5.6.3 (1)
Interrupts NMI (Nonmaskable Interrupt)
* Source: NMI pin edge detection * Transition address: VBR + H'00000600 * Transition operations: The PC and SR contents for the instruction immediately after this exception is accepted are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'1C0 is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0600. When the BL bit in SR is 0, this interrupt is not masked by the interrupt mask bits in SR, and is accepted at the highest priority level. When the BL bit in SR is 1, a software setting can specify whether this interrupt is to be masked or accepted.
NMI() { SPC = PC; SSR = SR; SGR = R15; INTEVT = H'0000 01C0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0600; }
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Section 5 Exception Handling
(2)
General Interrupt Request
* Source: The interrupt mask level bits setting in SR is smaller than the interrupt level of interrupt request, and the BL bit in SR is 0 (accepted at instruction boundary). * Transition address: VBR + H'00000600 * Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR. The code corresponding to the each interrupt source is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to VBR + H'0600.
Module_interruption() { SPC = PC; SSR = SR; SGR = R15; INTEVT = H'0000 0400 ~ H'0000 3FE0; SR.MD = 1; SR.RB = 1; SR.BL = 1; if (cond) SR.IMASK = level_of accepted_interrupt (); PC = VBR + H'0000 0600; }
5.6.4
Priority Order with Multiple Exceptions
With some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. Care is required in these cases, as the exception priority order differs from the normal order. * Instructions that make two accesses to memory
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Section 5 Exception Handling
With MAC instructions, memory-to-memory arithmetic/logic instructions, TAS instructions, and MOVUA instructions, two data transfers are performed by a single instruction, and an exception will be detected for each of these data transfers. In these cases, therefore, the following order is used to determine priority. 1. Data address error in first data transfer 2. TLB miss in first data transfer 3. TLB protection violation in first data transfer 4. Initial page write exception in first data transfer 5. Data address error in second data transfer 6. TLB miss in second data transfer 7. TLB protection violation in second data transfer 8. Initial page write exception in second data transfer * Indivisible delayed branch instruction and delay slot instruction As a delayed branch instruction and its associated delay slot instruction are indivisible, they are treated as a single instruction. Consequently, the priority order for exceptions that occur in these instructions differs from the usual priority order. The priority order shown below is for the case where the delay slot instruction has only one data transfer. 1. A check is performed for the interrupt type and re-execution type exceptions of priority levels 1 and 2 in the delayed branch instruction. 2. A check is performed for the interrupt type and re-execution type exceptions of priority levels 1 and 2 in the delay slot instruction. 3. A check is performed for the completion type exception of priority level 2 in the delayed branch instruction. 4. A check is performed for the completion type exception of priority level 2 in the delay slot instruction. 5. A check is performed for priority level 3 in the delayed branch instruction and priority level 3 in the delay slot instruction. (There is no priority ranking between these two.) 6. A check is performed for priority level 4 in the delayed branch instruction and priority level 4 in the delay slot instruction. (There is no priority ranking between these two.) If the delay slot instruction has a second data transfer, two checks are performed in step 2, as in the above case (Instructions that make two accesses to memory). If the accepted exception (the highest-priority exception) is a delay slot instruction reexecution type exception, the branch instruction PR register write operation (PC PR operation performed in a BSR, BSRF, or JSR instruction) is not disabled. Note that in this case, the contents of PR register are not guaranteed.
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Section 5 Exception Handling
5.7
(1)
Usage Notes
Return from exception handling
1. Check the BL bit in SR with software. If SPC and SSR have been saved to memory, set the BL bit in SR to 1 before restoring them. 2. Issue an RTE instruction. When RTE is executed, the SPC contents are saved in PC, the SSR contents are saved in SR, and branch is made to the SPC address to return from the exception handling routine. (2) If an exception or interrupt occurs when BL bit in SR = 1
1. Exception When an exception other than a user break occurs, a manual reset is executed. The value in EXPEVT at this time is H'00000020; the SPC and SSR contents are undefined. 2. Interrupt If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or accepted according to the setting made by software. In sleep or standby mode, however, an interrupt is accepted even if the BL bit in SR is set to 1. (3) SPC when an exception occurs
1. Re-execution type exception The PC value for the instruction at which the exception occurred is set in SPC, and the instruction is re-executed after returning from the exception handling routine. If an exception occurs in a delay slot instruction, however, the PC value for the delayed branch instruction is saved in SPC regardless of whether or not the preceding delay slot instruction condition is satisfied. 2. Completion type exception or interrupt The PC value for the instruction following that at which the exception occurred is set in SPC. If an exception occurs in a branch instruction with delay slot, however, the PC value for the branch destination is saved in SPC. (4) RTE instruction delay slot
1. The instruction in the delay slot of the RTE instruction is executed only after the value saved in SSR has been restored to SR. The acceptance of the exception related to the instruction access is determined depending on SR before restoring, while the acceptance of other exceptions is determined depending on the processing mode by SR after restoring or the BL
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Section 5 Exception Handling
bit. The completion type exception is accepted before branching to the destination of RTE instruction. However, if the re-execution type exception is occurred, the operation cannot be guaranteed. 2. The user break is not accepted by the instruction in the delay slot of the RTE instruction. (5) Changing the SR register value and accepting exception
1. When the MD or BL bit in the SR register is changed by the LDC instruction, the acceptance of the exception is determined by the changed SR value, starting from the next instruction.* In the completion type exception, an exception is accepted after the next instruction has been executed. However, an interrupt of completion type exception is accepted before the next instruction is executed. Note: * When the LDC instruction for SR is executed, following instructions are fetched again and the instruction fetch exception is evaluated again by the changed SR.
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Section 6 Memory Management Unit (MMU)
Section 6 Memory Management Unit (MMU)
This LSI supports an 8-bit address space identifier, a 32-bit virtual address space, and a 29-bit physical address space. Address translation from virtual addresses to physical addresses is enabled by the memory management unit (MMU) in this LSI. The MMU performs high-speed address translation by caching user-created address translation table information in an address translation buffer (translation lookaside buffer: TLB). This LSI has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with four page sizes (1, 4, and 64 Kbytes, and 1 Mbyte) supported. It is possible to set the virtual address space access right and implement memory protection independently for privileged mode and user mode.
6.1
Overview of MMU
The MMU was conceived as a means of making efficient use of physical memory. As shown in (0) in figure 6.1, when a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory, but if the process increases in size to the point where it does not fit into physical memory, it becomes necessary to divide the process into smaller parts, and map the parts requiring execution onto physical memory as occasion arises ((1) in figure 6.1). Having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process. The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden ((2) in figure 6.1). With a virtual memory system, the size of the available virtual memory is much larger than the actual physical memory, and processes are mapped onto this virtual memory. Thus processes only have to consider their operation in virtual memory, and mapping from virtual memory to physical memory is handled by the MMU. The MMU is normally managed by the OS, and physical memory switching is carried out so as to enable the virtual memory required by a process to be mapped smoothly onto physical memory. Physical memory switching is performed via secondary storage, etc. The virtual memory system that came into being in this way works to best effect in a time sharing system (TSS) that allows a number of processes to run simultaneously ((3) in figure 6.1). Running a number of processes in a TSS did not increase efficiency since each process had to take account of physical memory mapping. Efficiency is improved and the load on each process reduced by the use of a virtual memory system ((4) in figure 6.1). In this virtual memory system, virtual memory is allocated to each process. The task of the MMU is to map a number of virtual memory areas onto physical memory in an efficient manner. It is also provided with memory protection functions to prevent a process from inadvertently accessing another process's physical memory.
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Section 6 Memory Management Unit (MMU)
When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake. In such cases, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could be implemented by software alone, having address translation performed by software each time a process accessed physical memory would be very inefficient. For this reason, a buffer for address translation (the translation lookaside buffer: TLB) is provided by hardware, and frequently used address translation information is placed here. The TLB can be described as a cache for address translation information. However, unlike a cache, if address translation fails--that is, if an exception occurs--switching of the address translation information is normally performed by software. Thus memory management can be performed in a flexible manner by software. There are two methods by which the MMU can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space called a page. In the following descriptions, the address space in virtual memory in this LSI is referred to as virtual address space, and the address space in physical memory as physical address space.
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Section 6 Memory Management Unit (MMU)
Virtual Memory Physical Memory Process 1 Process 1 Physical Memory Process 1
MMU Physical Memory
(0) (1) (2)
Process 1
Physical Memory
Process 1
Virtual Memory MMU Physical Memory
Process 2
Process 2
Process 3
Process 3
(3)
(4)
Figure 6.1 Role of MMU
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Section 6 Memory Management Unit (MMU)
6.1.1
Address Spaces
Virtual Address Space: This LSI supports a 32-bit virtual address space, and can access a 4Gbyte address space. The virtual address space is divided into a number of areas, as shown in figures 6.2 and 6.3. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed. In user mode, a 2-Gbyte space in the U0 area can be accessed. When the SQMD bit in the MMU control register (MMUCR) is 0, a 64-Mbyte space in the store queue area can be accessed. When the RMD bit in the on-chip memory control register (RAMCR) is 1, a 16-Mbyte space in on-chip memory area can be accessed. Accessing areas other than the U0 area, store queue area, and on-chip memory area in user mode will cause an address error. When the AT bit in MMUCR is set to 1 and the MMU is enabled, the P0, P3, and U0 areas can be mapped onto any physical address space in 1-, 4-, or 64-Kbyte, or 1-Mbyte page units. By using an 8-bit address space identifier, the P0, P3, and U0 areas can be increased to a maximum of 256. Mapping from the virtual address space to the 29-bit physical address space is carried out using the TLB.
Physical address space
H'0000 0000
P0 area Cacheable
Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7
H'0000 0000
U0 area Cacheable
H'8000 0000 H'A000 0000 H'C000 0000
H'E000 0000
P1 area Cacheable P2 area Non-cacheable P3 area Cacheable P4 area Non-cacheable Privileged mode Address error
H'8000 0000
Store queue area Address error
H'E000 0000
H'FFFF FFFF
H'E400 0000 H'E500 0000 On-chip memory area H'E600 0000 Address error H'FFFF FFFF User mode
Figure 6.2 Virtual Address Space (AT in MMUCR = 0)
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Section 6 Memory Management Unit (MMU)
256
Physical 256 address space
Area 0 Area 1 Area 2 P0 area Cacheable Address translation possible Area 3 Area 4 Area 5 Area 6 Area 7 U0 area Cacheable Address translation possible
H'0000 0000
H'0000 0000
H'8000 0000
P1 area Cacheable H'A000 0000 Address translation not possible P2 area Non-cacheable Address translation not possible H'C000 0000 P3 area Cacheable Address translation possible H'E000 0000 P4 area Non-cacheable H'FFFF FFFF Address translation not possible Privileged mode
H'8000 0000
Address error
Store queue area Address error On-chip memory area Address error User mode
H'E000 0000 H'E400 0000 H'E500 0000 H'E600 0000 H'FFFF FFFF
Figure 6.3 Virtual Address Space (AT in MMUCR = 1)
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Section 6 Memory Management Unit (MMU)
* P0, P3, and U0 Areas: The P0, P3, and U0 areas allow address translation using the TLB and access using the cache. When the MMU is disabled, replacing the upper 3 bits of an address with 0s gives the corresponding physical address. Whether or not the cache is used is determined by the CCR setting. When the cache is used, switching between the copy-back method and the writethrough method for write accesses is specified by the WT bit in CCR. When the MMU is enabled, these areas can be mapped onto any physical address space in 1-, 4-, or 64-Kbyte, or 1-Mbyte page units using the TLB. When CCR is in the cache enabled state and the C bit for the corresponding page of the TLB entry is 1, accesses can be performed using the cache. When the cache is used, switching between the copy-back method and the write-through method for write accesses is specified by the WT bit of the TLB entry. When the P0, P3, and U0 areas are mapped onto the control register area which is allocated in the area 7 in physical address space by means of the TLB, the C bit for the corresponding page must be cleared to 0. * P1 Area: The P1 area does not allow address translation using the TLB but can be accessed using the cache. Regardless of whether the MMU is enabled or disabled, clearing the upper 3 bits of an address to 0 gives the corresponding physical address. Whether or not the cache is used is determined by the CCR setting. When the cache is used, switching between the copy-back method and the write-through method for write accesses is specified by the CB bit in CCR. * P2 Area: The P2 area does not allow address translation using the TLB and access using the cache. Regardless of whether the MMU is enabled or disabled, clearing the upper 3 bits of an address to 0 gives the corresponding physical address. * P4 Area: The P4 area is mapped onto the internal resource of this LSI. This area except the store queue and on-chip memory areas does not allow address translation using the TLB. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 6.4.
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Section 6 Memory Management Unit (MMU)
H'E000 0000 H'E400 0000 H'E500 0000 H'E600 0000 H'F000 0000 H'F100 0000 H'F200 0000 H'F300 0000 H'F400 0000 H'F500 0000 H'F600 0000 H'F700 0000 H'F800 0000
Store queue Reserved area On-chip memory area Reserved area Instruction cache address array Instruction cache data array Instruction TLB address array Instruction TLB data array Operand cache address array Operand cache data array Unified TLB and PMB address array Unified TLB and PMB data array
Reserved area
H'FC00 0000 Control register area H'FFFF FFFF
Figure 6.4 P4 Area The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). In user mode, the access right is specified by the SQMD bit in MMUCR. For details, see section 7.7, Store Queues. The area from H'E500 0000 to H'E5FF FFFF comprises addresses for accessing the on-chip memory. In user mode, the access right is specified by the RMD bit in RAMCR. For details, see section 8, L Memory. The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache address array. For details, see section 7.6.1, IC Address Array. The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data array. For details, see section 7.6.2, IC Data Array. The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB address array. For details, see section 6.6.1, ITLB Address Array. The area from H'F300 0000 to H'F37F FFFF is used for direct access to instruction TLB data array. For details, see section 6.6.2, ITLB Data Array.
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Section 6 Memory Management Unit (MMU)
The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address array. For details, see section 7.6.3, OC Address Array. The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data array. For details, see section 7.6.4, OC Data Array. The area from H'F600 0000 to H'F60F FFFF is used for direct access to the unified TLB address array. For details, see section 6.6.3, UTLB Address Array. The area from H'F700 0000 to H'F70F FFFF is used for direct access to unified TLB data array. For details, see section 6.6.4, UTLB Data Array. The area from H'F610 0000 to H'F61F FFFF is used for direct access to the PMB address array. For details, see section 6.7.5, Memory-Mapped PMB Configuration. The area from H'F710 0000 to H'F71F FFFF is used for direct access to the PMB data array. For details, see section 6.7.5, Memory-Mapped PMB Configuration. The area from H'FC00 0000 to H'FFFF FFFF is the on-chip peripheral module control register area. For details, see register descriptions in each section. Physical Address Space: This LSI supports a 29-bit physical address space. The physical address space is divided into eight areas as shown in figure 6.5. Area 7 is a reserved area. Only when area 7 in the physical address space is accessed using the TLB, addresses H'1C00 0000 to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the control register area in the P4 area in the virtual address space.
H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 H'1FFF FFFF
Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 (reserved area)
Figure 6.5 Physical Address Space
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Section 6 Memory Management Unit (MMU)
Address Translation: When the MMU is used, the virtual address space is divided into units called pages, and translation to physical addresses is carried out in these page units. The address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes. Fast address translation is achieved by caching the contents of the address translation table located in external memory into the TLB. In this LSI, basically, the ITLB is used for instruction accesses and the UTLB for data accesses. In the event of an access to an area other than the P4 area, the accessed virtual address is translated to a physical address. If the virtual address belongs to the P1 or P2 area, the physical address is uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3 area, the TLB is searched using the virtual address, and if the virtual address is recorded in the TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and processing switches to the TLB miss exception handling routine. In the TLB miss exception handling routine, the address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the TLB. After the return from the exception handling routine, the instruction which caused the TLB miss exception is re-executed. Single Virtual Memory Mode and Multiple Virtual Memory Mode: There are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the SV bit in MMUCR. In the single virtual memory system, a number of processes run simultaneously, using virtual address space on an exclusive basis, and the physical address corresponding to a particular virtual address is uniquely determined. In the multiple virtual memory system, a number of processes run while sharing the virtual address space, and particular virtual addresses may be translated into different physical addresses depending on the process. The only difference between the single virtual memory and multiple virtual memory systems in terms of operation is in the TLB address comparison method (see section 6.3.3, Address Translation Method). Address Space Identifier (ASID): In multiple virtual memory mode, an 8-bit address space identifier (ASID) is used to distinguish between multiple processes running simultaneously while sharing the virtual address space. Software can set the 8-bit ASID of the currently executing process in PTEH in the MMU. The TLB does not have to be purged when processes are switched by means of ASID. In single virtual memory mode, ASID is used to provide memory protection for multiple processes running simultaneously while using the virtual address space on an exclusive basis. Note: Two or more entries with the same virtual page number (VPN) but different ASID must not be set in the TLB simultaneously in single virtual memory mode.
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Section 6 Memory Management Unit (MMU)
6.2
Register Descriptions
The following registers are related to MMU processing. Table 6.1 Register Configuration
Abbreviation R/W PTEH PTEL TTB TEA MMUCR PASCR IRMCR R/W R/W R/W R/W R/W R/W R/W P4 Address* H'FF00 0000 H'FF00 0004 H'FF00 0008 H'FF00 000C H'FF00 0010 H'FF00 0070 H'FF00 0078 Area 7 Address* H'1F00 0000 H'1F00 0004 H'1F00 0008 H'1F00 000C H'1F00 0010 H'1F00 0070 H'1F00 0078 Size 32 32 32 32 32 32 32
Register Name Page table entry high register Page table entry low register Translation table base register TLB exception address register MMU control register Physical address space control register Instruction re-fetch inhibit control register
Note:
*
These P4 addresses are for the P4 area in the virtual address space. These area 7 addresses are accessed from area 7 in the physical address space by means of the TLB.
Table 6.2
Register States in Each Processing State
Abbreviation PTEH PTEL TTB TEA MMUCR PASCR IRMCR Power-on Reset Undefined Undefined Undefined Undefined Manual Reset Undefined Undefined Undefined Retained Sleep Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained
Register Name Page table entry high register Page table entry low register Translation table base register TLB exception address register MMU control register Physical address space control register Instruction re-fetch inhibit control register
H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained
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Section 6 Memory Management Unit (MMU)
6.2.1
Page Table Entry High Register (PTEH)
PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN bit by hardware. VPN varies according to the page size, but the VPN set by hardware when an exception occurs consists of the upper 22 bits of the virtual address which caused the exception. VPN setting can also be carried out by software. The number of the currently executing process is set in the ASID bit by software. ASID is not updated by hardware. VPN and ASID are recorded in the UTLB by means of the LDTLB instruction. After the ASID field in PTEH has been updated, execute one of the following three methods before an access (including an instruction fetch) to the P0, P3, or U0 area that uses the updated ASID value is performed. 1. Execute a branch using the RTE instruction. In this case, the branch destination may be the P0, P3, or U0 area. 2. Execute the ICBI instruction for any address (including non-cacheable area). 3. If the R2 bit in IRMCR is 0 (initial value) before updating the ASID field, the specific instruction does not need to be executed. However, note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after the ASID field has been updated. Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 VPN
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W
23
22
21
20
19
18
17
16
15
14
13
12 VPN
11
10
9
8
7
6
5
4 ASID
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
0 R
0 R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 31 to 10 9, 8
Bit Name VPN
Initial Value All 0
R/W R/W R
Description Virtual Page Number Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
7 to 0
ASID
R/W
Address Space Identifier
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Section 6 Memory Management Unit (MMU)
6.2.2
Page Table Entry Low Register (PTEL)
PTEL is used to hold the physical page number and page management information to be recorded in the UTLB by means of the LDTLB instruction. The contents of this register are not changed unless a software directive is issued.
Bit: Initial value: R/W: Bit: Initial value: R/W:
31
30
29
28
27
26
25
24
23
PPN
22
21
20
19
18
17
16
0 R 15
0 R 14
0 R 13
R/W 12
R/W 11
R/W 10
R/W 9
R/W 8 V
R/W 7 SZ1 R/W
R/W 6 PR1 R/W
R/W 5 PR0 R/W
R/W 4 SZ0 R/W
R/W 3 C R/W
R/W 2 D R/W
R/W 1 SH R/W
R/W 0 WT R/W
PPN R/W R/W R/W R/W R/W
R/W
0 R
R/W
Bit 31 to 29
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
28 to 10 9
PPN
0
R/W R
Physical Page Number Reserved For details on reading from or writing to this bit, see description in General Precautions on Handling of Product.
8 7 6 5 4 3 2 1 0
V SZ1 PR1 PR0 SZ0 C D SH WT

R/W R/W R/W R/W R/W R/W R/W R/W R/W
Page Management Information The meaning of each bit is same as that of corresponding bit in Common TLB (UTLB). For details, see section 6.3, TLB Functions.
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Section 6 Memory Management Unit (MMU)
6.2.3
Translation Table Base Register (TTB)
TTB is used to store the base address of the currently used page table, and so on. The contents of TTB are not changed unless a software directive is issued. This register can be used freely by software.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 TTB R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 TTB R/W R/W R/W R/W R/W
R/W
23
22
21
20
19
18
17
16
R/W 7
R/W 6
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6.2.4
TLB Exception Address Register (TEA)
After an MMU exception or address error exception occurs, the virtual address at which the exception occurred is stored. The contents of this register can be changed by software.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30
TEA
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Virtual address at which MMU exception or address error occurred R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0
R/W 15
R/W 14
TEA
Virtual address at which MMU exception or address error occurred R/W R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6.2.5
MMU Control Register (MMUCR)
The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area. After MMUCR has been updated, execute one of the following three methods before an access (including an instruction fetch) to the P0, P3, U0, or store queue area is performed. 1. Execute a branch using the RTE instruction. In this case, the branch destination may be the P0, P3, or U0 area. 2. Execute the ICBI instruction for any address (including non-cacheable area). 3. If the R2 bit in IRMCR is 0 (initial value) before updating MMUCR, the specific instruction does not need to be executed. However, note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after MMUCR has been updated.
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Section 6 Memory Management Unit (MMU)
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series. MMUCR contents can be changed by software. However, the LRUI and URC bits may also be updated by hardware.
Bit: Initial value: R/W: Bit: Initial value: R/W:
31
30
29
LRUI
28
27
26
25
24
23
22
21
URB
20
19
18
17
16
0 R/W 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R 9 SQMD
0 R 8 SV 0 R/W
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2 TI
0 R 1
0 R 0 AT
URC 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
0 R/W
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R
0 R/W
Bit 31 to 26
Bit Name LRUI
Initial Value All 0
R/W R/W
Description Least Recently Used ITLB These bits indicate the ITLB entry to be replaced. The LRU (least recently used) method is used to decide the ITLB entry to be replaced in the event of an ITLB miss. The entry to be purged from the ITLB can be confirmed using the LRUI bits. LRUI is updated by means of the algorithm shown below. x means that updating is not performed. 000xxx: ITLB entry 0 is used 1xx00x: ITLB entry 1 is used x1x1x0: ITLB entry 2 is used xx1x11: ITLB entry 3 is used xxxxxx: Other than above When the LRUI bit settings are as shown below, the corresponding ITLB entry is updated by an ITLB miss. Ensure that values for which "Setting prohibited" is indicated below are not set at the discretion of software. After a power-on or manual reset, the LRUI bits are initialized to 0, and therefore a prohibited setting is never made by a hardware update. x means "don't care". 111xxx: ITLB entry 0 is updated 0xx11x: ITLB entry 1 is updated x0x0x1: ITLB entry 2 is updated xx0x00: ITLB entry 3 is updated Other than above: Setting prohibited
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Section 6 Memory Management Unit (MMU)
Bit 25, 24
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
23 to 18
URB
All 0
R/W
UTLB Replace Boundary These bits indicate the UTLB entry boundary at which replacement is to be performed. Valid only when URB 0.
17, 16
All 0
R
Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
15 to 10
URC
All 0
R/W
UTLB Replace Counter These bits serve as a random counter for indicating the UTLB entry for which replacement is to be performed with an LDTLB instruction. This bit is incremented each time the UTLB is accessed. If URB > 0, URC is cleared to 0 when the condition URC = URB is satisfied. Also note that if a value is written to URC by software which results in the condition of URC > URB, incrementing is first performed in excess of URB until URC = H'3F. URC is not incremented by an LDTLB instruction.
9
SQMD
0
R/W
Store Queue Mode Bit Specifies the right of access to the store queues. 0: User/privileged access possible 1: Privileged access possible (address error exception in case of user access)
8
SV
0
R/W
Single Virtual Memory Mode/Multiple Virtual Memory Mode Switching Bit When this bit is changed, ensure that 1 is also written to the TI bit. 0: Multiple virtual memory mode 1: Single virtual memory mode
7 to 3
All 0
R
Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
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Section 6 Memory Management Unit (MMU)
Bit 2
Bit Name TI
Initial Value 0
R/W R/W
Description TLB Invalidate Bit Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB bits. This bit is always read as 0.
1
0
R
Reserved For details on reading from or writing to this bit, see description in General Precautions on Handling of Product.
0
AT
0
R/W
Address Translation Enable Bit These bits enable or disable the MMU. 0: MMU disabled 1: MMU enabled MMU exceptions are not generated when the AT bit is 0. In the case of software that does not use the MMU, the AT bit should be cleared to 0.
6.2.6
Physical Address Space Control Register (PASCR)
PASCR controls the operation in the physical address space.
Bit: Initial value: R/W: Bit: Initial value: R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4 UB
0 R 3
0 R 2
0 R 1
0 R 0
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
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Section 6 Memory Management Unit (MMU)
Bit 7 to 0
Initial Bit Name Value UB All 0
R/W R/W
Description Buffered Write Control for Each Area (64 Mbytes) When writing is performed without using the cache or in the cache write-through mode, these bits specify whether the next bus access from the CPU waits for the end of writing for each area. 0: The CPU does not wait for the end of writing bus access and starts the next bus access 1: The CPU waits for the end of writing bus access and starts the next bus access UB[7]: Corresponding to the control register area UB[6]: Corresponding to area 6 UB[5]: Corresponding to area 5 UB[4]: Corresponding to area 4 UB[3]: Corresponding to area 3 UB[2]: Corresponding to area 2 UB[1]: Corresponding to area 1 UB[0]: Corresponding to area 0
6.2.7
Instruction Re-Fetch Inhibit Control Register (IRMCR)
When the specific resource is changed, IRMCR controls whether the instruction fetch is performed again for the next instruction. The specific resource means the part of control registers, TLB, and cache. In the initial state, the instruction fetch is performed again for the next instruction after changing the resource. However, the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction every time the resource is changed. Therefore, it is recommended that each bit in IRMCR is set to 1 and the specific instruction should be executed after all necessary resources have been changed prior to execution of the program which uses changed resources. For details on the specific sequence, see descriptions in each resource.
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Section 6 Memory Management Unit (MMU)
Bit: Initial value: R/W: Bit: Initial value: R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4 R2
0 R 3 R1 0 R/W
0 R 2 LT 0 R/W
0 R 1 MT 0 R/W
0 R 0 MC 0 R/W
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
Bit 31 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
4
R2
0
R/W
Re-Fetch Inhibit 2 after Register Change When MMUCR, PASCR, CCR, PTEH, or RAMCR is changed, this bit controls whether re-fetch is performed for the next instruction. 0: Re-fetch is performed 1: Re-fetch is not performed
3
R1
0
R/W
Re-Fetch Inhibit 1 after Register Change When a register allocated in addresses H'FF200000 to H'FF2FFFFF is changed, this bit controls whether refetch is performed for the next instruction. 0: Re-fetch is performed 1: Re-fetch is not performed
2
LT
0
R/W
Re-Fetch Inhibit after LDTLB Execution This bit controls whether re-fetch is performed for the next instruction after the LDTLB instruction has been executed. 0: Re-fetch is performed 1: Re-fetch is not performed
1
MT
0
R/W
Re-Fetch Inhibit after Writing Memory-Mapped TLB This bit controls whether re-fetch is performed for the next instruction after writing memory-mapped ITLB/UTLB while the AT bit in MMUCR is set to 1. 0: Re-fetch is performed 1: Re-fetch is not performed
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Section 6 Memory Management Unit (MMU)
Bit 0
Bit Name MC
Initial Value 0
R/W R/W
Description Re-Fetch Inhibit after Writing Memory-Mapped IC This bit controls whether re-fetch is performed for the next instruction after writing memory-mapped IC while the ICE bit in CCR is set to 1. 0: Re-fetch is performed 1: Re-fetch is not performed
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Section 6 Memory Management Unit (MMU)
6.3
6.3.1
TLB Functions
Unified TLB (UTLB) Configuration
The UTLB is used for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2. As a table of address translation information to be recorded in the ITLB in the event of an ITLB miss The UTLB is so called because of its use for the above two purposes. Information in the address translation table located in external memory is cached into the UTLB. The address translation table contains virtual page numbers and address space identifiers, and corresponding physical page numbers and page management information. Figure 6.6 shows the UTLB configuration. The UTLB consists of 64 fully-associative type entries. Figure 6.7 shows the relationship between the page size and address format.
Entry 0 Entry 1 Entry 2
ASID [7:0] VPN [31:10] V ASID [7:0] VPN [31:10] V ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT PPN [28:10] SZ [1:0] SH C PR [1:0] D WT PPN [28:10] SZ [1:0] SH C PR [1:0] D WT
Entry 63
ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT
Figure 6.6 UTLB Configuration [Legend] * VPN: Virtual page number For 1-Kbyte page: Upper 22 bits of virtual address For 4-Kbyte page: Upper 20 bits of virtual address For 64-Kbyte page: Upper 16 bits of virtual address For 1-Mbyte page: Upper 12 bits of virtual address * ASID: Address space identifier Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, this identifier is compared with the ASID in PTEH when address comparison is performed.
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Section 6 Memory Management Unit (MMU)
* SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. * SZ[1:0]: Page size bits Specify the page size. 00: 1-Kbyte page 01: 4-Kbyte page 10: 64-Kbyte page 11: 1-Mbyte page * V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. * PPN: Physical page number Upper 22 bits of the physical address of the physical page number. With a 1-Kbyte page, PPN[28:10] are valid. With a 4-Kbyte page, PPN[28:12] are valid. With a 64-Kbyte page, PPN[28:16] are valid. With a 1-Mbyte page, PPN[28:20] are valid. The synonym problem must be taken into account when setting the PPN (see section 6.4.5, Avoiding Synonym Problems). * PR[1:0]: Protection key data 2-bit data expressing the page access right as a code. 00: Can be read from only in privileged mode 01: Can be read from and written to in privileged mode 10: Can be read from only in privileged or user mode 11: Can be read from and written to in privileged mode or user mode
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Section 6 Memory Management Unit (MMU)
* C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When the control register area is mapped, this bit must be cleared to 0. * D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed * WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode
* 1-Kbyte page 31
Virtual address 10 9
VPN Offset
0
28
Physical address 10 9
PPN Offset
0
* 4-Kbyte page 31
Virtual address 12 11
VPN Offset
0
28
Physical address 12 11
PPN Offset
0
* 64-Kbyte page 31
Virtual address 16 15 VPN Offset 0
28
Physical address 16 15 PPN Offset 0
* 1-Mbyte page Virtual address 31 20 19 VPN Offset
0
28 PPN
Physical address 20 19
Offset
0
Figure 6.7 Relationship between Page Size and Address Format
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Section 6 Memory Management Unit (MMU)
6.3.2
Instruction TLB (ITLB) Configuration
The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 6.8 shows the ITLB configuration. The ITLB consists of four fully-associative type entries.
Entry 0 ASID [7:0] VPN [31:10] V Entry 1 ASID [7:0] VPN [31:10] V Entry 2 ASID [7:0] VPN [31:10] V Entry 3 ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR PPN [28:10] SZ [1:0] SH C PR PPN [28:10] SZ [1:0] SH C PR PPN [28:10] SZ [1:0] SH C PR
Notes: 1. The D and WT bits are not supported. 2. There is only one PR bit, corresponding to the upper bit of the PR bits in the UTLB.
Figure 6.8 ITLB Configuration
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Section 6 Memory Management Unit (MMU)
6.3.3
Address Translation Method
Figure 6.9 shows a flowchart of a memory access using the UTLB.
Data access to virtual address (VA) VA is in P4 area VA is in P2 area
0
VA is in P1 area
CCR.OCE?
VA is in P0, U0, or P3 area MMUCR.AT = 1
No Yes
0
CCR.OCE?
1
1
1
CCR.CB?
0
0
CCR.WT?
1
No No
SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)
Yes
VPNs match and V = 1
Yes No
VPNs match, ASIDs match, and V=1
Yes
Data TLB miss exception
No
Only one entry matches
Yes
Data TLB multiple hit exception 0 (User)
PR? 00 or 01 W 10 R/W? R 11 R/W? R D? 0 W W 1 01 or 11 R/W? R PR?
SR.MD?
1 (Privileged)
00 or 10 W R/W? R
Data TLB protection violation exception
Initial page write exception
Data TLB protection violation exception
No
C = 1 and CCR.OCE = 1
Yes
0
WT? 1
Internal resource access
Memory access (Non-cacheable)
Cache access in copy-back mode
Cache access in write-through mode
Figure 6.9 Flowchart of Memory Access Using UTLB
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Section 6 Memory Management Unit (MMU)
Figure 6.10 shows a flowchart of a memory access using the ITLB.
Instruction access to virtual address (VA) VA is in P4 area VA is in P2 area VA is in P1 area VA is in P0, U0, or P3 area
No 0 CCR.ICE? 1
MMUCR.AT = 1
Yes
No No
SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)
Yes
VPNs match and V = 1
Yes No
Hardware ITLB miss handling
Yes
VPNs match, ASIDs match, and V=1
Yes
Search UTLB
No
Record in ITLB
Match?
No
Only one entry matches
Yes
Instruction TLB miss exception
Instruction TLB multiple hit exception 0 (User)
0
SR.MD? 1 (Privileged)
PR?
1
Instruction TLB protection violation exception
No
C=1 and CCR.ICE = 1
Yes
Internal resource access
Memory access (Non-cacheable)
Cache access
Figure 6.10 Flowchart of Memory Access Using ITLB
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Section 6 Memory Management Unit (MMU)
6.4
6.4.1
MMU Functions
MMU Hardware Management
This LSI supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 2. The MMU determines the cache access status on the basis of the page management information read during address translation (C and WT bits). 3. If address translation cannot be performed normally in a data access or instruction access, the MMU notifies software by means of an MMU exception. 4. If address translation information is not recorded in the ITLB in an instruction access, the MMU searches the UTLB. If the necessary address translation information is recorded in the UTLB, the MMU copies this information into the ITLB in accordance with the LRUI bit setting in MMUCR. 6.4.2 MMU Software Management
Software processing for the MMU consists of the following: 1. Setting of MMU-related registers. Some registers are also partially updated by hardware automatically. 2. Recording, deletion, and reading of TLB entries. There are two methods of recording UTLB entries: by using the LDTLB instruction, or by writing directly to the memory-mapped UTLB. ITLB entries can only be recorded by writing directly to the memory-mapped ITLB. Deleting or reading UTLB/ITLB entries is enabled by accessing the memory-mapped UTLB/ITLB. 3. MMU exception handling. When an MMU exception occurs, processing is performed based on information set by hardware.
Rev. 1.00 Oct. 01, 2007 Page 162 of 1956 REJ09B0256-0100
Section 6 Memory Management Unit (MMU)
6.4.3
MMU Instruction (LDTLB)
A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, this LSI copies the contents of PTEH and PTEL to the UTLB entry indicated by the URC bit in MMUCR. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry. As the LDTLB instruction changes address translation information, ensure that it is issued by a program in the P1 or P2 area. After the LDTLB instruction has been executed, execute one of the following three methods before an access (include an instruction fetch) the area where TLB is used to translate the address is performed. 1. Execute a branch using the RTE instruction. In this case, the branch destination may be the area where TLB is used to translate the address. 2. Execute the ICBI instruction for any address (including non-cacheable area). 3. If the LT bit in IRMCR is 0 (initial value) before executing the LDTLB instruction, the specific instruction does not need to be executed. However, note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after MMUCR has been updated. Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH series. The operation of the LDTLB instruction is shown in figure 6.11.
Rev. 1.00 Oct. 01, 2007 Page 163 of 1956 REJ09B0256-0100
Section 6 Memory Management Unit (MMU)
MMUCR 31
LRUI
26252423
-- URB
18171615
-- URC
10 9 8 7
SV --
3210
TI -- AT
Entry specification
SQMD
PTEH 31 VPN
10 9 8 7
-- ASID
0
PTEL 31 2928
--
PPN
10 9 8 7 6 5 4 3 2 1 0
--V
SZ1 PR[1:0] SZ0 C
D SH WT
Write
Entry 0 Entry 1 Entry 2
ASID [7:0] ASID [7:0] ASID [7:0]
VPN [31:10] VPN [31:10] VPN [31:10]
V V V
PPN [28:10] PPN [28:10] PPN [28:10]
SZ [1:0] SZ [1:0] SZ [1:0]
SH C PR [1:0] SH C PR [1:0] SH C PR [1:0]
D D D
WT WT WT
Entry 63
ASID [7:0]
VPN [31:10]
V
PPN [28:10]
UTLB
SZ [1:0]
SH C PR [1:0]
D
WT
Figure 6.11 Operation of LDTLB Instruction 6.4.4 Hardware ITLB Miss Handling
In an instruction access, this LSI searches the ITLB. If it cannot find the necessary address translation information (ITLB miss occurred), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB. This procedure is known as hardware ITLB miss handling. If the necessary address translation information is not found in the UTLB search, an instruction TLB miss exception is generated and processing passes to software.
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Section 6 Memory Management Unit (MMU)
6.4.5
Avoiding Synonym Problems
When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses are mapped onto a single physical address, the same physical address data is recorded in a number of cache entries, and it becomes impossible to guarantee data integrity. This problem does not occur with the instruction TLB and instruction cache because data is only read in these cases. In this LSI, entry specification is performed using bits 12 to 5 of the virtual address in order to achieve fast operand cache operation. However, bits 12 to 10 of the virtual address in the case of a 1-Kbyte page, and bit 12 of the virtual address in the case of a 4-Kbyte page, are subject to address translation. As a result, bits 12 to 10 of the physical address after translation may differ from bits 12 to 10 of the virtual address. Consequently, the following restrictions apply to the recording of address translation information in UTLB entries. * When address translation information whereby a number of 1-Kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN[12:10] values are the same. * When address translation information whereby a number of 4-Kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN[12] value is the same. * Do not use 1-Kbyte page UTLB entry physical addresses with UTLB entries of a different page size. * Do not use 4-Kbyte page UTLB entry physical addresses with UTLB entries of a different page size. The above restrictions apply only when performing accesses using the cache. Note: When multiple items of address translation information use the same physical memory to provide for future expansion of the SuperH RISC engine family, ensure that the VPN[20:10] values are the same. Also, do not use the same physical address for address translation information of different page sizes.
Rev. 1.00 Oct. 01, 2007 Page 165 of 1956 REJ09B0256-0100
Section 6 Memory Management Unit (MMU)
6.5
MMU Exceptions
There are seven MMU exceptions: instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. Refer to figures 6.9 and 6.10 for the conditions under which each of these exceptions occurs. 6.5.1 Instruction TLB Multiple Hit Exception
An instruction TLB multiple hit exception occurs when more than one ITLB entry matches the virtual address to which an instruction access has been made. If multiple hits occur when the UTLB is searched by hardware in hardware ITLB miss handling, an instruction TLB multiple hit exception will result. When an instruction TLB multiple hit exception occurs, a reset is executed and cache coherency is not guaranteed. Hardware Processing: In the event of an instruction TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The ITLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated.
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Section 6 Memory Management Unit (MMU)
6.5.2
Instruction TLB Miss Exception
An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling routine. The instruction TLB miss exception processing carried out by hardware and software is shown below. This is the same as the processing for a data TLB miss exception. Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. 2. 3. 4. Sets the VPN of the virtual address at which the exception occurred in PTEH. Sets the virtual address at which the exception occurred in TEA. Sets exception code H'040 in EXPEVT. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. Sets the MD bit in SR to 1, and switches to privileged mode. Sets the BL bit in SR to 1, and masks subsequent exception requests. Sets the RB bit in SR to 1. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the instruction TLB miss exception handling routine.
5. 6. 7. 8. 9.
Software Processing (Instruction TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. 2. When the entry to be replaced in entry replacement is specified by software, write that value to the URC bits in MMUCR. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH and PTEL to the TLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction.
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Section 6 Memory Management Unit (MMU)
6.5.3
Instruction TLB Protection Violation Exception
An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an instruction TLB protection violation exception, hardware carries out the following processing: 1. 2. 3. 4. Sets the VPN of the virtual address at which the exception occurred in PTEH. Sets the virtual address at which the exception occurred in TEA. Sets exception code H'0A0 in EXPEVT. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. Sets the MD bit in SR to 1, and switches to privileged mode. Sets the BL bit in SR to 1, and masks subsequent exception requests. Sets the RB bit in SR to 1. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the instruction TLB protection violation exception handling routine.
5. 6. 7. 8. 9.
Software Processing (Instruction TLB Protection Violation Exception Handling Routine): Resolve the instruction TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction.
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Section 6 Memory Management Unit (MMU)
6.5.4
Data TLB Multiple Hit Exception
A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. When a data TLB multiple hit exception occurs, a reset is executed, and cache coherency is not guaranteed. The contents of PPN in the UTLB prior to the exception may also be corrupted. Hardware Processing: In the event of a data TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The UTLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. 6.5.5 Data TLB Miss Exception
A data TLB miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the UTLB entries. The data TLB miss exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1.
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Section 6 Memory Management Unit (MMU)
9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the data TLB miss exception handling routine. Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. 2. When the entry to be replaced in entry replacement is specified by software, write that value to the URC bits in MMUCR. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH and PTEL to the UTLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 6.5.6 Data TLB Protection Violation Exception
A data TLB protection violation exception occurs when, even though a UTLB entry contains address translation information matching the virtual address to which a data access is made, the actual access type is not permitted by the access right specified by the PR bit. The data TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB protection violation exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'0A0 in the case of a read, or H'0C0 in the case of a write in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
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Section 6 Memory Management Unit (MMU)
8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the data TLB protection violation exception handling routine. Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 6.5.7 Initial Page Write Exception
An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted. The initial page write exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an initial page write exception, hardware carries out the following processing: 1. 2. 3. 4. Sets the VPN of the virtual address at which the exception occurred in PTEH. Sets the virtual address at which the exception occurred in TEA. Sets exception code H'080 in EXPEVT. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. Sets the MD bit in SR to 1, and switches to privileged mode. Sets the BL bit in SR to 1, and masks subsequent exception requests. Sets the RB bit in SR to 1. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the initial page write exception handling routine.
5. 6. 7. 8. 9.
Software Processing (Initial Page Write Exception Handling Routine): Software is responsible for the following processing: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry.
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Section 6 Memory Management Unit (MMU)
3. Write to PTEL the values of the PPN, PR, SZ, C, D, WT, SH, and V bits in the page table entry recorded in external memory. 4. When the entry to be replaced in entry replacement is specified by software, write that value to the URC bits in MMUCR. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 5. Execute the LDTLB instruction and write the contents of PTEH and PTEL to the UTLB. 6. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction.
6.6
Memory-Mapped TLB Configuration
To enable the ITLB and UTLB to be managed by software, their contents are allowed to be read from and written to by a program in the P2 area with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. After the memory-mapped TLB has been accessed, execute one of the following three methods before an access (including an instruction fetch) to an area other than the P2 area is performed. 1. Execute a branch using the RTE instruction. In this case, the branch destination may be an area other than the P2 area. 2. Execute the ICBI instruction for any address (including non-cacheable area). 3. If the MT bit in IRMCR is 0 (initial value) before accessing the memory-mapped TLB, the specific instruction does not need to be executed. However, note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after MMUCR has been updated. Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series. The ITLB and UTLB are allocated to the P4 area in the virtual address space. VPN, V, and ASID in the ITLB can be accessed as an address array, PPN, V, SZ, PR, C, and SH as a data array. VPN, D, V, and ASID in the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D, WT, and SH as a data array. V and D can be accessed from both the address array side and the data array side. Only longword access is possible. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined.
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Section 6 Memory Management Unit (MMU)
6.6.1
ITLB Address Array
The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field. In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array and the entry is specified by bits [9:8]. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, bits [31:10] indicate VPN, bit [8] indicates V, and bits [7:0] indicate ASID. The following two kinds of operation can be used on the ITLB address array: 1. ITLB address array read VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB address array write VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to the entry set in the address field.
24 23 31 10 9 8 7 2 10 Address field 1 1 1 1 0 0 1 0 * * * * * * * * * * * * * E * * * * * * 0 0 31 Data field VPN: V: E: *: VPN Virtual page number Validity bit Entry Don't care 10 9 8 7 V ASID 0
ASID: Address space identifier : Reserved bits (write value should be 0, and read value is undefined )
Figure 6.12 Memory-Mapped ITLB Address Array
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Section 6 Memory Management Unit (MMU)
6.6.2
ITLB Data Array
The ITLB data array is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field. In the address field, bits [31:23] have the value H'F30 indicating ITLB data array and the entry is specified by bits [9:8]. In the data field, bits [28:10] indicate PPN, bit [8] indicates V, bits [7] and [4] indicate SZ, bit [6] indicates PR, bit [3] indicates C, and bit [1] indicates SH. The following two kinds of operation can be used on ITLB data array: 1. ITLB data array read PPN, V, SZ, PR, C, and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB data array write PPN, V, SZ, PR, C, and SH specified in the data field are written to the ITLB entry corresponding to the entry set in the address field.
31 24 23 10 9 8 7 210 Address field 1 1 1 1 0 0 1 1 0 * * * * * * * * * * * * E * * * * * * 0 0
31 30 29 28 10 9 8 7 6 5 4 3 2 1 0
PPN
Data field
V
C
PPN: V: E: SZ[1:0]: *:
Physical page number Validity bit Entry Page size bits Don't care
PR: C: SH: :
SZ1 SZ0 PR SH Protection key data Cacheability bit Share status bit Reserved bits (write value should be 0, and read value is undefined )
Figure 6.13 Memory-Mapped ITLB Data Array
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Section 6 Memory Management Unit (MMU)
6.6.3
UTLB Address Array
The UTLB address array is allocated to addresses H'F600 0000 to H'F60F FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, D, V, and ASID to be written to the address array are specified in the data field. In the address field, bits [31:20] have the value H'F60 indicating the UTLB address array and the entry is specified by bits [13:8]. Bit [7] that is the association bit (A bit) in the address field specifies whether address comparison is performed in a write to the UTLB address array. In the data field, bits [31:10] indicate VPN, bit [9] indicates D, bit [8] indicates V, and bits [7:0] indicate ASID. The following three kinds of operation can be used on the UTLB address array: 1. UTLB address array read VPN, D, V, and ASID are read into the data field from the UTLB entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. UTLB address array write (non-associative) VPN, D, V, and ASID specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. UTLB address array write (associative) When a write is performed with the A bit in the address field set to 1, comparison of all the UTLB entries is carried out using the VPN specified in the data field and ASID in PTEH. The usual address comparison rules are followed, but if a UTLB miss occurs, the result is no operation, and an exception is not generated. If the comparison identifies a UTLB entry corresponding to the VPN specified in the data field, D and V specified in the data field are written to that entry. This associative operation is simultaneously carried out on the ITLB, and if a matching entry is found in the ITLB, V is written to that entry. Even if the UTLB comparison results in no operation, a write to the ITLB is performed as long as a matching entry is found in the ITLB. If there is a match in both the UTLB and ITLB, the UTLB information is also written to the ITLB.
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Section 6 Memory Management Unit (MMU)
31
20 19
14 13 E
87
210
Address field 1 1 1 1 0 1 1 0 0 0 0 0 * * * * * * 31 Data field VPN: V: E: D: *: Virtual page number Validity bit Entry Dirty bit Don't care VPN
A*****00 0 ASID
10 9 8 7 DV
ASID: Address space identifier A: Association bit : Reserved bits (write value should be 0 and read value is undefined )
Figure 6.14 Memory-Mapped UTLB Address Array 6.6.4 UTLB Data Array
The UTLB data array is allocated to addresses H'F700 0000 to H'F70F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to data array are specified in the data field. In the address field, bits [31:20] have the value H'F70 indicating UTLB data array and the entry is specified by bits [13:8]. In the data field, bits [28:10] indicate PPN, bit [8] indicates V, bits [7] and [4] indicate SZ, bits [6:5] indicate PR, bit [3] indicates C, bit [2] indicates D, bit [1] indicates SH, and bit [0] indicates WT. The following two kinds of operation can be used on UTLB data array: 1. UTLB data array read PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array write PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry corresponding to the entry set in the address field.
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Section 6 Memory Management Unit (MMU)
31
2019
14 13
87 E
210
Address field 1 1 1 1 0 1 1 1 0 0 0 0 * * * * * * 31 Data field PPN: V: E: SZ: D: *: 29 28
PPN
* * * * * *0 0
10 9 8 7 6 5 4 3 2 1 0 V PR: C: SH: WT: :
PR CD
Physical page number Validity bit Entry Page size bits Dirty bit Don't care
SH Protection key data SZ1 WT Cacheability bit Share status bit Write-through bit Reserved bits (write value should be 0 and read value is undefined )
Figure 6.15 Memory-Mapped UTLB Data Array
6.7
32-Bit Address Extended Mode
Setting the SE bit in PASCR to 1 changes mode from 29-bit address mode which handles the 29bit physical address space to 32-bit address extended mode which handles the 32-bit physical address space.
29-bits address space 0.5GB 32-bit address space
Virtual address space
Virtual address space U0/P0 (2GB)
U0/P0 (2GB)
4GB P1(0.5GB) P2(0.5GB) P3(0.5GB) P4(0.5GB) P1/P2 (1GB) P3(0.5GB) P4(0.5GB)
29-bit Physical address space (Normal mode)
32-bit Physical address space (Extended mode)
Figure 6.16 Physical Address Space (32-Bit Address Extended Mode)
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Section 6 Memory Management Unit (MMU)
6.7.1
Overview of 32-Bit Address Extended Mode
In 32-bit address extended mode, the privileged space mapping buffer (PMB) is introduced. The PMB maps virtual addresses in the P1 or P2 area which are not translated in 29-bit address mode to the 32-bit physical address space. In areas which are target for address translation of the TLB (UTLB/ITLB), upper three bits in the PPN field of the UTLB or ITLB are extended and then addresses after the TLB translation can handle the 32-bit physical addresses. As for the cache operation, P1 area is cacheable and P2 area is non-cacheable in the case of 29-bit address mode, but the cache operation of both P1 and P2 area are determined by the C bit and WT bit in the PMB in the case of 32-bit address mode. 6.7.2 Transition to 32-Bit Address Extended Mode
This LSI enters 29-bit address mode after a power-on reset. Transition is made to 32-bit address extended mode by setting the SE bit in PASCR to 1. In 32-bit address extended mode, the MMU operates as follows. 1. When the AT bit in MMUCR is 0, virtual addresses in the U0, P0, or P3 area become 32-bit physical addresses. Addresses in the P1 or P2 area are translated according to the PMB mapping information. B'10 should be set to the upper 2 bits of virtual page number (VPN[31:30]) in the PMB in order to indicate P1 or P2 area. The operation is not guaranteed when the value except B'10 is set to these bits. 2. When the AT bit in MMUCR is 1, virtual addresses in the U0, P0, or P3 area are translated to 32-bit physical addresses according to the TLB conversion information. Addresses in the P1 or P2 area are translated according to the PMB mapping information. B'10 should be set to the upper 2 bits of virtual page number (VPN[31:30]) in the PMB in order to indicate P1 or P2 area. The operation is not guaranteed when the value except B'10 is set to these bits. 3. Regardless of the setting of the AT bit in MMUCR, bits 31 to 29 in physical addresses become B'111 in the control register area (addresses H'FC00 0000 to H'FFFF FFFF). When the control register area is recorded in the UTLB and accessed, B'111 should be set to PPN[31:29].
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Section 6 Memory Management Unit (MMU)
6.7.3
Privileged Space Mapping Buffer (PMB) Configuration
In 32-bit address extended mode, virtual addresses in the P1 or P2 area are translated according to the PMB mapping information. The PMB has 16 entries and configuration of each entry is as follows.
Entry 0 Entry 1 Entry 2
VPN [31:24] VPN [31:24] VPN [31:24]
V V V
PPN [31:24] PPN [31:24] PPN [31:24]
SZ [1:0] SZ [1:0] SZ [1:0]
C UB WT C UB WT C UB WT
Entry 15
VPN [31:24]
V
PPN [31:24]
SZ [1:0]
C UB WT
Figure 6.17 PMB Configuration [Legend] * VPN: Virtual page number For 16-Mbyte page: Upper 8 bits of virtual address For 64-Mbyte page: Upper 6 bits of virtual address For 128-Mbyte page: Upper 5 bits of virtual address For 512-Mbyte page: Upper 3 bits of virtual address Note: B'10 should be set to the upper 2 bits of VPN in order to indicate P1 or P2 area. * SZ: Page size bits Specify the page size. 00: 16-Mbyte page 01: 64-Mbyte page 10: 128-Mbyte page 11: 512-Mbyte page * V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset.
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Section 6 Memory Management Unit (MMU)
* PPN: Physical page number Upper 8 bits of the physical address of the physical page number. With a 16-Mbyte page, PPN[31:24] are valid. With a 64-Mbyte page, PPN[31:26] are valid. With a 128-Mbyte page, PPN[31:27] are valid. With a 512-Mbyte page, PPN[31:29] are valid. * C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable * WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode * UB: Buffered write bit Specifies whether a buffered write is performed. 0: Buffered write (Data access of subsequent processing proceeds without waiting for the write to complete.) 1: Unbuffered write (Data access of subsequent processing is stalled until the write has completed.)
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Section 6 Memory Management Unit (MMU)
6.7.4
PMB Function
This LSI supports the following PMB functions. 1. Only memory-mapped write can be used for writing to the PMB. The LDTLB instruction cannot be used to write to the PMB. 2. Software must ensure that every accessed P1 or P2 address has a corresponding PMB entry before the access occurs. When an access to an address in the P1 or P2 area which is not recorded in the PMB is made, this LSI is reset by the TLB. In this case, the accessed address in the P1 or P2 area which causes the TLB reset is stored in the TEA and code H140 in the EXPEVT. 3. This LSI does not guarantee the operation when multiple hit occurs in the PMB. Special care should be taken when the PMB mapping information is recorded by software. 4. The PMB does not have an associative write function. 5. Since there is no PR field in the PMB, read/write protection cannot be preformed. The address translation target of the PMB is the P1 or P2 address. In user mode access, an address error exception occurs. 6. Both entries from the UTLB and PMB are mixed and recorded in the ITLB by means of the hardware ITLB miss handling. However, these entries can be identified by checking whether VPN[31:30] is 10 or not. When an entry from the PMB is recorded in the ITLB, H00, 01, and 1 are recorded in the ASID, PR, and SH fields which do not exist in the PMB, respectively.
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Section 6 Memory Management Unit (MMU)
6.7.5
Memory-Mapped PMB Configuration
To enable the PMB to be managed by software, its contents are allowed to be read from and written to by a P1 or P2 area program with a MOV instruction in privileged mode. The PMB address array is allocated to addresses H'F610 0000 to H'F61F FFFF in the P4 area and the PMB data array to addresses H'F710 0000 to H'F71F FFFF in the P4 area. VPN and V in the PMB can be accessed as an address array, PPN, V, SZ, C, WT, and UB as a data array. V can be accessed from both the address array side and the data array side. A program which executes a PMB memory-mapped access should be placed in the page area at which the C bit in PMB is cleared to 0. 1. PMB address array read When memory reading is performed while bits 31 to 20 in the address field are specified as H'F61 which indicates the PMB address array and bits 11 to 8 in the address field as an entry, bits 31 to 24 in the data field are read as VPN and bit 8 in the data field as V. 2. PMB address array write When memory writing is performed while bits 31 to 20 in the address field are specified as H'F61 which indicates the PMB address array and bits 11 to 8 in the address field as an entry, and bits 31 to 24 in the data field are specified as VPN and bit 8 in the data field as V, data is written to the specified entry. 3. PMB data array read When memory reading is performed while bits 31 to 20 in the address field are specified as H'F71 which indicates the PMB data array and bits 11 to 8 in the address field as an entry, bits 31 to 24 in the data field are read as PPN, bit 9 in the data field as UB, bit 8 in the data field as V, bits 7 and 4 in the data field as SZ, bit 3 in the data field as C, and bit 0 in the data field as WT. 4. PMB data array write When memory writing is performed while bits 31 to 20 in the address field are specified as H'F71 which indicates the PMB data array and bits 11 to 8 in the address field as an entry, and bits 31 to 24 in the data field are specified as PPN, bit 9 in the data field as UB, bit 8 in the data field as V, bits 7 and 4 in the data field as SZ, bit 3 in the data field as C, and bit 0 in the data field as WT, data is written to the specified entry.
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Section 6 Memory Management Unit (MMU)
87 31 20 19 0 12 11 Address field 1 1 1 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 E 00 0 0 0 0 0 0
31 Data field
VPN
24 23
8
0
V : Reserved bits (write value should be 0 and read value is undefined )
VPN: Physical page number V: Validity bit E: Entry
Figure 6.18 Memory-Mapped PMB Address Array
31 0 20 19 87 12 11 Address field 1 1 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 E 00000000
31 Data field
PPN
24 23
10 9 8 7 6 5 4 3 2 1 0 UB V
C
PPN: Physical page number V: Validity bit E: Entry SZ: Page size bits
UB: Buffered write bit SZ C: Cacheability bit WT: Write-through bit : Reserved bits (write value should be 0 and read value is undefined )
WT
Figure 6.19 Memory-Mapped PMB Data Array
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Section 6 Memory Management Unit (MMU)
6.7.6
Notes on Using 32-Bit Address Extended Mode
When using 32-bit address extended mode, note that the items described in this section are extended or changed as follows. PASCR: The SE bit is added in bit 31 in the control register (PASCR). The bits 6 to 0 of the UB in the PASCR are invalid (Note that the bit 7 of the UB is still valid). When writing to the P1 or P2 area, the UB bit in the PMB controls whether a buffered write is performed or not. When the MMU is enabled, the UB bit in the TLB controls writing to the P0, P3, or U0 area. When the MMU is disabled, writing to the P0, P3, or U0 area is always performed as a buffered write.
Bit 31 30 to 8 Bit Name SE Initial Value 0 All 0 R/W R/W R Description 0: 29-bit address mode 1: 32-bit address extended mode Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product. 7 to 0 UB All 0 R/W Buffered Write Control for Each Area (64 Mbytes) When writing is performed without using the cache or in the cache write-through mode, these bits specify whether the CPU waits for the end of writing for each area. 0: The CPU does not wait for the end of writing 1: The CPU stalls and waits for the end of writing UB[7]: Corresponding to the control register area UB[6:0]: These bits are invalid in 32-bit address extended mode.
ITLB: The PPN field in the ITLB is extended to bits 31 to 10. UTLB: The PPN field in the UTLB is extended to bits 31 to 10. The same UB bit as that in the PMB is added in each entry of the UTLB.
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Section 6 Memory Management Unit (MMU)
* UB: Buffered write bit Specifies whether a buffered write is performed. 0: Buffered write (Subsequent processing proceeds without waiting for the write to complete.) 1: Unbuffered write (Subsequent processing is stalled until the write has completed.) In a memory-mapped TLB access, the UB bit can be read from or written to by bit 9 in the data array. PTEL: The same UB bit as that in the PMB is added in bit 9 in PTEL. This UB bit is written to the UB bit in the UTLB by the LDTLB instruction. The PPN field is extended to bits 31 to 10. CCR.CB: The CB bit in CCR is invalid. Whether a cacheable write for the P1 area is performed in copy-back mode or write-though mode is determined by the WT bit in the PMB. IRMCR.MT: The MT bit in IRMCR is valid for a memory-mapped PMB write. QACR0, QACR1: AREA0[4:2]/AREA1[4:2] fields of QACR0/QACR1 are extended to AREA0[7:2]/AREA1[7:2] corresponding to physical address [31:26]. See section 7.2.2, Queue Address Control Register 0 (QACR0) and section 7.2.3, Queue Address Control Register 1 (QACR1). LSA0, LSA1, LDA0, LDA1: L0SADR, L1SADR, L0DADR and L1DADR fields are extended to bits 31 to 10. See section 8.2.2, L Memory Transfer Source Address Register 0 (LSA0), section 8.2.3, L Memory Transfer Source Address Register 1 (LSA1), section 8.2.4, L Memory Transfer Destination Address Register 0 (LDA0), and section 8.2.5, L Memory Transfer Destination Address Register 1 (LDA1). When using 32-bit address mode, the following notes should be applied to software. 1. For the SE bit switching, only switching from 0 to 1 is supported in Cache and MMU disabled boot routine after a power-on reset or manual reset. 2. After switching the SE bit, an area in which the program is allocated becomes the target of the PMB address translation. Therefore, the area should be recorded in the PMB before switching the SE bit. An address which may be accessed in the P1 or P2 area such as the exception handler should also be recorded in the PMB. 3. When an external memory access occurs by an operand memory access located before the MOV.L instruction which switches the SE bit, external memory space addresses accessed in both address modes should be the same. 4. Note that the V bit is mapped to both address array and data array in PMB registration. That is, first write 0 to the V bit in one of arrays and then write 1 to the V bit in another array.
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Section 6 Memory Management Unit (MMU)
6.8
Usage Notes
When using an LDTLB instruction instead of software to a value to the MMUCR. URC, execute 1 or 2 below. 1. In 29-bit address mode, follow A. and B. below. In 32-bit address mode, follow A. through B. below. A. Place the TLB miss exception handling routine*1 only in the P1 or P2 area so that all the instruction accesses*3 in the TLB miss exception handling routine should occur solely in the P1 or P2 area. B. Use only one page of the PMB for instruction accesses*3 in the TLB miss exception handling routine*1. In 32-bit address mode, do not place them in the last 64 bytes of a page of the PMB. C. In 32-bit address mode, obey 1 and 2 below when recording information in the UTLB in the MMU-related exception*2 handling routine. a. If a TLB miss exception occurs, do not record the page, in which the exception has occurred, in the UTLB using the following two operations. - Specifies the protection key data that causes a protection violation exception upon reexecution of the instruction that has caused the TLB miss exception and records the page, in which the TLB miss exception has occurred, in the UTLB. - Specifies the protection key data that does not cause a protection violation exception in the protection violation exception handling routine to record the page in the UTLB and re-executes the instruction that has caused the protection violation exception. b. Exclude the pages for which software has once set 1 to the dirty bit upon occurrence of an initial page write exception and intentionally deleted from the TLB or set 0 to the dirty bit. D. Do not make an attempt to execute the FDIV or FSQRT instruction in the MMU-related exception handling routine. 2. If a TLB miss exception occurs, add 1 to MMUCR.URC before executing an LDTLB instruction. Notes: 1. An exception handling routine is an entire set of instructions that are executed from the address (VBR + offset) upon occurrence of an exception to the RTE for returning to the original program or to the RTE delay slot. 2. MMU-related exceptions are: instruction TLB miss exception, instruction TLB miss protection violation exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. 3. Instruction accesses include the PREFI and ICBI instructions.
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Section 7 Caches
Section 7 Caches
This LSI has an on-chip 32-Kbyte instruction cache (IC) for instructions and an on-chip 32-Kbyte operand cache (OC) for data.
7.1
Features
The features of the cache are given in table 7.1. This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. The features of the store queues are given in table 7.2. Table 7.1
Item Capacity Type Line size Entries Write method Replacement method
Cache Features
Instruction Cache 32-Kbyte cache Operand Cache 32-Kbyte cache
4-way set-associative, virtual 4-way set-associative, virtual address index/physical address tag address index/physical address tag 32 bytes 256 entries/way 32 bytes 256 entries/way Copy-back/write-through selectable
LRU (least-recently-used) algorithm LRU (least-recently-used) algorithm
Table 7.2
Item Capacity Addresses Write Write-back Access right
Store Queue Features
Store Queues 32 bytes x 2 H'E000 0000 to H'E3FF FFFF Store instruction (1-cycle write) Prefetch instruction (PREF instruction) When MMU is disabled: Determined by SQMD bit in MMUCR When MMU is enabled: Determined by PR for each page
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Section 7 Caches
The operand cache of this LSI uses the 4-way set-associative, each way comprising 256 cache lines. Figure 7.1 shows the configuration of the operand cache. The instruction cache is 4-way set-associative, each way is comprising 256 cache lines. Figure 7.2 shows the configuration of the instruction cache.
Virtual address 31
12
10
54
2
0
Entry selection
22
[12:5]
Longword (LW) selection
8
0
Address array (way 0 to way 3) Tag U V
3
Data array (way 0 to way3)
LRU
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
MMU
19
255
19 bits
1 bit 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
6 bits
Comparison
Read data
(Way 0 to way 3)
Write data
Hit signal
Figure 7.1 Configuration of Operand Cache (OC)
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Section 7 Caches
Virtual address 31 13 12 10 54 2 0
[12:5] Entry selection 22 8 0 Address array (way 0 to way 3) Tag V
Longword (LW) selection
3
Data array (way 0 to way3) LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
LRU
MMU
19
255
19 bits
1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
6 bits
Comparison Read data (Way 0 to way 3) Hit signal
Figure 7.2 Configuration of Instruction Cache (IC) * Tag Stores the upper 19 bits of the 29-bit physical address of the data line to be cached. The tag is not initialized by a power-on or manual reset. * V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. * U bit (dirty bit) The U bit is set to 1 if data is written to the cache line while the cache is being used in copyback mode. That is, the U bit indicates a mismatch between the data in the cache line and the data in external memory. The U bit is never set to 1 while the cache is being used in writethrough mode, unless it is modified by accessing the memory-mapped cache (see section 7.6, Memory-Mapped Cache Configuration). The U bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
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Section 7 Caches
* Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. * LRU In a 4-way set-associative method, up to 4 items of data can be registered in the cache at each entry address. When an entry is registered, the LRU bit indicates which of the 4 ways it is to be registered in. The LRU mechanism uses 6 bits of each entry, and its usage is controlled by hardware. The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset. The LRU bits cannot be read from or written to by software.
7.2
Register Descriptions
The following registers are related to cache. Table 7.3 Register Configuration
Abbreviation R/W CCR QACR0 QACR1 RAMCR R/W R/W R/W R/W P4 Address* H'FF00 001C H'FF00 0038 H'FF00 003C H'FF00 0074 Area 7 Address* H'1F00 001C H'1F00 0038 H'1F00 003C H'1F00 0074 Size 32 32 32 32
Register Name Cache control register Queue address control register 0 Queue address control register 1 On-chip memory control register
Note:
*
These P4 addresses are for the P4 area in the virtual address space. These area 7 addresses are accessed from area 7 in the physical address space by means of the TLB.
Table 7.4
Register States in Each Processing State
Abbreviation CCR Power-on Reset Manual Reset H'0000 0000 Undefined Undefined H'0000 0000 H'0000 0000 Undefined Undefined H'0000 0000 Sleep Retained Retained Retained Retained Standby Retained Retained Retained Retained
Register Name Cache control register
Queue address control register 0 QACR0 Queue address control register 1 QACR1 On-chip memory control register RAMCR
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Section 7 Caches
7.2.1
Cache Control Register (CCR)
CCR controls the cache operating mode, the cache write mode, and invalidation of all cache entries. CCR modifications must only be made by a program in the non-cacheable P2 area. After CCR has been updated, execute one of the following three methods before an access (including an instruction fetch) to the cacheable area is performed. 1. Execute a branch using the RTE instruction. In this case, the branch destination may be the cacheable area. 2. Execute the ICBI instruction for any address (including non-cacheable area). 3. If the R2 bit in IRMCR is 0 (initial value) before updating CCR, the specific instruction does not need to be executed. However, note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after CCR has been updated. Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 ICI 0 R/W 0 R 0 R 26 0 R 10 25 0 R 9 24 0 R 8 ICE 0 R/W 0 R 0 R 0 R 0 R 23 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 OCI 0 R/W 18 0 R 2 CB 0 R/W 17 0 R 1 WT 0 R/W 16 0 R 0 OCE 0 R/W
Bit 31 to 12
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
11
ICI
0
R/W
IC Invalidation Bit When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit is always read as 0.
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Section 7 Caches
Bit 10, 9
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
8
ICE
0
R/W
IC Enable Bit Selects whether the IC is used. Note however when address translation is performed, the IC cannot be used unless the C bit in the page management information is also 1. 0: IC not used 1: IC used
7 to 4
All 0
R
Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
3
OCI
0
R/W
OC Invalidation Bit When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit is always read as 0.
2
CB
0
R/W
Copy-Back Bit Indicates the P1 area cache write mode. 0: Write-through mode 1: Copy-back mode
1
WT
0
R/W
Write-Through Mode Indicates the P0, U0, and P3 area cache write mode. When address translation is performed, the value of the WT bit in the page management information has priority. 0: Copy-back mode 1: Write-through mode
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Section 7 Caches
Bit 0
Bit Name OCE
Initial Value 0
R/W R/W
Description OC Enable Bit Selects whether the OC is used. Note however when address translation is performed, the OC cannot be used unless the C bit in the page management information is also 1. 0: OC not used 1: OC used
7.2.2
Queue Address Control Register 0 (QACR0)
QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is disabled.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 19 0 R 3 AREA0 R/W R/W R/W 0 R 0 R 18 0 R 2 17 0 R 1 16 0 R 0
Bit 31 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
4 to 2 1, 0
AREA0
Undefined R/W All 0 R
When the MMU is disabled, these bits generate physical address bits [28:26] for SQ0. Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
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Section 7 Caches
7.2.3
Queue Address Control Register 1 (QACR1)
QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is disabled.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 19 0 R 3 AREA1 R/W R/W R/W 0 R 0 R 18 0 R 2 17 0 R 1 16 0 R 0
Bit 31 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
4 to 2 1, 0
AREA1
Undefined R/W All 0 R
When the MMU is disabled, these bits generate physical address bits [28:26] for SQ1. Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
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Section 7 Caches
7.2.4
On-Chip Memory Control Register (RAMCR)
RAMCR controls the number of ways in the IC and OC. RAMCR modifications must only be made by a program in the non-cacheable P2 area. After RAMCR has been updated, execute one of the following three methods before an access (including an instruction fetch) to the cacheable area or the L memory area is performed. 1. Execute a branch using the RTE instruction. In this case, the branch destination may be the non-cacheable area or the L memory area. 2. Execute the ICBI instruction for any address (including non-cacheable area). 3. If the R2 bit in IRMCR is 0 (initial value) before updating RAMCR, the specific instruction does not need to be executed. However, note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after RAMCR has been updated. Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 RMD 0 R/W 24 0 R 8 RP 0 R/W 23 0 R 7 0 R/W 22 0 R 6 0 R/W 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 0 R 16 0 R 0 0 R
IC2W OC2W
Bit 31 to 10
Bit Name
Initial Value All 0
R/W R
Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
9
RMD
0
R/W
On-Chip Memory Access Mode Bit For details, see section 8.4, L Memory Protective Functions.
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Section 7 Caches
Bit 8
Bit Name RP
Initial Value 0
R/W R/W
Description On-Chip Memory Protection Enable Bit For details, see section 8.4, L Memory Protective Functions.
7
IC2W
0
R/W
IC Two-Way Mode bit 0: IC is a four-way operation 1: IC is a two-way operation For details, see section 7.4.3, IC Two-Way Mode.
6
OC2W
0
R/W
OC Two-Way Mode bit 0: OC is a four-way operation 1: OC is a two-way operation For details, see section 7.3.6, OC Two-Way Mode.
5 to 0
All 0
R
Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
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Section 7 Caches
7.3
7.3.1
Operand Cache Operation
Read Operation
When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is read from a cacheable area, the cache operates as follows: 1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2. The tag read from the each way is compared with bits [28:10] of the physical address resulting from virtual address translation by the MMU: * If there is a way whose tag matches and its V bit is 1, see No. 3. * If there is no way whose tag matches and its V bit is 1 and the U bit of the way which is selected to replace using the LRU bits is 0, see No. 4. * If there is no way whose tag matches and its V bit is 1 and the U bit of the way which is selected to replace using the LRU bits is 1, see No. 5. 3. Cache hit The data indexed by virtual address bits [4:0] is read from the data field of the cache line on the hitted way in accordance with the access size. Then the LRU bits are updated to indicate the hitted way is the latest one. 4. Cache miss (no write-back) Data is read into the cache line on the way, which is selected to replace, from the physical address space corresponding to the virtual address. Data reading is performed, using the wraparound method, in order from the quad-word data(8 bytes) including the cache-missed data. When the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining data on the cache line is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the physical address is recorded in the cache, 1 is written to the V bit and 0 is written to the U bit on the way. Then the LRU bit is updated to indicate the way is latest one.
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Section 7 Caches
5. Cache miss (with write-back) The tag and data field of the cache line on the way which is selected to replace are saved in the write-back buffer. Then data is read into the cache line on the way which is selected to replace from the physical address space corresponding to the virtual address. Data reading is performed, using the wraparound method, in order from the quad-word data (8 bytes) including the cache-missed data, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the physical address is recorded in the cache, 1 is written to the V bit, and 0 to the U bit. And the LRU bits are updated to indicate the way is latest one. The data in the write-back buffer is then written back to external memory. 7.3.2 Prefetch Operation
When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is prefetched from a cacheable area, the cache operates as follows: 1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2. The tag, read from each way, is compared with bits [28:10] of the physical address resulting from virtual address translation by the MMU: * If there is a way whose tag matches and its V bit is 1, see No. 3. * If there is no way whose tag matches and the V bit is 1, and the U bit of the way which is selected to replace using the LRU bits is 0, see No. 4. * If there is no way whose tag matches and the V bit is 1, and the U bit of the way which is selected to replace using the LRU bits is 1, see No. 5. 3. Cache hit (copy-back) Then the LRU bits are updated to indicate the hitted way is the latest one. 4. Cache miss (no write-back) Data is read into the cache line on the way, which is selected to replace, from the physical address space corresponding to the virtual address. Data reading is performed, using the wraparound method, in order from the quad-word data (8 bytes) including the cache-missed data. In the prefetch operation the CPU doesn't wait the data arrives. While the one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the physical address is recorded in the cache, 1 is written to the V bit and 0 is written to the U bit on the way. And the LRU bit is updated to indicate the way is latest one.
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Section 7 Caches
5. Cache miss (with write-back) The tag and data field of the cache line on the way which is selected to replace are saved in the write-back buffer. Then data is read into the cache line on the way which is selected to replace from the physical address space corresponding to the virtual address. Data reading is performed, using the wraparound method, in order from the quad-word data (8 bytes) including the cache-missed data. In the prefetch operation the CPU doesn't wait the data arrives. While the one cache line of data is being read, the CPU can execute the next processing. And the LRU bits are updated to indicate the way is latest one. The data in the write-back buffer is then written back to external memory. 7.3.3 Write Operation
When the Operand cache (OC) is enabled (OCE = 1 in CCR) and data is written to a cacheable area, the cache operates as follows: 1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2. The tag, read from each way, is compared with bits [28:10] of the physical address resulting from virtual address translation by the MMU: * If there is a way whose tag matches and its V bit is 1, see No. 3 for copy-back and No. 4 for write-through. * I If there is no way whose tag matches and its V bit is 1 and the U bit of the way which is selected to replace using the LRU bits is 0, see No. 5 for copy-back and No. 7 for writethrough. * If there is no way whose tag matches and its V bit is 1 and the U bit of the way which is selected to replace using the LRU bits is 1, see No. 6 for copy-back and No. 7 for writethrough. 3. Cache hit (copy-back) A data write in accordance with the access size is performed for the data field on the hit way which is indexed by virtual address bits [4:0]. Then 1 is written to the U bit. The LRU bits are updated to indicate the way is the latest one. 4. Cache hit (write-through) A data write in accordance with the access size is performed for the data field on the hit way which is indexed by virtual address bits [4:0]. A write is also performed to external memory corresponding to the virtual address. Then the LRU bits are updated to indicate the way is the latest one. In this case, the U bit isn't updated.
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Section 7 Caches
5. Cache miss (copy-back, no write-back) A data write in accordance with the access size is performed for the data of the data field on the hit way which is indexed by virtual address bits [4:0]. Then, the data, excluding the cachemissed data which is written already, is read into the cache line on the way which is selected to replace from the physical address space corresponding to the virtual address. Data reading is performed, using the wraparound method, in order from the quad-word data (8 bytes) including the cache-missed data. While the remaining data on the cache line is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the physical address is recorded in the cache, 1 is written to the V bit and the U bit on the way. Then the LRU bit is updated to indicate the way is latest one. 6. Cache miss (copy-back, with write-back) The tag and data field of the cache line on the way which is selected to replace are saved in the write-back buffer. Then a data write in accordance with the access size is performed for the data field on the hit way which is indexed by virtual address bits [4:0]. Then, the data, excluding the cache-missed data which is written already, is read into the cache line on the way which is selected to replace from the physical address space corresponding to the virtual address. Data reading is performed, using the wraparound method, in order from the quadword data (8 bytes) including the cache-missed data. While the remaining data on the cache line is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the physical address is recorded in the cache, 1 is written to the V bit and the U bit on the way. Then the LRU bit is updated to indicate the way is latest one. Then the data in the write-back buffer is then written back to external memory. 7. Cache miss (write-through) A write of the specified access size is performed to the external memory corresponding to the virtual address. In this case, a write to cache is not performed.
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Section 7 Caches
7.3.4
Write-Back Buffer
In order to give priority to data reads to the cache and improve performance, this LSI has a writeback buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. The write-back buffer contains one cache line of data and the physical address of the purge destination.
Physical address bits [28:5]
LW0
LW1
LW2
LW3
LW4
LW5
LW6
LW7
Figure 7.3 Configuration of Write-Back Buffer 7.3.5 Write-Through Buffer
This LSI has a 64-bit buffer for holding write data when writing data in write-through mode or writing to a non-cacheable area. This allows the CPU to proceed to the next operation as soon as the write to the write-through buffer is completed, without waiting for completion of the write to external memory.
Physical address bits [28:0]
LW0
LW1
Figure 7.4 Configuration of Write-Through Buffer 7.3.6 OC Two-Way Mode
When the OC2W bit in RAMCR is set to 1, OC two-way mode which only uses way 0 and way 1 in the OC is entered. Thus, power consumption can be reduced. In this mode, only way 0 and way 1 are used even if a memory-mapped OC access is made. The OC2W bit should be modified by a program in the P2 area. At that time, if the valid line has already been recorded in the OC, data should be written back by software, if necessary, 1 should be written to the OCI bit in CCR, and all entries in the OC should be invalid before modifying the OC2W bit.
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Section 7 Caches
7.4
7.4.1
Instruction Cache Operation
Read Operation
When the IC is enabled (ICE = 1 in CCR) and instruction fetches are performed from a cacheable area, the instruction cache operates as follows: 1. The tag, V bit, U bit and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2. The tag, read from each way, is compared with bits [28:10] of the physical address resulting from virtual address translation by the MMU: * If there is a way whose tag matches and the V bit is 1, see No. 3. * If there is no way whose tag matches and the V bit is 1, see No. 4. 3. Cache hit The data indexed by virtual address bits [4:2] is read as an instruction from the data field on the hit way. The LRU bits are updated to indicate the way is the latest one. 4. Cache miss Data is read into the cache line on the way which selected using LRU bits to replace from the physical address space corresponding to the virtual address. Data reading is performed, using the wraparound method, in order from the quad-word data (8 bytes) including the cachemissed data, and when the corresponding data arrives in the cache, the read data is returned to the CPU as an instruction. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the physical address is recorded in the cache, and 1 is written to the V bit, the LRU bits are updated to indicate the way is the latest one.
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Section 7 Caches
7.4.2
Prefetch Operation
When the IC is enabled (ICE = 1 in CCR) and instruction prefetches are performed from a cacheable area, the instruction cache operates as follows: 1. The tag, V bit, Ubit and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2. The tag, read from each way, is compared with bits [28:10] of the physical address resulting from virtual address translation by the MMU: * If there is a way whose tag matches and the V bit is 1, see No. 3. * If there is no way whose tag matches and the V bit is 1, see No. 4. 3. Cache hit The LRU bits is updated to indicate the way is the latest one. 4. Cache miss Data is read into the cache line on a way which selected using the LRU bits to replace from the physical address space corresponding to the virtual address. Data reading is performed, using the wraparound method, in order from the quad-word data (8 bytes) including the cachemissed data. In the prefetch opreration, the CPU doesn't wait the data arrived. While the one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the physical address is recorded in the cache, and 1 is written to the V bit, the LRU bits is updated to indicate the way is the latest one. 7.4.3 IC Two-Way Mode
When the IC2W bit in RAMCR is set to 1, IC two-way mode which only uses way 0 and way 1 in the IC is entered. Thus, power consumption can be reduced. In this mode, only way 0 and way 1 are used even if a memory-mapped IC access is made. The IC2W bit should be modified by a program in the P2 area. At that time, if the valid line has already been recorded in the IC, 1 should be written to the ICI bit in CCR and all entries in the IC should be invalid before modifying the IC2W bit.
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Section 7 Caches
7.5
7.5.1
Cache Operation Instruction
Coherency between Cache and External Memory
Coherency between cache and external memory should be assured by software. In this LSI, the following six instructions are supported for cache operations. Details of these instructions are given in the Programming Manual. * Operand cache invalidate instruction: OCBI @Rn Operand cache invalidation (no write-back) * Operand cache purge instruction: OCBP @Rn Operand cache invalidation (with write-back) * Operand cache write-back instruction: OCBWB @Rn Operand cache write-back * Operand cache allocate instruction: MOVCA.L R0,@Rn Operand cache allocation * Instruction cache invalidate instruction: ICBI @Rn Instruction cache invalidation * Operand access synchronization instruction: SYNCO Wait for data transfer completion The operand cache can receive "PURGE" and "FLUSH" transaction from SuperHyway bus to control the cache coherency. Since the address used by the PURGE and FLUSH transaction is a physical address, the following restrictions occur to avoid cache synonym problem in MMU enable mode. * 1 Kbyte page size cannot be used.
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Section 7 Caches
PURGE transaction: When the operand cache is enabled, the PURGE transaction checks the operand cache and invalidates the hit entry. If the invalidated entry is dirty, the data is written back to the external memory. If the transaction is not hit to the cache, it is no-operation. FLUSH transaction: When the operand cache is enabled, the FLUSH transaction checks the operand cache and if the hit line is dirty, then the data is written back to the external memory. If the transaction is not hit to the cache or the hit entry is not dirty, it is no-operation. 7.5.2 Prefetch Operation
This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance. If a prefetch instruction is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or a protection violation, the result is no operation, and an exception is not generated. Details of the prefetch instruction are given in the Programming Manual. * Prefetch instruction (OC) * Prefetch instruction (IC) : PREF @Rn : PREFI @Rn
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Section 7 Caches
7.6
Memory-Mapped Cache Configuration
To enable the IC and OC to be managed by software, the IC contents can be read from or written to by a program in the P2 area by means of a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, execute one of the following three methods for executing a branch to the P0, U0, P1, or P3 area. 1. Execute a branch using the RTE instruction. 2. Execute a branch to the P0, U0, P1, or P3 area after executing the ICBI instruction for any address (including non-cacheable area). 3. If the MC bit in IRMCR is 0 (initial value) before making an access to the memory-mapped IC, the specific instruction does not need to be executed. However, note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after making an access to the memory-mapped IC. Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series. In privileged mode, the OC contents can be read from or written to by a program in the P1 or P2 area by means of a MOV instruction. Operation is not guaranteed if access is made from a program in another area. The IC and OC are allocated to the P4 area in the virtual address space. Only data accesses can be used on both the IC address array and data array and the OC address array and data array, and accesses are always longword-size. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified and the read value is undefined. 7.6.1 IC Address Array
The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, and the way is specified by bits [14:13] and the entry by bits [12:5]. The association bit (A bit) [3] in the address field specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0].
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Section 7 Caches
In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the way and entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the way and entry set in the address field. The A bit in the address field should be cleared to 0. 3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag in each way stored in the entry specified in the address field is compared with the tag specified in the data field. The way numbers of bits [14:13] in the address field are not used. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit in the way is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. Note: This function may not be supported in the future SuperH Series. Therefore, it is recommended that the ICBI instruction should be used to operate the IC definitely by handling ITLB miss and reporting ITLB miss exception.
24 23 31 1514 13 12 Address field 1 1 1 1 0 0 0 0 * * * * * * * * * 31 Data field Tag Way 543210 Entry 10 9 0A000 10 V
V : Validity bit A : Association bit : Reserved bits (write value should be 0 and read value is undefined ) * : Don't care
Figure 7.5 Memory-Mapped IC Address Array
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Section 7 Caches
7.6.2
IC Data Array
The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the way is specified by bits [14:13] and the entry by bits [12:5]. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field.
24 23 1514 13 12 31 Address field 1 1 1 1 0 0 0 1 * * * * * * * * * 31 Data field L : Longword specification bits * : Don't care
Way
54 Entry L
210
00
0
Longword data
Figure 7.6 Memory-Mapped IC Data Array
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Section 7 Caches
7.6.3
OC Address Array
The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the way is specified by bits [14:13] and the entry by bits [12:5]. The association bit (A bit) [3] in the address field specifies whether or not association is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the way and entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the way and entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written.
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Section 7 Caches
3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag in each way stored in the entry specified in the address field is compared with the tag specified in the data field. The way numbers of bits [14:13] in the address field are not used. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit in the way is 1, the U bit and V bit specified in the data field are written into the OC entry. In other cases, no operation is performed. This operation is used to invalidate a specific OC entry. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If a UTLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. Note: This function may not be supported in the future SuperH Series. Therefore, it is recommended that the OCBI, OCBP, or OCBWB instruction should be used to operate the OC definitely by reporting data TLB miss exception.
24 23 31 15 141312 Address field 1 1 1 1 0 1 0 0 * * * * * * * * * 31 Data field Tag Way 543210 Entry 10 9 0A000 210 UV
V : Validity bit U : Dirty bit A : Association bit : Reserved bits (write value should be 0 and read value is undefined ) * : Don't care
Figure 7.7 Memory-Mapped OC Address Array 7.6.4 OC Data Array
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the way is specified by bits [14:13] and the entry by bits [12:5]. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0].
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Section 7 Caches
The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field. This write does not set the U bit to 1 on the address array side.
31 24 23 15 141312 Address field 1 1 1 1 0 1 0 1 * * * * * * * * * 31 Data field L : Longword specification bits * : Don't care
Way
543210 Entry
L 00
0
Longword data
Figure 7.8 Memory-Mapped OC Data Array
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Section 7 Caches
7.7
Store Queues
This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. 7.7.1 SQ Configuration
There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 7.9. These two store queues can be set independently.
SQ0
SQ0[0]
SQ0[1]
SQ0[2]
SQ0[3]
SQ0[4]
SQ0[5]
SQ0[6]
SQ0[7]
SQ1
SQ1[0] 4B
SQ1[1] 4B
SQ1[2] 4B
SQ1[3] 4B
SQ1[4] 4B
SQ1[5] 4B
SQ1[6] 4B
SQ1[7] 4B
Figure 7.9 Store Queue Configuration 7.7.2 Writing to SQ
A write to the SQs can be performed using a store instruction for addresses H'E000 0000 to H'E3FF FFFC in the P4 area. A longword or quadword access size can be used. The meanings of the address bits are as follows: [31:26] [25:6] [5] [4:2] [1:0] : 111000 : Don't care : 0/1 : LW specification : 00 Fixed at 0 Store queue specification Used for external memory transfer/access right 0 : SQ0 specification 1: SQ1 specification Specifies longword position in SQ0/SQ1
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Section 7 Caches
7.7.3
Transfer to External Memory
Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF). Issuing a PREF instruction for addresses H'E000 0000 to H'E3FF FFFC in the P4 area starts a transfer from the SQs to external memory. The transfer length is fixed at 32 bytes, and the start address is always at a 32-byte boundary. While the contents of one SQ are being transferred to external memory, the other SQ can be written to without a penalty cycle. However, writing to the SQ involved in the transfer to external memory is kept waiting until the transfer is completed. The physical address bits [28:0] of the SQ transfer destination are specified as shown below, according to whether the MMU is enabled or disabled. * When MMU is enabled (AT = 1 in MMUCR) The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer destination physical address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same meaning as for normal address translation, but the C and WT bits have no meaning with regard to this page. When a prefetch instruction is issued for the SQ area, address translation is performed and physical address bits [28:10] are generated in accordance with the SZ bit specification. For physical address bits [9:5], the address prior to address translation is generated in the same way as when the MMU is disabled. Physical address bits [4:0] are fixed at 0. Transfer from the SQs to external memory is performed to this address. * When MMU is disabled (AT = 0 in MMUCR) The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address at which a PREF instruction is issued. The meanings of address bits [31:0] are as follows: [31:26] [25:6] [5] : 111000 : Address : 0/1 Store queue specification Transfer destination physical address bits [25:6] 0: SQ0 specification 1: SQ1 specification and transfer destination physical address bit [5] No meaning in a prefetch Fixed at 0
[4:2] [1:0]
: Don't care : 00
Physical address bits [28:26], which cannot be generated from the above address, are generated from QACR0 and QACR1. QACR0[4:2] QACR1[4:2] : Physical address bits [28:26] corresponding to SQ0 : Physical address bits [28:26] corresponding to SQ1
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Section 7 Caches
Physical address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. 7.7.4 Determination of SQ Access Exception
Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is enabled or disabled. If an exception occurs during a write to an SQ, the SQ contents before the write are retained. If an exception occurs in a data transfer from an SQ to external memory, the transfer to external memory will be aborted. * When MMU is enabled (AT = 1 in MMUCR) Operation is in accordance with the address translation information recorded in the UTLB, and the SQMD bit in MMUCR. Write type exception judgment is performed for writes to the SQs, and read type exception judgment for transfer from the SQs to external memory (using a PREF instruction). As a result, a TLB miss exception or protection violation exception is generated as required. However, if SQ access is enabled in privileged mode only by the SQMD bit in MMUCR, an address error will occur even if address translation is successful in user mode. * When MMU is disabled (AT = 0 in MMUCR) Operation is in accordance with the SQMD bit in MMUCR. 0: Privileged/user mode access possible 1: Privileged mode access possible If the SQ area is accessed in user mode when the SQMD bit in MMUCR is set to 1, an address error will occur. 7.7.5 Reading from SQ
In privileged mode in this LSI, reading the contents of the SQs may be performed by means of a load instruction for addresses H'FF00 1000 to H'FF00 103C in the P4 area. Only longword access is possible. [31:6] [5] [4:2] [1:0] : H'FF00 1000 : 0/1 : LW specification : 00 Store queue specification 0: SQ0 specification 1: SQ1 specification Specifies longword position in SQ0/SQ1 Fixed at 0
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Section 7 Caches
7.8
Notes on Using 32-Bit Address Extended Mode
In 32-bit address extended mode, the items described in this section are extended as follows. 1. The tag bits [28:10] (19 bits) in the IC and OC are extended to bits [31:10] (22 bits). 2. An instruction which operates the IC (a memory-mapped IC access and writing to the ICI bit in CCR) should be located in the P1 or P2 area. The cacheable bit (C bit) in the corresponding entry in the PMB should be 0. 3. Bits [4:2] (3 bits) for the AREA0 bit in QACR0 and the AREA1 bit in QACR1 are extended to bits [7:2] (6 bits).
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Section 7 Caches
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Section 8 L Memory
Section 8 L Memory
This LSI includes on-chip L-memory which stores instructions or data.
8.1
Features
* Capacity Total L memory capacity is 16 Kbytes. * Page The L memory is divided into two pages (pages 0 and 1). * Memory map The L memory is allocated in the addresses shown in table 8.1 in both the virtual address space and the physical address space. Table 8.1 L Memory Addresses
Memory Size (Two Pages Total) Page Page 0 of L memory Page 1 of L memory 16 Kbytes H'E500E000 to H'E500FFFF H'E5010000 to H'E5011FFF
* Ports Each page has three independent read/write ports and is connected to each bus. The instruction bus is used when L memory is accessed through instruction fetch. The operand bus is used when L memory is accessed through operand access. The SuperHyway bus is used for L memory access from the SuperHyway bus master module. * Priority In the event of simultaneous accesses to the same page from different buses, the access requests are processed according to priority. The priority order is: SuperHyway bus > operand bus > instruction bus.
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Section 8 L Memory
8.2
Register Descriptions
The following registers are related to L memory. Table 8.2
Name On-chip memory control register
Register Configuration
Abbreviation RAMCR R/W R/W R/W R/W R/W P4 Address* H'FF000074 H'FF000050 H'FF000054 H'FF000058 Area 7 Address* H'1F000074 H'1F000050 H'1F000054 H'1F000058 Access Size 32 32 32 32
L memory transfer source LSA0 address register 0 L memory transfer source LSA1 address register 1 L memory transfer destination address register 0 L memory transfer destination address register 1 Note: * LDA0
LDA1
R/W
H'FF00005C
H'1F00005C
32
The P4 address is the address used when using P4 area in the virtual address space. The area 7 address is the address used when accessing from area 7 in the physical address space using the TLB.
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Section 8 L Memory
Table 8.3
Name
Register Status in Each Processing State
Abbreviation Power-On Reset H'00000000 Undefined Manual Reset Sleep H'00000000 Undefined Retained Retained Standby Retained Retained
On-chip memory control RAMCR register L memory transfer LSA0 source address register 0 L memory transfer LSA1 source address register 1 L memory transfer destination address register 0 L memory transfer destination address register 1 LDA0
Undefined
Undefined
Retained
Retained
Undefined
Undefined
Retained
Retained
LDA1
Undefined
Undefined
Retained
Retained
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Section 8 L Memory
8.2.1
On-Chip Memory Control Register (RAMCR)
RAMCR controls the protective functions in the L memory.
Bit : Initial value : R/W:
Bit : Initial value : R/W:
31
0 R 15
0 R
30
0 R 14
0 R
29
0 R 13
0 R
28
0 R 12
0 R
27
0 R 11
0 R
26
0 R 10
0 R
25
0 R 9
24
0 R 8
23
0 R 7
22
0 R 6
21
0 R 5
0 R
20
0 R 4
0 R
19
0 R 3
0 R
18
0 R 2
0 R
17
0 R 1
0 R
16 0 R
0 0 R
RMD RP IC2W OC2W 0 0 0 0 R/W R/W R/W R/W
Bit 31to10
Bit Name --
Initial Value All 0
R/W R
Description Reserved For read/write in these bits, refer to General Precautions on Handling of Product.
9
RMD
0
R/W
On-Chip Memory Access Mode Specifies the right of access to the L memory from the virtual address space. 0: An access in privileged mode is allowed. (An address error exception occurs in user mode.) 1: An access user/privileged mode is allowed.
8
RP
0
R/W
On-Chip Memory Protection Enable Selects whether or not to use the protective functions using ITLB and UTLB for accessing the L memory from the virtual address space. 0: Protective functions are not used. 1: Protective functions are used. For further details, refer to section 8.4, L Memory Protective Functions.
7
IC2W
0
R/W
IC Two-Way Mode For further details, refer to section 7.4.3, IC Two-Way Mode.
6
OC2W
0
R/W
OC Two-Way Mode For further details, refer to section 7.3.6, OC Two-Way Mode.
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Section 8 L Memory
Bit 5 to 0
Bit Name --
Initial Value All 0
R/W R
Description Reserved For read/write in these bits, refer to General Precautions on Handling of Product.
8.2.2
L Memory Transfer Source Address Register 0 (LSA0)
When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA0 specifies the transfer source physical address for block transfer to page 0 of the L memory.
Bit : Initial value : R/W:
Bit :
31
0 R 15
30
0 R 14
29
0 R 13
28
27
26
25
24
23
22
L0SADR
21
20
19
18
17
16
R/W 12
R/W 11
R/W 10
R/W 9
0 R
R/W 8
0 R
R/W 7
0 R
R/W 6
0 R
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W
0
L0SADR
Initial value : R/W: R/W R/W R/W R/W R/W R/W R/W R/W
L0SSZ
R/W R/W R/W R/W
Bit 31 to 29
Bit Name --
Initial Value All 0
R/W R
Description Reserved For read/write in these bits, refer General Precautions on Handling of Product.
28 to 10
L0SADR
Undefined R/W
L Memory Page 0 Block Transfer Source Address When MMUCR.AT = 0 or RAMCR.RP = 0, these bits specify the transfer source physical address for block transfer to page 0 in the L memory.
9 to 6
--
All 0
R
Reserved For read/write in these bits, refer to General Precautions on Handling of Product.
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Section 8 L Memory
Bit 5 to 0
Bit Name L0SSZ
Initial Value
R/W
Description L Memory Page 0 Block Transfer Source Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L0SADR values are used as bits 15 to 10 of the transfer source physical address for block transfer to the L memory. L0SSZ[5:0] correspond to the transfer source physical addresses[15:10]. 0: The operand address is used as the transfer source physical address. 1: The L0SADR value is used as the transfer source physical address. Settable values: 111111: Transfer source physical address is specified in 1-Kbyte units. 111110: Transfer source physical address is specified in 2-Kbyte units. 111100: Transfer source physical address is specified in 4-Kbyte units. 111000: Transfer source physical address is specified in 8-Kbyte units. 110000: Transfer source physical address is specified in 16-Kbyte units. 100000: Transfer source physical address is specified in 32-Kbyte units. 000000: Transfer source physical address is specified in 64-Kbyte units. Settings other than the ones given above are prohibited.
Undefined R/W
Rev. 1.00 Oct. 01, 2007 Page 222 of 1956 REJ09B0256-0100
Section 8 L Memory
8.2.3
L Memory Transfer Source Address Register 1 (LSA1)
When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA1 specifies the transfer source physical address for block transfer to page 1 in the L memory.
Bit : Initial value : R/W:
Bit :
31
0 R 15
30
0 R 14
29
0 R 13
28
27
26
25
24
23
22
L1SADR
21
20
19
18
17
16
R/W 12
R/W 11
R/W 10
R/W 9
0 R
R/W 8
0 R
R/W 7
0 R
R/W 6
0 R
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W
0
L1SADR
Initial value : R/W: R/W R/W R/W R/W R/W R/W R/W R/W
L1SSZ
R/W R/W R/W R/W
Bit 31 to 29
Bit Name --
Initial Value All 0
R/W R
Description Reserved For read/write in these bits, refer to General Precautions on Handling of Product.
28 to 10
L1SADR
Undefined R/W
L Memory Page 1 Block Transfer Source Address When MMUCR.AT = 0 or RAMCR.RP = 0, these bits specify transfer source physical address for block transfer to page 1 in the L memory.
9 to 6
--
All 0
R
Reserved For read/write in these bits, refer to General Precautions on Handling of Product.
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Section 8 L Memory
Bit 5 to 0
Bit Name L1SSZ
Initial Value
R/W
Description L Memory Page 1 Block Transfer Source Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L1SADR values are used as bits 15 to 10 of the transfer source physical address for block transfer to page 1 in the L memory. L1SSZ bits [5:0] correspond to the transfer source physical addresses [15:10]. 0: The operand address is used as the transfer source physical address. 1: The L1SADR value is used as the transfer source physical address. Settable values: 111111: Transfer source physical address is specified in 1-Kbyte units. 111110: Transfer source physical address is specified in 2-Kbyte units. 111100: Transfer source physical address is specified in 4-Kbyte units. 111000: Transfer source physical address is specified in 8-Kbyte units. 110000: Transfer source physical address is specified in 16-Kbyte units. 100000: Transfer source physical address is specified in 32-Kbyte units. 000000: Transfer source physical address is specified in 64-Kbyte units. Settings other than the ones given above are prohibited.
Undefined R/W
Rev. 1.00 Oct. 01, 2007 Page 224 of 1956 REJ09B0256-0100
Section 8 L Memory
8.2.4
L Memory Transfer Destination Address Register 0 (LDA0)
When MMUCR.AT = 0 or RAMCR.RP = 0, LDA0 specifies the transfer destination physical address for block transfer to page 0 of the L memory.
Bit : Initial value : R/W:
Bit :
31
0 R 15
30
0 R 14
29
0 R 13
28
27
26
25
24
23
22 21 L0DADR
R/W 6
0 R
20
19
18
17
16
R/W 12
R/W 11
R/W 10
R/W 9
0 R
R/W 8
0 R
R/W 7
0 R
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W
0
L0DADR
Initial value : R/W: R/W R/W R/W R/W R/W R/W R/W R/W
L0DSZ
R/W R/W R/W R/W
Bit 31 to 29
Bit Name --
Initial Value All 0
R/W R
Description Reserved For read/write in these bits, refer to General Precautions on Handling of Product.
28 to 10
L0DADR
Undefined R/W
L Memory Page 0 Block Transfer Destination Address When MMUCR.AT = 0 or RAMCR.RP = 0, these bits specify transfer destination physical address for block transfer to page 0 in the L memory.
9 to 6
--
All 0
R
Reserved For read/write in these bits, refer to General Precautions on Handling of Product.
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Section 8 L Memory
Bit 5 to 0
Bit Name L0DSZ
Initial Value
R/W
Description L Memory Page 0 Block Transfer Destination Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L0DADR values are used as bits 15 to 10 of the transfer destination physical address for block transfer to page 0 in the L memory. L0DSZ bits [5:0] correspond to the transfer destination physical address bits [15:10]. 0: The operand address is used as the transfer destination physical address. 1: The L0DADR value is used as the transfer destination physical address. Settable values: 111111: Transfer destination physical address is specified in 1-Kbyte units. 111110: Transfer destination physical address is specified in 2-Kbyte units. 111100: Transfer destination physical address is specified in 4-Kbyte units. 111000: Transfer destination physical address is specified in 8-Kbyte units. 110000: Transfer destination physical address is specified in 16-Kbyte units. 100000: Transfer destination physical address is specified in 32-Kbyte units. 000000: Transfer destination physical address is specified in 64-Kbyte units. Settings other than the ones given above are prohibited.
Undefined R/W
Rev. 1.00 Oct. 01, 2007 Page 226 of 1956 REJ09B0256-0100
Section 8 L Memory
8.2.5
L Memory Transfer Destination Address Register 1 (LDA1)
When MMUCR.AT = 0 or RAMCR.RP = 0, LDA1 specifies the transfer destination physical address for block transfer to page 1 in the L memory.
Bit : Initial value : R/W:
Bit :
31
0 R 15
30
0 R 14
29
0 R 13
28
27
26
25
24
23
22 21 L0SADR
R/W 6
0 R
20
19
18
17
16
R/W 12
R/W 11
R/W 10
R/W 9
0 R
R/W 8
0 R
R/W 7
0 R
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W
0
L0SADR
Initial value : R/W: R/W R/W R/W R/W R/W R/W R/W R/W
L0SSZ
R/W R/W R/W R/W
Bit 31 to 29
Bit Name --
Initial Value All 0
R/W R
Description Reserved For read/write in these bits, refer to General Precautions on Handling of Product.
28 to 10
L1DADR
Undefined R/W
L Memory Page 1 Block Transfer Destination Address When MMUCR.AT = 0 or RAMCR.RP = 0, these bits specify transfer destination physical address for block transfer to page 1 in the L memory.
9 to 6
--
All 0
R
Reserved For read/write in these bits, refer to General Precautions on Handling of Product.
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Section 8 L Memory
Bit 5 to 0
Bit Name L1DSZ
Initial Value
R/W
Description L Memory Page 1 Block Transfer Destination Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L1DADR values are used as bits 15 to 10 of the transfer destination physical address for block transfer to page 1 in the L memory. L1DSZ bits [5:0] correspond to the transfer destination physical addresses [15:10]. 0: The operand address is used as the transfer destination physical address. 1: The L1DADR value is used as the transfer destination physical address. Settable values: 111111: Transfer destination physical address is specified in 1-Kbyte units. 111110: Transfer destination physical address is specified in 2-Kbyte units. 111100: Transfer destination physical address is specified in 4-Kbyte units. 111000: Transfer destination physical address is specified in 8-Kbyte units. 110000: Transfer destination physical address is specified in 16-Kbyte units. 100000: Transfer destination physical address is specified in 32-Kbyte units. 000000: Transfer destination physical address is specified in 64-Kbyte units. Settings other than the ones given above are prohibited.
Undefined R/W
Rev. 1.00 Oct. 01, 2007 Page 228 of 1956 REJ09B0256-0100
Section 8 L Memory
8.3
8.3.1
Operation
Access from the CPU and FPU
L memory access from the CPU and FPU is direct via the instruction bus and operand bus by means of the virtual address. As long as there is no conflict on the page, the L memory is accessed in one cycle. 8.3.2 Access from the SuperHyway Bus Master Module
L memory is always accessed by the SuperHyway bus master module, such as DMAC, via the SuperHyway bus which is a physical address bus. The same addresses as for the virtual addresses must be used. 8.3.3 Block Transfer
High-speed data transfer can be performed through block transfer between the L memory and external memory without cache utilization. Data can be transferred from the external memory to the L memory through a prefetch instruction (PREF). Block transfer from the external memory to the L memory begins when the PREF instruction is issued to the address in the L memory area in the virtual address space. Data can be transferred from the L memory to the external memory through a write-back instruction (OCBWB). Block transfer from the L memory to the external memory begins when the OCBWB instruction is issued to the address in the L memory area in the virtual address space. In either case, transfer rate is fixed to 32 bytes. Since the start address is always limited to a 32byte boundary, the lower five bits of the address indicated by Rn are ignored, and are always dealt with as all 0s. In either case, other pages and cache can be accessed during block transfer, but the CPU will stall if the page which is being transferred is accessed before data transfer ends. The physical addresses [28:0] of the external memory performing data transfers with the L memory are specified as follows according to whether the MMU is enabled or disabled. (1) When MMU is Enabled (MMUCR.AT = 1) and RAMCR.RP = 1
An address of the L memory area is specified to the UTLB VPN field, and to the physical address of the transfer source (in the case of the PREF instruction) or the transfer destination (in the case
Rev. 1.00 Oct. 01, 2007 Page 229 of 1956 REJ09B0256-0100
Section 8 L Memory
of the OCBWB instruction) to the PPN field. The ASID, V, SZ, SH, PR, and D bits have the same meaning as normal address conversion; however, the C and WT bits have no meaning in this page. When the PREF instruction is issued to the L memory area, address conversion is performed in order to generate the physical address bits [28:10] in accordance with the SZ bit specification. The physical address bits [9:5] are generated from the virtual address prior to address conversion. The physical address bits [4:0] are fixed to 0. Block transfer is performed to the L memory from the external memory which is specified by these physical addresses. When the OCBWB instruction is issued to the L memory area, address conversion is performed in order to generate the physical address bits [28:10] in accordance with the SZ bit specification. The physical address bits [9:5] are generated from the virtual address prior to address conversion. The physical address bits [4:0] are fixed to 0. Block transfer is performed from the L memory to the external memory specified by these physical addresses. In PREF or OCBWB instruction execution, an MMU exception is checked as read type. After the MMU execution check, a TLB miss exception or protection error exception occurs if necessary. If an exception occurs, the block transfer is inhibited. (2) When MMU is Disabled (MMUCR.AT = 0) or RAMCR.RP = 0
The transfer source physical address in block transfer to page 0 in the L memory is set in the L0SADR bits of the LSA0 register. And the L0SSZ bits in the LSA0 register choose either the virtual addresses specified through the PRFF instruction or the L0SADR values as bits 15 to 10 of the transfer source physical address. In other words, the transfer source area can be specified in units of 1 Kbyte to 64 Kbytes. The transfer destination physical address in block transfer from page 0 in the L memory is set in the L0DADR bits of the LDA0 register. And the L0DSZ bits in the LDA0 register choose either the virtual addresses specified through the OCBWB instruction or the L0DADR values as bits 15 to 10 of the transfer destination physical address. In other words, the transfer source area can be specified in units of 1 Kbyte to 64 Kbytes. Block transfer to page 1 in the L memory is set to LSA1 and LDA1 as with page 0 in the L memory. When the PREF instruction is issued to the L memory area, the physical address bits [28:10] are generated in accordance with the LSA0 or LSA1 specification. The physical address bits [9:5] are generated from the virtual address. The physical address bits [4:0] are fixed to 0. Block transfer is performed from the external memory specified by these physical addresses to the L memory.
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Section 8 L Memory
When the OCBWB instruction is issued to the L memory area, the physical address bits [28:10] are generated in accordance with the LDA0 or LDA1 specification. The physical address bits [9:5] are generated from the virtual address. The physical address bits [4:0] are fixed to 0. Block transfer is performed from the L memory to the external memory specified by these physical addresses.
8.4
L Memory Protective Functions
This LSI implements the following protective functions to the L memory by using the on-chip memory access mode bit (RMD) and the on-chip memory protection enable bit (RP) in the on-chip memory control register (RAMCR). * Protective functions for access from the CPU and FPU When RAMCR.RMD = 0, and the L memory is accessed in user mode, it is determined to be an address error exception. When MMUCR.AT = 1 and RAMCR.RP = 1, MMU exception and address error exception are checked in the L memory area which is a part of P4 area as with the area P0/P3/U0. The above descriptions are summarized in table 8.4. Table 8.4 Protective Function Exceptions to Access L Memory
RAMCR. RMD 0 1 1 1 0 0 * 0 1 1 1 0 * 0 1 1 Note: * Don't care * Always Occurring Exceptions Address error exception -- -- Address error exception -- -- Address error exception -- -- Possibly Occurring Exceptions -- -- -- -- -- -- -- MMU exception MMU exception
MMUCR.AT RAMCR.RP SR.MD 0 * 0
Rev. 1.00 Oct. 01, 2007 Page 231 of 1956 REJ09B0256-0100
Section 8 L Memory
8.5
8.5.1
Usage Notes
Page Conflict
In the event of simultaneous access to the same page from different buses, page conflict occurs. Although each access is completed correctly, this kind of conflict tends to lower L memory accessibility. Therefore it is advisable to provide all possible preventative software measures. For example, conflicts will not occur if each bus accesses different pages. 8.5.2 L Memory Coherency
In order to allocate instructions in the L memory, write an instruction to the L memory, execute the following sequence, then branch to the rewritten instruction. * SYNCO * ICBI @Rn In this case, the target for the ICBI instruction can be any address (L memory address may be possible) within the range where no address error exception occurs, and cache hit/miss is possible. 8.5.3 Sleep Mode
The SuperHyway bus master module, such as DMAC, cannot access L memory in sleep mode.
8.6
Note on Using 32-Bit Address Extended Mode
In 32-bit address extended mode, L0SADR fields in LSA0, L1SADR fields in LSA1, L0DADR fields in LDA0, and L1DADR fields in LDA1 are extended from 19-bit [28:10] to 22-bit [31:10].
Rev. 1.00 Oct. 01, 2007 Page 232 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Section 9 Interrupt Controller (INTC)
The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt requests to the CPU (SH-4A). The INTC has a register that sets the priority of each interrupt and interrupt requests are processed according to the priority set in this register by the user.
9.1
Features
SH-4 compatible specifications * Fifteen levels of external interrupt priority can be set By setting the interrupt priority registers, the priorities of external interrupts can be selected from 15 levels for individual request sources. * NMI noise canceller function An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt exception handling routine, the pin state can be checked, enabling it to be used as a noise canceller. * NMI request masking when the block bit (BL) in the status register (SR) is set to 1 Whether to mask NMI requests when the BL bit in SR is set to 1 can be selected. Extended function for SH-4A * Automatically updates the IMASK bit in SR according to the accepted interrupt level * Thirteen levels of on-chip module interrupt priority can be set By setting thirteen interrupt priority registers, the priorities of on-chip module interrupts can be selected from 30 levels for individual request sources. * User-mode interrupt disabling function Specifying an interrupt mask level in the user interrupt mask level register (USERIMASK) disables interrupts which are not higher in priority than the specified mask level in user mode. Figure 9.1 shows a block diagram of the INTC.
Rev. 1.00 Oct. 01, 2007 Page 233 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
NMI IRQ7/IRL7 to IRQ0/IRL0
NMI Input control 8 IRL IRQ Interrupt Priority determination
Comparator
CPU exception handing SR.IMASK
USERIMASK.UIMASK
INTPRI ICR0, ICR1 GPIO ports PINT15 to PINT0 WDT H-UDI DMAC PCIC Peripheral module on-chip Module 16 GPIO interrupt Interrupt request Interrupt request Interrupt request Interrupt request Interrupt request On- chip Module Interrupt Prority determination
Bus interface
INT2PRI0 to INT2PRI13 INTC INT2GPIC
Bus Interface
[Legend] WDT: Watch Dog Timer H-UDI: User Debugging interface DMAC: Direct Memory Access Controller PCIC: PCI controller INTPRI: Interrupt priority Level Setting Register ICR0, ICR1: Interrupt Control Register 0, 1 INT2PRI0 to13: Interrupt priority Register INT2GPIC: GPIO interrupt set register SR.IMASK: Status Register . IMASK bit USERIMASK.UIMASKWDT: User interrupt ask level register UIMASK bit Note: The following module csn issue on-chip peripheral module interrupt RTC, TMU, SCIF, IIC, STIF, TPU, SIM, CMT, HAC, SIOF, MMCIF, SSI, ADC, PCC, USBH, USBF, GETHER, LCDC, SECURITY However, SECURITY is incorporated only in the R5S77630, not in the R5S77631.
Figure 9.1 Block Diagram of INTC
Rev. 1.00 Oct. 01, 2007 Page 234 of 1956 REJ09B0256-0100
Peripheral bus
Section 9 Interrupt Controller (INTC)
9.1.1
Interrupt Method
The basic exception handling flow for the interrupt is as follows. In interrupt exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), and the CPU starts execution of the appropriate interrupt exception handling routine according to the vector address. An interrupt exception handling routine is a program written by the user to handle a specific exception. The interrupt exception handling routine is terminated and control returned to the original program by executing a return-from-exception instruction (RTE). This instruction restores the PC and SR contents and returns control to the normal processing routine at the point at which the exception occurred. The SGR contents are not written back to R15 with an RTE instruction. The PC, SR and R15 contents are saved to SPC, SSR and SGR, respectively. The block (BL) bit in SR is set to 1. The mode (MD) bit in SR is set to 1. The register bank (RB) bit in SR is set to 1. In a reset, the FPU disable (FD) bit in SR is cleared to 0. The exception code is written to bits 13 to 0 in the interrupt event register (INTEVT) of the exception source. 7. The processing is jumped to the start address of the interrupt exception handling routine, vector base register (VBR) + H'600. 8. The processing is branched to the vector address of the determined interrupt exception handling and the interrupt exception handling routine is started. 1. 2. 3. 4. 5. 6.
Rev. 1.00 Oct. 01, 2007 Page 235 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.1.2
Interrupt Types in INTC
Table 9.1 shows an example of the interrupt types. The INTC supports both the external interrupts and on-chip module interrupts. The external interrupts is the interrupt input from external pins, NMI, IRL, and IRQ. The IRQ and IRL are assigned to the same pin in the SH7763. The pin function is selected according to the system. IRQ input can be selected as a level, or a rising or falling edge. Table 9.1 Interrupt Types
Number of Sources Priority (Max.)
Source External NMI interrupts IRL
interrupt*
1
INTEVT H'1C0 H'200
Remarks
IRL[7:4] pin = H'0 IRL[3:0] pin = H'0
1 2
Inversion values of input pin values (because of negative pins) For example IRL[7:4] pin = H'0 means external pin input level is, IRL[7] pin = Low IRL[6] pin = Low IRL[5] pin = Low IRL[4] pin = Low then priority level is,15 (H'F) (See table 9.6)
High
H'220
IRL[7:4] pin = H'1 IRL[3:0] pin = H'1
H'240
IRL[7:4] pin = H'2 IRL[3:0] pin = H'2
H'260
IRL[7:4] pin = H'3 IRL[3:0] pin = H'3
H'280
IRL[7:4] pin = H'4 IRL[3:0] pin = H'4
H'2A0
IRL[7:4] pin = H'5 IRL[3:0] pin = H'5
H'2C0
IRL[7:4] pin = H'6 IRL[3:0] pin = H'6
H'2E0
IRL[7:4] pin = H'7 IRL[3:0] pin = H'7
H'300
IRL[7:4] pin = H'8 IRL[3:0] pin = H'8
Low
Rev. 1.00 Oct. 01, 2007 Page 236 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC) Number of Sources (Max.) Priority
Source
INTEVT H'320
Remarks
IRL[7:4] pin = H'9 IRL[3:0] pin = H'9
External IRL 2 interrupts interrupt*1
Inversion values of input pin values (because of negative pins)
High
For example IRL[7:4] pin = H'0 means external pin input level is, H'360 IRL[7] pin = Low IRL[6] pin = Low H'380 IRL[5] pin = Low IRL[4] pin = Low then priority level is,15 H'3A0 (H'F) (See table 9.6) H'3C0
H'340
IRL[7:4] pin = H'A IRL[3:0] pin = H'A IRL[7:4] pin = H'B IRL[3:0] pin = H'B IRL[7:4] pin = H'C IRL[3:0] pin = H'C IRL[7:4] pin = H'D IRL[3:0] pin = H'D IRL[7:4] pin = H'E IRL[3:0] pin = H'E
IRQ 8 interrupt
Values set in INTPRI
H'240 H'280 H'2C0 H'300 H'340 H'380 H'3C0 H'200
IRQ[0] IRQ[1] IRQ[2] IRQ[3] IRQ[4] IRQ[5] IRQ[6] IRQ[7] ATI PRI CUI SECI ITI TUNI0 TUNI1 TUNI2 TICPI2 H-UDI Low
On-chip RTC module 2 interrupts*
SECURITY *3
3
Setting value of INT2PRI0 H'480 to INT2PRI13 H'4A0 H'4C0 H'4E0 H'560 H'580 H'5A0 H'5C0 H'5E0 H'600
1 1 1 1 2 1
WDT TMU0 TMU1 TMU2 H-UDI
Rev. 1.00 Oct. 01, 2007 Page 237 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC) Number of Sources (Max.) Priority
Source LCDC On-chip module 2 DMAC interrupts*
INTEVT LCDCI DMTE0 DMTE1 DMTE2 DMTE3 DMAE ERI0 RXI0 BRI0 TXI0 DMTE4 DMTE5 IICI0 IICI1 CMTI GEINT0 GEINT1 GEINT2 HACI SERR INTA INTB INTC INTD ERR PWD3 PWD2 PWD1 PWD0 STIFI0 STIFI1
Remarks
1 7(5/7)
Setting value of INT2PRI0 H'620 to INT2PRI13 H'640 H'660 H'680 H'6A0 H'6C0
SCIF0
4
H'700 H'720 H'740 H'760
DMAC IIC0 IIC1 CMT
7(2/7) 1 1 1
H'780 H'7A0 H'8A0 H'8C0 H'900 H'920 H'940 H'960
GETHER 3
HAC PCIC0 PCIC1 PCIC2 PCIC3 PCIC4 PCIC5
1 1 1 1 1 1 5
H'980 H'A00 H'A20 H'A40 H'A60 H'A80 H'AA0 H'AC0 H'AE0 H'B00 H'B20
STIF0 STIF1
1 1
H'B40 H'B60
Rev. 1.00 Oct. 01, 2007 Page 238 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC) Number of Sources (Max.) Priority
Source SCIF1 On-chip module 2 interrupts*
INTEVT ERI1 RXI1 BRI1 TXI1 SIOFI0 SIOFI1 SIOFI2 USBHI USBFI0 USBFI1 TPI PCCI FSTAT TRAN ERR FRDY ERI RXI TXI TEND TUNI3 TUNI4 TUNI5 ADI SSII0 SSII1 SSII2 SSII3 ERI2 RXI2 BRI2 TXI2
Remarks
4
Setting value of INT2PRI0 H'B80 to INT2PRI13 H'BA0 H'BC0 H'BE0
SIOF0 SIOF1 SIOF2 USBH USBF TPU PCC MMCIF
1 1 1 1 2 1 1 4
H'C00 H'C20 H'C40 H'C60 H'C80 H'CA0 H'CC0 H'CE0 H'D00 H'D20 H'D40 H'D60
SIM
4
H'D80 H'DA0 H'DC0 H'DE0
TMU3 TMU4 TMU5 ADC SSI0 SSI1 SSI2 SSI3 SCIF2
1 1 1 1 1 1 1 1 4
H'E00 H'E20 H'E40 H'E60 H'E80 H'EA0 H'EC0 H'EE0 H'F00 H'F20 H'F40 H'F60
Rev. 1.00 Oct. 01, 2007 Page 239 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC) Number of Sources (Max.) Priority
Source
On-chip module 2 interrupts*
INTEVT CH0 CH1 CH2 CH3
Remarks
GPIO
4
Setting value of INT2PRI0 H'F80 to INT2PRI13 H'FA0 H'FC0 H'FE0
Notes: 1. Since the IRL interrupt request by IRL[3:0] (IRQ3/IRL3 to IRQ0/IRL0 pins) and IRL interrupt request by IRL[7:4] (IRQ7/IRL7 to IRQ4/IRL4 pins) have the same INTEVT codes, it is impossible to distinguish the former from the latter. Note that there is no flags in this LSI for distinguishing between them. 2. ITI: Interval timer interrupt TUNI0 to TUNI5: TMU channel 0 to 5 under flow interrupt TICPI2: TMU channel 2 input capture interrupt DMINT0 to DMINT11: DMAC channel 0 to 5 transfer end interrupt DMAE: DMAC address error interrupt (channel 0 to 5) ERI0, ERI1: SCIF channel 0, 1 receive error interrupt RXI0, RXI1: SCIF channel 0, 1 receive data full interrupt BRI0, BRI1: SCIF channel 0, 1 break interrupt TXI0, TXI1: SCIF channel 0, 1 transmission data empty interrupt 3. The SECURITY is not incorporated in the R5S77631. Therefore, the INTEVT code is reserved in the R5S77631.
9.2
Input/Output Pins
Table 9.2 shows the pin configuration. Table 9.2
Pin Name NMI IRQ3/IRL3 to IRQ0/IRL0
INTC Pin Configuration
Function Nonmaskable interrupt input pin I/O Input Description Nonmaskable interrupt request signal input Interrupt request signal input IRL [3:0] 4-bit level-encoded interrupt input when ICR0.IRLM0 = 0 IRQ3 to IRQ0 individual interrupt input when ICR0.IRLM0 = 1
External interrupt input pin Input
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Section 9 Interrupt Controller (INTC)
Pin Name IRQ7/IRL7 to IRQ4/IRL4
Function
I/O
Description Interrupt request signal input IRL [7:4] 4-bit level-encoded interrupt input when ICR0.IRLM1 = 0 IRQ7 to IRQ4 individual interrupt input when ICR0.IRLM1 = 1 Notifies that an interrupt request has generated This pin is asserted even if the CPU does not accept the interrupt request, but not asserted when the interrupt is masked.
External interrupt input pin Input
IRQOUT
Interrupt request output
Output
PINT15 to PINT0
Port interrupt input pins
Input
Port interrupt request signal input
9.3
Register Descriptions
Table 9.3 shows the INTC register configuration. These registers maintain software interfaces with the CPU (SH-4A) and are initialized by a power-on reset and a manual reset. Table 9.3 shows the INTC register configuration. Table 9.4 shows the register states in each operating mode. Table 9.3
Name Interrupt control register 0 Interrupt control register 1 Interrupt priority register Interrupt source register Interrupt mask register 0 Interrupt mask register 1 Interrupt mask register 2 Interrupt mask clear register 0 Interrupt mask clear register 1 Interrupt mask clear register 2
INTC Register Configuration
Abbreviation ICR0 ICR1 INTPRI INTREQ INTMSK0 INTMSK1 INTMSK2 INTMSKCLR0 INTMSKCLR1 INTMSKCLR2 R/W R/W R/W R/W P4 Address H'FFD0 0000 H'FFD0 001C H'FFD0 0010 Area 7 Address H'1FD0 0000 H'1FD0 001C H'1FD0 0010 H'1FD0 0024 H'1FD0 0044 H'1FD0 0048 H'1FD4 0080 H'1FD0 0064 H'1FD0 0068 H'1FD4 0084 Access Size 32 32 32 32 32 32 32 32 32 32
R/(W) H'FFD0 0024 R/W R/W R/W R/W R/W R/W H'FFD0 0044 H'FFD0 0048 H'FFD4 0080 H'FFD0 0064 H'FFD0 0068 H'FFD4 0084
Rev. 1.00 Oct. 01, 2007 Page 241 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Name NMI flag control register User interrupt mask level register Interrupt priority register 0 Interrupt priority register 1 Interrupt priority register 2 Interrupt priority register 3 Interrupt priority register 4 Interrupt priority register 5 Interrupt priority register 6 Interrupt priority register 7 Interrupt priority register 8 Interrupt priority register 9 Interrupt priority register 10 Interrupt priority register 11 Interrupt priority register 12 Interrupt priority register 13 Interrupt source register 0 (mask state is not affected) Interrupt source register 01 (mask state is not affected) Interrupt source register 1 (mask state is affected) Interrupt source register 11 (mask state is affected) Interrupt mask register Interrupt mask register 1 Interrupt mask clear register
Interrupt mask clear register 1
Abbreviation NMIFCR USERIMASK INT2PRI0 INT2PRI1 INT2PRI2 INT2PRI3 INT2PRI4 INT2PRI5 INT2PRI6 INT2PRI7 INT2PRI8 INT2PRI9 INT2PRI10 INT2PRI11 INT2PRI12 INT2PRI13 INT2A0 INT2A01 INT2A1 INT2A11 INT2MSKR INT2MSKR1 INT2MSKCR INT2MSKCR1 INT2B0 INT2B1
R/W
P4 Address
Area 7 Address H'1FD0 00C0 H'1FD3 0000 H'1FD4 0000 H'1FD4 0004 H'1FD4 0008 H'1FD4 000C H'1FD4 0010 H'1FD4 0014 H'1FD4 0018 H'1FD4 001C H'1FD4 00A0 H'1FD4 00A4 H'1FD4 00A8 H'1FD4 00AC H'1FD4 00B0 H'1FD4 00B4 H'1FD4 0030 H'1FD4 00C0 H'1FD4 0034 H'1FD4 00C4 H'1FD4 0038 H'1FD4 00D0 H'1FD4 003C H'1FD4 00D4 H'1FD4 0040 H'1FD4 0044
Access Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
R/(W) H'FFD0 00C0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W W W R R H'FFD3 0000 H'FFD4 0000 H'FFD4 0004 H'FFD4 0008 H'FFD4 000C H'FFD4 0010 H'FFD4 0014 H'FFD4 0018 H'FFD4 001C H'FFD4 00A0 H'FFD4 00A4 H'FFD4 00A8 H'FFD4 00AC H'FFD4 00B0 H'FFD4 00B4 H'FFD4 0030 H'FFD4 00C0 H'FFD4 0034 H'FFD4 00C4 H'FFD4 0038 H'FFD4 00D0 H'FFD4 003C H'FFD4 00D4 H'FFD4 0040 H'FFD4 0044
Individual module interrupt source register 0 Individual module interrupt source register 1
Rev. 1.00 Oct. 01, 2007 Page 242 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Name Individual module interrupt source register 2 Individual module interrupt source register 3 Individual module interrupt source register 4 Individual module interrupt source register 5 Individual module interrupt source register 6 Individual module interrupt source register 7 Individual module interrupt source register 9 Individual module interrupt source register 10 Individual module interrupt source register 11 GPIO interrupt set register
Abbreviation INT2B2 INT2B3 INT2B4 INT2B5 INT2B6 INT2B7 INT2B9 INT2B10 INT2B11 INT2GPIC
R/W R R R R R R R R R R/W
P4 Address H'FFD4 0048 H'FFD4 004C H'FFD4 0050 H'FFD4 0054 H'FFD4 0058 H'FFD4 005C H'FFD4 0064 H'FFD4 0068 H'FFD4 006C H'FFD4 0090
Area 7 Address H'1FD4 0048 H'1FD4 004C H'1FD4 0050 H'1FD4 0054 H'1FD4 0058 H'1FD4 005C H'1FD4 0064 H'1FD4 0068 H'1FD4 006C H'1FD4 0090
Access Size 32 32 32 32 32 32 32 32 32 32
Rev. 1.00 Oct. 01, 2007 Page 243 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Table 9.4
Name
Register States in Each Operating Mode
Power-on Abbreviation Reset ICR0 ICR1 INTPRI INTREQ INTMSK0 INTMSK1 INTMSK2
INTMSKCLR0 INTMSKCLR1 INTMSKCLR2
Manual Reset Sleep H'x000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'FF00 0000 H'FF00 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'x000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Interrupt control register 0 Interrupt control register 1 Interrupt priority register Interrupt source register Interrupt mask register 0 Interrupt mask register 1 Interrupt mask register 2
Interrupt mask clear register 0 Interrupt mask clear register 1 Interrupt mask clear register 2
H'x000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'FF00 0000 H'FF00 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'x000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000
NMI flag control register
NMIFCR
User interrupt mask level register USERIMASK
Interrupt priority register 0 Interrupt priority register 1 Interrupt priority register 2 Interrupt priority register 3 Interrupt priority register 4 Interrupt priority register 5 Interrupt priority register 6 Interrupt priority register 7 Interrupt priority register 8 Interrupt priority register 9 Interrupt priority register 10 Interrupt priority register 11 Interrupt priority register 12 Interrupt priority register 13 Interrupt source register 0 (mask state is not affected) Interrupt source register 01 (mask state is affected)
INT2PRI0 INT2PRI1 INT2PRI2 INT2PRI3 INT2PRI4 INT2PRI5 INT2PRI6 INT2PRI7 INT2PRI8 INT2PRI9 INT2PRI10 INT2PRI11 INT2PRI12 INT2PRI13 INT2A0 INT2A01
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Section 9 Interrupt Controller (INTC)
Name Interrupt source register 1 (mask state is affected) Interrupt source register 11 (mask state is affected) Interrupt mask register Interrupt mask register 1 Interrupt mask clear register
Interrupt mask clear register 1
Power-on Abbreviation Reset INT2A1 INT2A11 INT2MSKR
INT2MSKR1 INT2MSKCR INT2MSKCR1
Manual Reset Sleep H'0000 0000 H'0000 0000 H'FFFF FFFF H'FFFF FFFF H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
H'0000 0000 H'0000 0000 H'FFFF FFFF H'FFFF FFFF H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000
Individual module interrupt source registers 0 Individual module interrupt source registers 1 Individual module interrupt source registers 2 Individual module interrupt source registers 3 Individual module interrupt source registers 4 Individual module interrupt source registers 5 Individual module interrupt source registers 6 Individual module interrupt source registers 7 Individual module interrupt source registers 9 Individual module interrupt source registers 10 Individual module interrupt source registers 11 GPIO interrupt set register
INT2B0 INT2B1 INT2B2 INT2B3 INT2B4 INT2B5 INT2B6 INT2B7 INT2B9 INT2B10 INT2B11 INT2GPIC
Rev. 1.00 Oct. 01, 2007 Page 245 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.3.1
Interrupt Control Register 0 (ICR0)
ICR0 is a 32-bit readable and partially writable register that sets the input signal detection mode of the external interrupt input pins (IRQ7/IRL7 to IRQ0/IRL0) and NMI pin, and indicates the input level to the NMI pin.
Bit: 31 NMIL Initial value: R/W: Bit: 30 MAI 0 R/W 14 29
-
R 15
-
0 R
28
-
0 R
27
-
0 R
26
-
0 R
25
24
23
22
21
20
19
18
17
16
NMIB NMIE IRLM0 IRLM1 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6
-
0 R 5
-
0 R 4
-
0 R 3
-
0 R 2
-
0 R 1
-
0 R 0
13
12
11
10
-
Initial value: R/W: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
Bit 31
Bit Name NMIL
Initial Value Undefined
R/W R
Description NMI Input Level Sets the signal level input to the NMI pin. Reading this bit allows the user to know the NMI pin level, and writing is invalid. 0: Low level is input to the NMI pin 1: High level is input to the NMI pin
30
MAI
0
R/W
MAI Interrupt Mask Specifies whether all interrupts are masked during the low level period of the NMI pin level regardless of the BL bit in SR of the CPU. 0: Interrupts are enabled even if the NMI pin goes low 1: Interrupts are disabled if the NMI pin goes low
29 to 26
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 246 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 25
Bit Name NMIB
Initial Value 0
R/W R/W
Description NMI Block Mode Selects whether an NMI interrupt is held until the BL bit in SR is cleared to 0 or detected immediately when the BL bit in SR of the CPU is set to 1. 0: An NMI interrupt is held when the BL bit in SR is set to 1 (initial value) 1: An NMI interrupt is not held when the BL bit in SR is set to 1 Note: If interrupts are accepted with the BL bit in SR set to 1, previous exception information (SSR, SPC, SGR, and INTEVT) is lost.
24
NMIE
0
R/W
NMI Edge Select Selects whether an interrupt request signal to the NMI pin is detected at the rising edge or the falling edge. 0: An interrupt request is detected at the falling edge of NMI input (initial value) 1: An interrupt request is detected at the rising edge of NMI input
23
IRLM0
0
R/W
IRL Pin Mode 0 Selects whether IRQ3/IRL3 to IRQ0/IRL0 are used as the 4-bit encoded interrupt requests or as four independent interrupts. 0: IRQ3/IRL3 to IRQ0/IRL0 are used as the 4-bit levelencoded interrupt requests (IRL [3:0] interrupt; initial value) 1: IRQ3/IRL3 to IRQ0/IRL0 are used as four independent interrupt requests (IRQ [n] interrupt; n = 3 to 0) Note: The level-encoded IRL interrupt is not detected unless the pin levels sampled at every bus clock cycle remain unchanged for four consecutive cycles.
Rev. 1.00 Oct. 01, 2007 Page 247 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 22
Bit Name IRLM1
Initial Value 0
R/W R/W
Description IRL Pin Mode 1 Selects whether IRQ7/IRL7 to IRQ4/IRL4 are used as the 4-bit encoded interrupt requests or as four independent interrupts. 0: IRQ7/IRL7 to IRQ4/IRL4 are used as the 4-bit levelencoded interrupt requests (IRL [7:4] interrupt; initial value) 1: IRQ7/IRL7 to IRQ4/IRL4 are used as four independent interrupt requests (IRQ [n] interrupt; n = 7 to 4) Note: The level-encoded IRL interrupt is not detected unless the pin levels sampled at every bus clock cycle remain unchanged for four consecutive cycles.
21 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9.3.2
Interrupt Control Register 1 (ICR1)
ICR1 is a 32-bit readable/writable register that specifies the individual input signal detection modes of external interrupt input pins IRQ7/IRL7 to IRQ4/IRL4. This setting is valid only when using IRL7 to IRL4 and IRL3 to IRL0 as IRQ independent interrupts input to set the IRLM0 and IRLM1 bits to 1 in ICR0.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IRQ0S
Initial value: R/W: Bit:
IRQ1S 0 R/W 13 0 R/W 12
IRQ2S 0 R/W 11 0 R/W 10
IRQ3S 0 R/W 9 0 R/W 8
IRQ4S 0 R/W 7 0 R/W 6
IRQ5S 0 R/W 5 0 R/W 4
IRQ6S 0 R/W 3 0 R/W 2
IRQ7S 0 R/W 1 0 R/W 0
0 R/W 15
0 R/W 14
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
Initial value: R/W:
Rev. 1.00 Oct. 01, 2007 Page 248 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 31, 30 29, 28 27, 26 25, 24 23, 22 21, 20 19, 18 17, 16
Bit Name IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S IRQ5S IRQ6S IRQ7S
Initial Value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description IRQn Sense Select (n = 0 to 7) Selects whether interrupt signals to the IRQ7/IRL7 to IRQ0/IRL0 pins are detected at the rising edge, falling edge, high level, or low level. 00: Interrupt requests are detected at the falling edge of IRQn input 01: Interrupt requests are detected at the rising edge of IRQn input 10: Interrupt requests are detected at the low level of IRQn input 11: Interrupt requests are detected at the high level of IRQn input Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
All 0
R
Note: When the IRQ is set as level input (IRQnS1 = 1), an interrupt source is held until the CPU accepts an interrupt (not always IRQ). Therefore even if an interrupt source is disabled before this LSI returns from sleep mode, it is guaranteed that processing is branched to the interrupt handler when this LSI returns from sleep mode. The held interrupt can be cleared by setting the corresponding interrupt mask bit (the IM bit in the interrupt mask register) to 1.
9.3.3
Interrupt Priority Register (INTPRI)
INTPRI is a 32-bit readable/writable register that sets the IRQ[7:0] interrupt priorities (levels 15 to 0). This setting is valid only when using IRQ7/IRL7 to IRQ4/IRL4 and IRQ3/IRL3 to IRQ0/IRL0 as IRQ independent interrupts input to set the IRLM0 and IRLM1 bits to 1 in ICR0.
Bit:
31
30 IP0
29
28
27
26 IP1
25
24
23
22 IP2
21
20
19
18 IP3
17
16
Initial value: R/W: Bit:
0 R/W 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
IP4
Initial value: R/W:
IP5 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
IP6 0 R/W 0 R/W 0 R/W 0 R/W
IP7 0 R/W 0 R/W 0 R/W
0 R/W
0 R/W
0 R/W
Rev. 1.00 Oct. 01, 2007 Page 249 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit
Bit Name
Initial Value H'0 H'0 H'0 H'0 H'0 H'0 H'0 H'0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Set priority of an independent interrupt request of IRQ0. Set priority of an independent interrupt request of IRQ1. Set priority of an independent interrupt request of IRQ2. Set priority of an independent interrupt request of IRQ3. Set priority of an independent interrupt request of IRQ4. Set priority of an independent interrupt request of IRQ5. Set priority of an independent interrupt request of IRQ6. Set priority of an independent interrupt request of IRQ7.
31 to 28 IP0 27 to 24 IP1 23 to 20 IP2 19 to 16 IP3 15 to 12 IP4 11 to 8 7 to 4 3 to 0 IP5 IP6 IP7
Interrupt priorities should be determined by setting a value from H'F to H'1 to each 4-bit field. If the value is larger, the priority is higher. When the value of H'0 is set to a field, a corresponding interrupt is masked (initial value). 9.3.4 Interrupt Source Register (INTREQ)
INTREQ is a 32-bit readable and writable with conditions register that indicates which IRQ [n] (n = 0 to 7) interrupt is requested to the INTC. Even if interrupts are masked by INTPRI and INTMSK0, the INTREQ bits are not affected.
Bit:
31 IR0
30 IR1 0 R/W 14
29 IR2 0 R/W 13
28 IR3 0 R/W 12
27 IR4 0 R/W 11
26 IR5 0 R/W 10
25 IR6 0 R/W 9
24 IR7 0 R/W 8
23
-
0 R 7
22
-
21
-
20
-
19
-
18
-
0 R 2
17
-
0 R 1
16
-
Initial value: R/W: Bit:
0 R/W 15
0 R 6
0 R 5
0 R 4
0 R 3
0 R 0
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
Initial value: R/W:
Rev. 1.00 Oct. 01, 2007 Page 250 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Description Initial Value 0 0 0 0 0 0 0 0 At Edge Detection (IRQnS = 00 or 01, n = 0 to 7) [When reading] 0: A corresponding IRQ interrupt request is not detected 1: A corresponding IRQ interrupt request is detected [When writing]* 0: Each bit is cleared by writing 0 after reading 1 1: Holds detected interrupt request Note: Write 1 to the corresponding bit read as 0. 23 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. At Level Detection (IRQnS = 10 or 11, n = 0 to 7) [When reading] 0: A corresponding IRQ interrupt pin is not asserted 1: A corresponding IRQ interrupt pin has asserted, but the CPU does not accept it yet Writing is ignored.
Bit 31 30 29 28 27 26 25 24
Bit Name IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
R/W R/W R/W R/W R/W R/W R/W R/W R/W
9.3.5
Interrupt Mask Register 0 (INTMSK0)
INTMSK0 is 32-bit readable and writable with conditions registers that control mask settings for each interrupt request. To clear the mask settings for interrupts, write 1 to the corresponding bits in INTMSKCLR0. Writing 0 to bits in INTMSK0 is invalid. Note: Write B'1111 to the IM [03:00] or IM [07:04] bits when IRQ3/IRL3 to IRQ0/IRL0 or IRQ7/IRL7 to IRQ4/IRL4 is set to the 4-bit encoded interrupt input.
Rev. 1.00 Oct. 01, 2007 Page 251 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IM00 IM01 IM02 IM03 IM04 IM05 IM06 IM07
Initial value: R/W: Bit:
-
0 R 7
-
0 R 6
-
0 R 5
-
0 R 4
-
0 R 3
-
0 R 2
-
0 R 1
-
0 R 0
1 R/W 15
1 R/W 14
1 R/W 13
1 R/W 12
1 R/W 11
1 R/W 10
1 R/W 9
1 R/W 8
-
Initial value: R/W:
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
0 R
Bit 31 30 29 28 27 26 25 24 23 to 0
Bit Name IM00 IM01 IM02 IM03 IM04 IM05 IM06 IM07
Initial Value 1 1 1 1 1 1 1 1 All 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Description Sets masking of an [When reading] independent interrupt 0: Interrupts are accepted request of IRQ0. 1: Interrupts are masked Sets masking of an [When writing] independent interrupt 0: Invalid request of IRQ1. 1: Interrupts are masked Sets masking of an independent interrupt request of IRQ2. Sets masking of an independent interrupt request of IRQ3. Sets masking of an independent interrupt request of IRQ4. Sets masking of an independent interrupt request of IRQ5. Sets masking of an independent interrupt request of IRQ6. Sets masking of an independent interrupt request of IRQ7. Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 252 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.3.6
Interrupt mask register 1 (INTMSK1)
INTMSK1 is 32-bit readable and writable with conditions registers that control mask settings for each interrupt request. To clear the mask settings for interrupts, write 1 to the corresponding bits in INTMSKCLR1. Writing 0 to bits in INTMSK1 is invalid.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IM10 IM11
Initial value: R/W: Bit:
-
1 R 13
-
1 R 12
-
1 R 11
-
1 R 10
-
1 R 9
-
1 R 8
-
0 R 7
-
0 R 6
-
0 R 5
-
0 R 4
-
0 R 3
-
0 R 2
-
0 R 1
-
0 R 0
1 R/W 15
1 R/W 14
-
Initial value: R/W:
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
0 R
Bit 31
Bit Name IM10
Initial Value 1
R/W R/W
Description Sets masking of IRL3 to IRL0 interrupt requests when IRQ3/IRL3 to IRQ0/IRL0 are encoded interrupt input. [When reading] 0: Interrupts are accepted 1: Interrupts are masked [When writing]
30
IM11
1
R/W
Sets masking of IRQ7/IRL7 0: Invalid to IRQ4/IRL4 interrupt 1: Interrupts are masked requests when IRL [7:4] are encoded interrupt input. Reserved These bits are always read as 1. The write value should always be 1.
29 to 24
All 1
R
23 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 253 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.3.7
Interrupt mask register 2 (INTMSK2)
INTMSK2 is 32-bit readable and writable with conditions registers that control mask settings for each interrupt request. To clear the mask settings for interrupts, write 1 to the corresponding bits in INTMSKCLR2. Writing 0 to bits in INTMSK2 is invalid. INTMSK2 is valid when an IRL interrupt, which is generated by encoding input signals on pins IRL7 to IRL4 or IRL3 to IRL0, is requested while an IRL interrupt is not masked by INTMSK1.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IM015 IM014 IM013 IM012 IM011 IM010 IM009 IM008 IM007 IM006 IM005 IM004 IM003 IM002 IM001
Initial value: R/W: Bit:
-
0 R 0
0 R/W 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
IM115 IM114 IM113 IM112 IM111 IM110 IM109 IM108 IM107 IM106 IM105 IM104 IM103 IM102 IM101
Initial value: R/W:
-
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31
Bit Name IM015
Initial Value 0
R/W R/W
Description Sets masking of an interrupt request when IRL [3:0] = LLLL (H'0). Sets masking of an interrupt request when IRL [3:0] = LLLH (H'1). Sets masking of an interrupt request when IRL [3:0] = LLHL (H'2). Sets masking of an interrupt request when IRL [3:0] = LLHH (H'3). Sets masking of an interrupt request when IRL [3:0] = LHLL (H'4).. Sets masking of an interrupt request when IRL [3:0] = LHLH (H'5). [When reading] 0: Interrupts are accepted 1: Interrupts are masked [When writing] 0: Invalid 1: Interrupts are masked
30
IM014
0
R/W
29
IM013
0
R/W
28
IM012
0
R/W
27
IM011
0
R/W
26
IM010
0
R/W
Rev. 1.00 Oct. 01, 2007 Page 254 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 25
Bit Name IM009
Initial Value 0
R/W R/W
Description Sets masking of an interrupt request when IRL [3:0] = LHHL (H'6). Sets masking of an interrupt request when IRL [3:0] = LHHH (H'7). Sets masking of an interrupt request when IRL [3:0] = HLLL (H'8). Sets masking of an interrupt request when IRL [3:0] = HLLH (H'9). Sets masking of an interrupt request when IRL [3:0] = HLHL (H'A). Sets masking of an interrupt request when IRL [3:0] = HLHH (H'B). Sets masking of an interrupt request when IRL [3:0] = HHLL (H'C). Sets masking of an interrupt request when IRL [3:0] = HHLH (H'D). Sets masking of an interrupt request when IRL [3:0] = HHHL (H'E). Reserved This bit is always read as 0. The write value should always be 0. [When reading] 0: Interrupts are accepted 1: Interrupts are masked [When writing] 0: Invalid 1: Interrupts are masked Initial value: 0
24
IM008
0
R/W
23
IM007
0
R/W
22
IM006
0
R/W
21
IM005
0
R/W
20
IM004
0
R/W
19
IM003
0
R/W
18
IM002
0
R/W
17
IM001
0
R/W
16
--
0
R
Rev. 1.00 Oct. 01, 2007 Page 255 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 15
Bit Name IM115
Initial Value 0
R/W R/W
Description Sets masking of an interrupt request when IRL [7:4] = LLLL (H'0). Sets masking of an interrupt request when IRL [7:4] = LLLH (H'1). Sets masking of an interrupt request when IRL [7:4] = LLHL (H'2). Sets masking of an interrupt request when IRL [7:4] = LLHH (H'3). Sets masking of an interrupt request when IRL [7:4] = LHLL (H'4). Sets masking of an interrupt request when IRL [7:4] = LHLH (H'5). Sets masking of an interrupt request when IRL [7:4] = LHHL (H'6). Sets masking of an interrupt request when IRL [7:4] = LHHH (H'7). Sets masking of an interrupt request when IRL [7:4] = HLLL (H'8). Sets masking of an interrupt request when IRL [7:4] = HLLH (H'9). Sets masking of an interrupt request when IRL [7:4] = HLHL (H'A). Sets masking of an interrupt request when IRL [7:4] = HLHH (H'B). [When reading] 0: Interrupts are accepted 1: Interrupts are masked [When writing] 0: Invalid 1: Interrupts are masked
14
IM114
0
R/W
13
IM113
0
R/W
12
IM112
0
R/W
11
IM111
0
R/W
10
IM110
0
R/W
9
IM109
0
R/W
8
IM108
0
R/W
7
IM107
0
R/W
6
IM106
0
R/W
5
IM105
0
R/W
4
IM104
0
R/W
Rev. 1.00 Oct. 01, 2007 Page 256 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 3
Bit Name IM103
Initial Value 0
R/W R/W
Description Sets masking of an interrupt request when IRL [7:4] = HHLL (H'C). Sets masking of an interrupt request when IRL [7:4] = HHLH (H'D). Sets masking of an interrupt request when IRL [7:4] = HHHL (H'E). Reserved
Bit [When reading] 0: Interrupts are accepted 1: Interrupts are masked [When writing] 0: Invalid 1: Interrupts are masked
2
IM102
0
R/W
1
IM101
0
R/W
0
--
0
R
This bit is always read as 0. The write value should always be 0.
9.3.8
Interrupt Mask Clear Register 0 (INTMSKCLR0)
INTMSKCLR0 is 32-bit write-only registers that clear the mask settings for IRQn (n = 0 to 7) interrupt requests. An undefined value is read.
Bit:
31 IC00
30 IC01 0 R/W 14
29 IC02 0 R/W 13
28 IC03 0 R/W 12
27 IC04 0 R/W 11
26 IC05 0 R/W 10
25 IC06 0 R/W 9
24 IC07 0 R/W 8
23
-
0 R 7
22
-
0 R 6
21
-
0 R 5
20
-
0 R 4
19
-
0 R 3
18
-
0 R 2
17
-
0 R 1
16
-
0 R 0
Initial value: R/W: Bit:
0 R/W 15
-
Initial value: R/W:
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
0 R
Rev. 1.00 Oct. 01, 2007 Page 257 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 31
Bit Name IC00
Initial Value 0
R/W R/W
Description Clears masking of an independent interrupt request of IRQ0. Clears masking of an independent interrupt request of IRQ1. Clears masking of an independent interrupt request of IRQ2. Clears masking of an independent interrupt request of IRQ3. Clears masking of an independent interrupt request of IRQ4. Clears masking of an independent interrupt request of IRQ5. Clears masking of an independent interrupt request of IRQ6. Clears masking of an independent interrupt request of IRQ7. Reserved These bits are always read as 0. The write value should always be 0. [When reading] An undefined value is read. [When writing] 0: Invalid 1: Clears the corresponding interrupt mask (Interrupts are enabled)
30
IC01
0
R/W
29
IC02
0
R/W
28
IC03
0
R/W
27
IC04
0
R/W
26
IC05
0
R/W
25
IC06
0
R/W
24
IC07
0
R/W
23 to 0
--
All 0
R
Rev. 1.00 Oct. 01, 2007 Page 258 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.3.9
Interrupt mask clear register 1 (INTMSKCLR1)
INTMSKCLR1 is 32-bit write-only registers that clear the mask settings for IRL interrupt requests. An undefined value is read.
Bit:
31 IC10
30 IC11 0 R/W 14
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
0 R 13
-
0 R 12
-
0 R 11
-
0 R 10
-
0 R 9
-
0 R 8
-
0 R 7
-
0 R 6
-
0 R 5
-
0 R 4
-
0 R 3
-
0 R 2
-
0 R 1
-
0 R 0
Initial value: R/W: Bit:
0 R/W 15
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
Initial value: R/W:
Bit 31
Bit Name IC10
Initial Value 0
R/W R/W
Description Clears masking of IRQ3/IRL3 to IRQ0/IRL0 interrupt requests when IRL[3:0] are encoded interrupt input. Clears masking of IRQ7/IRL7 to IRQ4/IRL4 interrupt requests when IRL[7:4] are encoded interrupt input. Reserved These bits are always read as 0. The write value should always be 0. [When reading] An undefined value is read. [When writing] 0: Invalid 1: Clears the corresponding interrupt mask (Interrupts are enabled)
30
IC11
0
R/W
29 to 0
All 0
R
Rev. 1.00 Oct. 01, 2007 Page 259 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.3.10
Interrupt mask clear register 2 (INTMSKCLR2)
INTMSKCLR2 is 32-bit write-only registers that clear the mask settings for IRL interrupt requests. An undefined value is read.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IC015 IC014 IC013 IC012 IC011 IC010 IC009 IC008 IC007 IC006 IC005 IC004 IC003 IC002 IC001
Initial value: R/W: Bit:
-
0 R 0
0 R/W 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
IC115 IC114 IC113 IC112 IC111 IC110 IC109 IC108 IC107 IC106 IC105 IC104 IC103 IC102 IC101
Initial value: R/W:
-
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31
Bit Name IC015
Initial Value 0
R/W R/W
Description Clears masking of an interrupt request when IRL[3:0] = LLLL (H'0). Clears masking of an interrupt request when IRL[3:0] = LLLH (H'1). Clears masking of an interrupt request when IRL[3:0] = LLHL (H'2). Clears masking of an interrupt request when IRL[3:0] = LLHH (H'3). Clears masking of an interrupt request when IRL[3:0] = LHLL (H'4). Clears masking of an interrupt request when IRL[3:0] = LHLH (H'5). Clears masking of an interrupt request when IRL[3:0] = LHHL (H'6). Clears masking of an interrupt request when IRL[3:0] = LHHH (H'7). [When reading] An undefined value is read. [When writing] 0: Invalid 1: Clears the corresponding interrupt mask (Interrupts are enabled)
30
IC014
0
R/W
29
IC013
0
R/W
28
IC012
0
R/W
27
IC011
0
R/W
26
IC010
0
R/W
25
IC009
0
R/W
24
IC008
0
R/W
Rev. 1.00 Oct. 01, 2007 Page 260 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 23
Bit Name IC007
Initial Value 0
R/W R/W
Description Clears masking of an interrupt request when IRL[3:0] = HLLL (H'8). Clears masking of an interrupt request when IRL[3:0] = HLLH (H'9). Clears masking of an interrupt request when IRL[3:0] = HLHL (H'A). Clears masking of an interrupt request when IRL[3:0] = HLHH (H'B). Clears masking of an interrupt request when IRL[3:0] = HHLL (H'C). Clears masking of an interrupt request when IRL[3:0] = HHLH (H'D). Clears masking of an interrupt request when IRL[3:0] = HHHL (H'E). Reserved This bit is always read as 0. The write value should always be 0. [When reading] An undefined value is read. [When writing] 0: Invalid 1: Clears the corresponding interrupt mask (Interrupts are enabled)
22
IC006
0
R/W
21
IC005
0
R/W
20
IC004
0
R/W
19
IC003
0
R/W
18
IC002
0
R/W
17
IC001
0
R/W
16
--
0
R
15
IC115
0
R/W
Clears masking of an interrupt request when IRL[7:4] = LLLL (H'0). Clears masking of an interrupt request when IRL[7:4] = LLLH (H'1). Clears masking of an interrupt request when IRL[7:4] = LLHL (H'2). Clears masking of an interrupt request when IRL[7:4] = LLHH (H'3).
[When reading] An undefined value is read. [When writing] 0: Invalid 1: Clears the corresponding interrupt mask (Interrupts are enabled)
14
IC114
0
R/W
13
IC113
0
R/W
12
IC112
0
R/W
Rev. 1.00 Oct. 01, 2007 Page 261 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 11
Bit Name IC111
Initial Value 0
R/W R/W
Description Clears masking of an interrupt request when IRL[7:4] = LHLL (H'4). Clears masking of an interrupt request when IRL[7:4] = LHLH (H'5). Clears masking of an interrupt request when IRL[7:4] = LHHL (H'6). Clears masking of an interrupt request when IRL[7:4] = LHHH (H'7). Clears masking of an interrupt request when IRL[7:4] = HLLL (H'8). Clears masking of an interrupt request when IRL[7:4] = HLLH (H'9). Clears masking of an interrupt request when IRL[7:4] = HLHL (H'A). Clears masking of an interrupt request when IRL[7:4] = HLHH (H'B). Clears masking of an interrupt request when IRL[7:4] = HHLL (H'C). Clears masking of an interrupt request when IRL[7:4] = HHLH (H'D). Clears masking of an interrupt request when IRL[7:4] = HHHL (H'E). Reserved This bit is always read as 0. The write value should always be 0. [When reading] An undefined value is read. [When writing] 0: Invalid 1: Clears the corresponding interrupt mask (Interrupts are enabled)
10
IC110
0
R/W
9
IC109
0
R/W
8
IC108
0
R/W
7
IC107
0
R/W
6
IC106
0
R/W
5
IC105
0
R/W
4
IC104
0
R/W
3
IC103
0
R/W
2
IC102
0
R/W
1
IC101
0
R/W
0
--
0
R
Rev. 1.00 Oct. 01, 2007 Page 262 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.3.11
NMI Flag Control Register (NMIFCR)
NMIFCR is a 32-bit readable and partially writable with conditions register that has an NMI flag (NMIFL bit) that can be read or cleared by software. The NMIFL bit is automatically set to 1 by hardware when an NMI interrupt is detected by the INTC. To clear the NMIFL bit, write 0 to the bit by software. The NMIFL bit value does not affect NMI acceptance by the CPU. Although the NMI request detected by the INTC is cleared by CPU acceptance, the NMIFL bit is not cleared automatically. Even if 0 is written to the NMIFL bit before the NMI request is accepted by the CPU, the NMI request is not canceled.
Bit: 31 NMIL Initial value: R/W: Bit: R 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NMIFL 0 R/W 0
-
0 R 14
-
0 R 13
-
0 R 12
-
0 R 11
-
0 R 10
-
0 R 9
-
0 R 8
-
0 R 7
-
0 R 6
-
0 R 5
-
0 R 4
-
0 R 3
-
0 R 2
-
0 R 1
-
Initial value: R/W: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
Bit 31
Bit Name NMIL
Initial Value Undefined
R/W R
Description NMI Input Level Indicates the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. 0: Low level is input to the NMI pin 1: High level is input to the NMI pin
30 to 17 --
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 263 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 16
Bit Name NMIFL
Initial Value 0
R/W R/W
Description NMI Interrupt Request Signal Detection Indicates whether an NMI interrupt request signal has been detected. This bit is automatically set to 1 when the INTC detects an NMI interrupt request. Write 0 to clear the bit. Writing 1 is ignored. [When reading] 1: NMI is detected 0: NMI is not detected [When writing] 0: The NMI flag is cleared 1: Writing 1 is ignored
15 to 0
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9.3.12
User Interrupt Mask Level Register (USERIMASK)
USERIMASK is a 32-bit readable and writable with conditions register that sets the acceptable interrupt level. When addresses in area 7 are accessed using the MMU address translation function, USERIMASK can be accessed in user mode. Since only USERIMASK is allocated in the 64-Kbyte page (other INTC registers are allocated to a different area), it can be set to be accessed in user mode. Interrupts whose priority levels are lower than the level set in the UIMASK bit are masked. If the value of H'F is set to the UIMASK bit, all interrupts other than the NMI are masked. Interrupts whose priority levels are higher than the level set in the UIMASK bit are accepted under the following conditions: * The corresponding interrupt mask bit in the interrupt mask register is cleared to 0 (the interrupt is enabled). * The priority level set in the IMASK bit in SR is lower than that of the interrupt. Even if interrupts are accepted, the UIMASK value is not changed. USERIMASK is initialized to H'0000 0000 (all interrupts are enabled) when returning from a power-on reset or a manual reset.
Rev. 1.00 Oct. 01, 2007 Page 264 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
To prevent incorrect writing, this register can only be written to with bits 31 to 24 set to H'A5.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit:
-
0 R/W 14
-
0 R/W 13
-
0 R/W 12
-
0 R/W 11
-
0 R/W 10
-
0 R/W 9
-
0 R/W 8
-
0 R 7
-
0 R 6
-
0 R 5
-
0 R 4
-
0 R 3
-
0 R 2
-
0 R 1
-
0 R 0
0 R/W 15
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R 0 R/W
UIMASK 0 R/W 0 R/W 0 R/W
-
0 R
-
0 R
-
0 R
-
0 R
Initial value: R/W:
Bit
Bit Name
Initial Value H'00 All 0
R/W R/W R
Description To write a value to bits 7 to 4, write H'A5 to them. These bits are always read as 0. Reserved These bits are always read as 0. The write value should always be 0.
31 to 24 -- 23 to 8 --
7 to 4
UIMASK
H'0
R/W
Interrupt Mask Level Masks interrupts whose priority levels are lower than the level set in the UIMASK bit.
3 to 0
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Procedure for Using User Interrupt Mask Level Register This function is used to save time by disabling interrupts whose priorities are low when a high priority interrupt is processed in the device driver. Setting the interrupt mask level in USERIMASK disables interrupts having an equal or lower priority level than the specified mask level. This function can disable less-urgent interrupts in a task (such as device driver) operating in user mode to accelerate urgent processing. USERIMASK is allocated to a different 64-Kbyte page than where the other INTC registers are allocated. When accessing this register in user mode, translate the address through the MMU. In the system that uses a multitasking OS, processes that can access USERIMASK must be controlled by using memory protection functions of the MMU. When terminating the task or switching to another task, be sure to clear USERIMASK to 0 before quitting the task. If the UIMASK bits are left set to a non-zero value, interrupts which are not higher in priority than the
Rev. 1.00 Oct. 01, 2007 Page 265 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
UIMASK level are held disabled, and correct operation may not be performed (for example, the OS cannot switch tasks). An example of the usage procedure is shown below. 1. Classify interrupts to A and B as described below and set the A priority higher than the B priority. A. Interrupts to be accepted in the device driver (interrupts to be used by the operating system: a timer interrupt etc.) B. Interrupts to be disabled in the device driver 2. Make the MMU settings so that the address space including USERIMASK can only be accessed by the device driver in which interrupts should be disabled. 3. Branch to the device driver. 4. Set the UIMASK bit to mask B interrupts in the device driver that is operating in user mode. 5. Process interrupts with high priority in the device driver. 6. Clear the UIMASK bit to 0 to return from processing in the device driver. 9.3.13 On-chip module Interrupt Priority Registers (INT2PRI0 to INT2PRI13)
INT2PRI0 to INT2PRI13 are 32-bit readable/writable registers that set priorities (levels 31 to 0) of the on-chip peripheral module interrupts. INT2PRI0 to INT2PRI13 are initialized to H'0000 0000 by a reset. INT2PRI0 to INT2PRI13 can set 30 priority levels (32 types of interrupt requests) to individual interrupt sources with five bits (interrupt requests are masked at H'00 and H'01).
Bit:
31
-
0 R
30
-
0 R
29
-
0 R
28
27
26
25
24
23
22
21
20
19
18
17
16
-
0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R 7
-
0 R 6
-
0 R 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0
Initial value: R/W: Bit:
15
14
13
-
Initial value: R/W:
-
0 R
-
0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
-
0 R
-
0 R
-
0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
0 R
Rev. 1.00 Oct. 01, 2007 Page 266 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Table 9.5 shows the correspondence between interrupt request sources and bits in INT2PRI0 to INT2PRI13. Table 9.5 Interrupt Request Sources and INT2PRI0 to INT2PRI13
Bit Register INT2PRI0 INT2PRI1 INT2PRI2 INT2PRI3 INT2PRI4 INT2PRI5 INT2PRI6 INT2PRI7 INT2PRI8 INT2PRI9 INT2PRI10 INT2PRI11 INT2PRI12 INT2PRI13 28 to 24 TMU0 (TUNI0) TMU1 (TUNI3) SCIF0 H-UDI CMT PCIC2 SIOF0 SCIF2 SSI3 LCDC TPU PCC Reserved Reserved 20 to 16 TMU0 (TUNI1) TMU1 (TUNI4) SCIF1 DMAC HAC PCIC3 USBF GPIO SSI2 Reserved SIM Reserved Reserved Reserved 12 to 8 TMU0 (TUNI2) TMU1 (TUNI5) WDT ADC PCIC0 PCIC4 MMCIF Reserved SSI1 IIC1 SIOF2 Reserved USBH STIF1 4 to 0 TMU0 (TICPI2) RTC Reserved Reserved PCIC1 PCIC5 SSI0 Reserved SECURITY* IIC0 SIOF1 Reserved GETHER STIF0
Note: If the value is larger, the priority is higher. Interrupt requests are masked at H'00 and H'01. * These bits are reserved in the R5S77631.
Rev. 1.00 Oct. 01, 2007 Page 267 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.3.14
Interrupt Source Register 0 (Mask State is not affected) (INT2A0)
INT2A0 (mask state is not affected) is a 32-bit read-only register that indicates interrupt source modules. Even if interrupt masking is set in the interrupt mask register, INT2A0 indicates a source module in a corresponding bit (the corresponding interrupt is not generated). If source indication is not necessary depending on the state of the interrupt mask register, use INT2A1.
Bit:
31
30
29
28
27
26
25
GPIO
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit:
-
0 R 14
-
0 R 13
-
0 R 12
-
0 R 11
-
0 R 10
-
0 R 8
SSIO MMCIF
-
0 R 5
SIOF0 PCIC5 PCIC4 PCIC3 PCIC2
0 R 15
0 R 9
0 R 7
0 R 6
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
PCIC1 PCIC0 HAC CMT Initial value: R/W:
-
0 R
-
0 R
-
0 R
DMAC H-UDI
-
0 R
WDT SCIF1 SCIF0 RTC TMU1 TMU0
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Function These bits are always read as 0. The write value should always be 0. Indicates GPIO interrupt source This bit is always read as 0. The write value should always be 0. Indicates SSI0 interrupt source Indicates MMCIF interrupt source This bit is always read as 0. The write value should always be 0. Indicates SIOF0 interrupt source Indicates PCIC5 interrupt source Indicates PCIC4 interrupt source Indicates PCIC3 interrupt source Indicates PCIC2 interrupt source Indicates PCIC1 interrupt source Indicates PCIC0 interrupt source Indicates HAC interrupt source
Description Indicates interrupt sources for each peripheral module (INT2A0 is not affected by the state of the interrupt mask register). 0: No interrupts 1: Interrupts are generated Note: Reading the INTEVT code notified to the CPU directly can identify interrupt sources. In this case, reading INT2A0 is not necessary.
31 to 26 --
25 24 23 22 21 20 19 18 17 16 15 14 13
GPIO -- SSI0 MMCIF -- SIOF0 PCIC5 PCIC4 PCIC3 PCIC2 PCIC1 PCIC0 HAC
0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R R R R R R R R
Rev. 1.00 Oct. 01, 2007 Page 268 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 12
Initial Bit Name Value CMT 0 All 0 0 0 0 0 0 0 0 0 0
R/W R R R R R R R R R R R
Function Indicates CMT interrupt source This bit is always read as 0. The write value should always be 0. Indicates DMAC interrupt source Indicates H-UDI interrupt source This bit is always read as 0. The write value should always be 0. Indicates WDT interrupt source Indicates SCIF1 interrupt source Indicates SCIF0 interrupt source Indicates RTC interrupt source Indicates TMU1 interrupt source Indicates TMU0 interrupt source
Description Indicates interrupt sources for each peripheral module (INT2A0 is not affected by the state of the interrupt mask register). 0: No interrupts 1: Interrupts are generated Note: Reading the INTEVT code notified to the CPU directly can identify interrupt sources. In this case, reading INT2A0 is not necessary.
11 to 9 -- 8 7 6 5 4 3 2 1 0 DMAC H-UDI -- WDT SCIF1 SCIF0 RTC TMU1 TMU0
9.3.15
Interrupt Source Register 01 (Mask State is not affected) (INT2A01)
INT2A01 (mask state is not affected) is a 32-bit read-only register that indicates interrupt source modules. Even if interrupt masking is set in the interrupt mask register, INT2A01 indicates a source module in a corresponding bit (the corresponding interrupt is not generated). If source indication is not necessary depending on the state of the interrupt mask register, use INT2A11.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GETH
-
Initial value: R/W: Bit:
-
0 R 14
-
0 R 13
-
0 R 12
ADC
-
0 R 11
TPU
-
0 R 10
SCIF2 USBF
-
0 R 7
-
0 R 6
STIF1 STIF0
-
0 R 3
SSI3
-
0 R 2
0 R 15
PCC
0 R 9
0 R 8
0 R 5
IIC1
0 R 4
IIC0
USBH ER 0 0 R R
-
0 R
-
0 R
SIM SIOF2 SIOF1 LCDC
-
0 R
1
0
SECU
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
SSI2 SSI1 RITY* 0 0 0 R R R
Note: * This bit is reserved in the R5S77631.
Rev. 1.00 Oct. 01, 2007 Page 269 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit
Bit Name
Initial Value All 0
R/W R
Function
Description
31 to 26 --
25 24 23, 22
SCIF2 USBF --
0 0 All 0
R R R
21 20 19, 18
STIF1 STIF0 --
0 0 All 0
R R R
This bit is always read as 0. Indicates interrupt sources for each The write value should peripheral module always be 0. (INT2A01 is not affected Indicates SCIF2 interrupt by the state of the source interrupt mask register). Indicates USBF interrupt 0: No interrupts source 1: Interrupts are These bits are always read generated as 0. The write value should Note: Reading the always be 0. INTEVT code Indicates STIF1 interrupt notified to the CPU source directly can identify interrupt sources. Indicates STIF0 interrupt In this case, source reading INT2A01 is Undefined values are read not necessary. from these bits. The write value should always be 0 Indicates USBH interrupt source Indicates GETHER interrupt source Indicates PCC interrupt source This bit is always read as 0. The write value should always be 0. Undefined value is read from this bit. The write value should always be 0.
17 16 15 14
USBH GETHER PCC --
0 0 0 0
R R R R
13
--
0
R
12 11 10
ADC TPU SIM
0 0 0
R R R
Indicates ADC interrupt source Indicates TPU interrupt source Indicates SIM interrupt source
Rev. 1.00 Oct. 01, 2007 Page 270 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 9 8 7 6
Bit Name SIOF2 SIOF1 LCDC --
Initial Value 0 0 0 0
R/W R R R R
Function Indicates SIOF2 interrupt source Indicates SIOF1 interrupt source Indicates LCDC interrupt source
Description Indicates interrupt sources for each peripheral module (INT2A01 is not affected by the state of the interrupt mask register).
5 4 3 2 1 0 Note:
IIC1 IIC0 SSI3 SSI2 SSI1
0 0 0 0 0
R R R R R R
0: No interrupts This bit is always read as 0. 1: Interrupts are The write value should generated always be 0. Note: Reading the Indicates IIC1 interrupt INTEVT code source notified to the CPU Indicates IIC0 interrupt directly can identify source interrupt sources. In this case, Indicates SSI3 interrupt reading INT2A01 is source not necessary. Indicates SSI2 interrupt source Indicates SSI1 interrupt source Indicates SECURITY interrupt source
SECURITY* 0
*
This bit is reserved in the R5S77631.
Rev. 1.00 Oct. 01, 2007 Page 271 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.3.16
Interrupt Source Register (Mask State is affected) (INT2A1)
INT2A1 (mask state is affected) is a 32-bit read-only register that indicates interrupt source modules. Note that if interrupt masking is set in the interrupt mask register, INT2A1 does not indicate a source module in a corresponding bit. To check whether interrupts are generated, regardless of the state of the interrupt mask register, use INT2A0
Bit:
31
-
0 R
30
-
0 R
29
-
0 R
28
-
0 R
27
-
0 R
26
-
0 R
25
GPIO
24
-
0 R 8
23
22
21
SSI0 MMCIF
-
0 R 5
20
19
18
17
16
SIOF0 PCIC5 PCIC4 PCIC3 PCIC2
Initial value: R/W: Bit:
0 R 9
0 R 7
0 R 6
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
15
14
13
12
CMT
11
PCIC1 PCIC0 HAC Initial value: R/W:
-
0 R
10
-
0 R
-
0 R
DMAC H-UDI
-
0 R
WDT SCIF1 SCIF0 RTC TMU1 TMU0
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 26
Initial Bit Name Value -- All 0
R/W R
Function These bits are always read as 0. The write value should always be 0.
Description
25 24
GPIO --
0 0
R R
23 22 21
SSI0 MMCIF --
0 0 0
R R R
Indicates interrupt sources for each peripheral module (INT2A1 is affected Indicates GPIO interrupt source by the state of the This bit is always read as 0. interrupt mask The write value should always register). be 0. 0: No interrupts Indicates SSI0 interrupt source 1: Interrupts are Indicates MMCIF interrupt source This bit is always read as 0. The write value should always be 0. generated Note: Reading the INTEVT code notified to the CPU directly can identify interrupt sources. In this case, reading INT2A1 is not necessary.
20 19 18
SIOF0 PCIC5 PCIC4
0 0 0
R R R
Indicates SIOF0 interrupt source Indicates PCIC5 interrupt source Indicates PCIC4 interrupt source
Rev. 1.00 Oct. 01, 2007 Page 272 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 17 16 15 14 13 12 11 to 9
Initial Bit Name Value PCIC3 PCIC2 PCIC1 PCIC0 HAC CMT -- 0 0 0 0 0 0 All 0
R/W R R R R R R R
Function
Description
Indicates PCIC3 interrupt source Indicates interrupt Indicates PCIC2 interrupt source sources for each peripheral module Indicates PCIC1 interrupt source (INT2A1 is affected by Indicates PCIC0 interrupt source the state of the interrupt mask Indicates HAC interrupt source register). Indicates CMT interrupt source 0: No interrupts These bits are always read as 0. 1: Interrupts are The write value should always generated be 0. Note: Reading the Indicates DMAC interrupt source INTEVT code notified to the Indicates H-UDI interrupt source CPU directly This bit is always read as 0. The can identify write value should always be 0. interrupt Indicates WDT interrupt source sources. In this case, reading Indicates SCIF1 interrupt source INT2A1 is not Indicates SCIF0 interrupt source necessary. Indicates RTC interrupt source Indicates TMU1 interrupt source Indicates TMU0 interrupt source
8 7 6 5 4 3 2 1 0
DMAC H-UDI -- WDT SCIF1 SCIF0 RTC TMU1 TMU0
0 0 0 0 0 0 0 0 0
R R R R R R R R R
Rev. 1.00 Oct. 01, 2007 Page 273 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.3.17
Interrupt Source Register 11 (Mask State is affected) (INT2A11)
INT2A11 (mask state is affected) is a 32-bit read-only register that indicates interrupt source modules. Note that if interrupt masking is set in the interrupt mask register, INT2A11 does not indicate a source module in a corresponding bit. To check whether interrupts are generated, regardless of the state of the interrupt mask register, use INT2A01.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
-
Initial value: R/W: Bit:
-
0 R 14
-
0 R 13
-
0 R 12
ADC
-
0 R 11
TPU
-
0 R 10
SCIF2 USBF
-
0 R 7
-
0 R 6
STIF1 STIF0
-
0 R 3
-
0 R 2
17 16 USBH GETH
ER
0 R 15
PCC
0 R 9
0 R 8
0 R 5
IIC1
0 R 4
IIC0
0 R 1
0 R 0
SECU
-
0 R
-
0 R
SIM SIOF2 SIOF1 LCDC
-
0 R
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
SSI3 SSI2 SSI1 RITY* 0 0 0 0 R R R R
Note: * This bit is reserved in the R5S77631.
Bit
Bit Name
Initial Value All 0
R/W R
Function These bits are always read as 0. The write value should always be 0. Indicates SCIF2 interrupt source Indicates USBF interrupt source These bits are always read as 0. The write value should always be 0. Indicates STIF1 interrupt source Indicates STIF0 interrupt source These bits are always read as 0. The write value should always be 0.
Description Indicates interrupt sources for each peripheral module (INT2A11 is affected by the state of the interrupt mask register). 0: No interrupts 1: Interrupts are generated Note: Reading the INTEVT code notified to the CPU directly can identify interrupt sources. In this case, reading INT2A11 is not necessary.
31 to 26 --
25 24 23, 22
SCIF2 USBF --
0 0 All 0
R R R
21 20 19, 18
STIF1 STIF0 --
0 0 All 0
R R R
Rev. 1.00 Oct. 01, 2007 Page 274 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 17 16 15 14, 13
Bit Name USBH GETHER PCC --
Initial Value 0 0 0 All 0
R/W R R R R
Function Indicates USBH interrupt source
Description
12 11 10 9 8 7 6
ADC TPU SIM SIOF2 SIOF1 LCDC --
0 0 0 0 0 0 0
R R R R R R R
Indicates interrupt sources for each peripheral module Indicates GETHER interrupt (INT2A11 is affected source by the state of the Indicates PCC interrupt source interrupt mask These bits are always read as register). 0. The write value should 0: No interrupts always be 0. 1: Interrupts are Indicates ADC interrupt source generated Indicates TPU interrupt source Note: Reading the INTEVT code Indicates SIM interrupt source notified to the Indicates SIOF2 interrupt CPU directly can source identify interrupt sources. In this Indicates SIOF1 interrupt case, reading source INT2A11 is not Indicates LCDC interrupt necessary. source This bit is always read as 0. The write value should always be 0. Indicates IIC1 interrupt source Indicates IIC0 interrupt source Indicates SSI3 interrupt source Indicates SSI2 interrupt source Indicates SSI1 interrupt source Indicates SECURITY interrupt source
5 4 3 2 1 0 Note: *
IIC1 IIC0 SSI3 SSI2 SSI1
0 0 0 0 0
R R R R R R
SECURITY* 0
This bit is reserved in the R5S77631.
Rev. 1.00 Oct. 01, 2007 Page 275 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.3.18
Interrupt Mask Register (INT2MSKR)
INT2MSKR is a 32-bit readable/writable register that sets masking for each source indicated in the interrupt source register. Interrupts whose corresponding bits in INT2MSKRG are set to 1 are not notified to the CPU. INT2MSKR is initialized to H'FFFF FFFF (mask state) by a reset.
Bit:
31
30
29
28
27
26
25
GPIO
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit:
-
1 R 14
-
1 R 13
-
1 R 12
-
1 R 11
-
1 R 10
-
1 R 8
SSI0 MMCIF
-
1 R 5
SIOF0 PCIC5 PCIC4 PCIC3 PCIC2
1 R 15
1 R/W 9
1 R/W 7
1 R/W 6
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
PCIC1 PCIC0 HAC CMT Initial value: R/W:
-
1 R
-
1 R
-
1 R
DMAC H-UDI
-
1 R
WDT SCIF1 SCIF0 RTC TMU1 TMU0
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit
Bit Name
Initial Value All 1
R/W R
Function
Description
31 to 26 --
These bits are always read as 1. Masks interrupts The write value should always be for each peripheral module. 1. Masks GPIO interrupts [When writing] This bit is always read as 1. The 0: Invalid write value should always be 1. 1: Interrupts are masked Masks SSI0 interrupts Masks MMCIF interrupts [When reading] 0: No mask setting This bit is always read as 1. The write value should always be 1. 1: Mask setting Masks SIOF0 interrupts Masks PCIC5 interrupts Masks PCIC4 interrupts Masks PCIC3 interrupts Masks PCIC2 interrupts Masks PCIC1 interrupts Masks PCIC0 interrupts
25 24 23 22 21 20 19 18 17 16 15 14
GPIO -- SSI0 MMCIF -- SIOF0 PCIC5 PCIC4 PCIC3 PCIC2 PCIC1 PCIC0
1 1 1 1 1 1 1 1 1 1 1 1
R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 276 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 13 12 11 to 9
Initial Bit Name Value HAC CMT -- 1 1 All 1
R/W R/W R/W R
Function Masks HAC interrupts Masks CMT interrupts
Description Masks interrupts for each peripheral module.
These bits are always read as 1. [When writing] The write value should always be 0: Invalid 1. Masks DMAC interrupts Masks H-UDI interrupts This bit is always read as 1. The write value should always be 1. Masks WDT interrupts Masks SCIF1 interrupts Masks SCIF0 interrupts Masks RTC interrupts Masks TMU1 interrupts Masks TMU0 interrupts 1: Interrupts are masked [When reading] 0: No mask setting 1: Mask setting
8 7 6 5 4 3 2 1 0
DMAC H-UDI -- WDT SCIF1 SCIF0 RTC TMU1 TMU0
1 1 1 1 1 1 1 1 1
R/W R/W R R/W R/W R/W R/W R/W R/W
9.3.19
Interrupt Mask Register 1 (INT2MSKR1)
INT2MSKR1 is a 32-bit readable/writable register that sets masking for each source indicated in the interrupt source register. Interrupts whose corresponding bits in INT2MSKR1 are set to 1 are not notified to the CPU. INT2MSK1 is initialized to H'FFFF FFFF (mask state) by a reset.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
USBH
16
GETH ER
-
Initial value: R/W: Bit:
-
1 R 14
-
1 R 13
-
1 R 12
ADC
-
1 R 11
TPU
-
1 R 10
SCIF2 USBF
-
1 R 7
-
1 R 6
STIF1 STIF0
-
1 R 3
-
1 R 2
1 R 15
PCC
1 R/W 9
1 R/W 8
1 R/W 5
IIC1
1 R/W 4
IIC0
1 R/W 1
SSI1
1 R/W 0
SECU RITY*
-
1 R
-
1 R
SIM SIOF2 SIOF1 LCDC
-
1 R
SSI3 SSI2
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: * This bit is reserved in the R5S77631.
Rev. 1.00 Oct. 01, 2007 Page 277 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 31 to 26
Initial Bit Name Value -- All 1
R/W R
Function
Description
These bits are always read as 1. Masks interrupts for The write value should always each peripheral be 1. module. Masks SCIF2 interrupts Masks USBF interrupts [When writing] 0: Invalid
25 24 23, 22
SCIF2 USBF --
1 1 All 1
R/W R/W R
These bits are always read as 1. 1: Interrupts are masked The write value should always be 1. [When reading] Masks STIF1 interrupts Masks STIF0 interrupts These bits are always read as 1. The write value should always be 1. Masks USBH interrupts Masks GETHER interrupts Masks PCC interrupts These bits are always read as 1. The write value should always be 1. Masks ADC interrupts Masks TPU interrupts Masks SIM interrupts Masks SIOF2 interrupts Masks SIOF1 interrupts Masks LCDC interrupts This bit is always read as 1. The write value should always be 1. Masks IIC1 interrupts Masks IIC0 interrupts Masks SSI3 interrupts 0: No mask setting 1: Mask setting
21 20 19, 18
STIF1 STIF0 --
1 1 All 1
R/W R/W R
17 16 15 14, 13
USBH GETHER PCC --
1 1 1 All 1
R/W R/W R/W R
12 11 10 9 8 7 6 5 4 3
ADC TPU SIM SIOF2 SIOF1 LCDC -- IIC1 IIC0 SSI3
1 1 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R R/W R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 278 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 2 1 0
Initial Bit Name Value SSI2 SSI1
SECURITY*
R/W R/W R/W R/W
Function Masks SSI2 interrupts Masks SSI1 interrupts Masks SECURITY interrupts
Description Masks interrupts for each peripheral module. [When writing] 0: Invalid 1: Interrupts are masked [When reading] 0: No mask setting 1: Mask setting
1 1 1
Note:
*
This bit is reserved in the R5S77631.
9.3.20
Interrupt Mask Clear Register (INT2MSKCR)
INT2MSKCR is a 32-bit write-only register that clears any masking set in the interrupt mask register. Setting bits in this register to 1 clears the masking of the corresponding interrupt sources. Reading bits in this register is always 0.
Bit:
31
30
29
28
27
26
25
GPIO
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit:
-
0 R 14
-
0 R 13
-
0 R 12
-
0 R 11
-
0 R 10
-
0 R 8
SSI0 MMC
-
0 R 5
SIOF0 PCIC5 PCIC4 PCIC3 PCIC2
0 R 15
0 R/W 9
0 R/W 7
0 R/W 6
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
PCIC1 PCIC0 HAC CMT Initial value: R/W:
-
0 R
-
0 R
-
0 R
DMAC H-UDI
-
0 R
WDT SCIF1 SCIF0 RTC TMU1 TMU0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Rev. 1.00 Oct. 01, 2007 Page 279 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit
Initial Bit Name Value All 0
R/W R
Function
Description
31 to 26 --
These bits are always read as Clears interrupt 0. The write value should masking for each always be 0 peripheral module. Clears GPIO interrupt masking [When writing] 0: Invalid This bit is always read as 0. 1: Interrupt mask is The write value should always cleared be 0 [When reading] Clears SSI0 interrupt masking Always 0 Clears MMC interrupt masking This bit is always read as 0. The write value should always be 0 Clears SIOF0 interrupt masking Clears PCIC5 interrupt masking Clears PCIC4 interrupt masking Clears PCIC3 interrupt masking Clears PCIC2 interrupt masking Clears PCIC1 interrupt masking Clears PCIC0 interrupt masking Clears HAC interrupt masking Clears CMT interrupt masking These bits are always read as 0. The write value should always be 0 Clears DMAC interrupt masking
25 24
GPIO --
0 0
R/W R
23 22 21
SSI0 MMC --
0 0 0
R/W R/W R
20 19 18 17 16 15 14 13 12 11 to 9
SIOF0 PCIC5 PCIC4 PCIC3 PCIC2 PCIC1 PCIC0 HAC CMT --
0 0 0 0 0 0 0 0 0 All 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R
8
DMAC
0
R/W
Rev. 1.00 Oct. 01, 2007 Page 280 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 7 6
Initial Bit Name Value H-UDI -- 0 0
R/W R/W R
Function Clears H-UDI interrupt masking
Description Clears interrupt masking for each peripheral module.
5 4 3 2 1 0
WDT SCIF1 SCIF0 RTC TMU1 TMU0
0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
This bit is always read as 0. The write value should always [When writing] be 0 0: Invalid Clears WDT interrupt masking 1: Interrupt mask is Clears SCIF1 interrupt masking Clears SCIF0 interrupt masking Clears RTC interrupt masking Clears TMU1 interrupt masking Clears TMU0 interrupt masking cleared [When reading] Always 0
9.3.21
Interrupt Mask Clear Register 1 (INT2MSKCR1)
INT2MSKCR1 is a 32-bit write-only register that clears any masking set in the interrupt mask register. Setting bits in this register to 1 clears the masking of the corresponding interrupt sources. Reading bits in this register is always 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19
-
Initial value: R/W: Bit: 0 R 15 PCC Initial value: R/W: 0 R/W
-
0 R 14
-
0 R 13
-
0 R 12 ADC 0 R/W
-
0 R 11 TPU 0 R/W
-
0 R 10
SCIF2 USBF 0 R/W 9 0 R/W 8
-
0 R 7
-
0 R 6
STIF1 STIF0 0 R/W 5 IIC1 0 R/W 0 R/W 4 IIC0 0 R/W
-
0 R 3
18
-
0 R 2
17 USBH 0 R/W 1
16
GETH ER
0 R/W 0
SECU
-
0 R
-
0 R
SIM SIOF2 SIOF1 LCDC 0 R/W 0 R/W 0 R/W 0 R/W
-
0 R
SSI3 SSI2 0 R/W 0 R/W
SSI1 RITY* 0 0 R/W R/W
Note: * This bit is reserved in the R5S77631.
Rev. 1.00 Oct. 01, 2007 Page 281 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit
Bit Name
Initial Value All 0
R/W R
Function These bits are always read as 0. The write value should always be 0
Description Clears interrupt masking for each peripheral module.
31 to 26 --
25 24 23, 22
SCIF2 USBF --
0 0 All 0
R/W R/W R
Clears SCIF2 interrupt masking [When writing] Clears USBF interrupt masking 0: Invalid These bits are always read as 0. The write value should always be 0 1: Interrupt mask is cleared
21 20 19, 18
STIF1 STIF0 --
0 0 All 0
R/W R/W R
[When reading] Clears STIF1 interrupt masking Always 0 Clears STIF0 interrupt masking These bits are always read as 0. The write value should always be 0 Clears USBH interrupt masking Clears GETHER interrupt masking Clears PCC interrupt masking These bits are always read as 0. The write value should always be 0 Clears ADC interrupt masking Clears TPU interrupt masking Clears SIM interrupt masking Clears SIOF2 interrupt masking Clears SIOF1 interrupt masking Clears LCDC interrupt masking This bit is always read as 0. The write value should always be 0 Clears IIC1 interrupt masking Clears IIC0 interrupt masking Clears SSI3 interrupt masking Clears SSI2 interrupt masking
17 16 15 14, 13
USBH GETHER PCC --
0 0 0 All 0
R/W R/W R/W R
12 11 10 9 8 7 6
ADC TPU SIM SIOF2 SIOF1 LCDC --
0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R
5 4 3 2
IIC1 IIC0 SSI3 SSI2
0 0 0 0
R/W R/W R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 282 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Bit 1 0
Bit Name SSI1
Initial Value 0
R/W R/W R/W
Function Clears SSI1 interrupt masking Clears SECURITY interrupt masking
Description Clears interrupt masking for each peripheral module. [When writing] 0: Invalid 1: Interrupt mask is cleared [When reading] Always 0
SECURITY* 0
Note:
*
This bit is reserved in the R5S77631.
9.3.22
On-chip Module Interrupt Source Registers (INT2B0 to INT2B7 and INT2B9 to INT2B11)
INT2B0 to INT2B7 and INT2B9 to INT2B11 are 32-bit read-only registers that indicate detailed sources for interrupt source modules indicated in the interrupt source register. INT2B0 to INT2B7 and INT2B9 to INT2B11 are not affected by the mask state of the interrupt mask register. When mask setting is made for individual detailed sources, set the interrupt mask register or interrupt enable register in the corresponding modules. The initial value of these registers is undefined (reserve bit is always read as 0).
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Rev. 1.00 Oct. 01, 2007 Page 283 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
INT2B0: Indicates detailed interrupt sources for the TMU.
Module TMU Bit 31 to 7 6 5 4 3 2 1 0 Source -- TUNI5 TUNI4 TUNI3 TICPI2 TUNI2 TUNI1 TUNI0 Function Description
These bits are always read as 0. The Indicates TMU interrupt write value should always be 0. sources. This register indicates the TMU TMU channel 5 underflow interrupt interrupt sources even if TMU channel 4 underflow interrupt mask setting is made in the interrupt mask TMU channel 3 underflow interrupt register for them. TMU channel 2 input capture interrupt TMU channel 2 underflow interrupt TMU channel 1 underflow interrupt TMU channel 0 underflow interrupt
INT2B1: Indicates detailed interrupt sources for the RTC.
Module RTC Bit 31 to 3 2 1 0 Source -- CUI PRI ATI Function Description
These bits are always read as 0. The Indicates RTC interrupt write value should always be 0. sources. This register indicates the RTC RTC carry interrupt interrupt sources even if RTC period interrupt mask setting is made in the interrupt mask RTC alarm interrupt register for them.
INT2B2: Indicates detailed interrupt sources for the SCIF.
Module SCIF1 Bit 31 to 8 7 6 5 Source -- TXI1 BRI1 RXI1 Function Description
These bits are always read as 0. The Indicates SCIF interrupt write value should always be 0. sources. This register indicates the SCIF SCIF channel 1 transmit FIFO data interrupt sources even if empty interrupt mask setting is made in SCIF channel 1 break interrupt or the interrupt mask overrun error interrupt register for them. SCIF channel 1 receive FIFO data full interrupt or receive data ready interrupt SCIF channel 1 receive error interrupt
4
ERI1
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Section 9 Interrupt Controller (INTC)
Module SCIF0
Bit 3 2 1
Source TXI0 BRI0 RXI0
Function SCIF channel 0 transmit FIFO data empty interrupt
Description
Indicates SCIF interrupt sources. This register indicates the SCIF SCIF channel 0 break interrupt or interrupt sources even if overrun error interrupt mask setting is made in SCIF channel 0 receive FIFO data full the interrupt mask interrupt or receive data ready register for them. interrupt
0
ERI0
SCIF channel 0 receive error interrupt
INT2B3: Indicates detailed interrupt sources for the DMAC.
Module DMAC Bit Source Function Description
31 to 13 -- 12 11 to 6 5 4 3 2 1 0 DMAE -- DMTE5 DMTE4 DMTE3 DMTE2 DMTE1 DMTE0
These bits are always read as 0. The Indicates DMAC write value should always be 0. interrupt sources. This register indicates DMAC DMA channels 0 to 5 address error interrupt sources even if interrupt mask setting is made in These bits are always read as 0. The the interrupt mask write value should always be 0. register for them. Channel 5 DMA transfer end interrupt Channel 4 DMA transfer end interrupt Channel 3 DMA transfer end interrupt Channel 2 DMA transfer end interrupt Channel 1 DMA transfer end interrupt Channel 0 DMA transfer end interrupt
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Section 9 Interrupt Controller (INTC)
INT2B4: Indicates detailed interrupt sources for the PCIC.
Module PCIC Bit Source Function Description
31 to 10 -- 9 8 7 6 5 4 3 2 1 0 PWD0 PWD1 PWD2 PWD3 ERR INTD INTC INTB INTA SERR
These bits are always read as 0. The Indicates PCIC interrupt write value should always be 0. sources. This register indicates the PCIC PCIC power state D0 state interrupt interrupt sources even if PCIC power state D1 state interrupt mask setting is made in the interrupt mask PCIC power state D2 state interrupt register for them. PCIC power state D3 state interrupt PCIC error interrupt PCIC INTD interrupt PCIC INTC interrupt PCIC INTB interrupt PCIC INTA interrupt PCIC SERR interrupt
INT2B5: Indicates detailed interrupt sources for the MMCIF.
Module MMCIF Bit 31 to 4 3 2 Source -- FRDY ERR Function Description
These bits are always read as 0. The Indicates MMC interrupt write value should always be 0. sources. This register indicates MMC interrupt FIFO ready interrupt sources even if mask CRC error interrupt, data timeout setting is made in the error interrupt, or command timeout interrupt mask register error interrupt for them. Data response interrupt, data transfer end interrupt, command response receive end interrupt, command transmit end interrupt, or data busy end interrupt MMC FIFO empty interrupt or FIFO full interrupt
1
TRAN
0
FSTAT
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Section 9 Interrupt Controller (INTC)
INT2B6: Indicates detailed interrupt sources for the SCIF2.
Module SCIF2 Bit 31 to 4 3 Source -- TXI2 Function Description
2
BRI2
These bits are always read as 0. The Indicates SCIF2 write value should always be 0. interrupt sources. This register indicates the SCIF channel 2 transmit FIFO data SCIF2 interrupt sources empty interrupt even if mask setting is made in the interrupt SCIF channel 2 break interrupt or mask register for them. overrun error interrupt SCIF channel 2 receive FIFO data full interrupt or receive data ready interrupt SCIF channel 2 receive error interrupt
1
RXI2
0
ERI2
INT2B7: Indicates detailed interrupt sources for the GPIO.
Module GPIO Bit Source Function Description
31 to 28 -- 27 26 25 24 PINT15I PINT14I PINT13I PINT12I
These bits are always read as 0. The Indicates GPIO interrupt write value should always be 0. sources. This register indicates GPIO interrupt GPIO interrupt from PINT15 pin sources even if mask GPIO interrupt from PINT14 pin setting is made in the interrupt mask register GPIO interrupt from PINT13pin for them. GPIO interrupt from PINT12 pin These bits are always read as 0. The write value should always be 0.
23 to 20 -- 19 18 17 16
PINT11I GPIO interrupt from PINT11 pin PINT10I GPIO interrupt from PINT10 pin PINT9I PINT8I GPIO interrupt from PINT9 pin GPIO interrupt from PINT8 pin These bits are always read as 0. The write value should always be 0. GPIO interrupt from PINT7 pin
15 to 12 -- 11 PINT7I
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Section 9 Interrupt Controller (INTC)
Module GPIO
Bit 10 9 8 7 to 4 3 2 1 0
Source PINT6I PINT5I PINT4I -- PINT3I PINT2I PINT1I PINT0I
Function GPIO interrupt from PINT6 pin
Description
Indicates GPIO interrupt sources. This register GPIO interrupt from PINT5 pin indicates GPIO interrupt GPIO interrupt from PINT4 pin sources even if mask These bits are always read as 0. The setting is made in the interrupt mask register write value should always be 0. for them. GPIO interrupt from PINT3 pin GPIO interrupt from PINT2 pin GPIO interrupt from PINT1 pin GPIO interrupt from PINT0 pin
INT2B9: Indicates detailed interrupt sources for the GETHER.
Module GETHER Bit 31 to 3 2 1 0 Source -- Function Description
These bits are always read as 0. The Indicates GETHER write value should always be 0. interrupt sources. This register indicates the GEINT2 GEINT2 interrupt GETHER interrupt GEINT1 GEINT1 interrupt sources even if mask setting is made in the GEINT0 GEINT0 interrupt interrupt mask register for them.
INT2B10: Indicates detailed interrupt sources for the USBF.
Module USBF Bit 31 to 2 1 0 Source -- USBFI1 USBFI0 Function Description
These bits are always read as 0. The Indicates USBF write value should always be 0. interrupt sources. This register indicates the USBFI1 interrupt USBF interrupt sources USBFI0 interrupt even if mask setting is made in the interrupt mask register for them.
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Section 9 Interrupt Controller (INTC)
INT2B11: Indicates detailed interrupt sources for the SIM.
Module SIM Bit 31 to 4 3 2 1 0 Source -- TEND TXI RXI ERI Function Description
These bits are always read as 0. The Indicates SIM interrupt write value should always be 0. sources. This register indicates the SIM Transmit end interrupt interrupt sources even Transmit data empty interrupt if mask setting is made in the interrupt mask Receive data full interrupt register for them. Transmit/receive error interrupt
9.3.23
GPIO Interrupt Set Register (INT2GPIC)
INT2GPIC enables interrupt requests input from the following pins: PTB0 to PTB7 and PTM0 to PTM7. A GPIO interrupt is a low active and level-sense signal. Before enabling an interrupt request, set the corresponding pin as an input with the corresponding port control register (PBCR, PMCR). For the port control registers, see section 40, General Purpose I/O (GPIO).
Bit:
31
-
0 R
30
-
0 R
-
29
-
28
27
PINT 15E
26
PINT 14E
25
PINT 13E
24
PINT 12E
23
22
21
20
19
PINT 11E
18
PINT 10E
17
PINT 9E
16
PINT 8E
-
0 R 7
-
0 R 6
-
0 R 5
-
0 R 4
Initial value: R/W: Bit:
0 R 13
0 R 12
0 R/W 11
PINT 7E
0 R/W 10
PINT 6E
0 R/W 9
PINT 5E
0 R/W 8
PINT 4E
0 R/W 3
PINT 3E
0 R/W 2
PINT 2E
0 R/W 1
PINT 1E
0 R/W 0
PINT 0E
15
-
0 R
14
-
0 R
-
-
-
0 R
-
0 R
-
0 R
-
0 R
Initial value: R/W:
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
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Section 9 Interrupt Controller (INTC)
Bit 31 to 28
Bit Name --
Initial Value All 0
R/W R
Function
Description
27 26 25 24 23 to 20
PINT15E PINT14E PINT13E PINT12E --
0 0 0 0 All 0
R/W R/W R/W R/W R
Reserved Enables a GPIO These bits are always read as 0. interrupt request for each pin. The write value should always be 0. 0: Disables an interrupt request Enables a GPIO interrupt request from PINT15 pin Enables a GPIO interrupt request from PINT14 pin Enables a GPIO interrupt request from PINT13 pin Enables a GPIO interrupt request from PINT12 pin Reserved These bits are always read as 0. The write value should always be 0. 1: Enables an interrupt request
19 18 17 16 15 to 12
PINT11E PINT10E PINT9E PINT8E --
0 0 0 0 All 0
R/W R/W R/W R/W R
Enables a GPIO interrupt request from PINT11 pin Enables a GPIO interrupt request from PINT10 pin Enables a GPIO interrupt request from PINT9 pin Enables a GPIO interrupt request from PINT8 pin Reserved These bits are always read as 0. The write value should always be 0.
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Section 9 Interrupt Controller (INTC)
Bit 11 10 9 8 7 to 4
Bit Name PINT7E PINT6E PINT5E PINT4E --
Initial Value 0 0 0 0 All 0
R/W R/W R/W R/W R/W R
Function Enables a GPIO interrupt request from PINT7 pin Enables a GPIO interrupt request from PINT6 pin Enables a GPIO interrupt request from PINT5 pin Enables a GPIO interrupt request from PINT4 pin Reserved These bits are always read as 0. The write value should always be 0.
Description Enables a GPIO interrupt request for each pin. 0: Disables an interrupt request 1: Enables an interrupt request
3 2 1 0
PINT3E PINT2E PINT1E PINT0E
0 0 0 0
R/W R/W R/W R/W
Enables a GPIO interrupt request from PINT3 pin Enables a GPIO interrupt request from PINT2 pin Enables a GPIO interrupt request from PINT1 pin Enables a GPIO interrupt request from PINT0 pin
When GPIO ports are used as interrupt ports, if the GPIO detects an interrupt, the interrupt is notified to the INTC from the GPIO. However, it is indicated as a one-bit source in the INT2A0 or INT2A1 register of the INTC. Referring to the on-chip module interrupt source register INT2B7. Referring to the INTEVT code in the CPU can specify from which port group an interrupt is generated.
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Section 9 Interrupt Controller (INTC)
9.4
Interrupt Sources
There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip modules. Each interrupt has a priority level (16 to 0), with level 16 as the highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt requests are ignored. 9.4.1 NMI Interrupt
The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in SR of the CPU is set to 1. In sleep mode, the interrupt is accepted even if the BL bit is set to 1. A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1. Input from the NMI pin is edge-detected. The NMI edge select bit (NMIE) in ICR0 is used to select either rising or falling edge as the detection edge. When the NMIE bit in ICR0 is modified, the NMI interrupt is not detected for a maximum of six bus clock cycles after the modification. If the INTMU bit in CPUOPM is set to 1, the IMASK value in SR is automatically set to 15 by the accepted NMI interrupt. If the INTMU bit in CPUOPM is set to 0, the IMASK value in SR is not affected by the NMI interrupt exception handling. 9.4.2 IRQ Interrupts
IRQ interrupts are available when using the IRQ7/IRL7 to IRQ0/IRL0 pin for IRQn (n = 7 to 0) independent interrupt inputs by setting the IRLM0 and IRLM1 bits to 1 in ICR0. The IRQnS1 and IRQnS0 bits in ICR1 are used to select either rising edge, falling edge, low level, or high level detection. A priority level can be set for each input by using the interrupt priority level setting register (INTPRI). When level detection is selected for IRQ interrupt requests, the IRQ interrupt pin input level should be held until the CPU accepts the interrupt and starts interrupt handling. In level detection mode, after an interrupt request is accepted, the interrupt request held in the detection circuit should be cleared. For the specific clearing procedure, see section 9.7.3, To Clear IRQ and IRL Interrupt Requests. Note: In level detection mode, once an IRQ interrupt request has been detected, the INTC holds the interrupt request as the interrupt source in INTREQ even if the corresponding IRQ interrupt pin level is changed to cancel the request before the CPU accepts the request. The interrupt source will be held until the CPU accepts any other interrupt request (IRQ or not) or the corresponding interrupt mask bit is set to 1. For details, see section 9.7, Usage Notes.
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Section 9 Interrupt Controller (INTC)
When the INTMU bit in CPUOPM is 1, the interrupt mask level (IMASK) in SR is automatically modified to the level of the accepted interrupt. When the INTMU bit is 0, the IMASK value in SR is not affected by the accepted interrupt. 9.4.3 IRL Interrupts
IRL interrupts are input by level at pins IRQ7/IRL7 to IRQ4/IRL4 or IRQ3/IRL3 to IRQ0/IRL0. The priority level is the level indicated by pins IRQ7/IRL7 to IRQ4/IRL4 or IRQ3/IRL3 to IRQ0/IRL0. An IRQ7/IRL7 to IRQ4/IRL4 or IRQ3/IRL3 to IRQ0/IRL0 pins input are all low level indicates the highest-level interrupt request (interrupt priority level 15), and all high level indicates no interrupt request (interrupt priority level 0). Figure 9.2 shows an example of IRL interrupt connection, and table 9.6 shows the correspondence between the IRL pins and interrupt levels.
SH7763 Interrupt request Priprity encoder IRQ3/IRL3 to IRQ0/IRL0
IRL3 to IRL0
Interrupt request
Priprity encoder
IRL7 to IRL4
IRQ7/IRL7 to IRQ4/IRL4
Figure 9.2 Example of IRL Interrupt Connection
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Section 9 Interrupt Controller (INTC)
Table 9.6
IRL3 or IRL7 Low Low Low Low Low Low Low Low High High High High High High High High
RL[3:0], IRL[7:4] Pins and Interrupt Levels
IRL2 or IRL6 Low Low Low Low High High High High Low Low Low Low High High High High IRL1 or IRL5 Low Low High High Low Low High High Low Low High High Low Low High High IRL0 or IRL4 Low High Low High Low High Low High Low High Low High Low High Low High Interrupt Priority Level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt Request Level 15 Interrupt Request Level 14 Interrupt Request Level 13 Interrupt Request Level 12 Interrupt Request Level 11 Interrupt Request Level 10 Interrupt Request Level 9 Interrupt Request Level 8 Interrupt Request Level 7 Interrupt Request Level 6 Interrupt Request Level 5 Interrupt Request Level 4 Interrupt Request Level 3 Interrupt Request Level 2 Interrupt Request Level 1 Interrupt Request No Interrupt Request
After an interrupt request is accepted, the interrupt request held in the detection circuit should be cleared. For the specific clearing procedure, see section 9.7.3, To Clear IRQ and IRL Interrupt Requests. Note: Although there is no interrupt source register for the IRL interrupt requests, once an IRL interrupt request has been detected, the INTC holds the IRL interrupt request with the highest priority level as the interrupt source in the detection circuit even if the corresponding IRL interrupt pin level is changed to cancel the request before the CPU accepts the request. The interrupt source will be held until the CPU accepts any other interrupt request (IRL or not) or the corresponding interrupt mask bit is set to 1. In this case, the IRL interrupt request should be cleared in the interrupt handling routine. For details, see section 9.7, Usage Notes. When the INTMU bit in CPUOPM is 1, the interrupt mask level (IMASK) in SR is automatically modified to the level of the accepted interrupt. When the INTMU bit is 0, the IMASK value in SR is not affected by the accepted interrupt.
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Section 9 Interrupt Controller (INTC)
9.4.4
On-chip Module Interrupts
On-chip module interrupts are interrupts generated by on-chip modules. Not every interrupt source is assigned a different interrupt vector, but sources are reflected in the interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT value as a branch offset in the exception handling routine. A priority level from 31 to 0 can be set for each module by means of INT2PRI0 to INT2PRI13. The INTC rounds off the lowest one bit and sends 4-bit code to the CPU. In detail, see section 9.4.5, Interrupt Priority Level of On-chip Module Interrupts. When the INTMU bit in the CPUOPM is set to 1, the interrupt mask level (IMASK) in SR is automatically modified to the level 15 of the accepted NMI interrupt. When the INTMU bit in CPUOPM is cleared to 0, the IMASK value in SR is not affected by the accepted NMI interrupt. Updating of the interrupt source flag and interrupt enable flag of a peripheral module should only be carried out when the BL bit in SR is set to 1 or while the corresponding interrupt does not occur by setting its mask bit. To prevent erroneous interrupt acceptance from an interrupt source that should have been updated, first read the on-chip peripheral register containing the relevant flag and wait the priority determination time shown in table 9.8, then clear the BL bit to 0. This will secure the necessary timing internally. When updating a number of flags, there is no problem if only the register containing the last flag updated is read from. If flag updating is performed while the BL bit is cleared to 0, the program may jump to the interrupt handling routine when the INTEVT value is 0. In this case, interrupt processing is initiated due to the timing relationship between the flag update and interrupt request recognition within this LSI. Processing can be continued without any problem by executing an RTE instruction. 9.4.5 Interrupt Priority Level of On-chip Module Interrupts
When an on-chip module interrupt is generated, the INTC outputs its interrupt exception code (INTEVT code) as individual source identification to the CPU. When the CPU accepts an interrupt, the corresponding INTEVT code is indicated in INTEVT. Even if the interrupt source register of the INTC is not read, the interrupt source can be identified by reading INTEVT of the CPU in the interrupt handler. Table 9.1 lists the source of on-chip module interrupt and the interrupt exception codes. On-chip module interrupt, it can be set individual interrupt sources to 30 (5-bit) priority levels (see figure 9.1). The interrupt level receive interface consists of four bits and there are 15 priority levels (H'0 is interrupt request mask). The INTC consists of five bits in which one bit is extended
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Section 9 Interrupt Controller (INTC)
and determines the priorities of individual interrupt sources. The lowest one bit is then rounded off, the data is converted to 4-bit data, and the priority levels are notified. For example, two interrupt sources whose priority levels are set to H'1A and H'1B are both output as 4-bit priority level H'D. That is, the two interrupt sources have the same value. However, in terms of the INTEVT code that is notified when a conflict occurs between two interrupt sources, the INTEVT code that corresponds to the interrupt with a priority level of H'1B has priority. This is because the priority level of H'1B is higher than that of H'1A when comparing 5-bit data. When a conflict occurs between interrupts with the same priority level, the INTEVT code is notified according to the priority level shown in table 9.1.
INTC can distinguish H'1A from H'1B on-chip module interrupt priority level that same for the CPU. Priority level H'01 is same with interrupt request mask.
INTC Priority level: high (H'1B) 0 0
low (H'1A)
INTC Priority level: H'01
0
0
1
1
1
0
1
0
0
0
0
0
1
0
CPU Priority level:
0
0
0
even (H'D)
1
1
0
1
0 0 0 0 CPU Priority level: H'0 (interrupt is masked)
When multiple interrupt from on-chip modules occur simultaneously, the INTC proesses the priority level H'1B is higher than that of H'1A. However, if an external interrupt will be higher priority in some case. NMI interrupt request IRQ or IRL interrupt request that the same priority level or more (H'D or more in this figure).
Priority level H'01 becomes H'00 by rounding off the lowest bit, and then interrupt is not notifited to the CPU. The setting rauge of the interrupt priority register is H'02 to H'1F (30 priority levels).
Figure 9.3 On-chip Module Interrupt Priority 9.4.6 Interrupt Exception Handling and Priority
Table 9.7 lists the codes for the interrupt event register (INTEVT), and the order of interrupt priority. Each interrupt source is assigned a unique INTEVT code. The start address of the exception handling routine is common to each interrupt source. Therefore, to identify the interrupt source, branching is performed at the start of the exception handling routine using the INTEVT value. For instance, the INTEVT value is used as a branch offset.
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Section 9 Interrupt Controller (INTC)
The priority order of the on-chip modules is specified as desired by setting priority levels from 31 to 0 in INT2PRI0 to INT2PRI14. The priority order of the on-chip modules is set to 0 by a reset. When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated simultaneously, they are handled according to the default priority order shown in table 9.7. Updating of INTPRI and INT2PRI0 to INT2PRI14 should only be carried out when the BL bit in SR is set to 1. To prevent erroneous interrupt acceptance, first read one of the interrupt priority level setting registers, then clear the BL bit to 0. This will secure the necessary timing internally. Table 9.7 Interrupt Exception Handling and Priority
Interrupt INTEVT Interrupt MASK/CLEAR Interrupt Source Code Priority Register -- INTMSK2[15] INTMSKCLR2[15] INTMSK2[31] INTMSKCLR2[31] INTMSK2[14] INTMSKCLR2[14] INTMSK2[30] INTMSKCLR2[30] INTMSK2[13] INTMSKCLR2[13] INTMSK2[29] INTMSKCLR2[29] INTMSK2[12] INTMSKCLR2[12] INTMSK2[28] INTMSKCLR2[28] INTMSK2[11] INTMSKCLR2[11] INTMSK2[27] INTMSKCLR2[27] Source Register Detail Source Register Priority in the Source Default Priority
NMI IRL L: Low level input H: High level input (See table 9.6)
-- IRL[7:4] = LLLL (H'0) IRL[3:0] = LLLL (H'0)
H'1C0 16 H'200 15
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
--
High
IRL[7:4] = LLLH H'220 14 (H'1) IRL[3:0] = LLLH (H'1) IRL[7:4] = LLHL H'240 13 (H'2) IRL[3:0] = LLHL (H'2) IRL[7:4] = LLHH H'260 12 (H'3) IRL[3:0] = LLHH (H'3) IRL[7:4] = LHLL H'280 11 (H'4) IRL[3:0] = LHLL (H'4)
Low
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Section 9 Interrupt Controller (INTC)
Interrupt INTEVT Interrupt MASK/CLEAR Interrupt Source Code Priority Register INTMSK2[10] INTMSKCLR2[10] INTMSK2[26] INTMSKCLR2[26] INTMSK2[9] INTMSKCLR2[9] INTMSK2[25] INTMSKCLR2[25] INTMSK2[8] INTMSKCLR2[8] INTMSK2[24] INTMSKCLR2[24] INTMSK2[7] INTMSKCLR2[7] INTMSK2[23] INTMSKCLR2[23] INTMSK2[6] INTMSKCLR2[6] INTMSK2[22] INTMSKCLR2[22] INTMSK2[5] INTMSKCLR2[5] INTMSK2[21] INTMSKCLR2[21] INTMSK2[4] INTMSKCLR2[4] INTMSK2[20] INTMSKCLR2[20] Source Register
Detail Source Register
Priority in the Source Default Priority
IRL L: Low level input H: High level input (See table 9.6)
IRL[7:4] = LHLH H'2A0 10 (H'5) IRL[3:0] = LHLH (H'5) IRL[7:4] = LHHL H'2C0 9 (H'6) IRL[3:0] = LHHL (H'6) IRL[7:4] = LHHH H'2E0 8 (H'7) IRL[3:0] = LHHH (H'7) IRL[7:4] = HLLL H'300 7 (H'8) IRL[3:0] = HLLL (H'8) IRL[7:4] = HLLH H'320 6 (H'9) IRL[3:0] = HLLH (H'9) IRL[7:4] = HLHL H'340 5 (H'A) IRL[3:0] = HLHL (H'A) IRL[7:4] = HLHH H'360 4 (H'B) IRL[3:0] = HLHH (H'B)
-- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- --
High
Low
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Section 9 Interrupt Controller (INTC)
Interrupt INTEVT Interrupt MASK/CLEAR Interrupt Source Code Priority Register INTMSK2[3] INTMSKCLR2[3] INTMSK2[19] INTMSKCLR2[19] INTMSK2[2] INTMSKCLR2[2] INTMSK2[18] INTMSKCLR2[18] INTMSK2[1] INTMSKCLR2[1] INTMSK2[17] INTMSKCLR2[17] Source Register
Detail Source Register
Priority in the Source Default Priority
IRL L: Low level input H: High level input (See table 9.6)
IRL[7:4] = HHLL H'380 3 (H'C) IRL[3:0] = HHLL (H'C) IRL[7:4] = HHLH H'3A0 2 (H'D) IRL[3:0] = HHLH (H'D) IRL[7:4] = HHHL H'3C0 1 (H'E) IRL[3:0] = HHHL (H'E)
-- -- -- -- -- --
-- -- -- -- -- -- High
High
IRQ
IRQ[0]
H'240
INTPRI [31:28]
INTMSK0[31] INTMSKCLR0[31] INTMSK0[30] INTMSKCLR0[30] INTMSK0[29] INTMSKCLR0[29] INTMSK0[28] INTMSKCLR0[28] INTMSK0[27] INTMSKCLR0[27] INTMSK0[26] INTMSKCLR0[26] INTMSK0[25] INTMSKCLR0[25] INTMSK0[24] INTMSKCLR0[24]
INTREQ -- [31] INTREQ -- [30] INTREQ -- [29] INTREQ -- [28] INTREQ -- [27] INTREQ -- [26] INTREQ -- [25] INTREQ -- [24]
IRQ[1] IRQ[2] IRQ[3] IRQ[4] IRQ[5] IRQ[6] IRQ[7]
H'280 H'2C0 H'300 H'340 H'380 H'3C0 H'200
INTPRI [27:24] INTPRI [23:20] INTPRI [19:16] INTPRI [15:12] INTPRI [11:8] INTPRI [7:4] INTPRI [3:0]
Low
Low
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Section 9 Interrupt Controller (INTC)
Interrupt INTEVT Interrupt MASK/CLEAR Interrupt Source Code Priority Register Source Register
Detail Source Register
Priority in the Source Default Priority
RTC
ATI PRI CUI
2
H'480 H'4A0 H'4C0 H'4E0
INT2PRI INT2MSKR[2] 1[4:0] INT2MSKCR[2]
INT2A0[2] INT2B1[0] INT2A1[2] INT2B1[1] INT2B1[2]
High
High
Low
SECURITY*
SECI
INT2PRI INT2MSKR1[0] 8[4:0] INT2MSKCR1[0]
INT2A01 [0] INT2A11 [0]
--
WDT TMU0 TMU1 TMU2
ITI*
1
H'560
1
INT2PRI INT2MSKR[5] 2[12:8] INT2MSKCR[5]
INT2A0[5] INT2A1[5]
--
TUNI0*
H'580 H'5A0 H'5C0 H'5E0 H'600 H'620
INT2PRI INT2MSKR[0] 0[28:24] INT2MSKCR[0]
INT2A0[0] INT2B0[0] INT2A1[0] INT2B0[1]
TUNI1*1 TUNI2*1 TICPI2*1
INT2PRI 0[20:16] INT2PRI 0[12:8] INT2PRI 0[4:0]
INT2B0[2]
INT2B0[3]
H-UDI LCDC
H-UDI LCDCI
INT2PRI INT2MSKR[7] 3[28:24] INT2MSKCR[7]
INT2A0[7] INT2A1[7] INT2A01[7 ] INT2A11[7 ]
-- --
INT2PRI INT2MSKR1[7] 9[28:24] INT2MSKCR1[7]
DMAC (0)
DMINT0* DMINT1* DMINT2* DMINT3*
1
H'640 H'660 H'680 H'6A0 H'6C0
INT2PRI INT2MSKR[8] 3[20:16] INT2MSKCR[8]
INT2A0[8] INT2B3[0] INT2A1[8] INT2B3[1] INT2B3[2] INT2B3[3] INT2B3 [12] INT2B3 [13]
High
1
1
1
DMAE (ch0 to 5)*1
Low
Low
Rev. 1.00 Oct. 01, 2007 Page 300 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Interrupt INTEVT Interrupt Interrupt Source Code Priority MASK/CLEAR Register Source Register INT2A0[3] INT2A1[3]
Detail Source Register INT2B2[0] INT2B2[1] INT2B2[2] INT2B2[3]
Priority in the Source Default Priority
SCIF0
ERI0* RXI0* BRI0* TXI0*
1 1
H'700 H'720 H'740 H'760
1
INT2PRI2 INT2MSKR[3] [28:24] INT2MSKCR[3]
High
High
1
Low DMAC (0) DMINT4* H'780 H'7A0 H'8A0 H'8C0 H'900 H'920 H'940 H'960 H'980 H'A00 H'A20 H'A40 H'A60 H'A80
INT2PRI4 INT2MSKR[13] [20:16] INT2MSKCR[13] INT2A0[13] INT2A1[13] INT2A0[14] INT2A1[14] INT2A0[15] INT2A1[15] INT2A0[16] INT2A1[16] INT2A0[17] INT2A1[17] INT2A0[18] INT2A1[18] INT2B4[4] INT2B4[3] INT2B4[2] INT2B4[1] INT2B4[0] INT2PRI3 INT2MSKR[8] [20:16] INT2MSKCR[8] INT2A0[8] INT2A1[8] INT2A01[4] INT2A11[4] INT2A01[5] INT2A11[5] INT2A0[12] INT2A1[12] INT2A01[16] INT2B9[0] INT2B3[4] INT2B3[5]
High Low
DMINT5* IIC0 IIC1 CMT GEther IICI0 IICI1 CMTI GEINT0 GEINT1 GEINT2 HAC PCIC0 PCIC1 PCIC2 PCIC3 PCIC4 HACI
1
INT2PRI9 INT2MSKR1[4] [4:0] INT2MSKCR1[4]
-- -- --
INT2PRI9 INT2MSKR1[5] [12:8] INT2MSKCR1[5]
INT2PRI4 INT2MSKR[12] [28:24] INT2PRI 12[4:0] INT2MSKCR[12] INT2MSKR1[16]
INT2MSKCR1[16] INT2A11[16] INT2B9[1] INT2B9[2]
--
PCISERR PCIINTA PCIINTB PCIINTC PCIINTD
INT2PRI4 INT2MSKR[14] [12:8] INT2MSKCR[14]
INT2PRI4 INT2MSKR[15] [4:0] INT2MSKCR[15]
INT2PRI5 INT2MSKR[16] [28:24] INT2MSKCR[16]
INT2PRI5 INT2MSKR[17] [20:16] INT2MSKCR[17]
INT2PRI5 INT2MSKR[18] [12:8] INT2MSKCR[18]
Low
Rev. 1.00 Oct. 01, 2007 Page 301 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Interrupt INTEVT Interrupt Interrupt Source Code Priority MASK/CLEAR Register Source Register INT2A0[19] INT2A1[19]
Detail Source Register INT2B4[5] INT2B4[6] INT2B4[7] INT2B4[8] INT2B4[9]
Priority in the Source Default Priority
PCIC5
PCIERR PCIPWD3 PCIPWD2 PCIPWD1 PCIPWD0
H'AA0 H'AC0 H'AE0 H'B00 H'B20 H'B40 H'B60 H'B80 H'BA0 H'BC0 H'BE0 H'C00 H'C20 H'C40 H'C60
INT2PRI5 INT2MSKR[19] [4:0] INT2MSKCR[19]
High
High
Low
STIF0 STIF1 SCIF1
STIFI0 STIFI1 ERI1*
1
INT2PRI 13[4:0] INT2PRI 13[12:8]
INT2MSKR1[20]
INT2A01[20]
-- -- High
INT2MSKCR1[20] INT2A11[20] INT2MSKR1[21] INT2A01[21]
INT2MSKCR1[21] INT2A11[21] INT2A0[4] INT2A1[4] INT2B2[4] INT2B2[5] INT2B2[6] INT2B2[7]
INT2PRI2 INT2MSKR[4] [20:16] INT2MSKCR[4]
RXI1* BRI1* TXI1* SIOF0 SIOF1 SIOF2 USBH
1
1
1
Low
SIOFI0 SIOFI1 SIOFI2 USBHI
INT2PRI6 INT2MSKR[14] [28:24] INT2MSKCR[14]
INT2A0[14] INT2A1[14] INT2A01[8] INT2A11[8] INT2A01[9] INT2A11[9]
-- -- -- --
INT2PRI1 INT2MSKR1[8] 0[4:0] INT2MSKCR1[8]
INT2PRI1 INT2MSKR1[9] 0[12:8] INT2MSKCR1[9]
INT2PRI1 INT2MSKR1[17] 2[12:8] INT2MSKCR1 [17]
INT2A01 [17] INT2A11 [17] INT2A01 [24] INT2A11 [24]
USBF
USBFI0 USBFI1
H'C80 H'CA0
INT2PRI6 INT2MSKR1[24] [20:16] INT2MSKCR1 [24]
INT2B10 [0] INT2B10 [1]
Low
Rev. 1.00 Oct. 01, 2007 Page 302 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Interrupt INTEVT Interrupt Interrupt Source Code Priority MASK/CLEAR Register Source Register
Detail Source Register
Priority in the Source Default Priority
TPU
TPI
H'CC0
INT2PRI10 INT2MSKR1[11] [28:24] INT2MSKCR1 [11]
INT2A01 -- [11] INT2A11 [11] INT2A01 -- [15] INT2A11 [15]
INT2A0[22] INT2B5[0]
High
PCC
PCCI
H'CE0
INT2PRI11 INT2MSKR1[15] [28:24] INT2MSKCR1 [15]
MMCIF
FSTAT TRAN ERR FRDY
H'D00 H'D20 H'D40 H'D60 H'D80 H'DA0 H'DC0 H'DE0
1
INT2PRI6 [12:8]
INT2MSKR[22]
High
INT2MSKCR[22] INT2A1[22] INT2B5[1] INT2B5[2] INT2B5[3]
Low SIM ERI RXI TXI TEND TMU3 TMU4 TMU5 ADC TUNI3*
INT2PRI10 INT2MSKR1[10] [20:16] INT2MSKCR1 [10]
INT2A01 [10] INT2A11 [10]
INT2A0[1] INT2A1[1]
INT2B11[0] INT2B11[1] INT2B11[2] INT2B11[3]
H'E00 H'E20 H'E40 H'E60
INT2PRI1 [28:24]
INT2MSKR[1] INT2MSKCR[1]
INT2B0[4]
TUNI4*1 TUNI5*1 ADI
INT2PRI1 [20:16] INT2PRI1 [12:8] INT2PRI3 [12:8] INT2MSKR1[12] INT2MSKCR1 [12]
INT2B0[5]
INT2B0[6]
INT2A01 -- [12] INT2A11 [12]
INT2A0[23]
SSI0 SSI1
SSII0 SSII1
H'E80 H'EA0
INT2PRI6 [4:0] INT2PRI8 [12:8]
INT2MSKR[23]
-- -- Low
INT2MSKCR[23] INT2A1[23] INT2MSKR1[1] INT2A01[1]
INT2MSKCR1[1] INT2A11[1]
Rev. 1.00 Oct. 01, 2007 Page 303 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Interrupt INTEVT Interrupt Source Code Interrupt Priority MASK/CLEAR Register Source Register INT2A01[2] INT2A11[2] INT2A01[3] INT2A11[3]
Detail Source Register
Priority in the Source Default Priority
SSI2 SSI3 SCIF2
SSII2 SSII3 ERI2 RXI2 BRI2 TXI2
H'EC0 H'EE0 H'F00 H'F20 H'F40 H'F60 H'F80 H'FA0 H'FC0 H'FE0
INT2PRI8 INT2MSKR1[2] [20:16] INT2MSKCR1[2]
-- -- High
High
INT2PRI8 INT2MSKR1[3] [28:24] INT2MSKCR1[3]
INT2PRI7 INT2MSKR1[25] [28:24] INT2MSKCR1[25]
INT2A01 [25] INT2A11 [25]
INT2B6[0] INT2B6[1] INT2B6[2] INT2B6[3]
Low
GPIO
CH0 CH1 CH2 CH3
INT2PRI7 INT2MSKR[25] [20:16] INT2MSKCR[25]
INT2A0[25] INT2A1[25]
INT2B7 High [3:0] INT2B7 [11:8] INT2B7 [19:16] INT2B7 [27:24] Low Low
Notes: 1. ITI: Interval timer interrupt TUNI0 to TUNI5: TMU channel 0 to 5 under flow interrupt TICPI2: TMU channel 2 input capture interrupt DMINT0 to DMINT5: DMAC channel 0 to 5 transfer end interrupt DMAE: DMAC address error interrupt (channel 0 to 5) ERI0, ERI1: SCIF channel 0, 1 receive error interrupt RXI0, RXI1: SCIF channel 0, 1 receive data full interrupt BRI0, BRI1: SCIF channel 0, 1 break interrupt TXI0, TXI1: SCIF channel 0, 1 transmission data empty interrupt 2. This bit is reserved in the R5S77631.
Rev. 1.00 Oct. 01, 2007 Page 304 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.5
9.5.1
Operation
Interrupt Sequence
The sequence of interrupt operations is described below. Figure 9.4 is the flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the INTC. 2. The INTC selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in INTPRI and INT2PRI0 to INT2PRI14. Lower-priority interrupts are held pending. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest priority is selected according to table 9.7. 3. The priority level of the interrupt selected by the INTC is compared with the interrupt mask level (IMASK) set in SR of the CPU. If the priority level is higher than the mask level, the INTC accepts the interrupt and sends an interrupt request signal to the CPU. 4. The CPU accepts an interrupt at a break in instructions. 5. The interrupt source code is set in the interrupt event register (INTEVT). 6. SR and program counter (PC) are saved to SSR and SPC, respectively. R15 is saved to SGR at this time. 7. The BL, MD, and RB bits in SR are set to 1. 8. Execution jumps to the start address of the interrupt exception handling routine (the sum of the value set in the vector base register (VBR) and H'0000 0600). In the exception handling routine, execution may branch with the INTEVT value used as its offset in order to identify the interrupt source. This enables execution to branch to the handling routine for the individual interrupt source. Notes: 1. When the INTMU bit in the CPU operating mode register (CPUOPM) is set to 1, the interrupt mask level (IMASK) in SR is automatically set to the level of the accepted interrupt. When the INTMU bit is cleared to 0, the IMASK value in SR is not affected by the accepted interrupt. 2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, wait for the time shown in table 9.8, and then clear the BL bit or execute an RTE instruction. 3. For some interrupt sources, the interrupt mask setting (INTMSK) for each interrupt source must be cleared by using INTMSKCLR.
Rev. 1.00 Oct. 01, 2007 Page 305 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Program execution state
Yes ICR0.MAI=1? No NMI input is low? No No Interrupt generated? Yes SR.BL = 0 or Sleep mode? No No ICR0.NMIB=1? No Yes Yes
Yes No NMI? Yes
NMI? Yes
Level 15 interrupt? Yes Yes
No
Level 14 interrupt? Yes SR. IMASK level is 14 or low No Yes
No
SR. IMASK level is 14 or low No Yes
Level 1 interrupt? Yes SR. IMASK level is 0? No
No
No CPUOPM.INTMU = 1? Yes Set SR. IMASK to accepted interrupt level
Set interrupt source code in INTEVT Save SR to SSR; save PC to SPC; save R15 to SGR Branch to exception handing routine
Figure 9.4 Interrupt Operation Flowchart
Rev. 1.00 Oct. 01, 2007 Page 306 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.5.2
Multiple Interrupts
When handling multiple interrupts, an interrupt handling routine should include the following procedures: 1. To identify the interrupt source, branch to a specific interrupt handling routine for the interrupt source by using the INTEVT code as an offset. 2. Clear the interrupt source in each specific interrupt handling routine. 3. Save SSR and SPC to the stack. 4. Clear the BL bit in SR. When the INTMU bit in CPUOPM is set to 1, the interrupt mask level (IMASK) in SR is automatically modified to the level of the accepted interrupt. When the INTMU bit in CPUOPM is cleared to 0, set the IMASK bit in SR by software to the accepted interrupt level. 5. Handle the interrupt as required. 6. Set the BL bit in SR to 1. 7. Restore SSR and SPC from memory. 8. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted if multiple interrupts occur after step 4. This reduces the interrupt response time for urgent processing. 9.5.3 Interrupt Masking by MAI Bit
Setting the MAI bit in ICR0 to 1 masks interrupts while the NMI signal is low regardless of the BL and IMASK bit settings in SR. * Normal operation or sleep mode All interrupts are masked while the NMI signal is low. Note that only NMI interrupts due to NMI signal input occur.
Rev. 1.00 Oct. 01, 2007 Page 307 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.6
Interrupt Response Time
Table 9.8 shows the interrupt response time, which is the interval from when an interrupt request occurs until the interrupt exception handling is started and the start instruction of the exception handling routine is fetched. Table 9.8 Interrupt Response Time
Number of States Peripheral Module
Other than GPIO/PCIC/ RTC GPIO/PCIC/ RTC
Item
Priority determination time Wait time until the CPU finishes the current sequence Interval from when interrupt exception handling begins (saving SR and PC) until a SHwy bus request is issued to fetch the start instruction of the exception handling routine Response Total time
NMI 5Bcyc + 2Pcyc
IRL 8Bcyc + 2Pcyc
IRQ 4Bcyc + 2Pcyc S-1 ( 0) x Icyc 11Icyc + 1Scyc
Remarks
5Pcyc
7Pcyc
(S + 10) Icyc + 1Scyc + 5Bcyc + 2Pcyc
(S + 10) Icyc + 1Scyc + 8Bcyc + 2Pcyc
(S + 10) Icyc + 1Scyc + 4Bcyc + 2Pcyc
(S + 10) Icyc + 1Scyc + 5Pcyc 32Icyc + SxIcyc*
(S + 10) Icyc + 1Scyc + 7Pcyc 40Icyc + SxIcyc*
When Icyc:Scyc: Bcyc:Pcyc = 4:2:1:1
Minimum 40Icyc
+ SxIcyc
52Icyc + SxIcyc
36Icyc + SxIcyc
[Legend] Icyc: Period for one CPU clock cycle Scyc: Period for one SHwy clock cycle Bcyc: Period for one bus clock cycle Pcyc: Period for one peripheral clock cycle (Pck0) S: Number of instruction execution states Note * In the case of Pcyc = Pck.
Rev. 1.00 Oct. 01, 2007 Page 308 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
9.7
9.7.1
Usage Notes
Example of Interrupt Handling Routine for Level-Encoded IRL and Level-Sensed IRQ
If an interrupt request is accepted when level-sensed IRQ or level-encoded IRL interrupt request is selected, the held request must be cleared in the interrupt handling routine. Figure 9.5 shows an example of clearing the interrupt request held in the detection circuit.
Start of level-encoded IRL or level-sensed IRQ interrupt handing
Interrupt handing
Clear the level-encoded IRL or level-sensed IRQ interrupt request source. Notify acceptance of the interrupt to external devices by using GPIO output or local bus space. Wait for the level-encoded IRL or level-sensed IRQ interrupt request to be cleared. An appropriate time is necessary for the interrupt request input to the IRQ/IRL pin to be cancelled and for the INTC to detect the cancellation (more than 8 bus clock cycles). Clear the interrupt request held in the detection circuit. Set the corresponding mask bit to 1 to clear the interrupt request held in the detection circuit.
1. Write to the GPIO register or local bus space. 2. Read the address to which writing has been made.
1. Set the corresponding bit in INTMSK0/INTMSK1. 2. Set the corresponding bit in INTMSKCLR0/INTMSKCLR1. 3. Read INTMSK0/INTMSK1.
End of level-encoded IRL or level-sensed IRQ interrupt handing
Figure 9.5 Example of Interrupt Handling Routine After the CPU accepts an interrupt request, acceptance of the request should be notified to the external devices and the request should be cancelled. For example, acceptance can be notified by outputting the accepted level and pin-related information via the GPIO (general I/O port) and writing the acceptance information to a specific address in the local bus space. Here, writing to the GPIO register or local bus space and reading from the location should be consecutively executed. When clearing the interrupt requests held in the detection circuit, adequate time is necessary for the CPU to detect the cancellation of the interrupt request. To secure the time, writing to
Rev. 1.00 Oct. 01, 2007 Page 309 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
INTMSK0/INTMSK1 and INTMSKCLR0/INTMSKCLR1 and reading from INTMSK0/INTMSK1 should be consecutively executed. 9.7.2 Notes on Setting IRQ7/IRL7 to IRQ0/IRL0 Pin Function
When switching the IRQ7/IRL7 to IRQ0/IRL0 pin function, it is possible that the INTC may hold an interrupt by mistake. Therefore, to prevent detecting unintentional interrupts, mask both all IRQ and IRL interrupts and then switch the IRQ7/IRL7 to IRQ0/IRL0 pin function. Table 9.9 Switching Sequence of IRQ7/IRL7 to IRQ0/IRL0 Pin Function
PROCEDURE Write 1 to all bits in INTMSK0 and INTMSK1 Write 010 to the PTSEL3[14:12] bits and the PTSEL3[2:0] bits in PSEL3 of GPIO Write 00 to the PL3MD[1:0], PL1MD[1:0], PL0MD[1:0] bits in PLCR 3 4 IRQ7/IRL7 to IRQ0/IRL0 pins setting to IRL or IRQ interrupt request input IRL and IRQ interrupt detection start Set the IRLM[1:0] bit in ICR0 Write 1 to the corresponding bit in INTMSKCLR0 and INTMSKCLR1
Sequence ITEM 1 2 IRL interrupt request and IRQ interrupt request masking IRQ7/IRL7 to IRQ4/IRL4 pins setting to IRL7 to IRL4 interrupt request input
9.7.3
To Clear IRQ and IRL Interrupt Requests
Clearing procedure of the interrupt held in the INTC is as follows * To clear IRL interrupt requests To clear an IRL interrupt request from the IRQ3/IRL3 to IRQ0/IRL0 pins, write 1 to the IM10 bit in INTMSK1, and to clear an IRL interrupt request from the IRQ7/IRL7 to IRQ4/IRL4 pins, write 1 to the IM11 bit in INTMSK1. The IRL interrupt requests detected by the INTC is not cleared even if each of the corresponding interrupt level is masked by setting INTMSK2. * To clear IRQ level-sense interrupt requests To clear an IRQ level-sense interrupt request from the IRQ7/IRL7 to IRQ0/IRL0 pins, write 1 to the corresponding mask bit (IM07 to IM00) in INTMSK0. The IRQ interrupt requests detected by the INTC is not cleared even if 0 is written to a corresponding bit in INTPRI. The IRQ interrupt sources detected by the INTC (be cleared)
Rev. 1.00 Oct. 01, 2007 Page 310 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
* To clear IRQ edge-detection interrupt requests To clear an IRQ edge-detection interrupt request from the IRQ7/IRL7 to IRQ0/IRL0 pins, write 0 after reading 1 in the corresponding IRn (n = 0 to 7) bit in INTREQ. The IRQ interrupt requests detected by the INTC is not cleared even if 1 is written to a corresponding bit in INTMSK0.
Rev. 1.00 Oct. 01, 2007 Page 311 of 1956 REJ09B0256-0100
Section 9 Interrupt Controller (INTC)
Rev. 1.00 Oct. 01, 2007 Page 312 of 1956 REJ09B0256-0100
Section 10 SuperHyway Bus Bridge (SBR)
Section 10 SuperHyway Bus Bridge (SBR)
The SuperHyway bus bridge (SBR) performs access protocol conversion between the SuperHyway (Shwy) bus and the SuperHyway bridge bus. At the same time, it also arbitrates between the accesses to the SuperHyway bus by the three peripheral modules (SECURITY, GETHER, and USBH) connected to the SuperHyway bridge bus.
10.1
Features
* SuperHyway bus interface Performs access protocol conversion between the SuperHyway bus and the SuperHyway bridge bus. * Arbitration The arbiter arbitrates between the accesses to the SuperHyway bus by the SECURITY, GETHER, and USBH modules connected to the SuperHyway bridge bus. Priority can be set for the individual modules or ports. Figure 10.1 shows a block diagram of the SBR.
SuperHyway (SHwy) bus
SHwy bus interface controller
Arbitor
SHwy bus bridge (SBR)
SuperHyway bridge bus
SECURITY
GETHER0
GETHER1
USBH
Figure 10.1 SBR Block Diagram
LMMS4AA0_010620040500
Rev. 1.00 Oct. 01, 2007 Page 313 of 1956 REJ09B0256-0100
Section 10 SuperHyway Bus Bridge (SBR)
10.2
Register Descriptions
Table 10.1 shows the SBR register configuration. Table 10.2 shows the register state in each operating mode. Table 10.1 Register Configuration
Register Name Bus arbitration priority level setting register SuperHyway bus priority control register Abbreviation R/W SBRIVCLV PRPRICR R/W R/W Area P4 Address* H'FF40 0010 H'FE60 0018 Area 7 Address* H'1F40 0010 H'1F60 0018 Access Size 32 32
Note: The area P4 address is the address when the P4 area of a virtual address space is used. The area 7 address is the address when the register is accessed through area 7 of a physical address space by using the TLB.
Table 10.2 Register State in Each Operating Mode
Register Name Bus arbitration priority level setting register SuperHyway bus priority control register Power-On Abbreviation Reset SBRIVCLV PRPRICR Manual Reset Sleep Standby Retained Retained
H'0000 0000 H'0000 0000 Retained H'0000 0001 H'0000 0001 Retained
Rev. 1.00 Oct. 01, 2007 Page 314 of 1956 REJ09B0256-0100
Section 10 SuperHyway Bus Bridge (SBR)
10.2.1
Bus Arbitration Priority Level Setting Register (SBRIVCLV)
SBRIVCLV sets the priority levels used when SuperHyway bus access requests from the SECURITY, GETHER, and USBH coincide.
Bit: 31
--
30
-- 0 R
29
-- 0 R
28
-- 0 R
27
-- 0 R
26
-- 0 R
25
-- 0 R
24
-- 0 R
23
-- 0 R
22
-- 0 R
21
-- 0 R
20
-- 0 R
19
-- 0 R
18
-- 0 R
17
-- 0 R
16
-- 0 R 0
USBH LV
Initial value: R/W: Bit:
0 R
15
--
14
-- 0 R
13
-- 0 R
12
-- 0 R
11
-- 0 R
10
-- 0 R
9
-- 0 R
8
-- 0 R
7
-- 0 R
6
SEC LV
5
4
3
-- 0 R
2
-- 0 R
1
-- 0 R
GEC0 GEC1 LV LV
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 7
6
SECLV
0
R/W
SECURITY Access Priority Level 0: Level 3 1: Level 2
5
GEC0LV
0
R/W
GETHER0 Access Priority Level 0: Level 3 1: Level 2
4
GEC1LV
0
R/W
GETHER1 Access Priority Level 0: Level 3 1: Level 2
3 to 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
USBHLV
0
R/W
USBH Access Priority Level 0: Level 3 1: Level 2
Rev. 1.00 Oct. 01, 2007 Page 315 of 1956 REJ09B0256-0100
Section 10 SuperHyway Bus Bridge (SBR)
10.2.2
SuperHyway Bus Priority Control Resister (PRPRICR)
PRPRICR controls the SuperHyway bus access priority given to the CPU and the other function modules.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit:
-
0 R 14
-
0 R 13
-
0 R 12
-
0 R 11
-
0 R 10
-
0 R 9
-
0 R 8
-
0 R 7
-
0 R 6
-
0 R 5
-
0 R 4
-
0 R 3
-
0 R 2
-
0 R 1
-
0 R 0
SBAPR
0 R 15
-
Initial value: R/W:
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
0 R
1 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 1
0
SBAPR
1
R/W
SuperHyway Bus Access Priority Sets whether to give the CPU priority over the other function modules when accessing the SuperHyway bus. 0: The CPU is given the same priority as the other function modules. 1: The CPU is given priority over the other function modules. Note: With this bit set to 1, when both of the data area accessed by the CPU and the data area accessed by the other function modules are placed in the areas for slow accesses, the CPU may be given priority, thus disabling accesses by the other function modules. To avoid this, place the data area accessed by the CPU or the other function modules in the DDR-SDRAM area, or set this bit to 0.
Rev. 1.00 Oct. 01, 2007 Page 316 of 1956 REJ09B0256-0100
Section 10 SuperHyway Bus Bridge (SBR)
10.3
10.3.1
Operation
SuperHyway Bus Interface
The SuperHyway bus bridge (SBR) performs access protocol conversion between the SuperHyway bus and the SuperHyway bridge bus. 10.3.2 Bus Arbitration
The SBR performs arbitration for the access requests from the four ports of the three modules (SECURITY, GETHER, and USBH) connected to the SuperHyway bridge bus. Figure 10.2 shows the concept of arbitration by the SBR.
Level 1
Level 2
Level 2 (5-round robin) GETHER1 GETHER0 USBH
USBH Write
USBH Read
Level 3
SECURITY Level 3 (4-round robin)
GETHER1
USBH
USBH Read
GETHER0
SECURITY
USBH Write
Figure 10.2 Bus Arbitration by the SBR The SBR performs arbitration for three groups level 1, level 2, and level 3. At level 3, roundrobin arbitration is performed for a total of four ports of three modules; at level 2, round-robin arbitration is performed for four ports of three modules plus the result of arbitration at level 3. Since there are no modules to compete with at level 1, the access from the module that won the arbitration at level 2 is immediately executed.
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Section 10 SuperHyway Bus Bridge (SBR)
The priority level of access requests from SECURITY, GETHER1, GETHER0, and USBH can be set to level 2 or level 3 through the SBRIVCLV register. Note that, in the USBH module, roundrobin arbitration is first performed between read and write requests, then inter-module arbitration is performed using the result.
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Section 11 Local Bus State Controller (LBSC)
Section 11 Local Bus State Controller (LBSC)
The local bus state controller (LBSC) divides the external memory space and outputs control signals corresponding to the specifications of various types of memory and bus interfaces. The LBSC enables the connection of SRAM or ROM, etc., to this LSI. It also supports the PCMCIA interface protocol, which is used to implement simplified system design and high-speed data transfers in a compact system.
11.1
Features
The LBSC has the following features. * Controls six areas, areas 0 to 2 and 4 to 6, of an external memory space divided into seven areas. Maximum 64 Mbytes for each of areas 0 to 2 and 4 to 6 Bus width of each area can be controlled through register settings (except area 0, which is controlled by the external pin setting) Wait-cycle insertion by the RDY pin Wait-cycle insertion can be controlled by a program Types of memory are specifiable for connection to each area Output of the control signals of memory to each area Automatic wait cycle insertion to prevent data bus collisions on consecutive memory accesses to different areas, or a read access followed by a write access to the same area Insertion of cycles to ensure the setup time and hold time to the write strobe on a write cycle enables connection to low-speed memory * SRAM interface Wait-cycle insertion can be controlled by a program Insertion of the wait cycle through the RDY pin Connectable areas : 0 to 2 and 4 to 6 Settable bus widths: 32, 16, and 8 bits * Burst ROM interface Wait-cycle insertion can be controlled by a program Burst length specified by the register Connectable areas: 0 to 2 and 4 to 6 Settable bus widths: 32, 16, and 8 bits
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Section 11 Local Bus State Controller (LBSC)
* MPX interface Address/data multiplexing Connectable areas: 0 to 2 and 4 to 6 Settable bus width: 32 bits * Byte control SRAM interface SRAM interface with byte control Connectable areas: 1 and 4 Settable bus widths: 32 and 16 bits * PCMCIA interface Wait-cycle insertion can be controlled by a program Bus sizing function for I/O bus width Little endian Connectable areas: 5 and 6 Settable bus widths: 16 and 8 bits
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Section 11 Local Bus State Controller (LBSC)
Figure 11.1 shows a block diagram of the LBSC.
Bus interface RDY Wait control unit Area control unit
CSnWCR
A0 to A25 BS RD RD/FRAME RDWR WE3/IOWR WE2/IORD WE1/WE WE0/PCC_REG BACK D0 to D31 IOIS16 BREQ MD3 to MD5
Memory control unit
BCR
CSnPCR
LBSC [Legned] BCR CSnBCR CSnPCR CSnWCR
Bus Control Register Bus Control Register (n = 0 to 2, 4 to 6) CSn Bus Control Register (n = 5 to 6) CSn Wat Control Register (n = 0 to 2, 4 to 6)
Figure 11.1 LBSC Block Diagram
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Module bus
CS0 to CS2 CS4 to CS6 CE2A, CE2B CE1A, CE1B
CSnBCR
SuperHyway bus
Section 11 Local Bus State Controller (LBSC)
11.2
Input/Output Pins
Table 11.1 shows the LBSC pin configuration. Table 11.1 Pin Configuration
Pin Name A25 to A0 D31 to D0 BS Function Address Bus Data Bus I/O Output I/O Description Address output Data input/output Signal that indicates the start of a bus cycle. Asserted once for a burst transfer when setting MPX interface. Asserted each data cycle for a burst transfer when setting other interfaces. CS6 to CS4, CS2 to CS0 RDWR Chip Select 6 to Output 4 and 2 to 0 Read/Write Output Chip select signal that indicates the area being accessed. CS5 and CS6 can also be used as CE1A to CE1B of PCMCIA. Data bus input/output direction designation signal. Also used as PCMCIA interface write designation signal. Strobe signal indicating a read cycle. FRAME signal when setting MPX interface. When setting SRAM interface: write strobe signal for D7 to D0 When setting PCMCIA interface: REG signal WE1/WE Data Enable 1 Output When setting SRAM interface: write strobe signal for D15 to D8 When setting PCMCIA interface: Write strobe signal WE2/IORD Data Enable 2 Output When setting SRAM interface: write strobe signal for D23 to D16 When setting PCMCIA interface: IORD signal WE3/IOWR Data Enable 3 Output When setting SRAM interface: write strobe signal for D31 to D24 When setting PCMCIA interface: IOWR signal RDY IOIS16 Ready 16-Bit I/O Input Input Wait cycle request signal 16-bit I/O signal when setting PCMCIA interface. Valid only in little endian mode
Bus Cycle Start Output
RD/FRAME WE0/PCC_REG
Read/Cycle Frame Data Enable 0
Output Output
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Section 11 Local Bus State Controller (LBSC)
Pin Name BREQ BACK CE2A*1, 1 CE2B* CE1A*1, 1 CE1B* MD3, MD4 MD5 DACK0*2
Function Bus Release Request Bus Request Acknowledge PCMCIA Card Select PCMCIA Card Select Area 0 Bus Width Endian Switchover DMAC0 Acknowledge Signal DMAC1 Acknowledge Signal DMAC2 Acknowledge Signal DMAC3 Acknowledge Signal DMAC0 Transfer End Signal DMAC1 Transfer End Signal DMAC2 Transfer End Signal DMAC3 Transfer End Signal
I/O Input Output Output
Description Bus release request signal Bus release acknowledge signal When setting PCMCIA, corresponds to PCMCIA card select signal D15 to D8. Valid only in little endian mode When setting PCMCIA, corresponds to PCMCIA card select signal D7 to D0. Signal setting area 0 bus width and MPX interface at power-on reset Endian setting at a power-on reset Data acknowledge of DMAC channel 0
Output Input Input Output
DACK1*2
Output
Data acknowledge of DMAC channel 1
DACK2*2
Output
Data acknowledge of DMAC channel 2
DACK3*2
Output
Data acknowledge of DMAC channel 3
TEND0*2
Output
Transfer end of DMAC channel 0
TEND1*2
Output
Transfer end of DMAC channel 1
TEND2*2
Output
Transfer end of DMAC channel 2
TEND3*2
Output
Transfer end of DMAC channel 3
Notes: 1. When bits TYPE [2:0] in the CS5 bus control register (CS5BCR) are set to B'100, CE2A and CE1A act as PCMCIA output pins, and bits TYPE [2:0] in the CS6 bus control register (CS6BCR) are set to b'100, CE2B and CE1B act as PCMCIA output pins.
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Section 11 Local Bus State Controller (LBSC)
2. Can be selectable the polarity (initial state is low active). For details, see section 14, Direct Memory Access Controller (DMAC).
11.3
11.3.1
Area Overview
Space Divisions
The architecture of this LSI provides a 32-bit virtual address space. The virtual address space is divided into five areas according to the upper address value. The external memory space indicated by the remaining 29 address bits is divided into eight areas. The virtual address can be allocated to any external address using the address translation function of the MMU. For details, see section 6, Memory Management Unit (MMU). This section describes the area division of the external address space. With this LSI, various types of memory or PC cards can be connected to each of the seven areas in the external address space as shown in table 11.2, and accordingly output the chip select signals (CS0 to CS2, CS4, CS5/CE1A, CS6/CE1B, CE2A, and CE2B). Area 3 is used for DDR-SDRAM. CS0 to CS2 are asserted when accessing area 0 to 2, and CS4 to CS6 when accessing area 4 to 6. When the PCMCIA interface is selected for area 5 or 6, CE2A or CE2B is asserted along with CS5/CE1A or CS6/CE1B for the bytes to be accessed.
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Section 11 Local Bus State Controller (LBSC)
256 H'0000 0000
Area 0 (CS0) Area 1 (CS1)
H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 H'1FFF FFFF
P0 and U0 areas
P0 and U0 areas
Area 2 (CS2) Area 3 Area 4 (CS4)
H'8000 0000 P1 area H'A000 0000 H'C000 0000 H'E000 0000 H'E400 0000 H'FFFF FFFF P2 area P3 area
Store queue area
Area 5 (CS5)
P1 area P2 area P3 area
Store queue area
Area 6 (CS6) Area7 (reserved area)
P4 area Physical address space (MMU off)
P4 area
Virtual address space (MMU on)
External memory space
Notes: 1. When the MMu is off (MMUCR.AT = 0), the top 3 bits of the 32-bit address are ignored, and memory is mapped onto a fixed 29-bit external address. 2. When the MMU is on (MMUCR.AT = 1), the P0, U0, P3, and store queue areas can be mapped onto any extrnal space using theTLB. For detalis, see section 6, Memory Management Unit (MMU).
Figure 11.2 Correspondence between Virtual Address Space and External Memory Space Table 11.2 LBSC External Memory Space Map
Area 0 External addresses H'0000 0000 to H'03FF FFFF Size 64 Mbytes Specifiable Connectable Memory Bus Width SRAM Burst ROM MPX 1 H'0400 0000 to H'07FF FFFF 64 Mbytes SRAM Burst ROM MPX Byte control SRAM 8, 16, 32*1 8, 16, 32* 32*1 8, 16, 32*2 8, 16, 32* 32*2 16, 32*
2 2 1
Access Size*7 8/16/32 bits and 32 bytes
8/16/32 bits and 32 bytes
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Section 11 Local Bus State Controller (LBSC)
Area 2
External addresses H'0800 0000 to H'0BFF FFFF
Size 64 Mbytes
Specifiable Connectable Memory Bus Width SRAM Burst ROM MPX (DDR-SDRAM* )
4
Access Size*7 8/16/32 bits and 32 bytes
8, 16, 32*2 8, 16, 32*2 32*2 32 32 8, 16, 32*2 8, 16, 32* 32*2 16, 32*2 32 32 8, 16, 32*2 8, 16, 32* 32*2 8, 16*2*5
4 2 2
3* 4
3
H'0C00 0000 to H'0FFF FFFF H'1000 0000 to H'13FF FFFF
64 Mbytes 64 Mbytes
(DDR-SDRAM) SRAM Burst ROM MPX Byte control SRAM (DDR-SDRAM*4) (PCI* )
4
8/16/32 bits and 32 bytes 8/16/32 bits and 32 bytes
5
H'1400 0000 to H'17FF FFFF
64 Mbytes
SRAM Burst ROM MPX PCMCIA (DDR-SDRAM* )
8/16/32 bits and 32 bytes
32 8, 16, 32*2 8, 16, 32* 32*2 8, 16* *
2 5 2
6
H'1800 0000 to H'1BFF FFFF
64 Mbytes
SRAM Burst ROM MPX PCMCIA
8/16/32 bits and 32 bytes
7*6
H'1C00 0000 to H'1FFF FFFF
64 Mbytes
--
Notes: 1. The memory bus width is specified by external pins. 2. The memory bus width is specified by the register. 3. Area 3 is used specifically for the DDR-SDRAM. For details, see section 12, DDRSDRAM Interface (DDRIF). 4. These areas can be used for the DDR-SDRAM or PCI by setting MMSELR. For details, see section 12, DDR-SDRAM Interface (DDRIF) or see section 13, PCI Controller (PCIC). 5. With the PCMCIA interface, the bus width is either 8 bits or 16 bits. 6. If a reserved area is accessed, operation cannot be guaranteed. 7. If 8 or 16 bytes access transfer by another LSI internal bus master module is being executed, the LBSC is executing two or four times 32-bit access individually.
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Section 11 Local Bus State Controller (LBSC)
Area 0: H'00000000
SRAM/burst ROM/MPX
Area 0: H'04000000
SRAM/burst ROM/MPX/byte control SRAM
Area 0: H'08000000
SRAM/burst ROM/MPX/DDR-SDRAM
Area 0: H'0C000000
DDR-SDRAM
Area 0: H'10000000
SRAM/burst ROM/MPX/byte control SRAM/ DDR-SDRAM/PCI SRAM/burst ROM/MPX/PCMCIA /DDR-SDRAM SRAM/vurst ROM/MPX/PCMCIA The PCMCIA interface is for memory and I/O card use.
Area 0: H'14000000
Area 0: H'18000000
Figure 11.3 External Memory Space Allocation
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Section 11 Local Bus State Controller (LBSC)
11.3.2
Memory Bus Width
The memory bus width of the LBSC can be set independently for each area. For area 0, a bus width of 8, 16, or 32 bits is set according to the external pin settings at a power-on reset by the PRESET pin. The correspondence between the external pins (MD4 and MD3) and the bus width at a power-on reset is shown in table 11.3. Table 11.3 Setting of bus width for area 0
MD4 0 0 1 1 MD3 0 1 0 1 Bus Width 32 bits (MPX interface) 8 bits 16 bits 32 bits
When either the SRAM or ROM interface is used in areas 1 to 2 and 4 to 6, a bus width of 8, 16, or 32 bits can be selected through the CSn bus control register (CSnBCR). When the burst ROM interface is used, a bus width of 8, 16, or 32 bits can be selected. When the byte-control SRAM interface is used, a bus width of 16 or 32 bits can be selected. When the MPX interface is used, a bus width of 32 bits should be selected. When using the PCMCIA interface, a bus width of 8 or 16 bits should be selected. For details, see section 11.5.5, PCMCIA Interface. For details, see section 11.4.3, CSn Bus Control Register (CSnBCR). The bus width of the DDR-SDRAM and the PCI interfaces is 32 bits. For details, see section 12, DDR-SDRAM Interface (DDRIF), and section 13, PCI Controller (PCIC). The addresses of area 7 (H'1C00 0000 to H'1FFF FFFF) are reserved and must not be used.
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Section 11 Local Bus State Controller (LBSC)
11.3.3
Data Alignment
This LSI supports big endian and little endian as data alignment. Data alignment is determined by the level of the external pin (MD5) at a power-on reset. Table 11.4 Correspondence between External Pin (MD5) and Endian
MD5 Low High Data Alignment Big endian Little endian
11.3.4
PCMCIA Support
This LSI supports the PCMCIA interface specifications for areas 5 and 6 in the external memory space. The IC memory card interface and I/O card interface prescribed in JEIDA specifications version 4.2 (PCMCIA2.1) are supported. Both the IC memory card interface and the I/O card interface are supported in areas 5 and 6 in the external memory space. The PCMCIA interface is only supported in little endian mode. Table 11.5 PCMCIA Interface Features
Item Access Data bus Memory type Common memory capacity Attribute memory capacity Others Features Random access 8/16 bits Masked ROM, OTPROM, EPROM, flash memory, SRAM Maximum 64 Mbytes Maximum 64 Mbytes Dynamic bus sizing for I/O bus width
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Section 11 Local Bus State Controller (LBSC)
Table 11.6 PCMCIA Support Interface
IC Memory Card Interface Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Signal Name*1 GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE READY VCC VPP1 I/O I/O I/O I/O I/O I I I I I I I I I O I/O*1 Function Ground Data Data Data Data Data Card enable Address Output enable Address Address Address Address Address Write enable Ready Signal Name*1 GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE IREQ I/O I/O I/O I/O I/O I I I I I I I I I O I/O Card Interface I/O*1 Function Ground Data Data Data Data Data Card enable Address Output enable Address Address Address Address Address Write enable Interrupt request Operation power supply Programming/ peripheral power supply I I I I I I I I I I I Address Address Address Address Address Address Address Address Address Address Address Corresponding Pin of this LSI D3 D4 D5 D6 D7 CS5 or CS6 A10 RD A11 A9 A8 A13 A14 WE1 Sensed on port
Operation power VCC supply Programming power supply I I I I I I I I I I I Address Address Address Address Address Address Address Address Address Address Address VPP1
19 20 21 22 23 24 25 26 27 28 29
A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0
A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0
A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0
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Section 11 Local Bus State Controller (LBSC)
IC Memory Card Interface Pin 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Signal Name*1 D0 D1 D2 WP GND GND CD1 D11 D12 D13 D14 D15 CE2 VS1 RSRVD RSRVD A17 A18 A19 A20 A21 VCC VPP2 I I I I I O I/O I/O I/O I/O I/O I I I/O*1 Function I/O I/O I/O O Data Data Data Write protect Ground Ground Card detection Data Data Data Data Data Card enable Reserved Reserved Address Address Address Address Address Power supply Programming power supply I I I I I O Address Address Address Address Reserved Reset Wait request Signal Name*1 D0 D1 D2 IOIS16 GND GND CD1 D11 D12 D13 D14 D15 CE2 IORD IOWR A17 A18 A19 A20 A21 VCC VPP2
I/O Card Interface I/O*1 Function I/O I/O I/O O Data Data Data 16-bit I/O port Ground Ground O I/O I/O I/O I/O I/O I I I I I I I I I Card detection Data Data Data Data Data Card enable Refresh request I/O read I/O write Address Address Address Address Address Power supply Programming/ peripheral power supply I I I I I O Address Address Address Address Reserved Reset Wait request Corresponding Pin of this LSI D0 D1 D2 IOIS16 Sensed on port D11 D12 D13 D14 D15 CE2A or CE2B Output from port IORD IOWR A17 A18 A19 A20 A21
Refresh request VS1
53 54 55 56 57 58 59
A22 A23 A24 A25 RSRVD RESET WAIT
A22 A23 A24 A25 RSRVD RESET WAIT
A22 A23 A24 A25 Output from port RDY*2
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Section 11 Local Bus State Controller (LBSC)
IC Memory Card Interface Pin 60 61 Signal Name*1 RSRVD REG I I/O*1 Function Reserved Attribute memory space select Battery voltage detection Battery voltage detection Data Data Data Card detection Ground Signal Name*1 INPACK REG
I/O Card Interface I/O*1 Function O I Attribute memory space select Corresponding Pin of this LSI REG
Input acknowledge
62 63 64 65 66 67 68
BVD2 BVD1 D8 D9 D10 CD2 GND
O O I/O I/O I/O O
SPKR
O
Digital voice signal Sensed on port Card status change Data Data Data Card detection Ground Sensed on port D8 D9 D10 Sensed on port
STSCHG O D8 D9 D10 CD2 GND I/O I/O I/O O
Notes: 1. I/O means input/output on the side of the PCMCIA card. The polarity of the PCMCIA card interface means that on the side of the card, while the polarity of the corresponding pin of this LSI means that on the side of this LSI. 2. Check the polarity.
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Section 11 Local Bus State Controller (LBSC)
11.4
Register Descriptions
The LBSC has 16 registers as shown in table 11.7 and 11.8. The following registers control memory interfaces, wait cycles, etc. Table 11.7 Register Configuration
Register Name Memory Address Map Select Register Bus Control Register CS0 Bus Control Register CS1 Bus Control Register CS2 Bus Control Register CS4 Bus Control Register CS5 Bus Control Register CS6 Bus Control Register CS0 Wait Control Register CS1 Wait Control Register CS2 Wait Control Register CS4 Wait Control Register CS5 Wait Control Register CS6 Wait Control Register CS5 PCMCIA Control Register CS6 PCMCIA Control Register Abbrev. MMSELR BCR CS0BCR CS1BCR CS2BCR CS4BCR CS5BCR CS6BCR CS0WCR CS1WCR CS2WCR CS4WCR CS5WCR CS6WCR CS5PCR CS6PCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 0000 H'x000 0000 H'7777 7770 H'7777 7770 H'7777 7770 H'7777 7770 H'7777 7770 H'7777 7770 H'7777 770F H'7777 770F H'7777 770F H'7777 770F H'7777 770F H'7777 770F H'7700 0000 H'7700 0000 P4 Address H'FE60 0020 H'FF80 1000 H'FF80 2000 H'FF80 2010 H'FF80 2020 H'FF80 2040 H'FF80 2050 H'FF80 2060 H'FF80 2008 H'FF80 2018 H'FF80 2028 H'FF80 2048 H'FF80 2058 H'FF80 2068 H'FF80 2070 H'FF80 2080 Area 7 Address H'1E60 0020 H'1F80 1000 H'1F80 2000 H'1F80 2010 H'1F80 2020 H'1F80 2040 H'1F80 2050 H'1F80 2060 H'1F80 2008 H'1F80 2018 H'1F80 2028 H'1F80 2048 H'1F80 2058 H'1F80 2068 H'1F80 2070 H'1F80 2080 Access Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Table 11.8 Register State in Each Operating Made.
Register Name Abbreviation Power-On Reset H'0000 0000 H'x000 0000 H'7777 7770 H'7777 7770 Manual Reset H'0000 0000 H'x000 0000 H'7777 7770 H'7777 7770 Sleep Retained Retained Retained Retained Standby Retained Retained Retained Retained
Memory Address Map Select Register MMSELR Bus Control Register CS0 Bus Control Register CS1 Bus Control Register BCR CS0BCR CS1BCR
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Section 11 Local Bus State Controller (LBSC)
Register Name CS2 Bus Control Register CS4 Bus Control Register CS5 Bus Control Register CS6 Bus Control Register CS0 Wait Control Register CS1 Wait Control Register CS2 Wait Control Register CS4 Wait Control Register CS5 Wait Control Register CS6 Wait Control Register CS5 PCMCIA Control Register CS6 PCMCIA Control Register
Abbreviation CS2BCR CS4BCR CS5BCR CS6BCR CS0WCR CS1WCR CS2WCR CS4WCR CS5WCR CS6WCR CS5PCR CS6PCR
Power-On Reset H'7777 7770 H'7777 7770 H'7777 7770 H'7777 7770 H'7777 770F H'7777 770F H'7777 770F H'7777 770F H'7777 770F H'7777 770F H'7700 0000 H'7700 0000
Manual Reset H'7777 7770 H'7777 7770 H'7777 7770 H'7777 7770 H'7777 770F H'7777 770F H'7777 770F H'7777 770F H'7777 770F H'7777 770F H'7700 0000 H'7700 0000
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
11.4.1
Memory Address Map Select Register (MMSELR)
The memory address map select register (MMSELR) is a 32-bit register that selects memory address maps for areas 2 to 5. This register should be accessed at the address H'FE60 0020 in longwords. Writing is accepted only when the upper 16-bit data is H'A5A5 to prevent unintentional writing. The upper 29 bits are always read as 0. This register is initialized by a power-on reset or a manual reset.
Bit:
-
31
30
-
29
-
28
-
27
-
26
-
25
-
24
-
-
23
22
-
-
21
20
-
19
-
18
-
17
-
16
-
Initial value: R/W: Bit:
0 R/W 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
-
Initial value: R/W:
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
AREASEL 0 R/W 0 R/W 0 R/W
0 R
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Section 11 Local Bus State Controller (LBSC)
Bit
Bit Name
Initial Value All 0
R/W R/W
Description Reserved Set these bits to H'A5A5 only when writing to AREASEL bits in this register. These bits are always read as 0.
31 to 16
15 to 3
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
AREASEL
000
R/W
DDRIF/PCIC Memory Space Select
000: Sets area 3 (H'0C00 0000 to H'0FFF FFFF) as the DDRIF space and other areas as the LBSC space 001: Sets area 3 (H'0C00 0000 to H'0FFF FFFF) as the DDRIF space, area 4 (H'1000 0000 to H'13FF FFFF) as the PCI memory space, and other areas as the LBSC space 010: Sets areas 2 and 3 (H'0800 0000 to H'0FFF FFFF) as the DDRIF space and other areas as the LBSC space 011: Sets areas 2 and 3 (H'0800 0000 to H'0FFF FFFF) as the DDRIF space, area 4 (H'1000 0000 to H'13FF FFFF) as PCI memory space, and other areas as the LBSC space 100: Sets areas 2 to 5 (H'0800 0000 to H'17FF FFFF) as the DDRIF space 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
The MMSELR must be written by the CPU. Writing to MMSELR, DMAC and PCIC module should be set not to access this register, and all processing in execution should be finished, for example execute SYNCO instruction preceding MOV instruction, and then modify MMSELR. And execute twice MOV instruction of read out MMSELR (dummy read) and SYNCO instruction in succession immediately after MOV instruction of write to MMSELR.
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Section 11 Local Bus State Controller (LBSC)
Example:
----------------------------------------------------------------------MOV.L MOV.L SYNCO MOV.L MOV.L MOV.L SYNCO ----------------------------------------------------------------------R1, @R0 @R0, R2 @R0, R2 #H'FE600020, R0 #MMSELR_DATA, R1 ; ; MMSELR_DATA=Writing value of MMSELR ; (upper word=H'A5A5)
; Writing to MMSELR
Modify executing instruction of MMSELR should allocate non-cacheable P2 area and the address that should not be affected by address map change. Write to MMSELR before enable Instruction cache, Operand cache, and MMU address translation and after this never write again until execute power-on reset or manual reset. 11.4.2 Bus Control Register (BCR)
The bus control register (BCR) is a 32-bit readable/writable register that specifies the function and bus cycle status for each area. It is initialized to H'0000 0000 in big-endian mode or H'8000 0000 in little-endian mode by a power-on reset or a mammal reset.
Bit:
31
END IAN
30
29
28
27
26 DPUP 0 R/W 10
25
24 OPUP 0 R/W 8
23
22
21
20
19
18
17
BREQ EN
16
DMA BST
-
0 R 14
HIZ CNT
-
0 R 13
-
0 R 12
-
0 R 11
-
0 R 9
DACKBST[3:0] 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4
-
0 R 3 ASYNC[6:0]
-
0 R 2
Initial value: R/W: Bit:
0/1* R/W 15
0 R/W 1
0 R/W 0
-
Initial value: R/W:
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R 0 R/W 0 R/W
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Rev. 1.00 Oct. 01, 2007 Page 336 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 31
Bit Name ENDIAN
Initial Value
R/W
Description Endian Flag The value of the external pin (MD5) designating the endian mode is sampled at a power-on reset by the PRESET pin. This bit determines the endian mode of all spaces. 0: Indicates that the external pin (MD5) designating the endian mode is low at a power-on reset and bigendian mode is specified for this LSI. 1: Indicates that the external pin (MD5) designating the endian mode is high at a power-on reset and littleendian mode is specified for this LSI.
Undefined R
30 to 27
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
26
DPUP
0
R/W
Data Pin Pull-Up Resistor Control Specifies the pull-up resistor state of the data pins (D31 to D0). This bit is initialized by a power-on reset. The pins are not pulled up when access is performed or when the bus is released, even if the pull-up resistor is on. Also, in standby mode, pins D31 to D16 are not pulled up regardless of the setting. 0: Cycles in which the pull-up resistors of the data pins (D31 to D0) are turned on are inserted before and after a memory access.* 1: Pull-up resistor is off for data pins (D31 to D0). Note: * We recommend that a pull-up resistor be externally connected to the data pins if it is required.
25
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 337 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 24
Bit Name OPUP
Initial Value 0
R/W R/W
Description Control Output Pin Pull-Up Resistor Control Specifies the pull-up resistor state (A25 to A0, BS, CS0 to CS2, CS4, CS5/CE1A, CS6/CE1B, RD, WEn, RDWR, CE2A, and CE2B) when the control output pins are high-impedance. This bit is initialized by a power-on reset. 0: Pull-up resistors are on for control output pins (A25 to A0, BS, CS0 to CS2, CS4, CS5/CE1A, CS6/CE1B, RD, WEn, RDWR, CE2A, and CE2B) 1: Pull-up resistors are off for control output pins (A25 to A0, BS, CS0 to CS2, CS4, CS5/CE1A, CS6/CE1B, RD, WEn, RDWR, CE2A, and CE2B) Note: In standby mode, the control output pins are pulled up, regardless of the bit setting.
23 to 20 DACKBST All 0 [3:0]
R/W
DACK Burst Select assert period of DACKn signals of DMA burst transfer mode during DMA transfer start to end. 0: DACKn signals does not keep assert from burst start to end 1: DACKn signals keep assert from burst start to end DACKBST[3]: DACK3 DACKBST[2]: DACK2 DACKBST[1]: DACK1 DACKBST[0]: DACK0
19, 18
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
17
BREQEN
0
R/W
BREQ Enable Indicates whether or not an external bus request can be accepted. This bit is initialized to the state where an external bus request is not accepted at a power-on reset. 0: An external bus request is not accepted 1: An external bus request is accepted
Rev. 1.00 Oct. 01, 2007 Page 338 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 16
Bit Name DMABST
Initial Value 0
R/W R/W
Description DMAC Burst Mode Transfer Priority Setting Specifies the priority of burst mode transfers by the DMAC. When this bit is cleared to 0, the priority is as follows: bus release, DMAC, CPU. When this bit is set to 1, the bus release is not performed until the completion of the DMAC burst transfer. This bit is initialized at a power-on reset. 0: DMAC burst mode transfer priority setting off 1: DMAC burst mode transfer priority setting on
15
0
R
Reserved This bit is always read as 0. The write value should always be 0.
14
HIZCNT
0
R/W
High Impedance (Hi-Z) Control Specifies the state of signals WEn and RD/FRAME during the software standby mode and the bus-released state. 0: Signals of WEn and RD/FRAME are high-impedance during the bus-released state 1: Signals of WEn and RD/FRAME are output during the bus-released state
13 to 7
0
R
Reserved These bits are always read as 0. The write value should always be 0.
6 to 0
ASYNC[6:0] All 0
R/W
Asynchronous Input Enable asynchronous input to the corresponding pins. 0: Input signals to the corresponding pins are synchronized with CLKOUT 1: Input signals to the corresponding pins are asynchronous to CLKOUT ASYNC[6]: DREQ3 ASYNC[5]: DREQ2 ASYNC[4]: DREQ1 ASYNC[3]: DREQ0 ASYNC[2]: IOIS16 ASYNC[1]: BREQ ASYNC[0]: RDY
Rev. 1.00 Oct. 01, 2007 Page 339 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
11.4.3
CSn Bus Control Register (CSnBCR)
CSnBCR is a 32-bit readable/writable register that specifies the bus width for area n (n = 0 to 2 and 4 to 6), numbers of wait, setup, and hold cycles to be inserted, burst length, and memory types. Some types of memory continue to drive the data bus immediately after the read signal is inactivated. Therefore, a data bus collision may occur when there is consecutive memory access to different areas or writing to a memory immediately after reading. This LSI automatically inserts the number of idle cycles set by CSnBCR to prevent data bus collision. During idle cycles, corresponding signals CS0 to CS2, CS4, CS5/CE1A, CS6/CE1B, RD, WE, CE2A, CE2B, and BS are not asserted and RDWR is in the high state and the data is not driven. CSnBCR is initialized to H'7777 7770 by a power-on reset or a manual reset.
Bit: Initial value: R/W: Bit: Initial value: R/W:
31
30
29 IWW
28
27
26
25 IWRWD
24
23
22
21 IWRWS
20
19
18
17 IWRRD
16
0 R 15
1 R/W 14
1 R/W 13 IWRRS
1 R/W 12
0 R 11
1 R/W 10
1 R/W 9 SZ
1 R/W 8
0 R 7
RDSPL
1 R/W 6
1 R/W 5 BW
1 R/W 4
0 R 3 MPX
1 R/W 2
1 R/W 1 TYPE 0 R/W
1 R/W 0
BST 1 R/W 0 R/W
0 R
1 R/W
1 R/W
1 1 1 0 R/W R/W* R/W* R/W
1 R/W
1 R/W
1 0 0 R/W R/W* R/W
0 R/W
Rev. 1.00 Oct. 01, 2007 Page 340 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 31
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
30 to 28 IWW
111
R/W
Idle Cycles between Write-Read/Write-Write Specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed. The target cycles are write-read cycles and write-write cycles. For details, see section 11.5.8, Wait Cycles between Accesses. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 3 idle cycles inserted 100: 4 idle cycles inserted 101: 5 idle cycles inserted 110: 6 idle cycles inserted 111: 7 idle cycles inserted
27
0
R
Reserved This bit is always read as 0. The write value should always be 0.
26 to 24 IWRWD
111
R/W
Idle Cycles between Read-Write to Different Spaces Specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed. The target cycles are read-write cycles to different spaces. For details, see section 11.5.8, Wait Cycles between Accesses. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 3 idle cycles inserted 100: 4 idle cycles inserted 101: 5 idle cycles inserted 110: 6 idle cycles inserted 111: 7 idle cycles inserted
Rev. 1.00 Oct. 01, 2007 Page 341 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 23
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
22 to 20 IWRWS
111
R/W
Idle Cycles between Read-Write to Same Space Specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed. The target cycles are read-write cycles to the same space. For details, see section 11.5.8, Wait Cycles between Accesses. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 3 idle cycles inserted 100: 4 idle cycles inserted 101: 5 idle cycles inserted 110: 6 idle cycles inserted 111: 7 idle cycles inserted
19
0
R
Reserved This bit is always read as 0. The write value should always be 0.
18 to 16 IWRRD
111
R/W
Idle Cycles between Read-Read to Different Spaces Specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed. The target cycles are read-read cycles to different spaces. For details, see section 11.5.8, Wait Cycles between Accesses. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 3 idle cycles inserted 100: 4 idle cycles inserted 101: 5 idle cycles inserted 110: 6 idle cycles inserted 111: 7 idle cycles inserted
Rev. 1.00 Oct. 01, 2007 Page 342 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 15
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
14 to 12 IWRRS
111
R/W
Idle Cycles between Read-Read to Same Space Specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed. The target cycles are read-read cycles to the same space. For details, see section 11.5.8, Wait Cycles between Accesses. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 3 idle cycles inserted 100: 4 idle cycles inserted 101: 5 idle cycles inserted 110: 6 idle cycles inserted 111: 7 idle cycles inserted
11, 10
BST
01
R/W
Burst Length When a burst ROM interface is used, these bits specify the number of accesses in a burst. The MPX interface is not affected. 00: 4 consecutive accesses (Can be used with 8-, 16-, or 32-bit bus width) 01: 8 consecutive accesses (Can be used with 8-, 16-, or 32-bit bus width) 10: 16 consecutive accesses (Can be used with 8-, or 16-bit bus width) 11: 32 consecutive accesses (Can be used with 8-bit bus width)
Rev. 1.00 Oct. 01, 2007 Page 343 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 9, 8
Bit Name SZ
Initial Value 11
R/W R/W*
Description Bus Width Specify the bus width. In CS0BCR, the external pins (MD3 and MD4) are sampled at a power-on reset. Set to 11 for the MPX interface, and set to 10 or 11 for the byte control SRAM interface. 00: Reserved 01: 8 bits 10: 16 bits 11: 32 bits Note: * Bits SZ in CS0BCR are read-only. The SZ bits in CS0BCR are set to 11 when area 0 is set to MPX interface by the MD3 and MD4 pins.
7
RDSPL
0
R/W
RD Hold Cycle Specify the number of cycles to be inserted into the RD assertion period to ensure the data hold time to the read data sample timing. When set this bit to 1, specify the number of RD negation-CSn negation delay cycle to be 1 or more by setting the RDH bit in CSnWCR. And RD negation-CSn negation delay cycle is reduced 1 cycle to set this bit to 1 (Available only when the SRAM interface or byte control SRAM interface). 0: No hold cycle inserted 1: 1 hold cycle inserted
6 to 4
BW
111
R/W
Burst Pitch When the burst ROM interface is used, these bits specify the number of wait cycles to be inserted after the second data access in a burst transfer. 000: No idle cycle inserted, RDY signal disabled 001: 1 idle cycle inserted, RDY signal enabled 010: 2 idle cycles inserted, RDY signal enabled 011: 3 idle cycles inserted, RDY signal enabled 100: 4 idle cycles inserted, RDY signal enabled 101: 5 idle cycles inserted, RDY signal enabled 110: 6 idle cycles inserted, RDY signal enabled 111: 7 idle cycles inserted, RDY signal enabled
Rev. 1.00 Oct. 01, 2007 Page 344 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 3
Bit Name MPX
Initial Value 0
R/W R/W*
Description MPX Interface Setting Selects the type of MPX interface 0: SRAM/byte-control SRAM interface selected 1: MPX interface selected Note: * The MPX bit in CS0BCR is read-only.
2 to 0
TYPE
000
R/W
Memory Type Setting Specify the type of memory connected to the space. 000: SRAM (Initial value) 001: SRAM with byte selection*1 010: Burst ROM (burst at read/SRAM at write) 011: Reserved (Setting prohibited) 100: PCMCIA *2 101: Reserved (Setting prohibited) 110: Reserved (Setting prohibited) 111: Reserved (Setting prohibited) Note: 1. Setting possible only in CS1BCR and CS4BCR 2. Setting possible only in CS5BCR and CS6BCR
Rev. 1.00 Oct. 01, 2007 Page 345 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
11.4.4
CSn Wait Control Register (CSnWCR)
The CSn wait control register (CSnWCR) is a 32-bit readable/writable register that specifies the number of wait cycles to be inserted, the pitch of data access for burst memory accesses, and the number of cycles to be inserted for the address setup time to the read/write strobe assertion or for the data hold time from the write strobe negation. This allows direct connection of even low-speed memories without an external circuit. CSnBCR is initialized to H'7777 770F by a power-on reset or a manual reset.
Bit:
31
30
29 ADS
28
27
26
25 ADH
24
23
22
21 RDS
20
19
18
17 RDH
16
-
Initial value: R/W: Bit:
-
1 R/W 12 0 R 11 1 R/W 10
-
1 R/W 8 0 R 7 1 R/W 6
-
1 R/W 4 0 R 3 1 R/W 2
0 R 15
1 R/W 14
1 R/W 13 WTS
1 R/W 9 WTH
1 R/W 5 BSH
1 R/W 1
1 R/W 0
-
Initial value: R/W:
-
1 R/W 0 R/W 1 R/W
-
1 R/W 0 R 0 R/W
IW[3:0] 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W
0 R
1 R/W
1 R/W
1 R/W
0 R/W
Bit 31
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
30 to 28 ADS
111
R/W
Address Setup Cycle Specify the number of cycles to be inserted to ensure the address setup time to the CSn assertion. (Available only when the SRAM interface, byte control SRAM interface, or burst ROM interface is selected.) 000: No cycle inserted 001: 1 cycle inserted 010: 2 cycles inserted 011: 3 cycles inserted 100: 4 cycles inserted 101: 5 cycles inserted 110: 6 cycles inserted 111: 7 cycles inserted
Rev. 1.00 Oct. 01, 2007 Page 346 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 27
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0. Address Hold Cycle Specify the number of cycles to be inserted to ensure the address hold time to the CSn negation. However, setting to over one cycle, one cycle decremented from the setting value when RD strobe cycle in read access or WE strobe cycle in write access is set to over 1 cycle. (Available only when the SRAM interface, byte control SRAM interface, or burst ROM interface is selected.) Note that, it will be no inserted cycle when setting to 0 for inserted wait cycle and setting to 0 for RD strobe hold wait in read access or WE strobe hold wait in write access. 000: No cycle inserted 001: 1 cycle inserted 010: 2 cycles inserted 011: 3 cycles inserted 100: 4 cycles inserted 101: 5 cycles inserted 110: 6 cycles inserted 111: 7 cycles inserted Reserved This bit is always read as 0. The write value should always be 0. RD Setup Cycle (CSn Assert-RD Assert Delay Cycle) Specify the number of cycles to be inserted to ensure the RD setup time to the T1. (Available only when the SRAM interface, byte control SRAM interface, or burst ROM interface is selected.) 000: No cycle inserted 001: 1 cycle inserted 010: 2 cycles inserted 011: 3 cycles inserted 100: 4 cycles inserted 101: 5 cycles inserted 110: 6 cycles inserted 111: 7 cycles inserted
26 to 24 ADH
111
R/W
23
0
R
22 to 20 RDS
111
R/W
Rev. 1.00 Oct. 01, 2007 Page 347 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 19
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
18 to 16 RDH
111
R/W
RD Hold Cycle (RD Negate-CSn Negate Delay Cycle) Specify the number of cycles to be inserted to ensure the RD hold time to the T2. However, setting to over 1 cycle for insertion, one cycle incremented for the setting value when address hold cycle is set to over 1 cycle. (Available only when the SRAM interface, byte control an SRAM interface, or burst ROM interface is selected.) 000: No cycle inserted 001: 1 cycle inserted 010: 2 cycles inserted 011: 3 cycles inserted 100: 4 cycles inserted 101: 5 cycles inserted 110: 6 cycles inserted 111: 7 cycles inserted
15
0
R
Reserved This bit is always read as 0. The write value should always be 0.
14 to 12 WTS
111
R/W
WEn Setup Cycle (CSn Assert-WEn Assert Delay Cycle) Specify the number of cycles to be inserted to ensure the WE setup time to the T2. (Available only when the SRAM interface, byte control an SRAM interface, or burst ROM interface is selected.) 000: No cycle inserted 001: 1 cycle inserted 010: 2 cycles inserted 011: 3 cycles inserted 100: 4 cycles inserted 101: 5 cycles inserted 110: 6 cycles inserted 111: 7 cycles inserted
Rev. 1.00 Oct. 01, 2007 Page 348 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 11
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
10 to 8
WTH
111
R/W
WEn Hold Cycle (WEn Negate-CSn Negate Delay Cycle) Specify the number of cycles to be inserted to ensure the WEn hold time to the T2. However, setting to over 1 cycle for insertion, one cycle incremented for the setting value when address hold cycle is set to over 1 cycle. (Available only when the SRAM interface, byte control SRAM interface, or burst ROM interface is selected.) 000: No cycle inserted 001: 1 cycle inserted 010: 2 cycles inserted 011: 3 cycles inserted 100: 4 cycles inserted 101: 5 cycles inserted 110: 6 cycles inserted 111: 7 cycles inserted
7
0
R
Reserved This bit is always read as 0. The write value should always be 0.
6 to 4
BSH
000
R/W
BS Hold Cycle Specify the number of cycles to be inserted to elongate the BS assertion time. (Available only when the SRAM interface, byte control SRAM interface, or burst ROM interface is selected.) 000: 1 cycle inserted 001: 2 cycles inserted 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 349 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 3 to 0
Bit Name IW[3:0]
Initial Value 1111
R/W R/W
Description Insert Wait Cycle Specify the number of wait cycles to be inserted. (Available only when the SRAM interface, byte control SRAM interface, or burst ROM interface is selected.) 0000: No cycle inserted 0001: 1 cycle inserted 0010: 2 cycles inserted 0011: 3 cycles inserted 0100: 4 cycles inserted 0101: 5 cycles inserted 0110: 6 cycles inserted 0111: 7 cycles inserted 1000: 8 cycles inserted 1001: 9 cycles inserted 1010: 11 cycles inserted 1011: 13 cycles inserted 1100: 15 cycles inserted 1101: 17 cycles inserted 1110: 21 cycles inserted 1111: 25 cycles inserted Note: IW[2:0] specify the number of wait cycles to be inserted into read and write cycles when MPX interface is selected. IW[1:0] specify the number of wait cycles to be inserted into first data. 00: 1 cycle inserted into read cycle and no cycle inserted into write cycle 01: 1 cycle inserted into read cycle and 1 cycle inserted into write cycle 10: 2 cycle inserted into read cycle and 2 cycle inserted into write cycle 11: 3 cycle inserted into read cycle and 3 cycle inserted into write cycle IW2 specifies the number of wait cycle to be inserted into second data or after. 0: No cycle inserted 1: 1 cycle inserted IW3: Reserved
Rev. 1.00 Oct. 01, 2007 Page 350 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
11.4.5
CSn PCMCIA Control Register (CSnPCR)
CSnPCR is a 32-bit readable/writable register that specifies the timing for the PCMCIA interface connected to area n (n = 5 and 6), the space property, and the assert/negate timing for the OE and WE signals. The pulse widths of OE and WE are set using the wait control bits in CSnWCR. CSnPCR is initialized to H'7700 0000 by a power-on reset or a manual reset.
Bit:
31
30
29 SAA
28
27
26
25 SAB
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit:
-
1 R/W 12 0 R 11 1 R/W 10
PCWA 1 R/W 8 0 R/W 7 0 R/W 6
PCWB 0 R/W 5 TEHA 0 R/W 4 0 R/W 3
PCIW 0 R/W 2 0 R/W 1 TEHB 0 R/W 0 R/W 0 R/W 0 R/W 0
0 R 15
1 R/W 14
1 R/W 13 TEDA
1 R/W 9 TEDB
-
Initial value: R/W:
-
0 R/W 0 R/W 0 R/W
-
0 R/W 0 R 0 R/W
-
0 R/W 0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
30 to 28 SAA
111
R/W
Space Property A Specify the space property of PCMCIA connected to first half of area 5 or 6. 000: ATA complement mode 001: Dynamic I/O bus sizing 010: 8-bit I/O space 011: 16-bit I/O space 100: 8-bit common memory 101: 16-bit common memory 110: 8-bit attribute memory 111: 16-bit attribute memory
27
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 351 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit
Bit Name
Initial Value 111
R/W R/W
Description Space Property B Specify the space property of PCMCIA connected to second half of area 5 or 6. 000: ATA complement mode 001: Dynamic I/O bus sizing 010: 8-bit I/O space 011: 16-bit I/O space 100: 8-bit common memory 101: 16-bit common memory 110: 8-bit attribute memory 111: 16-bit attribute memory
26 to 24 SAB
23, 22
PCWA
00
R/W
PCMCIA Wait A Wait cycle for low-speed PCMCIA. The number of wait cycles specified by these bits is added to the number designated by CSnWCR. These bits are valid, when the access area of PCMCIA interface is first half of area 5 or 6, 00: No wait cycle inserted 01: 15 wait cycles inserted 10: 30 wait cycles inserted 01: 50 wait cycles inserted
21, 20
PCWB
00
R/W
PCMCIA Wait B Wait cycle for low-speed PCMCIA. The number of wait cycles specified by these bits is added to the number designated by PCIW. These bits are valid, when the access area of PCMCIA interface is second half of area 5 or 6, 00: No wait cycle inserted 01: 15 wait cycles inserted 10: 30 wait cycles inserted 01: 50 wait cycles inserted
Rev. 1.00 Oct. 01, 2007 Page 352 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit
Bit Name
Initial Value 0000
R/W R/W
Description PCMCIA Insert Wait Cycle B Specify the number of wait cycles to be inserted. These bits are valid, when the access area of PCMCIA interface is second half of area 5 or 6, 0000: No cycle inserted 0001: 1 cycle inserted 0010: 2 cycles inserted 0011: 3 cycles inserted 0100: 4 cycles inserted 0101: 5 cycles inserted 0110: 6 cycles inserted 0111: 7 cycles inserted 1000: 8 cycles inserted 1001: 9 cycles inserted 1010: 11 cycles inserted 1011: 13 cycles inserted 1100: 15 cycles inserted 1101: 17 cycles inserted 1110: 21 cycles inserted 1111: 25 cycles inserted Note: Specify the number of wait cycle designated by CSnWCR when the access area of PCMCIA interface is first half of area 5 or 6.
19 to 16 PCIW
15
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 353 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit
Bit Name
Initial Value 000
R/W R/W
Description OE/WE Assert Delay A These bits set the delay time from address output to OE/WE assertion for the access of first half area of PCMCIA interface. 000: No wait cycle inserted 001: 1 wait cycle inserted 010: 2 wait cycles inserted 011: 3 wait cycles inserted 100: 6 wait cycles inserted 101: 9 wait cycles inserted 110: 12 wait cycles inserted 111: 15 wait cycles inserted
14 to 12 TEDA
11
0
R
Reserved This bit is always read as 0. The write value should always be 0.
10 to 8
TEDB
000
R/W
OE/WE Assert Delay B These bits set the delay time from address output to OE/WE assertion for the access of second half area of PCMCIA interface. 000: No wait cycle inserted 001: 1 wait cycle inserted 010: 2 wait cycles inserted 011: 3 wait cycles inserted 100: 6 wait cycles inserted 101: 9 wait cycles inserted 110: 12 wait cycles inserted 111: 15 wait cycles inserted
7
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 354 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Bit 6 to 4
Bit Name TEHA
Initial Value 000
R/W R/W
Description OE/WE Negate-Address Delay A These bits set the delay time from OE/WE negation to address hold for the access of first half area of PCMCIA interface. 000: No wait cycle inserted 001: 1 wait cycle inserted 010: 2 wait cycles inserted 011: 3 wait cycles inserted 100: 6 wait cycles inserted 101: 9 wait cycles inserted 110: 12 wait cycles inserted 111: 15 wait cycles inserted
3
0
R
Reserved This bit is always read as 0. The write value should always be 0.
2 to 0
TEHB
000
R/W
OE/WE Negate-Address Delay B These bits set the delay time from OE/WE negation to address hold for the access of second half area of PCMCIA interface. 000: No wait cycle inserted 001: 1 wait cycle inserted 010: 2 wait cycles inserted 011: 3 wait cycles inserted 100: 6 wait cycles inserted 101: 9 wait cycles inserted 110: 12 wait cycles inserted 111: 15 wait cycles inserted
Rev. 1.00 Oct. 01, 2007 Page 355 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
11.5
11.5.1
Operation
Endian/Access Size and Data Alignment
This LSI supports both big-endian mode, in which the upper byte (MSByte) in a string of byte data is at address 0, and little-endian mode, in which the lower byte (LSByte) in a string of byte data is at address 0. The mode is specified by the external pin (MD5 pin) at a power-on reset through the RESET pin. At a power-on reset by PRESET, big-endian mode is specified when the MD5 pin is low, and little-endian mode is specified when the MD5 pin is high. A data bus width of 8, 16, or 32 bits can be selected for the normal memory interface, and one of 8 or 16 bits can be selected for the PCMCIA interface. Data alignment is carried out according to the data bus width and endian mode of each device. Accordingly, when the data bus width is smaller than the access size, multiple bus cycles are automatically generated to reach the access size. In this case, access is performed by incrementing the addresses corresponding to the bus width. For example, when a longword access is performed at the area with an 8-bit width in the SRAM interface, each address is incremented one by one, and then access is performed four times. In the 32-byte transfer, a total of 32-byte data is continuously transferred according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed in wrap around method according to the set bus width. The bus is not released during these transfers. In this LSI, data alignment and data length conversion between different interfaces is performed automatically. The relationship between the endian mode, device data length, and access unit are shown in tables 11.9 to 11.14. Data Configuration
MSB Byte MSB Word MSB Longword Data 31 to 24 MSB Data 63 to 56 Data 23 to 16 Data 15 to 8 Data 7 to 0 LSB Data 7 to 0 Data 15 to 8 Data 7 to 0 LSB Data 7 to 0 LSB LSB
Quadword
Data 55 to 48
Data 47 to 40
Data 39 to 32
Data 31 to 24
Data 23 to 16
Data 15 to 8
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Section 11 Local Bus State Controller (LBSC)
Table 11.9 32-Bit External Device/Big-Endian Access and Data Alignment
Operation Access Size Byte Data Bus WE3 Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Strobe Signals WE2 WE1 WE0
D31 to D23 to D15 to D7 to Address No. D24 D16 D8 D0 4n 4n + 1 4n + 2 4n + 3 1 1 1 1 1 1 1 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0
Word
4n 4n + 2
Data Data 15 to 8 7 to 0 Data 31 to 24 Data 23 to 16
Data Data 15 to 8 7 to 0 Data Data 15 to 8 7 to 0
Longword 4n
Table 11.10 16-Bit External Device/Big-Endian Access and Data Alignment
Operation Access Size Byte Data Bus WE3 Strobe Signals WE2 WE1 Assert Assert Assert Assert Assert Assert WE0
D31 to D23 to D15 to D7 to Address No. D24 D16 D8 D0 2n 2n + 1 1 1 1 1 Data 7 to 0 Data 7 to 0
Word
2n
Data Data 15 to 8 7 to 0 Data 31 to 24 Data 23 to 16
Longword 4n
4n + 2
2
Data Data 15 to 8 7 to 0
Assert
Assert
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Section 11 Local Bus State Controller (LBSC)
Table 11.11 8-Bit External Device/Big-Endian Access and Data Alignment
Operation Access Size Byte Word Data Bus WE3 Strobe Signals WE2 WE1 WE0 Assert Assert Assert Assert
D31 to D23 to D15 to D7 to Address No. D24 D16 D8 D0 n 2n 2n + 1 1 1 2 1 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0
Longword 4n
4n + 1
2
Assert
4n + 2 4n + 3
3 4

Assert Assert
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Section 11 Local Bus State Controller (LBSC)
Table 11.12 32-Bit External Device/Little-Endian Access and Data Alignment
Operation Access Size Byte Data Bus WE3 Strobe Signals WE2 WE1 WE0 Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert
D31 to D23 to D15 to D7 to Address No. D24 D16 D8 D0 4n 4n + 1 4n + 2 4n + 3 1 1 1 1 1 1 1 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0
Word
4n 4n + 2
Data Data 15 to 8 7 to 0
Data Data 15 to 8 7 to 0 Data 31 to 24 Data 23 to 16
Longword 4n
Data Data 15 to 8 7 to 0
Table 11.13 16-Bit External Device/Little-Endian Access and Data Alignment
Operation Access Size Byte Data Bus WE3 Strobe Signals WE2 WE1 WE0 Assert Assert Assert Assert Assert Assert Assert Assert
D31 to D23 to D15 to D7 to Address No. D24 D16 D8 D0 2n 2n + 1 1 1 1 1 2 Data 7 to 0 Data 7 to 0
Word
2n
Data Data 15 to 8 7 to 0 Data Data 15 to 8 7 to 0 Data 31 to 24 Data 23 to 16
Longword 4n 4n + 2
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Section 11 Local Bus State Controller (LBSC)
Table 11.14 8-Bit External Device/Little-Endian Access and Data Alignment
Operation Access Size Byte Word Data Bus WE3 Strobe Signals WE2 WE1 WE0 Assert Assert Assert Assert Assert Assert
D31 to D23 to D15 to D7 to Address No. D24 D16 D8 D0 n 2n 2n + 1 1 1 2 1 2 3 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 23 to 16 Data 31 to 24
Longword 4n 4n + 1 4n + 2
4n + 3
4
Assert
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Section 11 Local Bus State Controller (LBSC)
11.5.2 (1)
Areas
Area 0
For area 0, external address bits A28 to A26 are 000. The interfaces that can be set for this area are the SRAM, MPX, and burst ROM interfaces. A bus width of 8, 16, or 32 bits is selectable with external pins MD4 and MD3 at a power-on reset. For details, see section 11.3.2, Memory Bus Width. When area 0 is accessed, the CS0 signal is asserted. In addition, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS0WCR can be selected. When the burst ROM interface is used, a burst pitch number in the range of 0 to 7 is selectable with bits BW[2:0] in CS0BCR. Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY). (When the insert number is 0, the RDY signal is ignored.) When the burst ROM interface is used, the number of transfer cycles for a burst cycle is selected from a range of 2 to 9 according to the number of wait cycles. The setup time and hold time (cycle number) of the address and CS0 signals to the read and write strobe signals can be set within a range of 0 to 7 cycles by CS0WCR. The BS hold cycles can be set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more. (2) Area 1
For area 1, external address bits A28 to A26 are 001. The interfaces that can be set for this area are the SRAM, MPX, burst ROM and byte-control SRAM interfaces. A bus width of 8, 16, or 32 bits is selectable with bits SZ[1:0] in CS1BCR. When the MPX interface is used, a bus width of 32 bits should be selected through bits SZ[1:0] in CS1BCR. When using the byte-control SRAM interface, select a bus width of 16 or 32 bits. When area 1 is accessed, the CS1 signal is asserted. In the case where the SRAM interface is set, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted.
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Section 11 Local Bus State Controller (LBSC)
As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS1WCR can be selected. When the burst ROM interface is used, a burst pitch number in the range of 0 to 7 is selectable with bits BW[2:0] in CS1BCR. Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY). (When the insert number is 0, the RDY signal is ignored.) The setup time and hold time (cycle number) of the address and CS1 signals to the read and write strobe signals can be set within a range of 0 to 7 cycles by CS1WCR. The BS hold cycles can be set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more. (3) Area 2
For area 2, external address bits A28 to A26 are 010. The interfaces that can be set for this area are the SRAM, MPX, burst ROM and DDR-SDRAM interfaces. When the SRAM interface is used, a bus width of 8, 16, or 32 bits is selectable with bits SZ[1:0] in CS2BCR. When the MPX interface is used, a bus width of 32 bits should be selected through bits SZ[1:0] in CS2BCR. When area 2 is accessed, the CS2 signal is asserted (except for DDR-SDRAM area). In the case where the SRAM interface is set, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS2WCR can be selected. Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY). (When the insert number is 0, the RDY signal is ignored.) The setup time and hold time (cycle number) of the address and CS2 signals to the read and write strobe signals can be set within a range of 0 to 7 cycles by CS2WCR. The BS hold cycles can be set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more. When the DDR-SDRAM is used, see section 12, DDR-SDRAM Interface (DDRIF). (4) Area 3
For area 3, external address bits A28 to A26 are 011. This area is used only for the DDR-SDRAM interface.
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Section 11 Local Bus State Controller (LBSC)
For details, see section 12, DDR-SDRAM Interface (DDRIF). (5) Area 4
For area 4, physical address bits A28 to A26 are 100. The interfaces that can be set for this area are the SRAM, MPX, burst ROM, byte control SRAM, DDR-SDRAM and PCI interfaces. A bus width of 8, 16, or 32 bits is selectable with bits SZ [1:0] in CS4BCR. When the MPX interface is used, a bus width of 32 bits should be selected through bits SZ[1:0] in CS4BCR. When the byte control SRAM interface is used, select a bus width of 16 or 32 bits. For details, see section 11.3.2, Memory Bus Width. When area 4 is accessed, the CS4 signal is asserted (except for DDR-SDRAM and PCI areas). In the case where the SRAM interface is set, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS4WCR can be selected. Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY). (When the insert number is 0, the RDY signal is ignored.) The setup time and hold time (cycle number) of the address and CS4 signals to the read and write strobe signals can be set within a range of 0 to 7 cycles by CS4WCR. The BS hold cycles can be set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more. When the DDR-SDRAM or PCI is used, see section 12, DDR-SDRAM Interface (DDRIF) or section 13, PCI Controller (PCIC), respectively. (6) Area 5
For area 5, external address bits A28 to A26 are 101. The interfaces that can be set for this area are the SRAM, MPX, burst ROM, PCMCIA, and DDRSDRAM interfaces. When the SRAM or burst ROM interface is used, a bus width of 8, 16, or 32 bits is selectable with bits SZ[1:0] in CS5BCR. When the MPX interface is used, a bus width of 32 bits should be selected through bits SZ[1:0] in CS5BCR. When the PCMCIA interface is used, select a bus width of 8 or 16 bits with SZ[1:0] in CS5BCR. For details, see section 11.3.2, Memory Bus Width. While the SRAM interface is used, the CS5 signal is asserted when area 5 is accessed. In addition, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted.
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Section 11 Local Bus State Controller (LBSC)
While the PCMCIA interface is used, the CE1A/CS5 and CE2A signals, the RD signal, (which can be used as OE), the WE0, WE1, WE2, and WE3 signals, (which can be used as, PCC_REG, WE, IORD, and IOWR, respectively) are asserted. As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS5WCR can be selected. Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY). (When the insert number is 0, the RDY signal is ignored.) The setup time and hold time (cycle number) of the address and CS5 signals to the read and write strobe signals can be set within a range of 0 to 7 cycles by CS5WCR. The BS hold cycles can be set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more. For the PCMCIA interface, the setup time of addresses to the read/write strobe signals (CE1A/CS5 and CE2A) can be specified within a range from 0 to 15 cycles through bits TEDA[2:0], TEDB[2:0], TEHA[2:0], and TEHB[2:0] in CS5PCR. In addition, the number of wait cycles can be specified within a range from 0 to 50 cycles through bits PCWA[1:0] and PCWB[1:0] The number of wait cycles specified by CS5PCR is added to the value specified by IW[3:0] in CS5WCR or PCIW[3:0] in CS5PCR. When the DDR-SDRAM is used, see section 12, DDR-SDRAM Interface (DDRIF). (7) Area 6
For area 6, external address bits A28 to A26 are 110. The interfaces that can be set for this area are the SRAM, MPX, burst ROM, and PCMCIA interfaces. When the SRAM or burst ROM is used, a bus width of 8, 16, or 32 bits is selectable with bits SZ[1:0] in CS6BCR. When the MPX interface is used, a bus width of 32 bits should be selected through bits SZ[1:0] in CS6BCR. When the PCMCIA interface is used, select a bus width of 8 or 16 bits with SZ[1:0] in CS6BCR. For details, see section 11.3.2, Memory Bus Width. While the SRAM interface is used, the CS6 signal is asserted when area 6 is accessed. In addition, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. While the PCMCIA interface is used, the CE1B/CS6 and CE2B signals, the RD signal (which can be used as OE), and the WE0, WE1, WE2, and WE3 signals (which can be used as PCC_REG, WE, IORD, and IOWR, respectively) are asserted. As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS6WCR can be selected.
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Section 11 Local Bus State Controller (LBSC)
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY). (When the insert number is 0, the RDY signal is ignored.) The setup time and hold time (cycle number) of the address and CS6 signals to the read and write strobe signals can be set within a range of 0 to 7 cycles by CS6WCR. The BS hold cycles can be set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more. For the PCMCIA interface, the setup time of addresses to the read/write strobe signals (CE1B/CS6 and CE2B) can be specified within a range from 0 to 15 cycles by bits TEDA[2:0], TEDB[2:0], TEHA[2:0], and TEHB[2:0] in CS6PCR. In addition, the number of wait cycles can be specified within a range from 0 to 50 cycles by bits PCWA[1:0] and PCWB[1:0]. The number of wait cycles specified by CS6PCR is added to the value specified by IW[3:0] in CS6WCR or PCIW[3:0] in CS6PCR. 11.5.3 (1) SRAM interface
Basic Timing
The strobe signals for the SRAM interface of this LSI are output primarily based on the SRAM connection. Figure 11.4 shows the basic timing of the SRAM interface. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. The CSn signal is asserted at the rising edge of the clock in the T1 state, and negated at the next rising edge of the clock in the T2 state. Therefore, there is no negation period in the case of access at minimum pitch. During reading, specification of an access size is not needed. The output of an access address on the address pins (A25 to A0) is correct, however, since the access size is not specified, 32-bit data is always output when a 32-bit device is in use, and 16-bit data is output when a 16-bit device is in use. During writing, only the WE signal corresponding to the byte to be written is asserted. For details, see section 11.5.1, Endian/Access Size and Data Alignment. In 32-byte transfer, a total of 32 bytes are transferred continuously according to the bus width set. The first access is performed on the data for which there was an access request, and the remaining accesses are performed in wrap around method according to the set bus width. The bus is not released during this transfer.
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Section 11 Local Bus State Controller (LBSC)
T1 CLKOUT A25 to A0 CSn RDWR RD D31 to D0 (read) WEn D31 to D0 (Write) BS RDY DACKn (DA)
T2
DA: Dual address DMA
Figure 11.4 Basic Timing of SRAM Interface
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Section 11 Local Bus State Controller (LBSC)
Figures 11.5 to 11.7 show examples of the connection to SRAM with data width of 32, 16, and 8 bits.
128 K x 8-bit SRAM
This LSI A18
...
A16
...
... ... ...
A2 CSn RD D31
...
A0 CS OE I/O7
...
...
D24 WE3 D23
...
I/O0 WE
...
D16 WE2 D15
...
A16
... ...
... ...
...
...
...
D0 WE0
A16
...
A0 CS OE I/O7
...
I/O0 WE
A16
...
...
Figure 11.5 Example of 32-Bit Data-Width SRAM Connection
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...
...
A0 CS OE I/O7 I/O0 WE
...
D8 WE1 D7
A0 CS OE I/O7 I/O0 WE
...
Section 11 Local Bus State Controller (LBSC)
This LSI A17 A1 CSn RD D15 D8 WE1 D7 D0 WE0
128 K x 8-bit SRAM A16
...
...
... ... ... ...
... ...
...
...
...
...
Figure 11.6 Example of 16-Bit Data-Width SRAM Connection
128K x 8-bit SRAM
This LSI
A16
A16
...
...
A0 CSn RD D7
...
D0 WE0
...
Figure 11.7 Example of 8-Bit Data-Width SRAM Connection
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...
I/O0 WE
...
A0 CS OE I/O7
...
I/O0 WE
...
A0 CS OE I/O7
...
I/O0 WE A16
...
A0 CS OE I/O7
Section 11 Local Bus State Controller (LBSC)
(2)
Wait Cycle Control
Wait cycle insertion for the SRAM interface can be controlled by CSnWCR. If the IW bits for each area in CSnWCR is not 0, a software wait is inserted in accordance with the wait-control bits. For details, see section 11.4.4, CSn Wait Control Register (CSnWCR). A specified number of Tw cycles is inserted as wait cycles in accordance with the CSnWCR setting. The insertion timing of the wait cycle is shown in figure 11.8.
T1 Tw T2
CLKOUT A25 to A0
CSn RDWR
RD D31 to D0 (read) WE D31 to D0 (Write) BS
RDY DACK (DA) DA: Dual address DMA
Figure 11.8 SRAM Interface Wait Timing (Software Wait Only)
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Section 11 Local Bus State Controller (LBSC)
When software wait insertion is specified by CSnWCR, the external wait input signal (RDY) is also sampled. The RDY signal sampling timing is shown in figure 11.9, where a single wait cycle is specified as a software wait. The RDY signal is sampled at the transition from the Tw state to the T2 state. Therefore, the assertion of the RDY signal has no effect in the T1 cycle or in the first Tw cycle. The RDY signal is sampled on the rising edge of the clock.
T1 CLKOUT Tw Twe T2
A25 to A0 CSn RDWR RD (read) D31 to D0 (read) WEn (Write) D31 to D0 (Write)
BS
RDY DACKn (DA)
DA: Dual address DMA
Figure 11.9 SRAM Interface Wait Cycle Timing (Wait Cycle Insertion by RDY Signal)
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Section 11 Local Bus State Controller (LBSC)
(3)
Read-Strobe Negate Timing
When the SRAM interface is used, the negation timing of the strobe signal during a read operation can be specified through the RDH bit in CSnWCR.
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Section 11 Local Bus State Controller (LBSC)
TAS1 CLKOUT
T1
TS1
TW
TW
TW
TW
T2
TH1
TH2
TAH1
A25 to A0 CSn RDWR RD (read) D31 to D0 (read)
TS1: RD Setup wait CSnWCR RDS (0 to 7) TAS1: Address Setup wait CSnWCR RDS (0 to 7) Tw: Access wait CSnWCR IW (0 to 25) TH1, TH2: RD Hold wait SnWCR RDH (0 to 7)
TAH1: Address Hold wait CSnWCR AHS (0 to 7)
*
CLKOUT
CLKOUT
WEn (Write)
D31 to D0 (Write)
TS1: WE Setup wait CSnWCR WTS (0 to 7) TAS1: Address Setup wait CSnWCR ADS (0 to 7) Tw: Access wait CSnWCR IW (0 to 25)
TH1, TH2: WE Hold wait CSnWCR WTH (0 to 7)
TAH1: Address Hold wait CSnWCR ADH (0 to 7)
BS
Note:
* When CSnBCR RDSPL is set to 1.
Figure 11.10 SRAM Interface Wait State Timing (Read-Strobe Negate Timing Setting)
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Section 11 Local Bus State Controller (LBSC)
11.5.4
Burst ROM Interface
Setting the TYPE bit in CSnBCR(n=0 to 2 and 4 to 6) to 010 allows a burst ROM to be connected to areas 0 to 2 and 4 to 6. The burst ROM interface provides high-speed access to ROM that has a burst access function. The burst access timing of burst ROM is shown in figure 11.11. The wait cycle is set to 0 cycle. Although the access is similar to that of the SRAM interface, only the address is changed when the first cycle ends and then the next access is started. When 8-bit ROM is used, the number of consecutive accesses can be set as 4, 8, 16, or 32 through bits BST[2:0] in CSnBCR(n=0 to 2 and 4 to 6). Similarly, when 16-bit ROM is used, 4, 8 or 16 accesses can be set; when 32-bit ROM is used, 4 or 8 accesses can be set. The RDY signal is always sampled when one or more wait cycles are set. Even when no wait is specified in the burst ROM settings, two access cycles are inserted in the second and subsequent accesses as shown in figure 11.12. A writing operation for the burst ROM interface is performed in the same way as for the SRAM interface. In a 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed in wrap around method according to the set bus width. The bus is not released during this transfer. Figure 11.13 shows the timing chart when the burst ROM is used and setup/hold is specified by CSnWCR.
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Section 11 Local Bus State Controller (LBSC)
T1 CLKOUT A25 to A5
TB2
TB1
TB2
TB1
TB2
TB1
T2
A4 to A0 CSn RDWR RD D31 to D0 (read) BS RDY
Figure 11.11 Burst ROM Basic Access Timing
T1 CLKOUT A25 to A5 A4 to A0 CSn RDWR RD D31 to D0 (read) BS RDY Tw Twe TB2 TB1 Tw TB2 TB1 Tw TB2 TB1 Tw T2
Figure 11.12 Burst ROM Wait Access Timing
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Section 11 Local Bus State Controller (LBSC)
TAS1
CLKOUT A25 to A5 A4 to A0 CSn RDWR RD D31 to D0 (read) BS RDY DACK
T1
TS1
TB2
TB1
TB2
TB1
TB2
TB1
T2
TH1
TAH1
*
Note: * When CSnBCR RDSPL is set to 1.
Figure 11.13 Burst ROM Wait Access Timing 11.5.5 PCMCIA Interface
Areas 5 and 6 can be set to the IC memory card interface or I/O card interface, which is stipulated in JEIDA specification version 4.2 (PCMCIA 2.1), by setting bits TYPE[2:0] in CS5BCR and CS6BCR. Figure 11.14 shows an example of PCMCIA card connection to this LSI. To enable hot insertion of PCMCIA cards (i.e., insertion or removal while system power is being supplied), a three-state buffer must be connected between this LSI bus interface and the PCMCIA cards. Since operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA standard, this LSI supports the PCMCIA interface only in little-endian mode through little-endian mode setting. PCMCIA interface can select space property from among 8-bit common memory, 16-bit common memory, 8-bit attribute memory, 16-bit attribute memory, 8-bit I/O space, 16-bit I/O space, dynamic I/O bus sizing, and ATA complement mode by setting bits SAA[2:0] and SAB[2:0] in CSnPCR.
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Section 11 Local Bus State Controller (LBSC)
When the first half area is accessed, bits IW[3:0] in CSnWCR (n=5 or 6) and bits PCWA[1:0], TEDA[2:0], and TEHA[2:0] in CSnPCR (n=5 or 6) are selected. When the second half area is accessed, bits IW[3:0] in CSnWCR (n=5 or 6) and bits PCWB[1:0], TEDB[2:0], and TEHB[2:0] in CSnPCR (n=5 or 6) are selected. Bits PCWA[1:0] and PCWB[1:0] can be used to set the number of wait cycles to be inserted in a low-speed bus cycle as 0, 15, 30, or 50. This value is added to the number of inserted wait cycles specified by IW bit in CSnWCR or PCIW bit in CSnPCR. Bits PEDA[2:0] and PEDB[2:0] (with a setting range from 0 to 15) can be used to ensure the setup times of the address, CSn, CE2A, CE2B, and PCC_REG to the RD and WE1 signals. Bits TEHA[2:0] and TEHB[2:0] (with a setting range from 0 to15) can be used to ensure the hold times of the address, CSn, CE2A, CE2B, and PCC_REG REG to the RD and WE1 signals.
Bits IW[3:0] in the CS5 bus control register (CS5BCR) or CS6 bus control register (CS6BCR) are used to set the number of idle cycles between cycles. The selected number of wait cycles between cycles depends only on the area to be accessed (area 5 or 6). When area 5 is accessed, bits IW[3:0] in CS5WCR are selected, and when area 6 is accessed, bits IW[3:0] in CS6WCR are selected. In 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed in wrap around method according to the set bus width. The bus is not released during this transfer. ATA complement mode is to access the ATA device register that connected to this LSI. Device Control Register, Alternate Status Register, Data Register, and Data Port can be accessed in ATA complement mode. To access Device Control Register and Alternate Status Register, PIO byte access is used, and to access Data Register, PIO word access is used. When PIO byte access is executed, CE1x is negated and CE2x is asserted. When PIO word access is executed, CE1x is asserted and CE2x is negated. To access Data Port is used DMA transfer. Then DMAC must be set burst mode, level detection, overrun 0, DACK output to the correspondent PCMCIA connected area, and set to 1 DACKBST[2:0] bit in BCR of correspondent DMA transfer channels. When DMA transfer of ATA complement mode area is executed, both CE1x and CE2x are not asserted. And set to 1 the DACKBST bit in BCR of correspondent DMA transfer channel, then the correspondent DACK signal is being asserted from the first to the end of the DMA transfer cycle.
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Section 11 Local Bus State Controller (LBSC)
Specify the number of wait cycles between accesses to be 0 for the DACK assertion area, when setting the size of DMA transfer is 16-byte. After the DMA burst transfer has finished, that DACKBST was enabled, set the DACKBST bit to 1 again before starting the next DMA transfer.
(a) IO Card Interface DACKBST Invalid CExx DACK
(b) ATA Complement Mode DACKBST Valid CExx
DACK Note: Number of DMA transter times: 4,DMA transter size: word (16-bit)
Figure 11.14 CExx and DACK Output of ATA Complete Mode in DMA Transfer
Rev. 1.00 Oct. 01, 2007 Page 377 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Table 11.15 Relationship between Address and CE When Using PCMCIA Interface
Read/ Write Read Access Size (bits)*1 8 Odd/ Even Even Odd 16 Even Even Odd Write 8 Even Odd 16 Even Even Odd 16 Read 8 Even Odd 16 Even Odd Write 8 Even Odd 16 Even Odd Dynamic Read Bus Sizing*2 8 Even Odd 16 Even Odd Write 8 Even Odd 16 Even Odd Read 8 Even Odd Odd 16 Even Even Odd
Bus (Bits) 8
IOIS16 x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Access First Second First Second First Second First Second
CE2 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1
CE1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0
A0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1
D15 to D8 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Read data
D7 to D0 Read data Read data Lower read data Upper read data Write data Write data Lower write data Upper write data Read data Invalid
Upper read data Lower read data Invalid Write data Write data Invalid
Upper write data Lower write data Invalid Read data Read data Invalid
Upper read data Lower read data Invalid Write data Write data Invalid
Upper write data Lower write data Invalid Invalid Invalid Invalid Invalid Read data Invalid Read data Lower read data Upper read data
Rev. 1.00 Oct. 01, 2007 Page 378 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
Access Read/ Bus (Bits) Dynamic Bus Sizing*2 Write Write Size (bits)*1 8 Odd/ Even Even Odd Odd 16 Even Even Odd ATA complement mode 16 Even Odd PIO write 16 8 Even Odd Even Odd DMA read 16 8 Even Odd Even Odd DMA write 16 8 Even Odd Even Odd PIO read 8 Even Odd IOIS16 1 1 1 1 1 1 x x x x x x x x x x x x x x x x Access First Second First Second CE2 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 CE1 0 1 0 0 0 1 0 1 0 1 1 1 1 1 1 A0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 1 D15 to D8 Invalid Invalid Invalid D7 to D0 Write data Write data Write data
Upper write data Lower write data Invalid Invalid Upper write data Read data
Upper read data Lower read data Invalid Write data
Upper write data Lower write data Invalid Read data Read data Invalid
Upper read data Lower read data Invalid Write data Write data Invalid
Upper write data Lower write data
[Legend] x: Don't care Notes: 1. In 32-bit/64-bit/32-byte transfer, the addresses are automatically incremented by the bus width, and then above accesses are repeated until the transfer data size is reached. 2. PCMCIA I/O card interface only.
Rev. 1.00 Oct. 01, 2007 Page 379 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
A25 to A0 D15 to D0 RDWR CE1B/(CS6) CE1A/(CS5) CE2B CE2A
D15 to D8
G DIR
A25 A0 A25 to A0
G
D7 to D0 G DIR
D0 D15 toD0
PC PC card (memory/IO I/O)
This LSI
CE1 CE2 RD WE1 IORD IOWR PCC_REG RDY IOIS16
Card detection circuit
G
OE WE/PGM IORD) IOWR)
REG WAIT
(IOIS16)
CD1, CD2 CD1 CD2
A25 to A0 A25 A0
G
D7 to D0
G DIR
D15 to D0 D15 D0
D15 to D8
G DIR
PC PC card (memory/IO I/O)
G
CE1 CE2 OE WE/PGM REG WAIT
Card detection circuit
CD1 CD2 CD1, CD2
Figure 11.15 Example of PCMCIA Interface
Rev. 1.00 Oct. 01, 2007 Page 380 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
(1)
Memory Card Interface Basic Timing
Figure 11.16 shows the basic timing for the PCMCIA memory card interface, and figure 11.17 shows the wait timing for the PCMCIA memory card interface.
Tpcm1 CLKOUT A25 to A0 CExx PCC_REG RDWR RD (read) D15 to D0 (read) WE1 (Write) D15 to D0 (Write) BS DACK (DA) DA: Dual address DMA. Tpcm2
Figure 11.16 Basic Timing for PCMCIA Memory Card Interface
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Section 11 Local Bus State Controller (LBSC)
Tpcm0 CLKOUT
Tpcm0w
Tpcm1
Tpcm1w
Tpcm1w
Tpcm2
Tpcm2w
A25 to A0 CExx PCC_REG RDWR RD (read) D15 to D0 (read) WE1 (Write) D15 to D0 (Write) BS RDY
DACK (DA)
DA: Dual address DMA
Figure 11.17 Wait Timing for PCMCIA Memory Card Interface
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Section 11 Local Bus State Controller (LBSC)
(2)
I/O Card Interface Timing
Figures 11.18 and 11.19 show the timing for the PCMCIA I/O card interface. When accessing a PCMCIA card via the I/O card interface, it is possible to perform dynamic sizing of the I/O bus width using the IOIS16 pin. With the 16-bit bus width selected, if the IOIS16 signal is high during the word-size I/O bus cycle, the I/O port is recognized as eight bits in bus width. In this case, a data access for only eight bits is performed in the I/O bus cycle being executed, and this is automatically followed by a data access for the remaining eight bits. Dynamic bus sizing is also performed for byte-size access to address 2n + 1. Figure 11.20 shows the basic timing for dynamic bus sizing.
Tpci1 CLKOUT Tpci2
A25 to A0 CExx PCC_REG (WE0) RDWR IORD (read) D15 to D0 (read) IOWR (Write) D15 to D0 (Write) BS
DACK (DA) DA: Dual address DMA
Figure 11.18 Basic Timing for PCMCIA I/O Card Interface
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Section 11 Local Bus State Controller (LBSC)
Tpci0 CLKOUT
Tpci0w
Tpci1
Tpci1w
Tpci1w
Tpci2
Tpci2w
A25 to A0 CExx PCC_REG (WE0) RDWR IORD (Write) D15 to D0 (Write) IOWR (Write) D15 to D0 (Write) BS
RDY
IOIS16 DACK (DA) DA: Dual address DMA
Figure 11.19 Wait Timing for PCMCIA I/O Card Interface
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Section 11 Local Bus State Controller (LBSC)
Tpci0 CLKOUT A25 to A1 A0 CExx PCC_REG (WE0) RDWR IORD (WE2) (read) D15 to D0 (read) IOWR (WE3) (Write) D15 to D0 (Write) BS RDY IOIS16 DACK (DA) DA: Dual address DMA
Tpci
Tpci1w
Tpci2
Tpci2w
Tpci0
Tpci
Tpci1w
Tpci2
Tpci2w
Figure 11.20 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface
Rev. 1.00 Oct. 01, 2007 Page 385 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
11.5.6
MPX Interface
When both the MODE4 and MODE3 pins are set to 0 at a power-on reset by the PRESET pin, the MPX interface is selected for area 0. The MPX interface is selected for areas 1, 2, and 4 to 6 by the MPX bit in CS1BCR, CS2BCR, and CS4BCR to CS6BCR. The MPX interface provides an address/data multiplex-type bus protocol and facilitates connection with external memory controller chips using an address/data multiplex-type 32-bit single bus. A bus cycle consists of an address phase and a data phase. Address information is output on D25 to D0 and the access size is output on D31 to D29 in the address phase. The BS signal is asserted for one cycle to indicate the address phase. The CSn signal is asserted at the rising edge in Tm1 and is negated after the end of the last data transfer in the data phase. Therefore, a negation cycle does not occur in the case of minimum pitch access. The FRAME signal is asserted at the rising edge in Tm1 and negated at the start of the last data transfer cycle in the data phase. Therefore, an external device for the MPX interface must internally store the address information and access size output in the address phase and perform data input/output for the data phase. For details, see section 11.5.1, Endian/Access Size and Data Alignment. Values output on address pins A25 to A20 are not guaranteed. In 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed according to the set bus width. If the access size is larger than the bus width in this case, a burst access with continuing multiple data cycle occurs after one address output. The bus is not released during this transfer.
D31 0 D30 0 D29 0 1 1 0 1 1 X X [Legend] X: Don't care Access Size Byte Word Longword Quadword 32-byte burst
Rev. 1.00 Oct. 01, 2007 Page 386 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
This LSI CLKOUT CSn BS RD RDWR D31 to D0 RDY
MPX device CLK CS BS FRAME WE I/O31 to I/O0 RDY
Figure 11.21 Example of 32-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for areas 1, 2, and 4 to 6, a bus size of 32 bits should be specified by CSnBCR. In wait control, either waits by CSnWCR or waits by the RDY pin can be inserted. In a read, one wait cycle is automatically inserted after address output, even if CSnWCR is cleared to 0.
Tm1 CLKOUT RD/FRAME D31 to D0 CSn RDWR Tmd1w
Tmd1
A
D0
RDY
BS
DACK (DA)
DA: Dual address DMA
Figure 11.22 MPX Interface Timing 1 (Single Read Cycle, IW = 0, No External Wait)
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Section 11 Local Bus State Controller (LBSC)
Tm1 CLKOUT RD/FRAME
Tmd1w
Tmd1w
Tmd1
D31 to D0
A
D0
CSn RDWR
RDY
BS
DACK (DA)
DA: Dual address DMA
Figure 11.23 MPX Interface Timing 2 (Single Read, IW = 0, One External Wait Inserted)
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Section 11 Local Bus State Controller (LBSC)
Tm1 CLKOUT RD/FRAME D31 to D0
Tmd1
A
D0
CSn RDWR
RDY BS DACK (DA) DA: Dual address DMA
Figure 11.24 MPX Interface Timing 3 (Single Write Cycle, IW = 0, No External Wait)
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Section 11 Local Bus State Controller (LBSC)
Tm1 CLKOUT RD/FRAME
Tmd1w
Tmd1w
Tmd1
D31 to D0
A
D0
CSn
RDWR
RDY BS DACK (DA) DA: Dual address DMA
Figure 11.25 MPX Interface Timing 4 (Single Write Cycle, IW = 1, One External Wait Inserted)
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Section 11 Local Bus State Controller (LBSC)
Tmd8
Tmd7
Tmd6
Tmd5
Tmd4
Tmd3
Tmd2
Tmd1w
Tmd1
A
D1
D2
D3
D4
D5
D6
D7
D8
RD/FRAME
D31 to D0
CLKOUT
RDWR
Figure 11.26 MPX Interface Timing 5 (Burst Read Cycle, IW = 0, No External Wait)
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DACK (DA)
RDY
CSn
BS
DA: Dual address DMA
Tm1
Section 11 Local Bus State Controller (LBSC)
Tmd8w
Tmd8
Tmd7
Tmd3
Tmd2w
Tmd2
Tmd1w
Tmd1
A
D1
D2
D3
D7
D8
Figure 11.27 MPX Interface Timing 6 (Burst Read Cycle, IW = 0, External Wait Control)
Rev. 1.00 Oct. 01, 2007 Page 392 of 1956 REJ09B0256-0100
DA: Dual address DMA
Tm1
RD/FRAME
D31 to D0
CLKOUT
RDWR
DACK (DA)
RDY
CSn
BS
Section 11 Local Bus State Controller (LBSC)
Tmd8
Tmd7
Tmd6
Tmd5
Tmd4
Tmd3
Tmd2
Tmd1
A
D1
D2
D3
D4
D5
D6
D7
D8
Figure 11.28 MPX Interface Timing 7 (Burst Write Cycle, IW = 0, No External Wait)
Rev. 1.00 Oct. 01, 2007 Page 393 of 1956 REJ09B0256-0100
DA: Dual address DMA
Tm1
RD/FRAME
D31 to D0
CLKOUT
RDWR
DACK (DA)
RDY
CSn
BS
Section 11 Local Bus State Controller (LBSC)
Tmd8
Tmd8w
Tmd7
Tmd2
Tmd3
Tmd1
Tmd2w
Tmd1w
A
D1
D2
D3
D7
D8
Figure 11.29 MPX Interface Timing 8 (Burst Write Cycle, IW = 1, External Wait Control)
Rev. 1.00 Oct. 01, 2007 Page 394 of 1956 REJ09B0256-0100
DA: Dual address DMA
Tm1
RD/FRAME
D31 to D0
CLKOUT
RDWR
DACK (DA)
RDY
CSn
BS
Section 11 Local Bus State Controller (LBSC)
Tmd8
Tmd7
Tmd6
Tmd5
Tmd4
Tmd3
Tmd2
Tmd1w
Tmd1
Tm1
A
D1
D2
D3
D4
D5
D6
D7
D8
Figure 11.30 MPX Interface Timing 9 (Burst Read Cycle, IW = 0, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer)
Rev. 1.00 Oct. 01, 2007 Page 395 of 1956 REJ09B0256-0100
DA: Dual address DMA
RD/FRAME
D31 to D0
CLKOUT
RDWR
DACK (DA)
RDY
CSn
BS
Section 11 Local Bus State Controller (LBSC)
Tmd8w
Tmd8
Tmd7
Tmd3
Tmd2w
Tmd2
Tmd1w
Tmd1
Tm1
A
D1
D2
D3
D7
D8
Figure 11.31 MPX Interface Timing 10 (Burst Read Cycle, IW = 0, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)
Rev. 1.00 Oct. 01, 2007 Page 396 of 1956 REJ09B0256-0100
DA: Dual address DMA
RD/FRAME
D31 to D0
CLKOUT
RDWR
DACK (DA)
RDY
CSn
BS
Section 11 Local Bus State Controller (LBSC)
Tmd8
Tmd7
Tmd6
Tmd5
Tmd4
Tmd3
Tmd2
Tmd1
Tm1
A
D1
D2
D3
D4
D5
D6
D7
D8
RD/FRAME
D31 to D0
CLKOUT
RDWR
Figure 11.32 MPX Interface Timing 11 (Burst Write Cycle, IW = 0, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer)
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DACK (DA)
RDY
CSn
BS
DA: Dual address DMA
Section 11 Local Bus State Controller (LBSC)
Tmd8
Tmd8w
Tmd7
Tmd2
Tmd3
Tmd1
Tmd2w
Tmd1w
Tm1
A
D1
D2
D3
D7
D8
Figure 11.33 MPX Interface Timing 12 (Burst Write Cycle, IW = 1, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)
Rev. 1.00 Oct. 01, 2007 Page 398 of 1956 REJ09B0256-0100
DA: Dual address DMA
RD/FRAME
D31 to D0
CLKOUT
RDWR
DACK (DA)
RDY
CSn
BS
Section 11 Local Bus State Controller (LBSC)
11.5.7
Byte Control SRAM Interface
The byte control SRAM interface is a memory interface that outputs a byte-select strobe (WEn) in both read and write bus cycles. This interface has 16-bit data pins and can be connected to SRAM having an upper byte select strobe and lower select strobe functions, such as UB and LB. Areas 1 and 4 can be specified as a byte control SRAM interface. However, when these areas are set to the MPX interface, the MPX interface has priority. The write timing for the byte control SRAM interface is identical to that of a normal SRAM interface. In read operations, on the other hand, the WEn pin timing is different. In a read access, only the WE signal for the byte being read is asserted. Assertion is synchronized with the falling edge of the CLKOUT clock in the same way as for the WE signal, while negation is synchronized with the rising edge of the CLKOUT clock in the same way as for the RD signal. In 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed in wrap around method according to the set bus width. The bus is not released during this transfer. Figure 11.37 shows an example of a byte control SRAM connection, and figures 11.38 to 11.40 show examples of byte-control SRAM read cycles.
64K x 16-bit SRAM A15 to A0 CS OE WE I/O15 to I/O0 UB LB A15 to A0 CS OE WE I/O15 to I/O0 UB LB
This LSI A18 to A3 CSn RD RDWR D31 to D16 WE3 WE2
D15 to D0 WE1 WE0
Figure 11.34 Example of 32-Bit Data-Width Byte-Control SRAM
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Section 11 Local Bus State Controller (LBSC)
T1 CLKOUT A25 to A0 CSn RDWR RD D31 to D0 (read)
WEn
T2
BS
RDY
DACKn (DA)
DA: Dual address DMA
Figure 11.35 Byte-Control SRAM Basic Read Cycle (No Wait)
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Section 11 Local Bus State Controller (LBSC)
T1 CLKOUT A25 to A0 CSn RDWR RD D31 to D0 (read) WEn BS RDY DACKn (DA) DA: Dual address DMA
Tw
T2
Figure 11.36 Byte-Control SRAM Basic Read Cycle (One Internal Wait Cycle)
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Section 11 Local Bus State Controller (LBSC)
T1 CLKOUT A25 to A0 CSn RDWR RD D31 to D0 (read) WEn BS RDY DACKn (DA) DA: Dual address DMA
Tw
Twe
T2
Figure 11.37 Byte-Control SRAM Basic Read Cycle (One Internal Wait + One External Wait)
Rev. 1.00 Oct. 01, 2007 Page 402 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
11.5.8
Wait Cycles between Accesses
A problem associated with higher operating frequencies for external memory buses is that the data buffer turn-off after completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and resulting in lower reliability or malfunctions. To prevent this problem, this module provides a data collision prevention function. It stores the preceding access area and the type of read/write and inserts a wait cycle before the access cycle if there is a possibility of a bus collision when the next access is started. The process for wait cycle insertion consists of inserting idle cycles between the access cycles as shown in section 11.4.3, CSn Bus Control Register (CSnBCR). If bits IWW, IWRWD, IWRWS, IWRRD and IWRRS in CSnBCR (n = 0 to 2 and 4 to 6) are used to set the number of idle cycles between accesses, the number of inserted idle cycles is only the specified number of idle cycles minus the number of idle cycles specified by the bits. When bus arbitration is performed, the bus is released after wait cycles are inserted between the cycles. When a DMA transfer (dual address mode) is performed, wait cycles are inserted as set in CSnBCR idle cycle bits. When access the MPX interface area continuously after read access, 1 wait cycle is inserted even if set the wait cycle to 0. When the access size is 8-byte or 16-byte, wait cycles are inserted every 4-byte access.
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Section 11 Local Bus State Controller (LBSC)
T1 CLKOUT A25 to A0 CSm CSn BS RDWR RD D31 to D0
T2
Twait
T1
T2
Twait
T1
T2
Area m space read
Area n space read
Area n space Write Area n inter-access wait specification
Area m inter-access wait specificaton
Figure 11.38 Wait Cycles between Access Cycles
Rev. 1.00 Oct. 01, 2007 Page 404 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
11.5.9
Bus Arbitration
This LSI is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. This bus arbitration supports master mode. In master mode the bus is held on a constant basis, and is released to another device in response to a bus request. The bus goes to the high-impedance state when not being held and it is possible to connect an external device that issues bus requests. In the following description, an external device that issues bus requests is also referred to as a slave. This LSI has three internal bus masters: the CPU, DMAC, and PCIC. In addition to these are bus requests from external devices. If requests occur simultaneously, priority is given, in high-to-low order, to a bus request from an external device, the PCIC, the DMAC, and the CPU. To prevent incorrect operation of connected devices when the bus is transferred between master and slave, all bus control signals are negated before the bus is released. When mastership of the bus is received, also, bus control signals begin driving the bus from the negated state. Since signals are driven to the same value by the master and slave exchanging the bus, output buffer collisions can be avoided. By turning off the output buffer on the side releasing the bus, and turning on the output buffer on the side receiving the bus, simultaneously with respect to the bus control signals, it is possible to eliminate the signal high-impedance period. It is not necessary to provide the pull-up resistors usually inserted in these control signal lines to prevent incorrect operation due to external noise in the high-impedance state. Bus transfer is executed between bus cycles. When the bus release request signal (BREQ) is asserted, this LSI releases the bus as soon as the currently executing bus cycle ends, and outputs the bus use permission signal (BACK). However, bus release is not performed during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus release is not performed between read and write cycles during execution of a TAS instruction, or between read and write cycles when DMAC dual address transfer is executed. When BREQ is negated, BACK is negated and use of the bus is resumed. As the CPU in this LSI is connected to cache memory by a dedicated internal bus, reading from cache memory can still be carried out when the bus is being used by another bus master inside or outside this LSI. When writing from the CPU, an external write cycle is generated when writethrough has been set for the cache in this LSI, or when an access is made to a cache-off area. There is consequently a delay until the bus is returned.
Rev. 1.00 Oct. 01, 2007 Page 405 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
CLKOUT BREQ
Asserted for least 2 cycles Negated within 2 cycles
BACK A25 to A0 CSn RDWR RD WEn D31 to D0 (Write) BS
Master access
HiZ HiZ HiZ HiZ HiZ HiZ HiZ
Slave access
Master access
(a) Master mode device access
CLKOUT
Must be asserted for at least 2 cycles
Must be negated within 2 cycles
BREQ BACK HiZ A25 to A0 HiZ CSn HiZ RDWR HiZ RD WEn D31 to D0 (Write) BS
Master access HiZ HiZ HiZ HiZ HiZ HiZ
HiZ
HiZ HiZ
HiZ
Slave access
Master access
(b) Slave mode device access
Figure 11.39 Arbitration Sequence
Rev. 1.00 Oct. 01, 2007 Page 406 of 1956 REJ09B0256-0100
Section 11 Local Bus State Controller (LBSC)
11.5.10 Master Mode The master mode processor holds the bus itself unless it receives a bus request. On receiving an assertion (low level) of the bus request signal (BREQ) from off-chip, the master mode processor releases the bus and asserts (drives low) the bus use permission signal (BACK) as soon as the currently executing bus cycle ends. On receiving the BREQ negation (high level) indicating that the slave has released the bus, the processor negates (drives high) the BACK signal and resumes use of the bus. When the bus is released, all bus interface related output signals and input/output signals go to the high-impedance state, except for the synchronous DRAM interface M_CKE signal and bus arbitration BACK signal, DACK0 to DACK3, and TEND0 to TEND3 which control DMA transfers. The actual bus release sequence is as follows. First, the bus use permission signal is asserted in synchronization with the rising edge of the clock. The address bus and data bus go to the high-impedance state in synchronization from next rising edge of the clock after this BACK assertion. At the same time, the bus control signals (BS, CSn, WEn, RD, RDWR, CE2A, and CE2B) go to the high-impedance state. These bus control signals are negated no later than one cycle before going to high-impedance. Bus request signal sampling is performed on the rising edge of the clock. The sequence for re-acquiring the bus from the slave is as follows. As soon as BREQ negation is detected on the rising edge of the clock, BACK is negated and bus control signal driving is started. Driving of the address bus and data bus starts at the next rising edge of an in-phase clock. The bus control signals are asserted and the bus cycle is actually started, at the earliest, at the clock rising edge at which the address and data signals are driven. In order to reacquire the bus and start execution of bus access, the BREQ signal must be negated for at least two cycles.
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Section 11 Local Bus State Controller (LBSC)
11.5.11 Cooperation between Master and Slave To enable system resources to be controlled in a harmonious fashion by master and slave, their respective roles must be clearly defined. When designing an application system that includes this LSI, all control, including initialization, and low power consumption control, are supposed to be carried out by this LSI. In a power-on reset, this LSI will not accept bus requests from the slave until the BREQ enable bit (BCR.BREQEN) is set to 1. To ensure that the slave processor does not access memory requiring initialization before use, write 1 to the BREQ enable bit only after this LSI has performed the initialization.
Rev. 1.00 Oct. 01, 2007 Page 408 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Section 12 DDR-SDRAM Interface (DDRIF)
The memory controller is a module that arbitrates accesses from the CPU and modules and outputs control signals for the DDR-SDRAM. This module allows direct connection with the DDRSDRAM. This module is provided with two interface modules (SHIF: SuperHyway bus interface and LCDIF: LCD interface) and one DDR-SDRAM controller (DDRC), and an arbiter (ARBT) that arbitrates accesses from interface modules to the DDRC.
12.1
* * * * * * *
Features
The data bus width of the DDRIF is 32 bits Supports DDR-SDRAM self-refreshing Supports the DDR266 (133MHz); DDR200 (100MHz) Efficient data transfer is possible using the SuperHyway bus (Internal bus) Supports a 4-bank DDR-SDRAM Supports a burst length of 2 Connectable memory size: 256 Mbits, 512 Mbits, 1 Gbit, and 2 Gbits Address x bit width (bit) for supported memory is as follows. DDR-SDRAM data bus width is 32 bits: Parallel connection of two 128-Mbit DDRs (x 16) (Total size 256-Mbits) Parallel connection of two 256-Mbit DDRs (x 16) (Total size 512-Mbits) Parallel connection of two 512-Mbit DDRs (x 16) (Total size 1-Gbit) Parallel connection of two 1-Gbit DDRs (x 16) (Total size 2-Gbits) * Big or little endian for external memory access can be switched at a power-on reset
Rev. 1.00 Oct. 01, 2007 Page 409 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Figure 12.1 shows a block diagram of the DDRIF.
From CPG
DLL
M_CLK0 M_CLK1 M_BKPRST M_CKE M_CS
DDRIF
LCDC
LCDC interface (LCDIF)
M_RAS Arbiter (ARBT) DDR-SDRAM controller (DDRC) DDR I/O M_CAS M_WE M_BA1, M_BA0 M_A13 to M_A 0 M_DQM3 to M_DQM0
SuperHyway (AHwy) bus
SuperHyway bus interface (SHIF)
M_DQS3 to M_DQS0 M_D31 to M_D0 M_VREF
Figure 12.1 DDRIF Block Diagram * The SuperHyway bus interface (SHIF) is an interface between the CPU and SDRAM. The SuperHyway bus protocol is used for interface. The bus width is 64 bits and the maximum operating frequency is 133 MHz. * The LCDC interface (LCDIF) is an interface with the LCDC. The bus width is 32 bits and the maximum operating frequency is 66 MHz. * The arbiter (ARBT) arbitrates SHIF that accesses the DDR-SDRAM and LCDIF requests among the requests from the abovementioned interfaces. * The DDR-SDRAM controller (DDRC) controls read/write accesses to the DDR-SDRAM. Commands are issued and read data is received according to the specified timing of the DDRSDRAM. Arbitration between the interfaces described above is performed with the priority order determination defined separately. The I/O block that drives the DDR-SDRAM interface signal and the register block related to the control of the DDR-SDRAM are included.
Rev. 1.00 Oct. 01, 2007 Page 410 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.2
Input/Output Pins
Table 12.1 shows the DDRIF pin configuration. For details on connection with the DDR-SDRAM, see the LSI pin information section. Note that clock-related signals will be determined later. Table 12.1 Pin Configuration
Pin Name M_CLK0 M_CLK1 M_CKE Function DDR-SDRAM clock DDR-SDRAM clock Clock enable I/O Output Output Output Description Clock output for DDR-SDRAM Clock output for DDR-SDRAM Inverted clock output of M_CLK0 When this pin goes high, the clock signal is active. When this pin goes low, the clock signal is inactive. Chip select output Write enable output Row/column address Bank address output Data I/O I/O data strobe I/O data mask signal Row address strobe signal Column address strobe signal When this pin goes low, the M_CKE pin shall go low Input reference voltage
M_CS M_WE M_A13 to M_A0 M_BA1, M_BA0 M_D31 to M_D0
Chip select Write enable Address Bank active Data
Output Output Output Output I/O I/O Output Output Output Input Input
M_DQS3 to M_DQS0 I/O data strobe M_DQM3 to M-DQM0 Data mask M_RAS M_CAS M_BKPRST M_VREF Row address strobe Column address strobe Power back-up reset Reference voltage input
Rev. 1.00 Oct. 01, 2007 Page 411 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.3
12.3.1
Data Conversion
Data Alignment
Data Alignment in DDR-SDRAM: The DDRIF supports both big endian mode where an address of the upper byte is 0 and little endian mode where an address of the lower byte is 0. These modes can be switched by using external pins at a power-on reset. The data alignment shown in the following tables is used when access is made from the peripheral modules. The data alignment in little endian mode differs from that in the physical memory map of the DDR-SDRAM. Table 12.2 Access and Data Alignment in Little Endian Mode (External Bus Width is 32 Bits)
M_D31 to M_D24 M_D23 to M_D16 M_D15 to M_D8 Byte access at address 0 Byte access at address 1 Byte access at address 2 Byte access at address 3 Byte access at address 4 Byte access at address 5 Byte access at address 6 Byte access at address 7 Word access at address 0 Word access at address 2 Word access at address 4 Word access at address 6 Data 15 to 8 Data 7 to 0 Data 23 to 16 Data 23 to 16 Data 23 to 16 Data 55 to 48 Data 15 to 8 Data 15 to 8 Data 15 to 8 Data 47 to 40 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 39 to 32 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 M_D7 to M_D0 Data 7 to 0
Longword access at address 0 Data 31 to 24 Longword access at address 4 Data 31 to 24 Quadword access at address 0 Data 31 to 24 (first time: address 0) Quadword access at address 0 Data 63 to 56 (second time: address 4)
Rev. 1.00 Oct. 01, 2007 Page 412 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Table 12.3 Access and Data Alignment in Big Endian Mode (External Bus Width is 32 Bits)
M_D31 to M_D24 M_D23 to M_D16 M_D15 to M_D8 Byte access at address 0 Byte access at address 1 Byte access at address 2 Byte access at address 3 Byte access at address 4 Byte access at address 5 Byte access at address 6 Byte access at address 7 Word access at address 0 Word access at address 2 Word access at address 4 Word access at address 6 Longword access at address 0 Longword access at address 4 Data 31 to 24 Data 31 to 24 Data 23 to 16 Data 23 to 16 Data 55 to 48 Data 23 to 16 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 15 to 8 Data 15 to 8 Data 47 to 40 Data 15 to 8 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 39 to 32 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 M_D7 to M_D0
Quadword access at address 0 Data 63 to 56 (first time: address 0) Quadword access at address 0 Data 31 to 24 (second time: address 4)
Rev. 1.00 Oct. 01, 2007 Page 413 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.3.2
Data Alignment in Peripheral Modules
The endian mode in the DDRIF matches that in the CPU, and both big endian and little endian are available.
Bit 31
DDR-SDRAM 32-bit
Bit 0
(Address A + 0)
(Address A + 4)
(Address A + 8) (Address A + 12)
Time
Example of memory address A[3:0] = (0000) Other than the above, the DDRC wraps around the data on command boundaries.
Write
read
Little Wndian
big endian
63 32 31 0 (Address A + 4) (Address A + 0)
Time
63 32 31 0 (Address A + 0) (Address A + 4)
(Address A + 8) (Address A + 12)
Time
64-bit width
(Address A + 12) (Address A + 8)
Figure 12.2 Data Alignment in DDR-SDRAM and DDRIF
Rev. 1.00 Oct. 01, 2007 Page 414 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.4
Register Descriptions
Table 12.4 shows the DDRIF registers. These registers should be set when access is not made to the DDR-SDRAM from peripheral modules. When the access is not made and the DCE bit (DDR-SDRAM control enable) in the memory interface mode register is cleared to 0 or the SELFS bit (self-refresh status) in that register is set to 1, set other registers. Although the bit width for registers is 64 bits, access the registers in longwords (32 bits). Writing to this register is reflected in longwords. Reading this register returns a current longword value. In big endian mode, when accessing bits 63 to 32, specify address 8n + 0. When accessing bits 31 to 0, specify address 8n + 4. Table 12.4 Register Configuration
Register Name Abbreviation R/W R/W R/W R/W R/W (W) R Area P4 Address*1 H'FE80 0008 H'FE80 0010 H'FE80 0018 H'FE80 0030 Area 7 Address*1 H'1E80 0008 H'1E80 0010 H'1E80 0018 H'1E80 0030 Access Size 32 32 32 32
Memory interface mode register MIM DDR-SDRAM control register DDR-SDRAM timing register DDR-SDRAM row attribute register DDR-SDRAM mode register DDR-SDRAM back-up register SCR STR SDR SDMR DBK
H'FE9x xxxx*2 H'1E9x xxxx*2 32 H'FE80 0400 H'1E80 0400 32
Notes: 1. P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB. 2. For details, see section 12.4.5, DDR-SDRAM Mode Register (SDMR).
Rev. 1.00 Oct. 01, 2007 Page 415 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Table 12.5 Register State in Each Operating Mode
Register Name Memory interface mode register DDR-SDRAM control register DDR-SDRAM timing register DDR-SDRAM row attribute register DDR-SDRAM mode register Power-On Abbreviation Reset MIM SCR STR SDR SDMR Manual Reset Sleep Standby Retained Retained Retained Retained Only writing Retained
H'0000 0000 H'0000 0000 Retained 0C34 xx00*1 0C34 xx00*1 H'0000 0000 H'0000 0000 Retained 0000 0000 0000 0000 H'0000 0000 H'0000 0000 Retained 0000 0000 0000 0000 H'0000 0000 H'0000 0000 Retained 0000 0100 0000 0100 Only writing Only writing Only writing H'0000 0000 H'0000 0000 Retained 0000 000x*2 0000 000x*2
DDR-SDRAM back-up register DBK
Notes: 1. The initial value of bit 8 (ENDIAN bit) depends on the setting of external pins (MD5). 2. The initial value of bit 0 (SDBUP bit) depends on the setting of external pin (M_BKPRST).
All bits are active-high signals and are initialized by a reset unless otherwise specified. All access is made in longwords using the SuperHyway bus.
Rev. 1.00 Oct. 01, 2007 Page 416 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.4.1
Bit:
Memory Interface Mode Register (MIM)
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
Initial value: R/W: Bit:
0 R 47
0 R 46
0 R 45
0 R 44
PC KE
0 R 43
0 R 42
0 R 41
0 R 40
0 R 39
0 R 38
0 R 37
0 R 36
0 R 35
0 R 34
SEL FS
0 R 33
R MODE
0 R 32
BOMODE
Initial value: R/W: Bit:
0 R/W 31
0 R/W 30
0 R 29
0 R/W 28
0 R 27
0 R 26
0 R 25
0 R 24
0 R 23
0 R 22 DRI[12:0]
0 R 21
0 R 20
0 R 19
0 R 18
0 R/W 17
0 R 16
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R/W 12
1 R/W 11
1 R/W 10
0 R/W 9 DRE
0 R/W 8
END IAN
0 R/W 7
0 R/W 6
1 R/W 5
1 R/W 4
0 R/W 3
DLLEN
1 R/W 2
0 R/W 1
0 R/W 0 DCE
LOCK
Initial value: R/W:
R
R
R
R
0 R
0 R
0 R/W
R
0 R
0 R
0 R
0 R
0 R/W
0 R
0 R
0 R/W
Note: * Depends on the setting of external pins (MD5).
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
63 to 49
48
0
R
Reserved This bit is always read as 0. The write value should always be 0.
47, 46
BOMODE1, All 0 BOMODE0
R/W
Access Mode Switch Switch access modes for the DDR-SDRAM. The DDRIF supports two DDR-SDRAM access modes. For details on the operation in each mode, see section 12.5.4, DDR-SDRAM Access Mode. 00: Bank open mode 01: Bank close mode Other than above: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 417 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Bit 45
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
44
PCKE
0
R/W
Power Down When the DDR-SDRAM is not accessed (in the idle state or bank active state), this bit sets the CKE pin low and the power-down mode is entered. When this bit is set to 1, the power-down mode is entered to reduce the DDR-DSRAM power consumption. For details, see section 12.5.5, Power-Down Modes. Note that the setting for enabling the CKE pin by the SMS bit in SCR is used for DDR-SDRAM initialization.
43 to 35
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
34
SELFS
0
R
Self-Refresh Decision Decides whether the DDR-SDRAM is in the self-refresh state. When this bit is set to 1, the DDR-SDRAM is in the self-refresh state. When this bit is cleared to 0, the DDR-SDRAM is not in the self-refresh state.
33
RMODE
0
R/W
Refresh Mode Select Specifies whether auto-refresh mode or self-refresh mode is set to the DDR-SDRAM. This bit is valid only when the DRE bit in MIM is set to 1. 0: Auto-refresh mode 1: Self-refresh mode
32 to 29
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 418 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Bit
Bit Name
Initial Value H'0C34
R/W R/W
Description DRAM Refresh Interval When refreshing is valid (the DRE bit in MIM is set to 1), these bits specify the maximum refresh interval (auto refresh). One count is the same as the cycle of the memory clock. At 133-MHz operation, one count corresponds to 7.5 ns. The minimum settable value is H'020. When a value less than H'020 is set, H'020 is added to the count value. The DDRIF has a 13-bit internal counter. When the DCE or DRE bit is cleared to 0, or the RMODE bit is set to 1, this counter is cleared to 0. Otherwise, this counter will increment by the external memory clock. This counter is compared with the DRI bit. If a match occurs, an auto-refresh request is generated in the controller and auto-refreshing is performed. Note that the counter is cleared to 0 at the match and then begins incrementing again. The single auto-refresh request that has been generated is recorded (max.). When the DCE and DRE bits are set to 1 and the RMODE bit is cleared to 0, an auto-refresh request is not cleared until auto refreshing is performed. To set this bit, the DRE bit should be cleared to 0 and should be written to, and then 1 should be written to the DRE bit. In this case, the previous written value should be set to the DRI bits.
28 to 16 DRI
15 to 12 LOCK
Undefined
R
DLL Lock Status These bits indicate the lock status of the DLL for generating the read timing for the DDR-SDRAM. When these bits are all set to 1, access to memory is possible.
11, 10
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9
DRE
0
R/W
DRAM Refresh Enable Sets whether the refresh mode is valid or invalid. 1: Valid 0: Invalid
Rev. 1.00 Oct. 01, 2007 Page 419 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Bit 8
Bit Name ENDIAN
Initial Value Undefined
R/W R
Description Endian Identification Indicates whether the big endian mode or little endian mode is set to the external data bus. 1: Big endian mode 0: Little endian mode
7 to 4
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
3
DLLEN
0
R/W
DLL Enable Sets whether the DLL for generating the read timing for the DDR-SDRAM is valid or invalid. When this bit is set to 1, the DLL is enabled and read access to memory is possible.
2, 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
DCE
0
R/W
DDR Controller Enable Enables SDRAM control by the DDRIF. 1: Enable 0: Disable
Rev. 1.00 Oct. 01, 2007 Page 420 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.4.2
Bit:
DDR-SDRAM Control Register (SCR)
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 47
Initial value: R/W: Bit:
0 R 47
0 R 46
0 R 45
0 R 44
0 R 43
0 R 42
0 R 41
0 R 40
0 R 39
0 R 38
0 R 37
0 R 36
0 R 35
0 R 34
0 R 33
0 R 32
Initial value: R/W: Bit:
0 R 31
0 R 30
0 R 29
0 R 28
0 R 27
0 R 26
0 R 25
0 R 24
0 R 23
0 R 22
0 R 21
0 R 20
0 R 19
0 R 18
0 R 17
0 R 16
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1 SMS
0 R 0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
Rev. 1.00 Oct. 01, 2007 Page 421 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Bit 63 to 3
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
SMS
000
R/W
SDRAM Mode Select These bits initialize the DDR-SDRAM at a power-on or after release of a reset. If this bit is set by software, the following commands are issued. For details on the initialization procedure, see section 12.5.2, DDRSDRAM Initialization Sequence. After the DDRSDRAM has been initialized, normal operation (000) is specified. 000: Normal operation 001: The NOP command is issued (valid only when the DCE bit in MIM is set to 1). 010: The PREALL command is issued (valid only when the DCE bit in MIM is set to 1). 011: The M_CKE pin is enabled. At that time, the DESELECT command is issued (valid only when the DCE bit in MIM is set to 1). 100: The REFA (auto) refresh command is issued (valid only when the DCE bit in MIM is set to 1). Settings other than above are prohibited. If such settings are made, correct operation is not guaranteed. Note that setting the M_CKE pin low by the PCKE bit in MIM is used to reduce the DDR-SDRAM power consumption.
Rev. 1.00 Oct. 01, 2007 Page 422 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.4.3
DDR-SDRAM Timing Register (STR)
STR specifies the DDR-SDRAM timing. (Details on the number range depend on the parameters used by each memory manufacturer.
Bit:
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
47
Initial value: R/W: Bit:
0 R 47
0 R 46
0 R 45
0 R 44
0 R 43
0 R 42
0 R 41
0 R 40
0 R 39
0 R 38
0 R 37
0 R 36
0 R 35
0 R 34
0 R 33
0 R 32
Initial value: R/W: Bit:
0 R 31
0 R 30
0 R 29
0 R 28
0 R 27
0 R 26
0 R 25
0 R 24
0 R 23
0 R 22
0 R 21
0 R 20
0 R 19 WR
0 R 18
0 R 17 RW 0 R/W 1
0 R 16
Initial value: R/W: Bit:
0 R 15
0 R 14 SRFC
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9 SRAS
0 R 8
0 R 7
0 R 6 SRC
0 R 5
0 R 4
0 R/W 3 SCL
0 R/W 2
0 R/W 0
SWR SRRD 0 R/W 0 R/W 0 R/W 0 R/W
SRCD SRP 0 R/W 0 R/W 0 R/W
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
63 to 20
19, 18
WR
00
R/W
Minimum Number of Cycles from Write command to Read Commands These bits specify the minimum number of cycles for the READ command issuance after the WRITE command is issued for the DDR-SDRAM. 00: 3 cycles 01: 4 cycles 10: 5 cycles 11: 6 cycles
Rev. 1.00 Oct. 01, 2007 Page 423 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Bit 17, 16
Bit Name RW
Initial Value 00
R/W R/W
Description Minimum Number of Cycles from Read command to Write Commands These bits specify the minimum number of cycles for the WRITE command issuance after the READ command is issued for the DDR-SDRAM. 00: 3 cycles 01: 4 cycles 10: 5 cycles 11: 6 cycles
15 to 13 SRFC
000
R/W
Number of Cycles in Same Bank These bits specify the number of cycles in the same bank for the following access times (Trfc). (1) From auto refresh to ACT command issuance (2) From auto refresh to auto refresh 000: 11 cycles 001: 12 cycles 010: 13 cycles 011: 14 cycles 100: 15 cycles Other than above: Setting prohibited
12
SWR
0
R/W
PRE/PREALL Command Issuance Cycle Specifies the number of cycles from the last postamble to PRE/PREALL command issuance in a write cycle (Twr). 0: 2 cycles 1: 3 cycles
11
SRRD
0
R/W
ACT Command Issuance Cycle between Banks Specifies the minimum number of cycles from ACT command issuance to ACT command issuance between different banks (Trrd). 0: 2 cycles 1: 3 cycles
Rev. 1.00 Oct. 01, 2007 Page 424 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Bit 10 to 8
Bit Name SRAS
Initial Value 000
R/W R/W
Description Minimum Number of Cycles between ACT and PRE Commands These bits specify the minimum number of cycles from ACT command issuance to PRE command issuance in the same bank (Tras). 000: 6 cycles 001: 7 cycles 010: 8 cycles 011: 9 cycles Other than above: Setting prohibited
7 to 5
SRC
000
R/W
Auto-Refresh/ACT Command Issuance Cycle These bits specify the number of cycles in the same bank for the following access times (Trc). (1) From ACT command issuance to auto refresh (2) From ACT command issuance to ACT command issuance 000: 6 cycles 001: 7 cycles 010: 8 cycles 011: 9 cycles 100: 10 cycles 101: 11 cycles 110: 12 cycles 111: 13 cycles Other than above: Setting prohibited
4 to 2
SCL
000
R/W
CAS Latency These bits specify the CAS latency (CL) in data read. 000: 2.5 cycles The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 425 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Bit 1
Bit Name SRCD
Initial Value 0
R/W R/W
Description Number of Cycles between RAS and CAS Commands Specifies the number of cycles from RAS (ACT) command issuance to CAS (READ/READA, WRITE/WRITEA) command issuance (Trcd). 0: 3 cycles 1: 4 cycles
0
SRP
0
R/W
Number of Cycles between PRE and ACT Commands Specifies the number of cycles from PRE command issuance to ACT command issuance (Trp). 0: 3 cycles 1: 4 cycles
12.4.4
Bit:
DDR-SDRAM Row Attribute Register (SDR)
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 47
Initial value: R/W: Bit:
0 R 47
0 R 46
0 R 45
0 R 44
0 R 43
0 R 42
0 R 41
0 R 40
0 R 39
0 R 38
0 R 37
0 R 36
0 R 35
0 R 34
0 R 33
0 R 32
Initial value: R/W: Bit:
0 R 31
0 R 30
0 R 29
0 R 28
0 R 27
0 R 26
0 R 25
0 R 24
0 R 23
0 R 22
0 R 21
0 R 20
0 R 19
0 R 18
0 R 17
0 R 16
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
SPLIT
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
1 R/W
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Rev. 1.00 Oct. 01, 2007 Page 426 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
63 to 12
11 to 8
SPLIT
0001
R/W
DDR-SDRAM Memory Configuration These bits specify the DDR-SDRAM row/column configuration. 0001: 12 x 9 (= 8 M x 16 bits product) 0011: 13 x 9 (= 16 M x 16 bits product) 0100: 13 x 10 (= 32 M x 16 bits product) 0110: 14 x 10 (= 64 M x 16 bits product) Other than above: Setting prohibited The relationship between the SPLIT bits and row/column is shown in section 12.5.12, Address Multiplexing.
7 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
12.4.5
DDR-SDRAM Mode Register (SDMR)
SDMR is used to set the DDR-SDRAM mode register and extended mode register. Since SDMR is not physically contained in the DDRIF, reading this register is invalid. Only write addresses have a meaning for the DDR-SDRAM and the write data is ignored. When SDMR is written to, signals are output to pins connected to the DDR-SDRAM according to the table shown below. Address bits 12 to 3 correspond to external pins M_A9 to M_A0, address bits 14 and 13 to external pins M_BA1 and M_BA0, and address bits 18 to 15 to external pins M_A13 to M_A10.
M_CKE n-1 H n H M_CS L M_RAS L M_CAS L M_WE L Address Bit Correspondence M_BA1 and M_A13 to M_A9 to M_BA0 M_A10 M_A0 Bits 14 and 13 Bits 18 to Bits 12 to 15 3
Rev. 1.00 Oct. 01, 2007 Page 427 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Figure 12.3 shows the relationship between write values in SDMR and output signals to the memory pins.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11111110100100000000001100001000
SDRAM address
DDR-SDRAM
H L L L L H H L L L L L L L L L M_CS M_RAS M_CAS M_WE L L L L MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 BA0 BA1 CS RAS CAS WE
L: Low level H: High level
Figure 12.3 Relationship between Write Values in SDMR and Output Signals to Memory Pins For example, when the DLL reset release, CAS latency of 2.5 cycles, sequential burst sequence, and burst length of 2 are set to the mode register in the DDR-SDRAM, the following signals must be output to the DDR-SDRAM pins. CS = low, RAS = low, CAS = low, WE = low, BA0 = low, BA1 = low, MA13/MA12/MA11/MA10/MA9 = low, MA8 = low, MA7 = low, MA6 = high, MA5 = high, MA4 = low, MA3 = low, MA2 = low, MA1 = low, and MA0 = high To output the above control signals, write access to address H'FE90 0308 in SDMR is made in longwords. Then the above control signals are output to the DDR-SDRAM pins. Write data to SDMR is Don't care.
Rev. 1.00 Oct. 01, 2007 Page 428 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.4.6
DDR-SDRAM Back-up Register (DBK)
This register indicates the DDR-SDRAM back-up status. For details, see section 18, Power-Down Mode.
Bit:
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
47
Initial value: R/W: Bit:
0 R 47
0 R 46
0 R 45
0 R 44
0 R 43
0 R 42
0 R 41
0 R 40
0 R 39
0 R 38
0 R 37
0 R 36
0 R 35
0 R 34
0 R 33
0 R 32
Initial value: R/W: Bit:
0 R 31
0 R 30
0 R 29
0 R 28
0 R 27
0 R 26
0 R 25
0 R 24
0 R 23
0 R 22
0 R 21
0 R 20
0 R 19
0 R 18
0 R 17
0 R 16
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
SDBUP
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
R
Bit 63 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
SDBUP
Undefined*
R
Determine whether DDR-SDRAM is battery back-up or not 0: Battery back-up 1: Not back-up
Note:
*
Depends on the setting of external pin BKPRST.
Rev. 1.00 Oct. 01, 2007 Page 429 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.5
12.5.1
Operation
DDR-SDRAM Access
The DDR-SDRAM is accessed with a burst length of 2. Read or write commands that hit the page are issued continuously and read data continuously.
Write command
ACT
WR Write data
WR
WR
WR
D
D
D
D
D
D
D
D
read command
ACT
RD read data
RD
RD
RD
D
D
D
D
D
D
D
D
Figure 12.4 DDR-SDRAM Access 12.5.2 DDR-SDRAM Initialization Sequence
Since the internal state of the DDR-SDRAM is undefined immediately after a power-on, initialize the SDRAM according to the following sequence. Otherwise the device may be damaged. An example of the initialization sequence for the DDR-SDRAM is shown below. For details, see each memory manufacturer's datasheet. 1. Turn on the four power supplies to the DDR-SDRAM in the following order: VDD, VDDQ, VREF, and VTT. 2. After the power supply, reference voltage, and clock are stabilized, maintain the current state for at least 200 s. 3. Perform a dummy read to any DDR-SDRAM address. 4. Set MIM to enable the DDR-SDRAM controller, set the endian mode, and so on. 5. Set SDR and STR. 6. Use the SMS field in SCR to enable the CKE pin. 7. Use the SMS field in SCR to issue the all-bank precharge (PREALL) command. 8. Use SDMR to issue the EMRS command and enable the DLL.
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Section 12 DDR-SDRAM Interface (DDRIF)
9. Use SDMR to issue the MRS command and reset the DLL. Also set the burst length, CAS latency, and so on. 10. After the PREALL command is issued, use the SMS field in SCR to issue the REF command twice. 11. Use SDMR to issue the MRS command, release the DLL reset (MA8 = low), and determine the operating mode. In this case, use the setting for the burst length, etc. that was specified in step 8. 12. After the DLL is reset, wait for 200 cycles of the memory clock: normal memory access will then be possible. Match the SDMR setting, etc. of the DDR-SDRAM with the register settings of the DDRIF.
Rev. 1.00 Oct. 01, 2007 Page 431 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.5.3
Supported DDR-SDRAM Commands
Table 12.6 shows the DDR-SDRAM commands supported by the DDRIF. Table 12.6 DDR-SDRAM Commands Issued by DDRIF
MA13 to MA11 X X V V V V V X X X X BA1 AP and (MA10) BA0 X X L H L H V L H X X X X V V V V V V X X X MA9 to MA0 X X V V V V V X X X X
Function Device deselect No operation Read
Symbol DESL NOP READ
CKEn - 1 CKEn CS H H H H H H H H H H H X X X X X X X X X H L H L L L L L L L L L L
RAS X H H H H H L L L L L
CAS X H L L L L H H H L L
WE X H H H L L H L L H H
Read with auto precharge READA Write WRITE
Write with auto precharge WRITEA Bank activate Precharge select bank Precharge all banks Auto refresh Self-refresh entry from IDLE Self-refresh exit Power-down entry Power-down exit Mode register set REFSX PWRDN PWRDNX MRS/ EMRS ACT PRE PREALL REFA REFS
L H L H
H L H X
H H H L
X X X L
X X X L
X X X L
X X X V
X X X V
X X X V
X X X V
[Legend] H: High level L: Low level X: High level or low level (either is acceptable) V: Valid data
The DESL command in table 12.6 is issued when the DDR-SDRAM is not accessed by modules. The DESL command therefore cannot be issued by the user.
Rev. 1.00 Oct. 01, 2007 Page 432 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.5.4
DDR-SDRAM Access Mode
The DDRIF supports the following two DDR-SDRAM access modes. Each mode can be set using the BOMODE bits in MIM. Bank Open Mode: The DDR-SDRAM is accessed without the PRE command immediately after memory read or memory write, meaning that the bank is always open. This mode is useful for applications in which bank hits continue to occur during consecutive memory accesses. When a bank miss occurs, the PRE command is automatically issued. Bank Close Mode: Immediately after memory read or memory write, the PRE command is output and the bank is closed. This mode is useful for applications in which a bank hit does not continue to occur in consecutive memory accesses. 12.5.5 (1) Power-Down Modes
Self-Refresh Mode
The self-refresh mode is a standby state where the refresh timing and refresh addresses are generated in the DDR-SDRAM. The self-refresh state is retained even if the CPU enters the sleep mode after the self-refresh mode is set by setting the DRE and RMODE bits in MIM to 1. If the sleep mode of CPU is canceled due to an interrupt, the self-refresh state is retained. Although the self-refresh state is entered through the register setting of the DDRIF, the following sequence should be used. [Transition to self-refresh state] 1. Confirm that the transaction to the memory controller is completed. 2. Through software control, set the SMS bits in SCR to issue the PREALL command. This closes any DDR-SDRAM bank that was open. After that, use the SMS bits in SCR to issue the REFA (auto-refresh) command to perform concentrated refresh on all memory rows ((REFA) (REFA) (REFA)). The STR settings do not establish a relationship between the timing of the PREALL and REFA commands that are issued by using SCR. A period of waiting that is suitable for the memory unit must be inserted by software. At that time, if concentrated refresh is necessary, execute the REFA command. 3. To make the DDR-SDRAM enter the self-refresh state, set the DRE and RMODE bits in MIM. (In this case, the DCE bit should remain at 1.) 4. The memory controller automatically issues the self-refresh command and set the CKE pin low. The DDR-SDRAM then automatically enters the power-down mode.
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Section 12 DDR-SDRAM Interface (DDRIF)
5. Whether the DDR-SDRAM enters the self-refresh mode can be checked by reading the SELFS bit in MIM. [Recovery from self-refresh state] 1. Clear the RMODE and DRE bits in MIM to 0 to clear the self-refresh state. 2. Whether the DDR-SDRAM recovers from the self-refresh mode can be checked by reading the SELFS bit in MIM. 3. After the self-refresh state is cleared, wait for the time required by the DDR-SDRAM before accessing the DDR-SDRAM (130 ns before issuing a command other than read and 200 clock cycles before issuing a read command). 4. When access becomes possible, use the SMS bits in SCR to issue the REFA command so that the concentrated refresh (REFA) is performed on all memory rows. 5. Dummy read a byte from any address. 6. Use the SMS bits in SCR to issue the PREALL command. 7. Use the SMS bits in SCR to issue the REFA command. This operation is required to make the delay adjustment unit in the memory controller operate. 8. Set MIM so that the counter for the auto-refresh function starts counting and thus drives autorefreshing at a regular interval. After this, normal memory access is possible. (2) Power-Down Mode (when CKE Goes Low)
When the PCKE bit in MIM is set, the CKE pin level is automatically changed and the DDRSDRAM then enters or leaves the power-down mode. This mode reduces DDR-SDRAM power consumption. Since the DDR-SDRAM enters the power-down mode after a memory access and leaves the power-down mode before a memory access, an overhead of one cycle in the external memory clock occurs in each case. 12.5.6 Registers that Set DDR-SDRAM Timing Restrictions
Registers that support connection to memory other than the DDR-SDRAM in a conventional microcomputer and registers that set timing restrictions for the DDR-SDRAM of the DDRIF differ with regard to the setting of the memory timing restrictions. The DDRIF registers are specialized with respect to the DDR-SDRAM timing restrictions. For details, see section 12.4, Register Descriptions.
Rev. 1.00 Oct. 01, 2007 Page 434 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.5.7
Operating Frequency
The DDRIF is supported only when the clock ratio between the SuperHyway bus clock and the external memory clock is 1:1 (DDR266 or DDR200). The maximum operating frequency for the SuperHyway bus is 133 MHz. The minimum operating frequency depends on the DDR-SDRAM clock frequency. Therefore see the DDR-SDRAM datasheet. 12.5.8 Note on Clock Stop
The clock supplied to the DDRIF is stopped in the following three modes: * DDR-SDRAM power supply backup mode * Software standby mode * RTC power supply backup mode Since the clock is not supplied in the above cases, auto-refreshing is not performed. As a result, the refresh cycle is not held and then the DDR-SDRAM data will be damaged. To prevent this, the DDR-SDRAM should enter the self-refresh state through software before the clock supply is stopped. For details on entering/canceling the self-refresh mode, see section 12.5.5 (1), SelfRefresh Mode. 12.5.9 Using SCR to Issue REFA Commands (Outside the Initialization Sequence)
This memory controller automatically opens the DDR-SDRAM bank by memory access (read/write). When issuing the REFA command with the SMS bits in SCR, be sure to close the bank by issuing the PREALL command with the SMS bits in SCR. This operation is also necessary when SCR is used to perform concentrated refresh (REFA) on all rows in the memory before self-refresh operations. 12.5.10 Note on Timing of Connected DDR-SDRAM This memory controller only supports memory in which the number of cycles (tRAP) required from issuing an ACT command to issuing a read or write with auto-precharge command and the number of cycles (tRDC) required from issuing an ACT command to issuing a read or write command are the same. If the two numbers differ, the DDR-SDRAM should be accessed in bankopen mode.
Rev. 1.00 Oct. 01, 2007 Page 435 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.5.11 Note on Setting Auto-Refresh Interval The auto-refresh interval is specified by the DRI bits in MIM. If the DRE bit is set to 1 at the same time as the DRI bits are set, the time until the first auto-refresh is that selected by the value of the DRI bits before the new setting was made. However, the second and subsequent auto-refresh intervals take on the value corresponding to the new setting for the DRI bits. To avoid this situation, clear the DRE bit to 0 when setting the DRI bits. When the DRE bit is subsequently set to 1, auto-refreshing proceeds with the specified interval from the first round. When writing 1 to the DRE bit, the previously written cycle number should be set to the DRI bits. 12.5.12 Address Multiplexing Address multiplexing is performed so that the DDR-SDRAM is connected without the external address multiplexing circuit according to the setting of the BW bits in MIM and the SPLIT bits in SDR. Table 12.7 shows the relationship between the DDR-SDRAM bus width and the addresses that are output to the address pins according to the setting of the SPLIT bits. If a setting not specified in table 12.7 is used, correct operation is not guaranteed. Table 12.7 DDR-SDRAM Address Multiplexing (32-Bit Data Bus)
SPLIT[3:0] ROW x COL M_ BA1 M_ BA0 M_ A13 M_ A12 M_ A11 M_ A10 M_ A9 M_ A8 M_ A7 M_ A6 M_ A5 M_ A4 M_ A3 M_ A2 M_ A1 M_ A0
128 M bits x 2 (8 M x 16-bit x 2) 256 M bits x 2 (16 M x 16-bit x 2) 512 M bits x 2 (32 M x 16-bit x 2) 1 G bits x 2 (64 M x 16-bit x 2)
0001
12 x 9
ROW COL
13 13 13 13 13 13 13 13
12 12 12 12 12 12 12 12
-- -- -- -- -- -- 27 --
-- -- 11 -- 26 -- 26 --
11 25 25 25
24 24 24 24
23 23 23 23
22 10 22 10 22 10 22 10
21 9 21 9 21 9 21 9
20 8 20 8 20 8 20 8
19 7 19 7 19 7 19 7
18 6 18 6 18 6 18 6
17 5 17 5 17 5 17 5
16 4 16 4 16 4 16 4
15 3 15 3 15 3 15 3
14 2 14 2 14 2 14 2
-- AP* -- -- AP* -- -- AP* 11 -- AP* 11
0011
13 x 9
ROW COL
0100
13 x 10
ROW COL
0110
14 x 10
ROW COL
Note:
*
Auto-precharge
12.5.13 DDR-SDRAM Access Arbitration (1) Priority Order of Access Arbitration
The DDRIF has the access arbitration function that arbitrates accesses to the DDR-SDRAM between the CPU and the LCDC. The priority order of the arbitration is divided in the following two levels.
Rev. 1.00 Oct. 01, 2007 Page 436 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
At level 0, DDR-SDRAM controls such as DDR-SDRAM refresh and page management have the highest priority. The memory is refreshed according to the memory refresh intervals specified separately. At level 1, access is rotated between access from the SHway bus and access from the LCDC (in round-robin method). However, immediately after a reset, access from the SHwy bus has priority over access from the LCDC. Access is not arbitrated based on the order of requests but by a request signal that is asserted between transactions. When read and write requests are made for the same device simultaneously, a read request has priority. Access arbitration is performed between transactions. (2) Access Arbitration When Burst and Non-Burst Transfers Coexist
The arbiter block receives inputs from the SHwy bus with the 133*1 MHz interface and the LCDC with the 66*2 MHz interface. Therefore, arbitration operation differs depending on a burst and non-burst transfers * In burst transfers, an arbitrated module can perform continuous transfers. Therefore, the SHwy bus and the LCDC have the same possibility of being arbitrated. * In non-burst transfers, arbitration is performed in 133*1 MHz units. Requests are continuously output to the DDRC. However, in actuality, burst and non-burst transfers coexist. Signals output from the interfaces are used to determine whether a burst transfer is expected or not. When making arbitration from nonburst transfers to burst transfers, if the arbitrated transaction is a burst transfer, the non-burst transfer is continued after the burst transfer. Notes: 1. This indicates the clock frequency when DDR266-SDRAM is used. The clock frequency is 100 MHz when DDR200-SDRAM is used. 2. This indicates the clock frequency when DDR266-SDRAM is used. The clock frequency is 50 MHz when DDR200-SDRAM is used. 12.5.14 Coherency When Accessing DDR-SDRAM In some cases, writing the DDR-SDRAM via the SHwy bus by software may be held for some reason and reading the DDR-SDRAM by the subsequently activated LCDC may be executed first. That is, incorrect operation may occur if coherency for accessing the DDR-SDRAM is not guaranteed. In this case, execute the SYNCO instruction between the write instruction for the DDR-SDRAM by software and the LCDC activation instruction. When the SYNCO instruction is executed, the next instruction is not activated until the data access being performed is completed.
Rev. 1.00 Oct. 01, 2007 Page 437 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
12.6
DDRIF Basic Timing
Figures 12.5 to 12.14 show examples of basic DDRIF timing. In every figure, the DDR-SDRAM is idle at T0. The various timings should be set in the STR register within the range specified by the DDRSDRAM used. Note that the DDRIF only supports 2.5-cycle CAS latency (CL).
T0
(MCLK) MCLK CKE Command ACT READ
PRE
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
tRCD (SRCD = 1)
MA9-0 MA13-11 MA10 BA1-0 MCS MRAS MCAS MWE MDQS CL = 2.5 MDA MDQM
D0 D1 Hi-Z
Row
Col 0
Row
Bank
Bank
Bank
Hi-Z
Figure 12.5 Basic DDRIF Timing (1 Burst Read: 1, 2, 4, or 8 Bytes; Without AutoPrecharge)
Rev. 1.00 Oct. 01, 2007 Page 438 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
T0
(MCLK) MCLK CKE Command ACT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
WRITE
PRE
tRCD (SRCD = 1)
MA9-0 MA13-11 MA10 BA1-0 MCS MRAS MCAS MWE MDQS MDA MDQM
D0 D1 Hi-Z
Hi-Z
Row
Row Bank
Col 0
Bank
Bank
Figure 12.6 Basic DDRIF Timing (1 Burst Write: 1, 2, 4, or 8 Bytes; Without AutoPrecharge)
Rev. 1.00 Oct. 01, 2007 Page 439 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
T0
(MCLK) MCLK CKE Command ACT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
READA
ACT
tRC (SRC = 011) tRCD (SRCD = 1) tRAS (SRAS = 000) tRP (SRP = 0)
MA9-0 MA13-11 MA10 BA1-0 MCS MRAS MCAS MWE MDQS MDA MDQM
Row Row Bank
Col 0
Row
Row
Bank
Bank
Hi-Z
CL = 2.5
D0 D1
Hi-Z
Figure 12.7 Basic DDRIF Timing (1 Burst Read: 1, 2, 4, or 8 Bytes; With Auto-Precharge)
Rev. 1.00 Oct. 01, 2007 Page 440 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
T0
(MCLK) MCLK CKE Command ACT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
WRITEA
ACT
tRC (SRC = 101) tRCD (SRCD = 1) tRAS (SRAS = 010) tWR (SWR = 0) tRP (SRP = 0)
MA9-0 MA13-11 MA10 BA1-0 MCS MRAS MCAS MWE MDQS MDA MDQM
D0 D1 Hi-Z Hi-Z
Row Row Bank
Col 0
Row Row
Bank
Bank
Figure 12.8 Basic DDRIF Timing (1 Burst Write: 1, 2, 4, or 8 Bytes; With Auto-Precharge)
Rev. 1.00 Oct. 01, 2007 Page 441 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
T0 (MCLK) MCLK CKE Command ACT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
READ READ READ READ tRCD (SRCD = 1)
PRE
MA9-0 MA13-11 MA10 BA1-0 MCS MRAS MCAS MWE MDQS
Row Row Bank
Col 0 Col 2 Col 4 Col 6
Bank Bank Bank Bank
Bank
Hi-Z CL = 2.5 Hi-Z D0 D1 D2 D3 D4 D5 D6 D7
MDA MDQM
Figure 12.9 Basic DDRIF Timing (4 Burst Read: 32 Bytes; Without Auto-Precharge)
Rev. 1.00 Oct. 01, 2007 Page 442 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
T0 (MCLK) MCLK CKE Command ACT
T1
T2
T3
T4
T5
T6
T7
T8
T9
WRITE WRITE WRITE WRITE
PRE
tRCD (SRCD = 1) MA9-0 MA13-11 MA10 BA1-0 MCS MRAS MCAS MWE MDQS MDA MDQM D0 D1 D2 D3 D4 D5 D6 D7 Hi-Z Hi-Z Row Row Bank Bank Bank Bank Bank Bank Col 0 Col 2 Col 4 Col 6
Figure 12.10 Basic DDRIF Timing (4 Burst Write: 32 Bytes; Without Auto-Precharge)
Rev. 1.00 Oct. 01, 2007 Page 443 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
T0
(MCLK) MCLK CKE Command
PREALL
T1
T2
T3
T4
ACT tRP (SRP = 1)
MA9-0 MA13-11 MA10 BA1-0 MCS MRAS MCAS MWE
Row
Row Bank
Hi-Z
MDQS
Hi-Z
MDA MDQM
Figure 12.11 Basic DDRIF Timing (Precharge all Banks (PREALL) to Bank Activate (ACT))
Rev. 1.00 Oct. 01, 2007 Page 444 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
T0 (MCLK) MCLK CKE Command MA9-0 MA13-11 MA10 BA1-0 MCS MRAS MCAS MWE MDQS MDA MDQM *1 *1 *2 MRS
T1
T2
T3
Hi-Z Hi-Z
Notes: 1. Sets the operating mode and other necessary parameters. 2. For mode register setting: BA1 = low, BA0 = low For extended mode register setting: BA1 = low, BA0 = high
Figure 12.12 Basic DDRIF Timing (Mode Register Set (MRS))
Rev. 1.00 Oct. 01, 2007 Page 445 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
T0 (MCLK) MCLK CKE Command REFA
T1
REFA
tRFC = 11 to 15 cycles tRFC = 11 to 15 cycles
ACT
MA9-0 MA13-11
MA10
Row
Row Bank
BA1-0 MCS MRAS MCAS MWE
Auto-refresh
Figure 12.13 Basic DDRIF Timing (Auto-Refresh (REFA) Enter/Exit to Bank Activate (ACT))
Rev. 1.00 Oct. 01, 2007 Page 446 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
T0 (MCLK) MCLK CKE Command REFS
T1
T0
T1
REFSX
Any Command
*1
tXSNR/tXSRD*2
MA9-0 MA13-11 MA10 BA1-0 MCS MRAS MCAS MWE
Self-refresh
Notes: 1. This timing should satisfy the conditions specified by the DDR-SDRAM used when driving CKE high. 2. This timing should satisfy the conditions specified by the DDR-SDRAM used. (tXSNR is for a non-READ command and tXSRD is for a READ command; tXSRD should usually be 200 clock cycles or longer.)
Figure 12.14 Basic DDRIF Timing (Self-Refresh Entry from IDLE (REFS)/Self-Refresh Exit (REFSX) to Any Command Input)
Rev. 1.00 Oct. 01, 2007 Page 447 of 1956 REJ09B0256-0100
Section 12 DDR-SDRAM Interface (DDRIF)
Rev. 1.00 Oct. 01, 2007 Page 448 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Section 13 PCI Controller (PCIC)
The PCI controller (PCIC) controls the PCI bus for data transfers between memory connected to an external bus and a PCI device connected to the PCI bus. The ability to connect PCI devices facilitates the design of systems using the PCI bus and enables more compact systems capable of faster data transfer. The PCIC functions as a bus bridge which connects an external PCI bus to the internal SuperHyway bus. It provides a device connected to the external PCI bus with a channel for access to the on-chip modules connected to the SuperHyway bus. The PCIC supports both the host bus bridge mode and normal mode (non-host mode). In host busbridge mode, PCI bus arbitration control is available and in normal mode, arbitration is executed by the external PCI bus arbiter.
13.1
Features
The PCIC has the following features: Supports subset of PCI Local Bus Specification Revision 2.2 PCI bus operating speeds of 33 MHz/66 MHz 32-bit data bus PCI master and target functions Supports subset of PCI power management Revision 1.1 Supports the host bus bridge mode and normal mode (selectable by MD6 pin settings) Supports the PCI bus arbiter (in host bus bridge mode) Supports four external masters Pseudo-round-robin or fixed priority arbitration Supports external bus arbiter mode * Supports configuration mechanism #1 (in host bus bridge mode) * Supports burst transfer * Parity check and error report * * * * * * *
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Section 13 PCI Controller (PCIC)
* Exclusive access (target only) Once locked, only accessible from the device that accessed the LOCK signal The SuperHyway bus in not locked during lock transfer * Can support cache coherency between a device connected to the PCI bus and system memory (PCI target) although device performance may become suboptimal * Supports four external interrupt inputs (INTD to INTA) in host bus bridge mode * Supports one external interrupt output (INTA) in normal mode * Supports both big endian and little endian formats for the SuperHyway bus (the PCI bus operates in the little endian format) * Number of devices which can be connected 33 MHz: 4 or less 66 MHz: 1 The PCIC does not support the following PCI functions. * * * * * * * Cache support (no SBO or SDONE pin) Address wrap-around mechanism PCI JTAG (other modules in this LSI can support the JTAG feature) Dual address cycles Interrupt acknowledge cycles Fast back-to-back transfer initiation (supported when performed as a target device) Extended ROM for initialization and system boot etc.
Note: When the ratio of the clocks (SHwy clock : PCICLK clock) is in the ranges of (2.1 : 1) to (3.3 : 1), the PCIC cannot be used.
Rev. 1.00 Oct. 01, 2007 Page 450 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Figure 13.1 is a block diagram of the PCIC.
PCIRESET PCICLK (PCI bus clock)
PCI local bus PCIC SuperHyway bus Interface SuperHyway bus Data FIFO 32-Byte x 2 (2 planes) Target control PCI standard signal
PCI bus Interface (PCI bus access control)
MODE6 Host/normal
PCIECR
Data FIFO 32-Byte x 2 (2 planes)
Register control Configuration/local register
SHck (SuperHyway bus clock)
Master control
Interrupt control
[Legend] PCIECR: PCI enable control register
Figure 13.1 PCIC Block Diagram The PCIC comprises two blocks: the PCI bus interface and SuperHyway bus interface block. The PCI bus interface block comprises the PCI configuration register, local register, PCI master, and PCI target controller. The functions of the PCI bus interface are transaction control on the PCI local bus. The SuperHyway bus interface block comprises the control register (PCIECR) and the data FIFO. The functions of the SuperHyway bus interface are access translation between the PCI bus interface and the CPU or DMAC via SuperHyway bus. The interrupt controller requests interrupt request to the INTC of this LSI.
Rev. 1.00 Oct. 01, 2007 Page 451 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
13.2
Input/Output Pins
Table 13.1 shows the pin configuration of the PCIC. Table 13.1 Input/Output Pins
Pin Name AD31 to AD0 PCI standard signal name I/O AD[31:0] I/O (TRI) Description PCI Address/Data Bus Address and data buses are multiplexed. Each bus transaction consists of an address phase followed by one or more data phases. PCI Command/Byte Enable Bus command and byte enables are multiplexed. These signals indicate the type of transaction during the address phase and the byte enables during the data phases. PCI Parity Generates/checks even parity across AD[31:0] and CBE[3:0]. PCI Clock Provides timing for all transactions on the PCI bus. PCIFRAME FRAME I/O (STRI) TRDY TRDY I/O (STRI) PCI Frame Current initiator drives this signal, which indicates the start and duration or end of a transaction. PCI Target Ready Selected target drives this signal, which indicates the target is ready to execute a transaction. During a write, this signal indicates that the target is ready to accept data. During a read, this signal indicates that valid data is present on the AD [31:0] lines. PCI Initiator Ready The current bus master drives this signal. During a write, this signal indicates that valid data is present on the AD [31:0] lines. During a read, this signal indicates that the master is ready to accept data. PCI Stop Selected target drives this signal to stop the current transaction. PCI Lock
CBE3 to CBE0 C/BE[3:0]
I/O (TRI)
PAR
PAR
I/O (TRI)
PCICLK
CLK
Input
IRDY
IRDY
I/O (STRI)
STOP
STOP
I/O (STRI)
LOCK
LOCK
I/O (STRI)
Rev. 1.00 Oct. 01, 2007 Page 452 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Pin Name IDSEL
PCI standard signal name I/O IDSEL Input
Description PCI Configuration Device Select This signal is input to the PCI device to select configuration cycles (only for normal mode).
DEVSEL
DEVSEL
I/O (STRI)
PCI Device Select Indicates the device driving this signal has decoded its address as the target. As an input, this signal indicates that a device has been selected. Interrupts D, C, and B Indicate that a PCI device is requesting an interrupt. Only these signals are available in host bus bridge mode.
INTD INTC INTB INTA
INTD INTC INTB INTA
Input
I/O (output: O/D)
Interrupt A Indicates that a PCI device is requesting an interrupt (input) in host bus bridge mode. This signal is used to request an interrupt (output: O/D) in normal mode. PCI Bus Request Available only in host bus bridge mode. PCI Bus Grant Available only in host bus bridge mode. PCI Bus Request Functions as an input or an output in host bus bridge mode and as an output in normal mode. PCI Bus Grant Functions as an input or an output in host bus bridge mode and as an input in normal mode. PCI System Error
REQ3 to REQ1*4 GNT3 to GNT1 REQ0/ REQOUT GNT0/ GNTIN SERR
REQ[3:1] GNT[3:1] REQ0
Input Output (TRI) I/O (TRI)
GNT0
I/O (TRI)
SERR
I/O (output: O/D)
PERR PCIRESET MD6*
PERR -- --
I/O (TRI) Output Input
PCI Parity Error PCI reset output (only for host bus bridge mode) PCI Operating Mode Select Low: PCI normal mode in which the PCIC operates as a PCI bridge on the PCICLK High: PCI host bus bridge mode in which the PCIC operates as a PCI bridge on the PCICLK
Rev. 1.00 Oct. 01, 2007 Page 453 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
[Legend] TRI: Tri-state STRI: Sustained tri-state O/D: Open Drain Note: * Clear the PCIC-related interrupt masks only after the PCIC-related pins are selected as the PCIC.
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Section 13 PCI Controller (PCIC)
13.3
Register Descriptions
Table 13.2 shows the PCIC register configuration. Table 13.3 shows the register states in each operating mode. The PCI configuration register address and its offset are used for little endian operation. Table 13.2 List of PCIC Registers
Name Control register space PCIC enable control register PCI configuration register space PCI vendor ID register PCI device ID register PCI command register PCI status register PCI revision ID register PCI program interface register PCI sub class code register PCI base class code register PCI cacheline size register PCI latency timer register PCI header type register PCI BIST register PCI I/O base address register PCI Memory base address register 0 PCI Memory base address register 1 PCI subsystem vendor ID register PCI subsystem ID register PCI capabilities pointer register PCI interrupt line register PCI interrupt pin register PCIVID PCIDID PCICMD PCISTATUS PCIRID PCIPIF PCISUB PCIBCC PCICLS PCILTM PCIHDR PCIBIST PCIIBAR PCIMBAR0 PCIMBAR1 PCISVID PCISID PCICP PCIINTLINE PCIINTPIN R R R/W R R R/W H'FE04 0000 H'FE04 0002 H'FE04 0004 H'1E04 0000 H'1E04 0002 H'1E04 0004 H'1E04 0006 H'1E04 0008 H'1E04 0009 H'1E04 000A H'1E04 000B H'1E04 000C H'1E04 000D H'1E04 000E H'1E04 000F H'1E04 0010 H'1E04 0014 H'1E04 0018 H'1E04 002C H'1E04 002E H'1E04 0034 H'1E04 003C H'1E04 003D 16 16 16 16 8 8 8 8 8 8 8 8 32 32 32 16 16 8 8 8 PCIECR R/W -- H'FE00 0008 H'1E00 00008 32 SH* Abbreviation R/W
1
PCI* R/W
1
P4 address
Access 2 Area 7 address Size*
R/WC R/WC H'FE04 0006 R R/W R/W R/W R R/W R R R/W R/W R/W R/W R/W R R/W R/W R R R R R R/W R R R/W R/W R/W R R R R/W R H'FE04 0008 H'FE04 0009 H'FE04 000A H'FE04 000B H'FE04 000C H'FE04 000D H'FE04 000E H'FE04 000F H'FE04 0010 H'FE04 0014 H'FE04 0018 H'FE04 002C H'FE04 002E H'FE04 0034 H'FE04 003C H'FE04 003D
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Section 13 PCI Controller (PCIC)
1 1
Name PCI minimum grant register PCI maximum latency register PCI capability ID register PCI next item pointer register PCI power management capability register PCI power management control/status register PCI PMCSR bridge support extension register
SH* Abbreviation R/W PCIMINGNT PCIMAXLAT PCICID PCINIP PCIPMC PCIPMCSR
PCIPMCSR BSE
PCI* R/W P4 address R R R R R/W R/W R R H'FE04 003E H'FE04 003F H'FE04 0040 H'FE04 0041 H'FE04 0042 H'FE04 0044 H'FE04 0046 H'FE04 0047
Access 2 Area 7 address Size* H'1E04 003E H'1E04 003F H'1E04 0040 H'1E04 0041 H'1E04 0042 H'1E04 0044 H'1E04 0046 H'1E04 0047 8 8 8 8 16 16 8 8
R R R R R/W R/W R R/W
PCI power consumption/dissipation PCIPCDD data register PCI local register space PCI control register PCI local space register 0 PCI local space register 1 PCI local address register 0 PCI local address register 1 PCI interrupt register PCI interrupt mask register PCI error address information register PCI error command information register PCI arbiter interrupt register PCI arbiter interrupt mask register PCI arbiter bus master error information register PCI PIO* address register PCI power management interrupt register PCI power management interrupt mask register
3
PCICR PCILSR0 PCILSR1 PCILAR0 PCILAR1 PCIIR PCIIMR PCIAIR PCICIR PCIAINT PCIAINTM PCIBMIR PCIPAR PCIPINT PCIPINTM
R/W R/W R/W R/W R/W
R R R R R
H'FE04 0100 H'FE04 0104 H'FE04 0108 H'FE04 010C H'FE04 0110 H'FE04 0114 H'FE04 0118 H'FE04 011C H'FE04 0120 H'FE04 0130 H'FE04 0134 H'FE04 0138 H'FE04 01C0 H'FE04 01CC H'FE04 01D0
H'1E04 0100 H'1E04 0104 H'1E04 0108 H'1E04 010C H'1E04 0110 H'1E04 0114 H'1E04 0118 H'1E04 011C H'1E04 0120 H'1E04 0130 H'1E04 0134 H'1E04 0138 H'1E04 01C0 H'1E04 01CC H'1E04 01D0
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
R/WC R R/W R R R R R
R/WC R R/WC R R R/W R --
R/WC -- R/W --
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Section 13 PCI Controller (PCIC)
1 1
Name PCI memory bank register 0 PCI memory bank mask register 0 PCI memory bank register 1 PCI memory bank mask register 1 PCI memory bank register 2 PCI memory bank mask register 2 PCI I/O bank register PCI I/O bank master register PCI cache snoop control register 0 PCI cache snoop control register 1
Abbreviation PCIMBR0 PCIMBMR0 PCIMBR1 PCIMBMR1 PCIMBR2 PCIMBMR2 PCIIOBR PCIIOBMR PCICSCR0 PCICSCR1
SH* R/W
PCI* R/W P4 address -- -- -- -- -- -- -- -- -- -- -- -- -- H'FE04 01E0 H'FE04 01E4 H'FE04 01E8 H'FE04 01EC H'FE04 01F0 H'FE04 01F4 H'FE04 01F8 H'FE04 01FC H'FE04 0210 H'FE04 0214 H'FE04 0218 H'FE04 021C H'FE04 0220
Access 2 Area 7 address Size* H'1E04 01E0 H'1E04 01E4 H'1E04 01E8 H'1E04 01EC H'1E04 01F0 H'1E04 01F4 H'1E04 01F8 H'1E04 01FC H'1E04 0210 H'1E04 0214 H'1E04 0218 H'1E04 021C H'1E04 0220 32 32 32 32 32 32 32 32 32 32 32 32 32
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PCI cache snoop address register 0 PCICSAR0 PCI cache snoop address register 1 PCICSAR1 PCI PIO* data register
3
PCIPDR
Notes: 1. SH: SuperHyway bus (internal bus). PCI: PCI local bus. WC: Cleared by writing 1 (Writing of 0 is no effect). --: Accessing is prohibited. 2. When accessing a register, do not use a size smaller than the register's access size. 3. PIO: Programmed I/O.
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Section 13 PCI Controller (PCIC)
Table 13.3 Register States in Each Operating Mode
Name Control register space PCIC enable control register PCI configuration register space PCI vendor ID register PCI device ID register PCI command register PCI status register PCI revision ID register PCI program interface register PCI sub class code register PCI base class code register PCI cache line size register PCI latency timer register PCI header type register PCI BIST register PCI I/O base address register PCI Memory base address register 0 PCI Memory base address register 1 PCI subsystem vendor ID register PCI subsystem ID register PCI capabilities pointer register PCI interrupt line register PCI interrupt pin register PCI minimum grant register PCI maximum latency register PCI capability ID register PCI next item pointer register PCIVID PCIDID PCICMD PCISTATUS PCIRID PCIPIF PCISUB PCIBCC PCICLS PCILTM PCIHDR PCIBIST PCIIBAR PCIMBAR0 PCIMBAR1 PCISVID PCISID PCICP PCIINTLINE PCIINTPIN PCIMINGNT H'1912 H'0004 H'0080 H'0290 H'00 H'00 H'00 H'00 H'20 H'00 H'00 H'00 H'1912 H'0004 H'0080 H'0290 H'00 H'00 H'00 H'00 H'20 H'00 H'00 H'00 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained PCIECR H'0000 0000 H'0000 0000 Retained Retained Power-On Abbreviation Reset Manual Reset Sleep Mode Standby
H'0000 0001 H'0000 0001 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 H'0000 H'40 H'00 H'01 H'00 H'0000 H'0000 H'40 H'00 H'01 H'00 H'00 H'01 H'00 Retained Retained Retained Retained Retained Retained Retained Retained Retained
PCIMAXLAT H'00 PCICID PCINIP H'01 H'00
Rev. 1.00 Oct. 01, 2007 Page 458 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Name PCI power management capability register PCI power management control/status register PCI PMCSR bridge support extension register
Power-On Abbreviation Reset PCIPMC PCIPMCSR
PCIPMCSR BSE
Manual Reset H'000A H'0000 H'00 H'00
Sleep Mode Retained Retained Retained Retained
Standby Retained Retained Retained Retained
H'000A H'0000 H'00 H'00
PCI power consumption/dissipation PCIPCDD data register PCI local register space PCI control register PCI local space register 0 PCI local space register 1 PCI local address register 0 PCI local address register 1 PCI interrupt register PCI interrupt mask register PCI error address information register PCI error command information register PCI arbiter interrupt register PCI arbiter interrupt mask register PCI arbiter bus master error information register PCI PIO address register PCI power management interrupt register PCI power management interrupt mask register PCI memory bank register 0 PCI memory bank mask register 0 PCI memory bank register 1 PCI memory bank mask register 1 PCI memory bank register 2 PCICR PCILSR0 PCILSR1 PCILAR0 PCILAR1 PCIIR PCIIMR PCIAIR PCICIR PCIAINT PCIAINTM PCIBMIR PCIPAR PCIPINT PCIPINTM PCIMBR0 PCIMBMR0 PCIMBR1 PCIMBMR1 PCIMBR2
H'0000 00xx
H'0000 00xx
Retained
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'xxxx xxxx H'xx00 000x H'xxxx xxxx H'xx00 000x Retained Retained
H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 00xx H'80xx xxxx H'0000 00xx H'80xx xxxx Retained Retained
H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained
Rev. 1.00 Oct. 01, 2007 Page 459 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Name PCI memory bank mask register 2 PCI I/O bank register PCI I/O bank master register PCI cache snoop control register 0 PCI cache snoop control register 1
Power-On Abbreviation Reset PCIMBMR2 PCIIOBR PCIIOBMR PCICSCR0 PCICSCR1
Manual Reset
Sleep Mode
Standby Retained Retained Retained Retained Retained Retained Retained Retained
H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'xxxx xxxx H'xxxx xxxx Retained
PCI cache snoop address register 0 PCICSAR0 PCI cache snoop address register 1 PCICSAR1 PCI PIO data register PCIPDR
[Legend] x: Undefined
13.3.1
Bit:
PCIC Enable Control Register (PCIECR)
31 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 0 R 16 0 R 0 ENBL 0 R/W
Initial value: R/W: Bit:
0 R 15
Initial value: R/W:
0 R
Bit 31 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
ENBL
0
R/W
PCI Enable Bit. Enable the PCIC 0: PCIC disable The access from both the CPU and external PCI devices to the PCIC is invalid (including the configuration and local register), except PCIECR. 1: PCIC enable
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Section 13 PCI Controller (PCIC)
13.3.2
Configuration Registers
The configuration registers defines the programming model and usages for the configuration register space in a PCI compliant device. For details, refer to "PCI Local Bus Specification Revision 2.2 Chapter 6 Configuration Space ". (1) PCI Vender ID Register (PCIVID)
This register identifies the manufacturer of device.
Bit: 15 14 13 12 11 10 9 8 VID Initial value: SH R/W: PCI R/W: 0 R R 0 R R 0 R R 1 R R 1 R R 0 R R 0 R R 1 R R 0 R R 0 R R 0 R R 1 R R 0 R R 0 R R 1 R R 0 R R 7 6 5 4 3 2 1 0
Bit 15 to 0
Bit Name VID
Initial Value H'1912
R/W SH: R PCI: R
Description PCI Vender ID Indicates the PCI device manufacture identifier (vender ID) that is allocated by PCI-SIG. Renesas Technology's vendor ID is H'1912.
(2)
PCI Device ID Register (PCIDID)
This register uniquely identifies this LSI amongst PCI devices manufactured by the vendor.
Bit: 15 14 13 12 11 10 9 8 DID Initial value: SH R/W: PCI R/W: 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 1 R R 0 R R 0 R R 7 6 5 4 3 2 1 0
Bit 15 to 0
Bit Name DID
Initial Value H'0004
R/W SH: R PCI: R
Description PCI Device ID These bits uniquely identify this LSI amongst PCI devices manufactured by the vendor indicated by the PCI vender field. This LSI's device ID is H'0004.
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Section 13 PCI Controller (PCIC)
(3)
PCI Command Register (PCICMD)
The PCI command register provides coarse control over a device's ability to generate and respond to PCI cycles. When 0 is written to this register, the device is logically disconnected from the PCI bus for all accesses except configuration accesses.
Bit: 15 Initial value: SH R/W: 0 R R 14 0 R R 13 0 R R 12 0 R R 11 0 R R 10 0 R R 9 8 7 6 5 4 3
SC
2
BM
1
MS
0
IOS
FBBE SERRE WCC
PER VGAPS MWIE
0 R R
0 R/W R/W
1 R/W R/W
0 R/W R/W
0 R R
0 R R
0 R R
0 R/W R/W
0 R/W R/W
0 R/W R/W
PCI R/W:
Bit
Bit Name
Initial Value All 0
R/W SH: R PCI: R
Description Reserved These bits are always read as 0. The write value should always be 0. PCI Fast Back-to-Back Enable Controls whether or not a master can do fast back-toback transactions to different device. 0: Fast back-to-back transactions are only allowed to the same target 1: Master is allowed to generate fast back-to-back transactions to different targets (not supported)
15 to 10
9
FBBE
0
SH: R PCI: R
8
SERRE
0
SH: R/W
PCI SERR Output Control 0: SERR output disabled 1: SERR output enabled
PCI: R/W Controls the SERR output.
7
WCC
1
SH: R/W
Wait Cycle Control When WCC = 1, both an address and data for a master write, only an address for a master read, and only data for a target read are output for at least two clock cycles. 0: Address/data stepping control disabled 1: Address/data stepping control enabled
PCI: R/W Controls the address/data stepping.
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Section 13 PCI Controller (PCIC)
Bit 6
Bit Name PER
Initial Value 0
R/W
Description
SH: R/W Parity Error PCI: R/W Controls the device's response when the PCIC detects a parity error or receives a parity error. When this bit is set to 1, the PERR signal is asserted. 0: No response parity error 1: Response parity error SH: R PCI: R VGA Palette Snoop Control 0: VGA compatible device 1: Palette register write is not supported (not supported)
5
VGAPS
0
4
MWIE
0
SH: R PCI: R
PCI Memory Write and Invalidate Control Controls issuance of a memory write and invalidate command in a master access. 0: Memory write is used 1: Memory write and invalidate command is executable (not supported)
3
SC
0
SH: R PCI: R
PCI Special Cycles Indicates whether or not to support the special cycle operations in a target access. 0: Special cycles ignored 1: Special cycles monitored (not supported)
2
BM
0
SH: R/W
PCI Bus Master Control 0: Bus master function disabled 1: Bus master function enabled
PCI: R/W Controls a bus master.
1
MS
0
SH: R/W
PCI Memory Space Control
PCI: R/W Controls accesses to memory space of this LSI. When this bit is cleared to 0, a memory transfer to the PCIC is terminated with a master abort. 0: Does not respond to memory space accesses 1: Respond to memory space accesses 0 IOS 0 SH: R/W PCI I/O Space PCI: R/W Controls accesses to I/O space of this LSI. When this bit is cleared to 0, a I/O transfer to the PCIC is terminated with a master abort. 0: Does not respond to I/O space accesses 1: Respond to I/O space accesses
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Section 13 PCI Controller (PCIC)
(4)
PCI Status Register (PCISTATUS)
This status register is used to record status information for PCI bus related events. The definition of each of the bits is given in the table below. A device may not need to implement all the bits, depending on device functionality. For instance, since a device that acts as a target does not inform a target abort, bit 11 does not need to be implemented. Reserved bits should be read-only and return zero when the bits are read. Reads from this register operates normally. Writes are slightly different in that bits can be cleared, but not set. A one bit is cleared whenever the register is written to, and the write data in the corresponding bit location is a 1. For instance, to clear bit 14 and not affect any other bits, write the value of B'0100 0000 0000 0000 to the register.
Bit: 15
DPE
14
SSE
13
RMA
12
RTA
11
STA
10
9
8
7
6 0 R/W R
5
66C
4
CL
3 0 R R
2 0 R R
1 0 R R
0 0 R R
DEVSEL
MDPE FBBC
Initial value: 0 0 0 0 0 SH R/W: R/WC R/WC R/WC R/WC R/WC
0 R R
1 R R
0 R/WC R/WC
1 R R
0 R/W R
1 R R
PCI R/W: R/WC R/WC R/WC R/WC R/WC
Bit 15
Bit Name DPE
Initial Value 0
R/W
Description
SH: R/WC Parity Error Detect Status PCI: R/WC Indicates that a parity error has been detected in read data when the PCIC is a master or in write data when the PCIC is a target. This bit must be set by the device whenever it detects a parity error, even if parity error handling is disabled. 0: Device is not detecting parity error. 1: Device is detecting parity error.
14
SSE
0
SH: R/WC System Error Output Status PCI: R/WC Indicates that the PCIC has asserted the SERR signal. 0: SERR has not been asserted 1: SERR has been asserted (the value retained until cleared)
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Section 13 PCI Controller (PCIC)
Bit 13
Bit Name RMA
Initial Value 0
R/W
Description
SH: R/WC Master Abort Receive Status PCI: R/WC Indicates that the PCIC has terminated a transaction with a master abort when the PCIC is a master. 0: PCIC has not terminated a transaction with a master abort 1: PCIC has terminated a transaction with a master abort
12
RTA
0
SH: R/WC Target Abort Receive Status PCI: R/WC Indicates that a transaction is terminated by a target device with a target abort when the PCIC functions as a master. 0: Transaction has not been terminated with a target abort 1: Transaction has been terminated with a target abort
11
STA
0
SH: R/WC Target Abort Execution Status PCI: R/WC Indicates that the PCIC has terminated a transaction with a target-abort when the PCIC functions as a target. 0: PCIC has not terminated a transaction with a target-abort 1: PCIC has terminated a transaction with target-abort
10, 9
DEVSEL
01
SH: R PCI: R
DEVSEL Timing Status Indicate the response timing status of the DEVSEL signal when the PCIC functions as a target. 00: Fast (not support) 01: Medium 10: Slow (not support) 11: Reserved
8
MDPE
0
SH: R/WC Data parity error PCI: R/WC Indicates that the PCIC has asserted the PERR signal or detected the assertion of the PERR signal if the PCIC functions as a master. Only when the parity response bit has been set to 1, this bit is set to 1. 0: Data parity error has not been generated 1: Data parity error has been generated
Rev. 1.00 Oct. 01, 2007 Page 465 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 7
Bit Name FBBC
Initial Value 1
R/W SH: R PCI: R
Description Fast Back-to-Back Status Indicates whether or not the PCIC is capable of accepting fast back-to-back transactions when the transactions are not to the same agent if the PCIC functions as a target. 0: Fast back-to-back transactions to different agents not supported 1: Fast back-to-back transactions to different agents supported
6
0
SH: R/W PCI: R
Reserved These bits are always read as 0. The write value should always be 0. 66MHz-Operation Capable Status Indicates whether or not the PCIC is capable of running at 66MHz. 0: PCIC runs at 33 MHz 1: PCIC runs at 66 MHz
5
66C
0
SH: R/W PCI: R
4
CL
1
SH: R PCI: R
PCI Power Management (Optional Function) Indicates whether or not the PCI power management function is supported. 0: Power management not supported 1: Power management supported
3 to 0
All 0
SH: R PCI: R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 466 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(5)
PCI Revision ID Register (PCIRID)
This register specifies a device specific revision identifier.
Bit: 7 6 5 4 RID Initial value: SH R/W: PCI R/W: 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 3 2 1 0
Bit 7 to 0
Bit Name RID
Initial Value H'00
R/W SH: R PCI: R
Description Revision ID Indicates the PCIC revision.The initial value is H'00.RID value varies according to the logic version of the PCIC and it may be changed in the future.
(6)
PCI Program Interface Register (PCIPIF)
This register is the programming interface for the IDE controller class code. For details of the class code, refer to "PCI Local Bus Specification Revision 2.2 Appendix D."
Bit: 7
MIDED
6 -- 0 R R
5 -- 0 R R
4 -- 0 R R
3 PIS 0 R/W R
2 OMS 0 R/W R
1 PIP 0 R/W R
0 OMP 0 R/W R
Initial value: SH R/W: PCI R/W:
0 R/W R
Bit 7
Bit Name MIDED
Initial Value 0
R/W SH: R/W PCI: R
Description PCI Master IDE Device Specifies the PCI master IDE device. 1: PCI master IDE device 0: PCI slave IDE device When the CFINIT bit in PCICR is 0, this bit is writable. When the CFINIT bit in PCICR is 1, writing is ignored. This bit is readable.
Rev. 1.00 Oct. 01, 2007 Page 467 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 6 to 4
Bit Name
Initial Value All 0
R/W SH: R PCI: R
Description Reserved These bits are always read as 0. The write value should always be 0. PCI Programmable Indicator (Secondary) When the CFINIT bit in PCICR is 0, this bit is writable. When the CFINIT bit in PCICR is 1, writing is ignored. This bit is readable. PCI Operating Mode (Secondary) When the CFINIT bit in PCICR is 0, this bit is writable. When the CFINIT bit in PCICR is 1, writing is ignored. This bit is readable. PCI Programmable Indicator (Primary) When the CFINIT bit in CR is 0, this bit is writable. When the CFINIT bit in PCICR is 1, writing is ignored. This bit is readable. PCI Operating Mode (Primary) When the CFINIT bit in PCICR is 0, this bit is writable. When the CFINIT bit in PCICR is 1, writing is ignored. This bit is readable.
3
PIS
0
SH: R/W PCI: R
2
OMS
0
SH: R/W PCI: R
1
PIP
0
SH: R/W PCI: R
0
OMP
0
SH: R/W PCI: R
Rev. 1.00 Oct. 01, 2007 Page 468 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(7)
PCI Sub Class Code Register (PCISUB)
This register identifies the sub class code. For details of the class code, refer to "PCI Local Bus Specification Revision 2.2 Appendix D."
Bit: 7 6 5 4 SUB Initial value: SH R/W: PCI R/W: 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 3 2 1 0
Bit 7 to 0
Bit Name SUB
Initial Value H'00
R/W SH: R/W PCI: R
Description Sub Class Code Indicate the sub class code. The initial value is H'00.
(8)
PCI Base Class Code Register (PCIBCC)
This register identifies the base class code. For details of the class code, refer to "PCI Local Bus Specification Revision 2.2 Appendix D."
Bit: 7 6 5 4 BCC Initial value: SH R/W: PCI R/W: 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 3 2 1 0
Bit 7 to 0
Bit Name BCC
Initial Value H'00
R/W
Description
SH: R/W Base Class Code PCI: R Indicates the base class code. The initial value is H'00.
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Section 13 PCI Controller (PCIC)
(9)
PCI Cacheline Size Register (PCICLS)
Bit: 7 6 5 4 CLS Initial value: SH R/W: PCI R/W: 0 R R 0 R R 1 R R 0 R R 0 R R 0 R R 0 R R 0 R R 3 2 1 0
Bit 7 to 0
Bit Name CLS
Initial Value H'20
R/W SH: R PCI: R
Description Cache Line Size: Not supported A memory target does not support a cache. SDON and SBO are ignored.
(10) PCI Latency Timer Register (PCILTM) This register specifies, in units of PCI bus clocks, the value of latency timer for this PCI bus master.
Bit: 7 6 5 4 LTM Initial value: SH R/W: PCI R/W: 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 3 2 1 0
Bit 7 to 0
Bit Name LTM
Initial Value H'00
R/W SH: R/W PCI: R/W
Description PCI Latency Timer Specifies the maximum number of acquisition clocks of PCI bus when the PCIC is operating as the master.
Rev. 1.00 Oct. 01, 2007 Page 470 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(11) PCI Header Type Register (PCIHDR)
Bit: 7
MFE
6
5
4
3 HDR
2
1
0
Initial value: SH R/W: PCI R/W:
0 R R
0 R R
0 R R
0 R R
0 R R
0 R R
0 R R
0 R R
Bit 7
Bit Name MFE
Initial Value 0
R/W SH: R PCI: R
Description Multiple Function Enable 0: Single function 1: Multiple (from two to eight) functions (not supported)
6 to 0
HDR
H'00
SH: R PCI: R
Configuration Layout Indicates the layout type of configuration registers. H'00: Type "00h" layout supported H'01: Type "01h" layout supported (not supported)
(12) PCI BIST Register (PCIBIST)
Bit: 7
BISTC
6 -- 0 R R
5 -- 0 R R
4 -- 0 R R
3 -- 0 R R
2 -- 0 R R
1 -- 0 R R
0 -- 0 R R
Initial value: SH R/W: PCI R/W:
0 R R
Bit 7
Bit Name BISTC
Initial Value 0
R/W SH: R PCI: R
Description This bit is used to control the BIST function and status. 0: Function not available 1: Function available (not supported)
6 to 0
All 0
SH: R PCI: R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 471 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(13) PCI I/O Base Address Register (PCIIBAR) This register packages the I/O space base address register of the PCI configuration register that is prescribed with PCI local bus specification. Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOB (upper) Initial value: SH R/W: PCI R/W: Bit: 0 R/W R/W 15 0 R/W R/W 14 0 R/W R/W 13 0 R/W R/W 12 0 R/W R/W 11 0 R/W R/W 10 0 R/W R/W 9 0 R/W R/W 8 0 R/W R/W 7 0 R/W R/W 6 0 R/W R/W 5 0 R/W R/W 4 0 R/W R/W 3 0 R/W R/W 2 0 R/W R/W 1 0 R R 0 R R 0 R R 0 R/W R/W 0
ASI
IOB (upper) Initial value: SH R/W: PCI R/W: 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R R 0 R R
IOB (lower) 0 R R 0 R R
1 R R
Bit 31 to 8
Bit Name IOB (upper)
Initial Value
R/W
Description I/O Space Base Address (upper 24 bits) Specifies the upper 24 bits of I/O base address that corresponds the PCIC local register space (PCIC control register space). I/O Space Base Address (lower 6 bits) These bits are fixed 000000 by hardware. Reserved These bits are always read as 0. The write value should always be 0. Address Space Indicator Indicates whether the base address in this register indicates the I/O or memory space. 0: Memory space 1: I/O space
H'000000 SH: R/W PCI: R/W
7 to 2 1
IOB (lower)
000000 0
SH: R PCI: R SH: R PCI: R
0
ASI
1
SH: R PCI: R
Rev. 1.00 Oct. 01, 2007 Page 472 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(14) PCI Memory Base Address Register 0 (PCIMBAR0) This register packages the memory space base address register of the PCI configuration register that is prescribed with PCI local bus specification. Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBA (upper) Initial value: SH R/W:
PCI R/W:
MBA (lower) 0 R/W R/W 8 0 R/W R/W 7 0 R/W R/W 6 0 R/W R/W 5 0 R/W R/W 4 0 R R 3 LAP 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 2
LAT
0 R/W R/W 15
0 R/W R/W 14
0 R/W R/W 13
0 R/W R/W 12
0 R/W R/W 11
0 R/W R/W 10
0 R/W R/W 9
0 R R 1
0 R R 0
ASI
Bit:
MBA (lower) Initial value: SH R/W: PCI R/W: 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R
0 R R
0 R R
Bit
Bit Name
Initial Value H'000
R/W SH: R/W PCI: R/W
Description Memory Space 0 Base Address (upper 12 bits) Specifies the upper 12 bits of memory base address that corresponds the local address space 0 (SuperHyway bus address space of this LSI). Update value PCILSR [28:20] 0 0000 0000 0 0000 0001 0 0000 0011 | 0 1111 1111 1 1111 1111 Address space Effective bit of MBA (upper) 1 Mbyte [31:20] 2 Mbytes [31:21] 4 Mbytes [31:22] | | 256 Mbytes [31:28] 512 Mbytes [31:29]
31 to 20 MBA (upper)
19 to 4 3
MBA (lower) LAP
H'0000 SH: R PCI: R 0 SH: R PCI: R
Memory Space 0 Base Address (lower 16 bits) These bits are fixed H'0000 by hardware. Prefetch Control Indicates whether or not local address space 0 is prefetchable. 0: Not prefetchable 1: Prefetchable (not supported)
Rev. 1.00 Oct. 01, 2007 Page 473 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 2, 1
Bit Name LAT
Initial Value 00
R/W SH: R PCI: R
Description Memory Type Indicates the memory type of local address space 0. 00: 32-bit base address and 32-bit space 01: 32-bit base address and 1-Mbyte space (Not supported) 10: 64-bit base address (Not supported) 11: Reserved
0
ASI
0
SH: R PCI: R
Address Space Indicator Indicates whether the base address in this register indicates the I/O or memory space. 0: Memory space 1: I/O space
(15) PCI Memory Base Address Register 1 (PCIMBAR1) This register packages the memory space base address register of the PCI configuration register that is prescribed with PCI local bus specification. Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBA (upper) Initial value: SH R/W:
PCI R/W:
MBA (lower) 0 R/W R/W 8 0 R/W R/W 7 0 R/W R/W 6 0 R/W R/W 5 0 R/W R/W 4 0 R R 3 LAP 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 2
LAT
0 R/W R/W 15
0 R/W R/W 14
0 R/W R/W 13
0 R/W R/W 12
0 R/W R/W 11
0 R/W R/W 10
0 R/W R/W 9
0 R R 1
0 R R 0
ASI
Bit:
MBA (lower) Initial value: SH R/W: PCI R/W: 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R
0 R R
0 R R
Rev. 1.00 Oct. 01, 2007 Page 474 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit
Bit Name
Initial Value H'000
R/W SH: R/W PCI: R/W
Description PCI Memory Space 1 Base Address (upper 12 bits) Specifies the upper 12 bits of PCI memory base address that corresponds the base address of local address space 1 (SuperHyway bus address space of this LSI). PCILSE0 [28:20] 0 0000 0000 0 0000 0001 0 0000 0011 | 0 1111 1111 1 1111 1111 Address space 1 Mbyte 2 Mbytes 4 Mbytes | 256 Mbytes 512 Mbytes Effective bit of MBA (upper) [31:20] [31:21] [31:22] | [31:28] [31:29]
31 to 20 MBA (upper)
19 to 4 3
MBA (lower) LAP
H'0000 SH: R PCI: R 0 SH: R PCI: R
Memory Space 1 Base Address (lower 16 bits) These bits are fixed H'0000 by hardware. Prefetch Control Indicates whether or not local address space 1 is prefetchable. 0: Not prefetchable 1: Prefetchable (Not supported)
2, 1
LAT
00
SH: R PCI: R
Memory Type Indicates the memory type of local address space 1. 00: 32-bit base address and 32-bit space 01: 32-bit base address and 1-Mbyte space (Not supported) 10: 64-bit base address (Not supported) 11: Reserved
0
ASI
0
SH: R PCI: R
Address Space Indicator Indicates whether the base address in this register indicates the I/O or memory space. 0: Memory space 1: I/O space
Rev. 1.00 Oct. 01, 2007 Page 475 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(16) PCI Subsystem vender ID Register (PCISVID) Refer to miscellaneous registers section of PCI local bus specification Revision 2.2.
Bit: 15 14 13 12 11 10 9 8 SVID Initial value: SH R/W: PCI R/W: 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 7 6 5 4 3 2 1 0
Bit 15 to 0
Bit Name SVID
Initial Value
R/W
Description Subsystem Vendor ID Specifies the subsystem vendor ID of the PCIC. The initial value is H'0000. This field can be modified during initializing PCIC registers (PCICR.CFINIT = 0), but cannot be modified after initialized PCIC register (PCICR.CFINIT = 1) even if writing this field.
H'0000 SH: R/W PCI: R
(17) PCI Subsystem ID Register (PCISID) Refer to section about miscellaneous registers of PCI local bus specification Revision 2.2.
Bit: 15 14 13 12 11 10 9 8 SSID Initial value: SH R/W: PCI R/W: 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 7 6 5 4 3 2 1 0
Bit 15 to 0
Bit Name SSID
Initial Value
R/W
Description Subsystem ID Specifies the subsystem ID of the PCIC. The initial value is H'0000. This field can be modified during initializing PCIC registers (PCICR.CFINIT = 0), but cannot be modified after initialized PCIC register (PCICR.CFINIT = 1) even if writing this field.
H'0000 SH: R/W PCI: R
Rev. 1.00 Oct. 01, 2007 Page 476 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(18) PCI Capability Pointer Register (PCICP) This register is the expansion function pointer register of the PCI configuration register that is prescribed in the PCI power management specification.
Bit: 7 6 5 4 CP Initial value: SH R/W: PCI R/W: 0 R R 1 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 3 2 1 0
Bit 7 to 0
Bit Name CP
Initial Value H'40
R/W SH: R PCI: R
Description Capabilities pointer The offset address of the expansion function register.
(19) PCI Interrupt Line Register (PCIINTLINE)
Bit: 7 6 5 4 3 2 1 0
INTLINE Initial value: SH R/W: PCI R/W: 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W 0 R/W R/W
Bit 7 to 0
Bit Name INTLINE
Initial Value H'00
R/W SH: R/W PCI: R/W
Description PCI Interrupt Line PCI interrupt connected to the external interrupt of this LSI. Specify these bits by system software during initialization. The initial value is H'00. The setting value of this field does not affect the operation of this LSI.
Rev. 1.00 Oct. 01, 2007 Page 477 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(20) PCI Interrupt Pin Register (PCIINTPIN)
Bit: 7 6 5 4 3 2 1 0
INTPIN Initial value: SH R/W: PCI R/W: 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 1 R/W R
Bit 7 to 0
Bit Name INTPIN
Initial Value H'01
R/W SH: R/W PCI: R
Description Interrupt Pin Select Specifies which interrupt pin is used for connection when the PCIC outputs interrupt request. H'00: Does not connect INTD to INTA H'01: INTA is used to request an interrupt H'02: INTB is used to request an interrupt H'03: INTC is used to request an interrupt H'04: INTD is used to request an interrupt H'05 to H'FF: Reserved
(21) PCI Minimum Grant Register (PCIMINGNT) This register is not programmable.
Bit: 7 6 5 4 3 2 1 0
MINGNT Initial value: SH R/W: PCI R/W: 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R
Bit 7 to 0
Bit Name MINGNT
Initial Value H'00
R/W SH: R PCI: R
Description Minimum Grant Specify the burst time to be required by the master device (not supported).
Rev. 1.00 Oct. 01, 2007 Page 478 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(22) PCI Maximum Latency Register (PCIMAXLAT) This register is not programmable.
Bit: 7 6 5 4 3 2 1 0
MAXLAT Initial value: SH R/W: PCI R/W: 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R
Bit 7 to 0
Bit Name MAXLAT
Initial Value H'00
R/W SH: R PCI: R
Description Maximum Latency Specify the worst time from the bus request by the PCI master device to the bus acquisition (not supported).
(23) PCI Capability Identifier Register (PCICID) When H'01 is read by system software, it indicates that the data structure currently being pointed to is the PCI power management data structure. Each function of a PCI device may have only one item in its capability list with PCICID set to H'01.
Bit: 7 6 5 4 CID Initial value: SH R/W: PCI R/W: 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 1 R R 3 2 1 0
Bit 7 to 0
Bit Name CID
Initial Value H'01
R/W SH: R PCI: R
Description Expansion Function ID Specifies the expansion function ID. H'01: The expansion function is power management.
Rev. 1.00 Oct. 01, 2007 Page 479 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(24) PCI Next Item Pointer Register (PCINIP) PCINIP gives the location of the next item in the function's capability list.
Bit: 7 6 5 4 NIP Initial value: SH R/W: PCI R/W: 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 3 2 1 0
Bit 7 to 0
Bit Name NIP
Initial Value H'00
R/W SH: R PCI: R
Description Next Item Pointer Specifies the offset to the next expansion function. H'00: Power management function is listed as the last item.
Rev. 1.00 Oct. 01, 2007 Page 480 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(25) PCI Power Management Capability Register (PCIPMC) PCIPMCS is a 16-bit register that provides information on the capabilities of the power management related functions. For details, refer to "PCI Bus Power Management Interface Specification Revision 1.1 Chapter 3 PCI Power Management Interface". This register must be set during initializing the PCIC registers (PCICR.CFINIT = 0).
Bit: 15 14 13 PMCS Initial value: SH R/W: 0 R R 0 R R 0 R R 0 R R 0 R R 12 11 10 D2S 0 R/W R 9 D1S 0 R/W R 8 0 R R 7 0 R R 6 0 R R 5 DSI 0 R R 4 0 R R 3 PMEC 1 R/W R 0 R/W R 2 1 PMV 1 R/W R 0 R/W R 0
PCI R/W:
Bit
Bit Name
Initial Value 00000
R/W SH: R PCI: R
Description PME_SUPPORT This 5-bit field indicates the power states in which the function may assert PME. A value of 0b for any bit indicates that the function is not capable of asserting the PME signal while in that power state. Bit11: xxxx1 - PME can be asserted from D0 Bit12: xxx1x - PME can be asserted from D1 Bit13: xx1xx - PME can be asserted from D2 Bit14: x1xxx - PME can be asserted from D3 hot Bit15: 1xxxx - PME can be asserted from D3 cold Note: This LSI dose not have the PME pin.
15 to 11 PMCS
10
D2S
0
SH: R/W PCI: R
When this bit is 1, This function supports the D2 power management state. When the D2 power management state is not supported, this bit is read as 0. When this bit is 1, This function supports the D1 power management state. When the D1 power management state is not supported, this bit is read as 0.
9
D1S
0
SH: R/W PCI: R
Rev. 1.00 Oct. 01, 2007 Page 481 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 8 to 6
Bit Name
Initial Value All 0
R/W SH: R PCI: R
Description Reserved These bits are always read as 0. The write value should always be 0. DSI Specifies whether or not the device requires the specific initialization. 0: Does not require the specific initialization Reserved These bits are always read as 0. The write value should always be 0. PCI PME clock Specifies whether or not the device requires the clock to support PME generation. 1: Requires the clock to support PME generation Note: This LSI dose not have the PME pin.
5
DSI
0
SH: R PCI: R
4
0
SH: R PCI: R
3
PMEC
1
SH: R/W PCI: R
2 to 0
PMV
010
SH: R/W PCI: R
Version Specifies the version of the power management specifications. 010: This LSI's power management specification is conformed to revision 1.1
Rev. 1.00 Oct. 01, 2007 Page 482 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(26) PCI Power Management Control/Status Register (PCIPMCSR) This 16-bit register is used to manage the PCI function's power management status as well as to enable/monitor PMEs. For details, refer to "PCI Bus Power Management Interface Specification Revision 1.1 Chapter 3 PCI Power Management Interface".
Bit: 15 PMES Initial value: SH R/W: 0 R R 0 R R 14 13 DSC 0 R R 0 R R 0 R R 12 11 DSL 0 R R 0 R R 10 9 8
PME EN
7 0 R R
6 0 R R
5 0 R R
4 0 R R
3 0 R R
2 0 R R
1 PS 0 R/W R
0
0 R R
0 R/W R
PCI R/W:
Bit 15
Bit Name PMES
Initial Value 0
R/W SH: R PCI: R
Description PME Status Indicates the state of the PME signal. (Not supported) Note: This LSI dose not have the PME pin. Data Scale Specify the scaling of data field. (Not supported) Data Select Specify the data output in the data filed. PME Enable Controls the PME output. (Not supported) Note: This LSI dose not have the PME pin. Reserved These bits are always read as 0. The write value should always be 0. Power State Specifies the power state. If software attempts to write an unsupported, optional state to these bits, the write operation must complete normally on the bus; however, the data is discarded and no state change occurs. 00: D0 state 01: D1 state 10: D2 state 11: D3 hot state (power-down mode)
14, 13 12 to 9 8
DSC DSL PMEEN
00 0000 0
SH: R PCI: R SH: R PCI: R SH: R PCI: R
7 to 2
All 0
SH: R PCI: R
1, 0
PS
00
SH: R/W PCI: R/W
Rev. 1.00 Oct. 01, 2007 Page 483 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(27) PCIPMCSR Bridge Support Extension Register (PCIPMCSRBSE) This register supports PCI bridge specific functionality and is required for all PCI-to-PCI bridges.
Bit: 7
BPC CEN
6
B2B3N
5 -- 0 R R
4 -- 0 R R
3 -- 0 R R
2 -- 0 R R
1 -- 0 R R
0 -- 0 R R
Initial value: SH R/W:
0 R R
0 R R
PCI R/W:
Bit 7
Bit Name BPCCEN
Initial Value 0
R/W SH: R PCI: R
Description When the bus power/clock control mechanism is disabled, the power state bits in bridge's PCIPMCSR cannot be used by the system software to control the power or clock of the bridge's secondary bus. The state of this bit determines the action that is to occur as a direct result of programming the function to the D3 hot state. 0: Indicates that when the bridge function is set to the D3 hot state, its secondary bus will have its power removed (B3). 1: Indicates that when the bridge function is set to the D3 hot state, its secondary bus's PCI clock will be stopped (B2). This bit is only valid if bit 7 (BPCCEN) is set to 1.
6
B2B3N
0
SH: R PCI: R
5 to 0
All 0
SH: R PCI: R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 484 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(28) PCI Power Consumption/Radiation Register (PCIPCDD) The data register is an 8-bit register that provides a mechanism for the function to report state dependent operating data such as power consumed or heat dissipation. For details, refer to "PCI Bus Power Management Interface Specification Revision 1.1 Chapter 3 PCI Power Management Interface".
Bit: 7 6 5 4 PCDD Initial value: SH R/W: PCI R/W: 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 0 R/W R 3 2 1 0
Bit 7 to 0
Bit Name PCDD
Initial Value H'00
R/W SH: R/W PCI: R
Description This register is used to report the state dependent data requested by the PCIPMCSR.DSL bits. The value of this register is scaled by the value reported by the PCIPMCSR.DSC bits.
Rev. 1.00 Oct. 01, 2007 Page 485 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
13.3.3 (1)
Local Register
PCI Control Register (PCICR)
PCICR is a 32-bit register which specifies the operation of the PCIC. The register is write protected; only writes in which the upper eight bits (that is, bits 31 to 24) have the value H'A5 are performed. All other writes are ignored.
Bit: 31 -- Initial value: SH R/W: PCI R/W: Bit: 0 R R 15 --
Initial value: SH R/W:
30 -- 0 R R 14 -- 0 R R
29 -- 0 R R 13 -- 0 R R
28 -- 0 R R 12 -- 0 R R
27 -- 0 R R 11
26 -- 0 R R 10
25 -- 0 R R 9 PFE 0 R/W R
24 -- 0 R R 8 TBS 0 R/W R
23 -- 0 R R 7 -- 0 R R
22 -- 0 R R 6
BMAM
21 -- 0 R R 5 -- -- R R
20 -- 0 R R 4 -- -- R R
19 -- 0 R R 3 -- 0 R R
18 -- 0 R R 2 IOCS 0 R/W R
17 -- 0 R R 1
RST CTL
16 -- 0 R R 0
CFI NIT
PFCS FTO 0 R/W R 0 R/W R
0 R R
0 R/W R
0 R/W R
0 R/W R
PCI R/W:
Bit
Bit Name
Initial Value H'00
R/W SH: R/W PCI: R
Description Reserved Set these bits to H'A5 only when writing to bits 11 to 8, 6, and 3 to 0. These bits are always read as 0. Reserved These bits are always read as 0. The write value should always be 0. PCI Pre-Fetch Command Setting This bit is valid only when the PFE bit is 1. 0: Always 8-byte pre-fetching 1: Always 32-byte pre-fetching PCI TRDY Control Enable In a target access, negate the TRDY, within 5 cycles before disconnection. 0: Disabled 1: Enabled PCI Pre-Fetch Enable 0: Disabled 1: Enabled
31 to 24
23 to 12
All 0
SH: R PCI: R SH: R/W PCI: R
11
PFCS
0
10
FTO
0
SH: R/W PCI: R
9
PFE
0
SH: R/W PCI: R
Rev. 1.00 Oct. 01, 2007 Page 486 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 8
Bit Name TBS
Initial Value 0
R/W
Description
SH: R/W Byte Swap PCI: R Specifies whether or not byte data is swapped when accessing to the PCI local bus. 0: No swap 1: Byte data is swapped For details, see section 13.4.3 (5), Endian or section 13.4.4 (6), Endian. SH: R PCI: R Reserved This bit is always read as 0. The write value should always be 0. Controls the PCI bus arbitration mode when the PCIC operates in host bus bridge mode. This bit is ignored when the PCIC operates in normal mode. 0: Fixed mode (PCIC > device0 > device1 > device2 > device3) 1: Pseudo round robin (the most recently granted device is assigned the lowest priority)
7
0
6
BMAM
0
SH: R/W Bus Master Arbitration PCI: R
5, 4
Undefined SH: R
Reserved These bits are always read as an undefined value. The write value should always be 0. Reserved This bit is always read as 0. The write value should always be 0. Controls the INTA output by software. This bit is valid only in normal mode. 0: Makes INTA output high-impedance state (driven high by pull-up register) 1: Asserts INTA output (low level output)
PCI: R 3 0 SH: R PCI: R 2 IOCS 0
SH: R/W INTA Output PCI: R
Rev. 1.00 Oct. 01, 2007 Page 487 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 1
Bit Name RSTCTL
Initial Value 0
R/W
Description Controls the PCIRESET output by software. This bit is valid when the PCIC operates in host bus bridge mode. 0: Negates PCIRESET output (high level output) 1: Asserts PCIRESET output (low level output) Note: The PCIRESET is also asserted during poweron reset.
SH: R/W PCIRESET Output PCI: R
0
CFINIT
0
SH: R/W PCI Internal Register Initialize Control PCI: R Set this bit to 1 after the initialization of the PCIC internal registers are completed. Setting this bit enables accesses from the PCI bus. During initialization in host bus bridge mode, the bus is not given to the device on the PCI bus. In normal mode, the PCIC returns RETRY when it is accessed from the PCI bus. 0: During initialization 1: Initialization completed
(2)
PCI Local Space Register 0 (PCILSR0)
Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Bit: 31 --
Initial value: SH R/W:
30 -- 0 R R
14 --
29 -- 0 R R
13
28
27
26
25
24 LSR
23
22
21
20
19 --
18 -- 0 R R
2
17 -- 0 R R
1
16 -- 0 R R
0
MBA RE
0 R R
15
0 R/W R
12
0 R/W R
11
0 R/W R
10
0 R/W R
9
0 R/W R
8
0 R/W R
7
0 R/W R
6
0 R/W R
5
0 R/W R
4
0 R R
3
PCI R/W:
Bit:
--
Initial value: SH R/W:
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
0 R R
0 R R
0 R/W R
PCI R/W:
Rev. 1.00 Oct. 01, 2007 Page 488 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit
Bit Name
Initial Value All 0
R/W SH: R PCI: R
Description Reserved These bits are always read as 0. The write value should always be 0. Size of Local Address Space 0 (9 bits) Specify the size of local address space 0 (SuperHyway bus address space of this LSI) in units of Mbyte. The value set in these bits must be the size minus 1 Mbytes. Setting all the bits to 0 ensures 1Mbyte space. 0 0000 0000: 1 Mbyte 0 0000 0001: 2 Mbytes 0 0000 0011: 4 Mbytes 0 0000 0111: 8 Mbytes 0 0000 1111: 16 Mbytes 0 0001 1111: 32 Mbytes 0 0011 1111: 64 Mbytes 0 0111 1111: 128 Mbytes 0 1111 1111: 256 Mbytes 1 1111 1111: 512 Mbytes Other than above: Setting prohibited
31 to 29
28 to 20 LSR
0 0000 SH: R/W 0000 PCI: R
19 to 1
All 0
SH: R PCI: R
Reserved These bits are always read as 0. The write value should always be 0. PCI Memory Base Address Register 0 Enable The local address space 0 can be accessed by setting this bit to 1. 0: PCIMBAR0 disabled 1: PCIMBAR0 enabled
0
MBARE
0
SH: R/W PCI: R
Rev. 1.00 Oct. 01, 2007 Page 489 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(3)
PCI Local Space Register 1 (PCILSR1)
Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Bit: 31 --
Initial value: SH R/W:
30 -- 0 R R
14 --
29 -- 0 R R
13
28
27
26
25
24 LSR
23
22
21
20
19 --
18 -- 0 R R
2
17 -- 0 R R
1
16 -- 0 R R
0
MBA RE
0 R R
15
0 R/W R
12
0 R/W R
11
0 R/W R
10
0 R/W R
9
0 R/W R
8
0 R/W R
7
0 R/W R
6
0 R/W R
5
0 R/W R
4
0 R R
3
PCI R/W:
Bit:
--
Initial value: SH R/W:
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
0 R R
0 R R
0 R/W R
PCI R/W:
Bit
Bit Name
Initial Value All 0
R/W SH: R PCI: R
Description Reserved These bits are always read as 0. The write value should always be 0. Size of Local Address Space 1 (9 bits) Specify the size of local address space 1 (SuperHyway bus address space of this LSI) in units of Mbyte. The value set in these bits must be the size minus 1 Mbytes. Setting all the bits to 0 ensures 1Mbyte space. 0 0000 0000: 1 Mbyte 0 0000 0001: 2 Mbytes 0 0000 0011: 4 Mbytes 0 0000 0111: 8 Mbytes 0 0000 1111: 16 Mbytes 0 0001 1111: 32 Mbytes 0 0011 1111: 64 Mbytes 0 0111 1111: 128 Mbytes 0 1111 1111: 256 Mbytes 1 1111 1111: 512 Mbytes Other than above: Setting prohibited
31 to 29
28 to 20 LSR
0 0000 SH: R/W 0000 PCI: R
19 to 1
All 0
SH: R PCI: R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 490 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 0
Bit Name MBARE
Initial Value 0
R/W SH: R/W PCI: R
Description PCI Memory Base Address Register 1 Enable The local address space 1 can be accessed by setting this bit to 1. 0: PCIMBAR1 disabled 1: PCIMBAR1 enabled
(4)
PCI Local Address Register 0 (PCILAR0)
Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Bit: 31 30 29 28 27 26 25 LAR
Initial value: SH R/W:
24
23
22
21
20
19 --
18 -- 0 R R
2
17 -- 0 R R
1
16 -- 0 R R
0
0 R/W R
15
0 R/W R
14 --
0 R/W R
13
0 R/W R
12
0 R/W R
11
0 R/W R
10
0 R/W R
9
0 R/W R
8
0 R/W R
7
0 R/W R
6
0 R/W R
5
0 R/W R
4
0 R R
3
PCI R/W:
Bit:
--
Initial value: SH R/W:
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
0 R R
0 R R
PCI R/W:
Bit
Initial Bit Name Value R/W PCI: R
Description Specify bits 31 to 20 of the start address in local address space 0. The effective bits of LAR depend on the capacity of local address space 0 as specified in PCILSR0. The effective bits are as follows:
PCILSR0.LS0([28:20]) = 0 0000 0000: Effective bits are [31:20] PCILSR0.LS0([28:20]) = 0 0000 0001: Effective bits are [31:21] PCILSR0.LS0([28:20]) = 0 0000 0011: Effective bits are [31:22] | |
31 to 20 LAR
H'000 SH: R/W Local Address (12 bits)
PCILSR0.LS0([28:20]) = 0 1111 1111: Effective bits are [31:28] PCILSR0.LS0([28:20]) = 1 1111 1111: Effective bits are [31:29]
19 to 0
All 0
SH: R PCI: R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 491 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(5)
PCI Local Address Register 1 (PCILAR1)
Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Bit: 31 30 29 28 27 26 25 LAR
Initial value: SH R/W:
24
23
22
21
20
19 --
18 -- 0 R R
2
17 -- 0 R R
1
16 -- 0 R R
0
0 R/W R
15
0 R/W R
14 --
0 R/W R
13
0 R/W R
12
0 R/W R
11
0 R/W R
10
0 R/W R
9
0 R/W R
8
0 R/W R
7
0 R/W R
6
0 R/W R
5
0 R/W R
4
0 R R
3
PCI R/W:
Bit:
--
Initial value: SH R/W:
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
0 R R
0 R R
PCI R/W:
Bit
Bit Name
Initial Value H'000
R/W SH: R/W PCI: R
Description Local Address (12 bits) Specify bits 31 to 20 of the start address in local address space 1. The effective bits of LAR depend on the capacity of local address space 1 as specified in PCILSR1. The effective bits are as follows:
PCILSR1.LS1([28:20]) = 0 0000 0000: Effective bits are [31:20] PCILSR1.LS1([28:20]) = 0 0000 0001: Effective bits are [31:21] PCILSR1.LS1([28:20]) = 0 0000 0011: Effective bits are [31:22] | |
31 to 20 LAR
PCILSR0.LS1([28:20]) = 0 1111 1111: Effective bits are [31:28] PCILSR1.LS1([28:20]) = 1 1111 1111: Effective bits are [31:29]
19 to 0
All 0
SH: R PCI: R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 492 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(6)
PCI Interrupt Register (PCIIR)
PCIIR records the source of an interrupt. When multiple interrupts occur, only the first source is registered. When an interrupt is disabled, the source is registered in corresponding bit (set to 1) in this register, however, no interrupt occurs.
Bit: 31
--
30
--
29
-- 0 R R
13
28
-- 0 R R
12
27
-- 0 R R
11
26
-- 0 R R
10
25
-- 0 R R
9
24
-- 0 R R
8
23
-- 0 R R
22
-- 0 R R
21
-- 0 R R
20
-- 0 R R
19
-- 0 R R
18
-- 0 R R
17
-- 0 R R
16
-- 0 R R
Initial value: SH R/W: PCI R/W:
Bit:
0 R R
15
0 R R
14
TTA DI
--
Initial value: SH R/W:
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
0 R R
0 R/WC R
7 6 5 4 3 2 1 0 APE SE DPEI DPEI TAD MAD MW MRD DI DI TW TR IM IM PDI PEI 0 0 0 0 0 0 0 0 0 0 R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC
TMT OI MDEI
PCI R/W:
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
Initial Value All 0
R/W SH: R PCI: R
Description Reserved These bits are always read as 0. The write value should always be 0. Target Target-Abort Interrupt Indicates that the PCIC has terminated a transaction with a target-abort when the PCIC functions as a target. A target-abort is detected as an illegal byte enable when the lower two bits (bits 1 and 0) of the address and the byte enable do not match during an I/O transfer (target). 0: Target-abort interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Target-abort interrupt occurs [Set condition] When a target-abort interrupt occurs.
31 to 15
14
TTADI
0
SH: R/WC PCI: R
Rev. 1.00 Oct. 01, 2007 Page 493 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit
Bit Name
Initial Value All 0
R/W SH: R PCI: R
Description Reserved These bits are always read as 0. The write value should always be 0. Target Memory Read Retry Timeout Interrupt When the PCIC functions as a target, the master did not attempt a retry within the prescribed number of 15 PCICLK clocks (2 ) (detected only in the case of memory read operations). 0: Target memory read retry timeout interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Target memory read retry timeout interrupt occurs [Set condition] When a target memory read retry timeout interrupt occurs.
13 to 10
9
TMTOI
0
SH: R/WC PCI: R
8
MDEI
0
SH: R/WC PCI: R
Master Function Disable Error Interrupt The PCIC attempted a master access when such accesses are disabled, that is, when PCICMD.BM is cleared to 0. 0: Master function disable error interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Master function disable error interrupt occurs [Set condition] When a master function disable error interrupt occurs.
Rev. 1.00 Oct. 01, 2007 Page 494 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 7
Bit Name APEDI
Initial Value 0
R/W SH: R/WC PCI: R
Description Address Parity Error Detection Interrupt Indicates an address parity error has been detected. When both the PER and SERRE bits in the PCI command register are set to 1, an address parity error is detected. 0: Address parity error detection interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Address parity error detection interrupt occurs [Set condition] When an address parity error detection interrupt occurs.
6
SEDI
0
SH: R/WC PCI: R
SERR Detection Interrupt Indicates that the assertion of the SERR signal has been detected when the PCIC operates in host bus bridge mode. 0: SERR detection interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: SERR detection interrupt occurs [Set condition] When a SERR detection interrupt occurs.
5
DPEITW
0
SH: R/WC PCI: R
Data Parity Error Interrupt for Target Write Indicates that a data parity error has been detected during a target write access (only detected when PCICMD.PER is set to 1) when the PCIC functions as a target. 0: Data parity error detection interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Data parity error detection interrupt occurs [Set condition] When a data parity error detection interrupt occurs.
Rev. 1.00 Oct. 01, 2007 Page 495 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 4
Bit Name PEDITR
Initial Value 0
R/W SH: R/WC PCI: R
Description Data Parity Error Interrupt for Target PERR Indicates that the PERR signal has been received during a target read access (only detected when PCICMD.PER is set to 1) when the PCIC functions as a target. 0: PERR detection interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: PERR detection interrupt occurs [Set condition] When a PERR detection interrupt occurs.
3
TADIM
0
SH: R/WC PCI: R
Target-Abort Detection Interrupt for Master When the PCIC functions as a master, it has detected a target-abort, that is, the transaction is terminated. 0: Target-abort interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Target-abort interrupt occurs [Set condition] When a target-abort interrupt occurs.
2
MADIM
0
SH: R/WC PCI: R
Master-Abort Interrupt for Master Indicates that the PCIC has terminated a transaction with a master-abort when the PCIC functions as a master. 0: Master-abort interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Master-abort interrupt occurs [Set condition] When a master-abort interrupt occurs.
Rev. 1.00 Oct. 01, 2007 Page 496 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 1
Bit Name MWPDI
Initial Value 0
R/W
Description Indicates that the PERR signal has been received during a master write access (only detected when PCICMD.PER is set to 1) when the PCIC functions as a master. 0: Master write PERR interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Master write PERR interrupt occurs [Set condition] When a master write PERR interrupt occurs.
SH: R/WC Master Write PERR Detection Interrupt PCI: R
0
MRDPEI
0
SH: R/WC Master Read Data Parity Error Interrupt PCI: R Indicates that a data parity error has been detected during a master read access (only detected when PCICMD.PER is set to 1) when the PCIC functions as a master. 0: Master read data perity error interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Master read data perity error interrupt occurs [Set condition] When a master read data perity error interrupt occurs.
Rev. 1.00 Oct. 01, 2007 Page 497 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(7)
PCI Interrupt Mask Register (PCIIMR)
This register is the mask register for PCIIR.
Bit: 31
--
30
--
29
-- 0 R R
13
28
-- 0 R R
12
27
-- 0 R R
11
26
-- 0 R R
10
25
-- 0 R R
9
TMT OIM
24
-- 0 R R
8
MDE IM
23
-- 0 R R
7 APE DIM 0 R/W
22
-- 0 R R
21
-- 0 R R
20
-- 0 R R
19
-- 0 R R
3 TAD IMM 0 R/W
18
-- 0 R R
17
-- 0 R R
16
-- 0 R R
Initial value: SH R/W: PCI R/W:
Bit:
0 R R
15
0 R R
14
TTA DIM
--
Initial value: SH R/W:
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
0 R R
0 R/W R
0 R/W R
0 R/W R
6 5 4 SE DPEI DPEI DIM TWM TRM 0 0 0 R/W R/W R/W
2 1 0 MAD MW MRD IMM PDIM PEIM 0 0 0 R/W R/W R/W
PCI R/W:
R
R
R
R
R
R
R
R
Bit
Bit Name
Initial Value All 0
R/W SH: R PCI: R
Description Reserved These bits are always read as 0. The write value should always be 0. Target Target-Abort Interrupt Mask 0: PCIIR.TTADI disabled (masked) 1: PCIIR.TTADI enabled (not masked) Reserved These bits are always read as 0. The write value should always be 0. Target Retry Time Out Interrupt Mask 0: PCIIR.TMTOI disabled (masked) 1: PCIIR. TMTOI enabled (not masked) Master Function Disable Error Interrupt Mask 0: PCIIR.MDEI disabled (masked) 1: PCIIR.MDEI enabled (not masked) Address Parity Error Detection Interrupt Mask 0: PCIIR.APEDI disabled (masked) 1: PCIIR.APEDI enabled (not masked)
31 to 15
14
TTADIM
0
SH: R/W PCI: R
13 to 10
All 0
SH: R PCI: R
9
TMTOIM
0
SH: R/W PCI: R
8
MDEIM
0
SH: R/W PCI: R
7
APEDIM
0
SH: R/W PCI: R
Rev. 1.00 Oct. 01, 2007 Page 498 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 6
Bit Name SEDIM
Initial Value 0
R/W SH: R/W PCI: R
Description SERR Detection Interrupt Mask 0: PCIIR.SEDI disabled (masked) 1: PCIIR.SEDI enabled (not masked) Data Parity Error Interrupt Mask for Target Write 0: PCIIR.DPEITW disabled (masked) 1: PCIIR.DPEITW enabled (not masked) PERR Detection Interrupt Mask for Target Read 0: PCIIR.PEDITR disabled (masked) 1: PCIIR.PEDITR enabled (not masked) Target-Abort Interrupt Mask for Master 0: PCIIR.TADIM disabled (masked) 1: PCIIR.TADIM enabled (not masked) Master-Abort Interrupt Mask for Master 0: PCIIR.MADIM disabled (masked) 1: PCIIR.MADIM enabled (not masked) Master Write Data Parity Error Interrupt Mask 0: PCIIR.MWPDI disabled (masked) 1: PCIIR.MWPDI enabled (not masked) Master Read Data Parity Error Interrupt Mask 0: PCIIR.MRDPEI disabled (masked) 1: PCIIR.MRDPEI enabled (not masked)
5
DPEITWM 0
SH: R/W PCI: R
4
PEDITRM
0
SH: R/W PCI: R
3
TADIMM
0
SH: R/W PCI: R
2
MADIMM
0
SH: R/W PCI: R
1
MWPDIM
0
SH: R/W PCI: R
0
MRDPEIM 0
SH: R/W PCI: R
Rev. 1.00 Oct. 01, 2007 Page 499 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(8)
PCI Error Address Information Register (PCIAIR)
This register records PCI address information when an error is detected.
Bit: 31 30 29 28 27 26 25 24 AIL Initial value: SH R/W: PCI R/W: Bit: -- R R 15 -- R R 14 -- R R 13 -- R R 12 -- R R 11 -- R R 10 -- R R 9 -- R R 8 AIL Initial value: SH R/W: PCI R/W: -- R R -- R R -- R R -- R R -- R R -- R R -- R R -- R R -- R R -- R R -- R R -- R R -- R R -- R R -- R R -- R R -- R R 7 -- R R 6 -- R R 5 -- R R 4 -- R R 3 -- R R 2 -- R R 1 -- R R 0 23 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name AIL
Initial Value
R/W PCI: R
Description Address Information Log This register holds address information (the states of the AD signals) when an error occurs.
Undefined SH: R
Rev. 1.00 Oct. 01, 2007 Page 500 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(9)
PCI Error Command Information Register (PCICIR)
This register records the PCI command information when an error is detected.
Bit: 31 MTEM Initial value: SH R/W: PCI R/W:
Bit:
30
--
29 -- 0 R R
13
28 -- 0 R R
12
27 -- 0 R R
11
-- R R
15
0 R R
14 --
26 RW TET -- R R
10
25 -- 0 R R
9
24 -- 0 R R
8
23 -- 0 R R
7
22 -- 0 R R
6
21 -- 0 R R
5
20 -- 0 R R
4
19 -- 0 R R
3
18 -- 0 R R
2
17 -- 0 R R
1
16 -- 0 R R
0
--
Initial value: SH R/W:
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R -- R R
ECL -- R R -- R R -- R R
0 R R
0 R R
PCI R/W:
Bit 31
Bit Name MTEM
Initial Value
R/W
Description Master Error
Undefined SH: R
PCI: R Indicates that an error has occurred during a master access. 0: Master error does not occur 1: Master error occurs 30 to 27 All 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. 26 RWTET Undefined SH: R Target Error PCI: R Indicates that an error has occurred during a target read or a target write access. 0: Target error does not occur 1: Target error occurs 25 to 4 All 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. 3 to 0 ECL Undefined SH: R Command Log PCI: R Hold PCI command information (the state of the CBE[3:0] signal) when an error occurs.
Rev. 1.00 Oct. 01, 2007 Page 501 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(10) PCI Arbiter Interrupt Register (PCIAINT) In host bus bridge mode, this register records source of an interrupt. When multiple interrupts occur, only the first source is registered. When an interrupt is disabled, source is registered in corresponding bit (set to 1) in this register, however, no interrupt occurs.
Bit: 31 -- Initial value: SH R/W: PCI R/W:
Bit:
30
--
29 -- 0 R R
13
28 -- 0 R R
12
TB TOI
27 -- 0 R R
11
MB TOI
26 -- 0 R R
10
25 -- 0 R R
9
24 -- 0 R R
8
23 -- 0 R R
7
22 -- 0 R R
6
21 -- 0 R R
5
20 -- 0 R R
4
19 -- 0 R R
3
18 -- 0 R R
2
17 -- 0 R R
1
RD PEI
16 -- 0 R R
0
WD PEI
0 R R
15
0 R R
14 --
--
Initial value: SH R/W:
MBI
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
TAI
MAI
0 R R
0 R R
0 0 0 R/WC R/WC R/WC R R R
0 0 0 0 R/WC R/WC R/WC R/WC R R R R
PCI R/W:
Bit
Bit Name
Initial Value All 0
R/W SH: R PCI: R
Description Reserved These bits are always read as 0. The write value should always be 0. An interrupt is detected when the PCIFRAME signal is not asserted within 16 clock cycles, although the PCIC gave a master the bus. 0: Master-broken interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Master-broken interrupt occurs [Set condition] When a master-broken interrupt occurs.
31 to 14
13
MBI
0
SH: R/WC Master-Broken Interrupt PCI: R
Rev. 1.00 Oct. 01, 2007 Page 502 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 12
Bit Name TBTOI
Initial Value 0
R/W
Description An interrupt is detected when the TRDY or STOP signal is not asserted within 16 clock cycles on the first data transfer. An interrupt is detected when the TRDY or STOP signal is not asserted within eight clock cycles during the data transfer subsequent to the 2nd. 0: Target bus time-out interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Target bus time-out interrupt occurs [Set condition] When a target bus time-out interrupt occurs.
SH: R/WC Target Bus Time-Out Interrupt PCI: R
11
MBTOI
0
SH: R/WC Master Bus Time-Out Interrupt PCI: R An interrupt is detected when the IRDY signal is not asserted within 8 clock cycles. 0: Master bus time-out interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Master bus time-out interrupt occurs [Set condition] When a master bus time-out interrupt occurs.
10 to 4
All 0
SH: R PCI: R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 503 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 3
Bit Name TAI
Initial Value 0
R/W SH: R/WC PCI: R
Description Target-Abort Interrupt Indicates that a transaction is terminated with a target-abort when a device other than the PCIC functions as a bus master. 0: Target-abort interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Target-abort interrupt occurs [Set condition] When a target-abort interrupt occurs.
2
MAI
0
SH: R/WC PCI: R
Master-Abort Interrupt Indicates that a transaction is terminated with a master-abort when a device other than the PCIC functions as a bus master. 0: Master-abort interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Master-abort interrupt occurs [Set condition] When a master-abort interrupt occurs.
1
RDPEI
0
SH: R/WC PCI: R
Read Parity Error Interrupt The PERR assertion is detected during a data read when a device other than the PCIC functions as a bus master. 0: Read parity error interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Read parity error interrupt occurs [Set condition] When a read parity error interrupt is detected by the PERR assertion.
Rev. 1.00 Oct. 01, 2007 Page 504 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 0
Bit Name WDPEI
Initial Value 0
R/W SH: R/WC PCI: R
Description Write Parity Error Interrupt The PERR assertion is detected during a data write when a device other than the PCIC functions as a bus master. 0: Write parity error interrupt does not occur [Clear condition] Write 1 to this bit (write clear). 1: Write parity error interrupt occurs [Set condition] When a write parity error interrupt is detected by the PERR assertion.
(11) PCI Arbiter Interrupt Mask Register (PCIAINTM) This register is the mask register for PCIAINT.
Bit: 31 -- Initial value: SH R/W: PCI R/W:
Bit:
30
--
29 -- 0 R R
13
28 -- 0 R R
12
TBT OIM
27 -- 0 R R
11
MBT OIM
26 -- 0 R R
10
25 -- 0 R R
9
24 -- 0 R R
8
23 -- 0 R R
7
22 -- 0 R R
6
21 -- 0 R R
5
20 -- 0 R R
4
19 -- 0 R R
18 -- 0 R R
17 -- 0 R R
16 -- 0 R R
0
WDP EIM
0 R R
15
0 R R
14 --
--
Initial value: SH R/W:
MBIM 0 R/W R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
3 2 1 TAIM MAIM RDP EIM
0 R R
0 R R
0 R/W R
0 R/W R
0 R/W R
0 R/W R
0 R/W R
0 R/W R
PCI R/W:
Bit
Bit Name
Initial Value All 0
R/W SH: R PCI: R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 14
Rev. 1.00 Oct. 01, 2007 Page 505 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 13
Bit Name MBIM
Initial Value 0
R/W SH: R/WC PCI: R
Description Master-Broken Interrupt Mask 0: PCIAINT.MBI disabled (masked) 1: PCIAINT.MBI enabled (not masked) Target Bus Time-Out Interrupt Mask 0: PCIAINT.TBTOI disabled (masked) 1: PCIAINT.TBTOI enabled (not masked) Master Bus Time-Out Interrupt Mask 0: PCIAINT.MBTOI disabled (masked) 1: PCIAINT.MBTOI enabled (not masked) Reserved These bits are always read as 0. The write value should always be 0. Target-Abort Interrupt Mask 0: PCIAINT.TAI disabled (masked) 1: PCIAINT.TAI enabled (not masked) Master-Abort Interrupt Mask 0: PCIAINT.MAI disabled (masked) 1: PCIAINT.MAI enabled (not masked) Read Data Parity Error Interrupt Mask 0: PCIAINT.RDPEI disabled (masked) 1: PCIAINT.RDPEI enabled (not masked) Write Data Parity Error Interrupt Mask 0: PCIAINT.WDPEI disabled (masked) 1: PCIAINT.WDPEI enabled (not masked)
12
TBTOIM
0
SH: R/WC PCI: R
11
MBTOIM
0
SH: R/WC PCI: R
10 to 4
All 0
SH: R PCI: R
3
TAIM
0
SH: R/WC PCI: R
2
MAIM
0
SH: R/WC PCI: R
1
RDPEIM
0
SH: R/WC PCI: R
0
WDPEIM
0
SH: R/WC PCI: R
Rev. 1.00 Oct. 01, 2007 Page 506 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(12) PCI Arbiter Bus Master Information Register (PCIBMIR) In host bridge mode, this register records when the interrupt is invoked by PCIAINT. When multiple interrupts occur, only the first source is registered. When an interrupt is masked, the source is registered in corresponding bit (set to 1), however, an interrupt occurs.
Bit: 31 -- Initial value: SH R/W: PCI R/W:
Bit:
30
--
29 -- 0 R R
13
28 -- 0 R R
12
27 -- 0 R R
11
26 -- 0 R R
10
25 -- 0 R R
9
24 -- 0 R R
8
23 -- 0 R R
7
22 -- 0 R R
6
21 -- 0 R R
5
20 -- 0 R R
4
19 -- 0 R R
3
18 -- 0 R R
2
17 -- 0 R R
1
16 -- 0 R R
0
0 R R
15
0 R R
14 --
--
Initial value: SH R/W:
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
-- 0 R R
REQ4 REQ3 REQ2 REQ1 REQ0 BME BME BME BME BME
0 R R
0 R R
-- R R
-- R R
-- R R
-- R R
-- R R
PCI R/W:
Bit 31 to 5
Bit Name
Initial Value All 0
R/W SH: R PCI: R
Description Reserved These bits are always read as 0. The write value should always be 0. REQ4 Error An error occurs when the PCIC functions as a bus master. REQ3 Error An error occurs when device 3 (REQ3) functions as a bus master REQ2 Error An error occurs when device 2 (REQ2) functions as a bus master REQ1 Error An error occurs when device 1 (REQ1) functions as a bus master REQ0 Error An error occurs when device 0 (REQ0) functions as a bus master
4
REQ4BME Undefined SH: R PCI: R
3
REQ3BME Undefined SH: R PCI: R
2
REQ2BME Undefined SH: R PCI: R
1
REQ1BME Undefined SH: R PCI: R
0
REQ0BME Undefined SH: R PCI: R
Rev. 1.00 Oct. 01, 2007 Page 507 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(13) PCI PIO Address Register (PCIPAR) This register is configuration address register. Refer to Section 13.4.5 (2), Configuration Space Access.
Bit: 31 CCIE Initial value: SH R/W: PCI R/W:
Bit:
30
--
29 -- 0 R
--
13 DN
28 -- 0 R
--
12
27 -- 0 R
--
11
26 -- 0 R
--
10
25 -- 0 R
--
9
24 -- 0 R
--
8
23
22
21
20 BN
19
18
17
16
1 R
--
15
0 R
--
14
-- R/W --
7
-- R/W --
6
-- R/W --
5
-- R/W --
4
-- R/W --
3
-- R/W --
2
-- R/W --
1
-- R/W --
0
FN -- R/W -- -- R/W -- -- R/W -- -- R/W -- -- R/W -- -- R/W -- -- R/W --
CRA -- R/W -- -- R/W -- -- R/W -- -- R/W --
-- 0 R --
-- 0 R --
Initial value: SH R/W:
-- R/W --
-- R/W --
-- R/W --
PCI R/W:
Bit 31
Bit Name CCIE
Initial Value 1
R/W SH: R PCI:
Description Configuration Cycle Issue Enable Enables a configuration cycle to be issued. 1: Indicates the configuration cycle generation enable
30 to 24
All 0
SH: R PCI:
Reserved These bits are always read as 0. The write value should always be 0. Specify the PCI bus number for a configuration access. The PCIC is connected to bus number 0. Bus numbers ranging from 0 to 255 are represented in 8 bits.
23 to 16 BN
Undefined SH: R/W PCI Bus Number PCI:
Rev. 1.00 Oct. 01, 2007 Page 508 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit
Bit Name
Initial Value
R/W PCI:
Description
15 to 11 DN
Undefined SH: R/W Device Number Specify the device number for a configuration access. Device numbers ranging from 0 to 31 are represented in five bits. A single bit of bits 31 to 16 of the AD signals is driven to high level instead of the IDSEL assertion. The bit driven to high level corresponds to the device number set in these bits. The correspondence between the device number and IDSEL (AD[31:16]) is shown below. If a device number is equal to H'10 or greater, all bits 31 to 16 of the AD signals are driven to low level. Device No. IDSEL H'0: AD[16] = high level H'1: AD[17] = high level H'2: AD[18] = high level H'3: AD[19] = high level H'4: AD[20] = high level H'5: AD[21] = high level H'6: AD[22] = high level H'7: AD[23] = high level Device No. IDSEL H'8: AD[24] = high level H'9: AD[25] = high level H'A: AD[26] = high level H'B: AD[27] = high level H'C: AD[28] = high level H'D: AD[29] = high level H'E: AD[30] = high level H'F: AD[31] = high level
Other than above AD[31:16] lines are driven to high level. 10 to 8 FN Undefined SH: R/W Function Number PCI: Specify the function number for a configuration access. The function numbers ranging from 0 to 7 are represented in three bits. Specify the register for a configuration access at a longword boundary. Reserved These bits are always read as 0. The write value should always be 0.
7 to 2
CRA
Undefined SH: R/W Configuration Register Address PCI:
1, 0
All 0
SH: R PCI:
Rev. 1.00 Oct. 01, 2007 Page 509 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(14) PCI Power Management Interrupt Register (PCIPINT) This register controls the power management interrupt.
Bit: 31 -- Initial value: SH R/W: PCI R/W:
Bit:
30 -- 0 R --
14 --
29 -- 0 R --
13
28 -- 0 R --
12
27 -- 0 R --
11
26 -- 0 R --
10
25 -- 0 R --
9
24 -- 0 R --
8
23 -- 0 R --
7
22 -- 0 R --
6
21 -- 0 R --
5
20 -- 0 R --
4
19 -- 0 R --
18 -- 0 R --
17 -- 0 R --
16 -- 0 R --
0 R --
15
--
Initial value: SH R/W:
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
0 R
0 R --
3 2 1 0 PMD PMD PMD PMD 3H 2 1 0 0 0 0 0 R/WC R/WC R/WC R/WC
PCI R/W:
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Bit 31 to 4
Initial Bit Name Value All 0
R/W SH: R PCI:
Description Reserved These bits are always read as 0. The write value should always be 0.
3
PMD3H
0
SH: R/WC PCI Power Management D3 Hot Status Transition Interrupt PCI: 0: Interrupt request for a transition to D3 is not detected 1: Interrupt request for a transition to D3 is detected
2
PMD2
0
SH: R/WC PCI Power Management D2 Status Transition Interrupt PCI: 0: Interrupt request for a transition to D2 is not detected 1: Interrupt request for a transition to D2 is detected
1
PMD1
0
SH: R/WC PCI Power Management D1 Status Transition Interrupt PCI: 0: Interrupt request for a transition to D1 is not detected 1: Interrupt request for a transition to D1 is detected
0
PMD0
0
SH: R/WC PCI Power Management D0 Status Transition Interrupt PCI: 0: Interrupt request for a transition to D0 is not detected 1: Interrupt request for a transition to D0 is detected
Rev. 1.00 Oct. 01, 2007 Page 510 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(15) PCI Power Management Interrupt Mask Register (PCIPINTM) This is the mask register for PCIPINT.
Bit: 31 -- Initial value: SH R/W: PCI R/W:
Bit:
30 -- 0 R --
14 --
29 -- 0 R --
13
28 -- 0 R --
12
27 -- 0 R --
11
26 -- 0 R --
10
25 -- 0 R --
9
24 -- 0 R --
8
23 -- 0 R --
7
22 -- 0 R --
6
21 -- 0 R --
5
20 -- 0 R --
4
19 -- 0 R --
18 -- 0 R --
17 -- 0 R --
16 -- 0 R --
0 R --
15
--
Initial value: SH R/W:
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
0 R
0 R --
3 2 1 0 PMD PMD PMD PMD 3HM 2M 1M 0M 0 0 0 0 R/W R/W R/W R/W
PCI R/W:
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Bit 31 to 4
Bit Name
Initial Value All 0
R/W SH: R PCI:
Description Reserved These bits are always read as 0. The write value should always be 0. PCI Power Management D3 Hot Status Transition Interrupt Mask 0: PCIPINT.PM D3H disabled (masked) 1: PCIPINT.PM D3H enabled (not masked)
3
PMD3HM
0
SH: R/W PCI:
2
PMD2M
0
SH: R/W PCI:
PCI Power Management D2 Status Transition Interrupt Mask 0: PCIPINT.PMD2 disabled (masked) 1: PCIPINT.PMD2 enabled (not masked)
1
PMD1M
0
SH: R/W PCI:
PCI Power Management D1 Status Transition Interrupt Mask 0: PCIPINT.PMD1 disabled (masked) 1: PCIPINT.PMD1 enabled (not masked)
0
PMD0M
0
SH: R/W PCI:
PCI Power Management D0 Status Transition Interrupt Mask 0: PCIPINT.PMD0 disabled (masked) 1: PCIPINT.PMD0 enabled (not masked)
Rev. 1.00 Oct. 01, 2007 Page 511 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(16) PCI Memory Bank Register 0 (PCIMBR0) This register specifies the upper 14-bit address of the PCI memory space 0 (address bits 31 to 18). Refer to Section 13.4.3 (2), Accessing PCI Memory Space.
Bit: 31 30 29 28 27 26 25 PMSBA0 Initial value: SH R/W: PCI R/W:
Bit:
24
23
22
21
20
19
18
17 --
16 -- 0 R --
0
0 R/W --
15
0 R/W --
14 --
0 R/W --
13
0 R/W --
12
0 R/W --
11
0 R/W --
10
0 R/W --
9
0 R/W --
8
0 R/W --
7
0 R/W --
6
0 R/W --
5
0 R/W --
4
0 R/W --
3
0 R/W --
2
0 R --
1
--
Initial value: SH R/W:
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
--
0 R
--
0 R
--
0 R
--
0 R
0 R
0 R --
PCI R/W:
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Bit
Bit Name
Initial Value
R/W
Description PCI Memory Space 0 Bank Address Specify the bank address in PCI memory space 0 for a master access. Reserved These bits are always read as 0. The write value should always be 0.
31 to 18 PMSBA0
H'0000 SH: R/W PCI: All 0 SH: R PCI:
17 to 0
Rev. 1.00 Oct. 01, 2007 Page 512 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(17) PCI Memory Bank Mask Register 0 (PCIMBMR0) This register specifies the size of the PCI memory space 0. Refer to Section 13.4.3 (2), Accessing PCI Memory Space.
Bit: 31
--
30
--
29
--
28
--
27
--
26
--
25
--
24
--
23
22
21
20
19
18
17
--
16
--
MSBAM0
Initial value: SH R/W: PCI R/W:
Bit:
0 R --
15
0 R --
14
0 R --
13
0 R --
12
0 R --
11
0 R --
10
0 R --
9
0 R --
8
0 R/W --
7
0 R/W --
6
0 R/W --
5
0 R/W --
4
0 R/W --
3
0 R/W --
2
0 R --
1
0 R --
0
--
Initial value: SH R/W:
--
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
0 R --
0 R --
PCI R/W:
Bit
Bit Name
Initial Value All 0
R/W SH: R PCI:
Description Reserved These bits are always read as 0. The write value should always be 0. PCI Memory Space 0 Bank Address Mask 0000 00 : 256 Kbytes 0000 01 : 512 Kbytes 0000 11 : 1 Mbyte 0001 11 : 2 Mbytes 0011 11 : 4 Mbytes 0111 11 : 8 Mbytes 1111 11 : 16 Mbytes Other than above: Setting prohibited
31 to 24
23 to 18 MSBAM0
000000 SH: R/W PCI:
17 to 0
All 0
SH: R PCI:
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 513 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(18) PCI Memory Bank Register 1 (PCIMBR1) This register specifies the upper 14-bit address of the PCI memory space 1 (address bits 31 to 18). Refer to Section 13.4.3 (2), Accessing PCI Memory Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
--
16
--
PMSBA1
Initial value: SH R/W: PCI R/W:
Bit:
0 R/W --
15
0 R/W --
14
0 R/W --
13
0 R/W --
12
0 R/W --
11
0 R/W --
10
0 R/W --
9
0 R/W --
8
0 R/W --
7
0 R/W --
6
0 R/W --
5
0 R/W --
4
0 R/W --
3
0 R/W --
2
0 R --
1
0 R --
0
--
Initial value: SH R/W:
--
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
0 R --
0 R --
PCI R/W:
Bit
Bit Name
Initial Value All 0
R/W SH: R/W PCI:
Description PCI Memory Space 1 Bank Address Specify the bank address in PCI memory space 1 for a master access. Reserved These bits are always read as 0. The write value should always be 0.
31 to 18 PMSBA1
17 to 0
All 0
SH: R PCI:
Rev. 1.00 Oct. 01, 2007 Page 514 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(19) PCI Memory Bank Mask Register 1 (PCIMBMR1) This register specifies the size of the PCI memory space 1. Refer to Section 13.4.3 (2), Accessing PCI Memory Space.
Bit: 31
--
30
--
29
-- 0 R --
13
28
-- 0 R --
12
27
-- 0 R --
11
26
-- 0 R --
10
25
24
23
22
21
20
19
18
17
--
16
-- 0 R --
0
MSBAM1 0 R/W --
9
Initial value: SH R/W: PCI R/W:
Bit:
0 R --
15
0 R --
14
0 R/W --
8
0 R/W --
7
0 R/W --
6
0 R/W --
5
0 R/W --
4
0 R/W --
3
0 R/W --
2
0 R --
1
--
Initial value: SH R/W:
--
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
0 R --
0 R --
PCI R/W:
Bit
Bit Name
Initial Value All 0
R/W SH: R PCI:
Description Reserved These bits are always read as 0. The write value should always be 0. PCI Memory Space 1 Bank Address Mask (8 bits) 00 0000 00: 256 Kbytes 00 0000 01: 512 Kbytes 00 0000 11: 1 Mbyte 00 0001 11: 2 Mbytes 00 0011 11: 4 Mbytes 00 0111 11: 8 Mbytes 00 1111 11: 16 Mbytes 01 1111 11: 32 Mbytes 11 1111 11: 64 Mbytes Other than above: Setting prohibited
31 to 26
25 to 18 MSBAM1
All 0
SH: R/W PCI:
17 to 0
All 0
SH: R PCI:
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 515 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(20) PCI Memory Bank Register 2 (PCIMBR2) This register specifies the upper 14-bit address of the PCI memory space 2 (address bits 31 to 18). Refer to Section 13.4.3 (2), Accessing PCI Memory Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
--
16
--
PMSBA2
Initial value: SH R/W: PCI R/W:
Bit:
0 R/W --
15
0 R/W --
14
0 R/W --
13
0 R/W --
12
0 R/W --
11
0 R/W --
10
0 R/W --
9
0 R/W --
8
0 R/W --
7
0 R/W --
6
0 R/W --
5
0 R/W --
4
0 R/W --
3
0 R/W --
2
0 R --
1
0 R --
0
--
Initial value: SH R/W:
--
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
0 R --
0 R --
PCI R/W:
Bit
Bit Name
Initial Value All 0
R/W SH: R/W PCI: SH: R PCI:
Description PCI Memory Space 2 Bank Address Specify the bank address in PCI memory space 2 for a master access. Reserved These bits are always read as 0. The write value should always be 0.
31 to 18 PMSBA2
17 to 0
All 0
Rev. 1.00 Oct. 01, 2007 Page 516 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(21) PCI Memory Bank Mask Register 2 (PCIMBMR2) This register specifies the size of the PCI memory space 2. Refer to Section 13.4.3 (2), Accessing PCI Memory Space.
Bit: 31
--
30
--
29
--
28
27
26
25
24
23
22
21
20
19
18
17
--
16
--
MSBAM2
Initial value: SH R/W: PCI R/W:
Bit:
0 R --
15
0 R --
14
0 R --
13
0 R/W --
12
0 R/W --
11
0 R/W --
10
0 R/W --
9
0 R/W --
8
0 R/W --
7
0 R/W --
6
0 R/W --
5
0 R/W --
4
0 R/W --
3
0 R/W --
2
0 R --
1
0 R --
0
--
Initial value: SH R/W:
--
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
0 R --
0 R --
PCI R/W:
Bit
Bit Name
Initial Value All 0
R/W SH: R PCI:
Description Reserved These bits are always read as 0. The write value should always be 0. PCI Memory Space 2 Bank Address Mask 0 0000 0000 00: 256 Kbytes 0 0000 0000 01: 512 Kbytes 0 0000 0000 11: 1 Mbyte 0 0000 0001 11: 2 Mbytes 0 0000 0011 11: 4 Mbytes 0 0000 0111 11: 8 Mbytes 0 0000 1111 11: 16 Mbytes 0 0001 1111 11: 32 Mbytes 0 0011 1111 11: 64 Mbytes 0 0111 1111 11: 128 Mbytes 0 1111 1111 11: 256 Mbytes 1 1111 1111 11: 512 Mbytes Other than above: Setting prohibited
31 to 29
28 to 18 MSBAM2
All 0
SH: R/W PCI:
17 to 0
All 0
SH: R PCI:
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 517 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(22) PCI I/O Bank Register (PCIIOBR) This register specifies the upper 14-bit address of the PCI I/O space (address bits 31 to 18). Refer to Section 13.4.3 (3), Accessing PCI I/O Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
--
16
--
PIOSBA
Initial value: SH R/W: PCI R/W:
Bit:
0 R/W --
15
0 R/W --
14
0 R/W --
13
0 R/W --
12
0 R/W --
11
0 R/W --
10
0 R/W --
9
0 R/W --
8
0 R/W --
7
0 R/W --
6
0 R/W --
5
0 R/W --
4
0 R/W --
3
0 R/W --
2
0 R --
1
0 R --
0
--
Initial value: SH R/W:
--
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
0 R --
0 R --
PCI R/W:
Bit
Bit Name
Initial Value All 0
R/W SH: R/W PCI:
Description PCI I/O Space Bank Address (14 bits) Specify the bank address in PCI I/O space for a master access. Reserved These bits are always read as 0. The write value should always be 0.
31 to 18 PIOSBA
17 to 0
All 0
SH: R PCI:
Rev. 1.00 Oct. 01, 2007 Page 518 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(23) PCI I/O Bank Mask Register (PCIIOBMR) This register specifies the size of the PCI I/O space. Refer to Section 13.4.3 (2), Accessing PCI Memory Space.
Bit: 31
--
30
--
29
--
28
--
27
--
26
--
25
--
24
--
23
--
22
--
21
--
20
19
IOBAMR
18
17
--
16
--
Initial value: SH R/W: PCI R/W:
Bit:
0 R --
15
0 R --
14
0 R --
13
0 R --
12
0 R --
11
0 R --
10
0 R --
9
0 R --
8
0 R --
7
0 R --
6
0 R --
5
0 R/W --
4
0 R/W --
3
0 R/W --
2
0 R --
1
0 R --
0
--
Initial value: SH R/W:
-- 0 R
--
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
-- 0 R --
0 R --
PCI R/W:
Bit
Bit Name
Initial Value All 0
R/W SH: R PCI:
Description Reserved These bits are always read as 0. The write value should always be 0. PCI I/O Space Bank Address Mask (3 bits) 000: 256 Kbytes 001: 512 Kbytes 011: 1 Mbyte 111: 2 Mbytes Other than above: Setting prohibited
31 to 21 --
20 to 18 IOBAMR
All 0
SH: R/W PCI:
17 to 0
All 0
SH: R PCI:
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 519 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(24) PCI Cache Snoop Control Register 0 (PCICSCR0) An external device can access local memory of this LSI via the PCIC. When an external PCI device accesses cacheable areas of this LSI, the PCIC can support cache snoop function to the onchip caches. The PCICSCR0 specifies this function that uses cache snoop address registers 0. Refer to section 13.4.4 (7), Cache Coherency.
Bit: 31
--
30
--
29
--
28
--
27
--
26
--
25
--
24
--
23
--
22
--
21
--
20
--
19
--
18
--
17
--
16
--
Initial value: SH R/W: PCI R/W:
Bit:
0 R
-- 15
0 R
-- 14
0 R
-- 13
0 R
-- 12
0 R
-- 11
0 R
-- 10
0 R
-- 9
0 R
-- 8
0 R
-- 7
0 R
-- 6
0 R
-- 5
0 R
-- 4
0 R
-- 3
0 R
-- 2
0 R
-- 1
0 R
-- 0
--
Initial value: SH R/W:
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
RANGE 0 R/W
--
SNPMD 0 R/W
--
0 R
--
0 R
--
0 R/W
--
0 R/W
--
0 R/W
--
PCI R/W:
Bit 31 to 5
Bit Name
Initial Value All 0
R/W SH: R PCI: --
Description Reserved These bits are always read as 0. The write value should always be 0. Address Range to be Compared Specify the address range of PCICSAR0 to be compared.
000: PCICSAR[n].CADR[31:12] compared (4 Kbytes) 001: PCICSAR[n].CADR[31:16] compared (64 Kbytes) 010: PCICSAR[n].CADR[31:20] compared (1 Mbyte) 011: PCICSAR[n].CADR[31:24] compared (16 Mbytes) 100: PCICSAR[n].CADR[31:25] compared (32 Mbytes) 101: PCICSAR[n].CADR[31:26] compared (64 Mbytes) 110: PCICSAR[n].CADR[31:27] compared (128 Mbytes) 111: PCICSAR[n].CADR[31:28] compared (256 Mbytes)
4 to 2
RANGE
All 0
SH: R/W PCI: --
Valid only when PCICSCR0.SNPMD = 10 or 11.
Rev. 1.00 Oct. 01, 2007 Page 520 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 1, 0
Bit Name SNPMD
Initial Value All 0
R/W SH: R/W PCI: --
Description Snoop Mode for PCICSAR0 Specify if PCICSAR0 is compared with address requested by an external device. Also, specify how snoop function is executed when PCICSAR0 is compared. 00: PCICSAR0 not compared 01: Reserved (setting prohibited) 10: PCICSAR0 compared. If hit, snoop function is not executed, otherwise executed. 11: PCICSAR0 compared. If hit, snoop function is executed, otherwise not executed.
Rev. 1.00 Oct. 01, 2007 Page 521 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(25) PCI Cache Snoop Control Register 1 (PCICSCR1) An external device can access local memory of this LSI via the PCIC. When an external PCI device accesses cacheable areas of this LSI, the PCIC can support cache snoop function to the onchip caches. The PCICSCR1 specifies this function that uses cache snoop address registers 1. Refer to section 13.4.4 (7), Cache Coherency.
Bit: 31
--
30
--
29
--
28
--
27
--
26
--
25
--
24
--
23
--
22
--
21
--
20
--
19
--
18
--
17
--
16
--
Initial value: SH R/W: PCI R/W:
Bit:
0 R
-- 15
0 R
-- 14
0 R
-- 13
0 R
-- 12
0 R
-- 11
0 R
-- 10
0 R
-- 9
0 R
-- 8
0 R
-- 7
0 R
-- 6
0 R
-- 5
0 R
-- 4
0 R
-- 3
0 R
-- 2
0 R
-- 1
0 R
-- 0
--
Initial value: SH R/W:
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
-- 0 R
--
RANGE 0 R/W
--
SNPMD 0 R/W
--
0 R
--
0 R
--
0 R/W
--
0 R/W
--
0 R/W
--
PCI R/W:
Bit 31 to 5
Bit Name
Initial Value All 0
R/W SH: R PCI: --
Description Reserved These bits are always read as 0. The write value should always be 0. Address Range to be Compared Specify the address range of PCICSAR1 to be compared.
000: PCICSAR[n].CADR[31:12] compared (4 Kbytes) 001: PCICSAR[n].CADR[31:16] compared (64 Kbytes) 010: PCICSAR[n].CADR[31:20] compared (1 Mbyte) 011: PCICSAR[n].CADR[31:24] compared (16 Mbytes) 100: PCICSAR[n].CADR[31:25] compared (32 Mbytes) 101: PCICSAR[n].CADR[31:26] compared (64 Mbytes) 110: PCICSAR[n].CADR[31:27] compared (128 Mbytes) 111: PCICSAR[n].CADR[31:28] compared (256 Mbytes)
4 to 2
RANGE
All 0
SH: R/W PCI: --
Valid only when PCICSCR1.SNPMD = 10 or 11.
Rev. 1.00 Oct. 01, 2007 Page 522 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
Bit 1, 0
Bit Name SNPMD
Initial Value All 0
R/W SH: R/W PCI: --
Description Snoop Mode for PCICSAR1 Specify if PCICSAR1 is compared with address requested by an external device. Also, specify how snoop function is executed when PCICSAR1 is compared. 00: PCICSAR1 not compared 01: Reserved (setting prohibited) 10: PCICSAR1 compared. If hit, snoop function is not executed, otherwise executed. 11: PCICSAR1 compared. If hit, snoop function is executed, otherwise not executed.
Rev. 1.00 Oct. 01, 2007 Page 523 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(26) PCI Cache Snoop Address Register 0 (PCICSAR0) PCICSAR0 specifies the address to be compared with the PCI address requested by an external device. Refer to section 13.4.4 (7), Cache Coherency.
Bit: 31 30 29 28 27 26 25 24 CADR Initial value: SH R/W: PCI R/W: Bit: 0 R/W -- 15 0 R/W -- 14 0 R/W -- 13 0 R/W -- 12 0 R/W -- 11 0 R/W -- 10 0 R/W -- 9 0 R/W -- 8 CADR Initial value: SH R/W: PCI R/W: 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 7 0 R/W -- 6 0 R/W -- 5 0 R/W -- 4 0 R/W -- 3 0 R/W -- 2 0 R/W -- 1 0 R/W -- 0 23 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name CADR
Initial Value All 0
R/W SH: R/W PCI: --
Description Address to be compared Specify address to be compared with the PCI address requested by external PCI devices
Rev. 1.00 Oct. 01, 2007 Page 524 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(27) PCI Cache Snoop Address Register 1 (PCICSAR1) PCICSAR1 specifies the address to be compared with the PCI address requested by an external device. Refer to section 13.4.4 (7), Cache Coherency.
Bit: 31 30 29 28 27 26 25 24 CADR Initial value: SH R/W: PCI R/W: Bit: 0 R/W -- 15 0 R/W -- 14 0 R/W -- 13 0 R/W -- 12 0 R/W -- 11 0 R/W -- 10 0 R/W -- 9 0 R/W -- 8 CADR Initial value: SH R/W: PCI R/W: 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 0 R/W -- 7 0 R/W -- 6 0 R/W -- 5 0 R/W -- 4 0 R/W -- 3 0 R/W -- 2 0 R/W -- 1 0 R/W -- 0 23 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name CADR
Initial Value All 0
R/W SH: R/W PCI: --
Description Address to be compared Specify address to be compared with the PCI address requested by external PCI devices
Rev. 1.00 Oct. 01, 2007 Page 525 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(28) PCI PIO Data Register (PCIPDR) When accessed, this register will cause the generation of a configuration cycle on the PCI bus. Refer to section 13.4.5 (2), Configuration Space Access.
Bit: 31 30 29 28 27 26 25 24 PDR Initial value: SH R/W: PCI R/W: Bit: -- R -- 15 -- R -- 14 -- R -- 13 -- R -- 12 -- R -- 11 -- R -- 10 -- R -- 9 -- R -- 8 PDR Initial value: SH R/W: PCI R/W: -- R -- -- R -- -- R -- -- R -- -- R -- -- R -- -- R -- -- R -- -- R -- -- R -- -- R -- -- R -- -- R -- -- R -- -- R -- -- R -- -- R -- 7 -- R -- 6 -- R -- 5 -- R -- 4 -- R -- 3 -- R -- 2 -- R -- 1 -- R -- 0 23 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name PDR
Initial Value
R/W PCI:
Description
Undefined SH: R/W PCI PIO Data Register A read from or write to this register will cause a PCI configuration cycle on the PCI bus.
Rev. 1.00 Oct. 01, 2007 Page 526 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
13.4
13.4.1
Operation
Supported PCI Commands
Table 13.4 Supported Bus Commands
CBE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command Type Interrupt acknowledge cycle Special cycle I/O read I/O write Reserved Reserved Memory read Memory write Reserved Reserved Configuration read Configuration write Memory read multiple Dual address cycle Memory read line Memory write and invalidate PCI Master No Yes*1 Yes Yes Yes Yes Yes*
1
PCI Target Yes*2 Yes*2 Yes Yes Yes*2 Yes*2 Partially yes*3 No Partially yes*3 Partially yes*4
Yes*1 No No No No
[Legend] 0: Low level 1: High level Notes: 1. Only the host bus bridge mode is supported. 2. Single transfer only is performed. 3. Operation is the same as that for the memory read command. 4. Operation is the same as that for the memory write command.
Rev. 1.00 Oct. 01, 2007 Page 527 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
13.4.2
PCIC Initialization
After a power-on reset, the PCIC enable bit (ENBL) of the PCIC enable control register (PCIECR) and the internal register initialization bit (CFINIT) of the PCI control register (PCICR) is cleared. At this point, if the PCIC is operating as the PCI bus host (host bus bridge mode), the bus privileges are permanently granted to the PCIC, and no device arbitration is performed on the PCI bus. When the PCIC is not operating as host (normal mode), retries are returned without accepting access from PCI external devices connected to the PCI bus. In addition, all accesses to the PCIC from the CPU are invalid except the access to the PCIECR if the PCIECR.ENBL is cleared to 0. A write access is invalid and a read access will read 0, none of the registers can be modified, and any access to the PCI bus will not be executed. To initialize the PCIC, first setting the enable bit in the PCIECR to 1. The PCIC's internal configuration registers and local registers must be initialized before setting the CFINIT bit in the PCICR to 1 (while the CFINIT bit is cleared to 0). On completion of initialization, set the CFINIT bit to 1. When operating as host, arbitration is enabled; when operating as non-host, the PCIC can be accessed from the PCI bus. Regardless of whether the PCIC is operating as the host or normal, external PCI devices cannot be accessed from the PCIC while the CFINIT bit is being cleared. Set the CFINIT bit to 1 before accessing an external PCIC device. Be sure to initialize the following registers while the CFINIT bit is being cleared (before setting to 1): PCI command (PCICMD), PCI status (PCISTATUS), PCI sub system vender ID (PCISVID), PCI subsystem ID (PCISID), PCI local space register 0/1 (PCILSR 0/1) and PCI local address register 0/1.
Rev. 1.00 Oct. 01, 2007 Page 528 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
13.4.3
Master Access
This section describes how the PCIC is accessed by software in this LSI and the restrictions on usage, such as buffering and synchronization with other devices, when the PCIC is used in both the host bus bridge and normal modes. (1) Address Space of PCIC
Table 13.5 shows the PCIC address map. Table 13.5 PCIC Address Map
Physical Address Memory Area PCI memory space1 (Area 4) PCI memory space 2 (Only 32-bit address extended mode) PCI memory space 0 Control register PCIC internal register (configuration and local registers) Reserved PCI I/O space Note: * 29-Bit Address Mode H'1000 0000 to H'13FF FFFF -- 32-Bit Address Extended Mode* H'1000 0000 to H'13FF FFFF H'C000 0000 to H'DFFF FFFF H'FD00 0000 to H'FDFF FFFF H'FE00 0000 to H'FE03 FFFF H'FE04 0000 to H'FE07 FFFF H'FE08 0000 to H'FE1F FFFF H'FE20 0000 to H'FE3F FFFF H'FD00 0000 to H'FDFF FFFF H'FE00 0000 to H'FE03 FFFF H'FE04 0000 to H'FE07 FFFF H'FE08 0000 to H'FE1F FFFF H'FE20 0000 to H'FE3F FFFF 2 Mbytes 1.5 Mbytes 256 Kbytes 256 Kbytes 16 Mbytes 512 Mbytes Space Size 64 Mbytes
For details, see section 7.8, Notes on Using 32-Bit Address Extended Mode.
The address space of the PCIC is divided into four main spaces (six spaces, altogether): the control register space (PCIECR), PCI internal control register (PCI configuration and PCI local registers) space, I/O space, and PCI memory (PCI memory space 0, PCI memory space 1, and PCI memory space 2).
Rev. 1.00 Oct. 01, 2007 Page 529 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(2)
Accessing PCI Memory Space
Figure 13.2 shows the method for accessing the PCI bus allocated to the PCI memory space from the SuperHyway bus.
SuperHyway bus address space (4GB) PCI local bus address space (4GB) 16 Mbytes PCI memory space 1 64 Mbytes 64 Mbytes 512 Mbytes
H'0000 0000 H'1000 0000
H'C000 0000
PCI memory space 2 512 Mbytes
H'FD00 0000 H'FE00 0000
H'FE20 0000
PCI memory space 0 16 Mbytes Register 2 Mbytes PCI I/O 2 Mbytes
Figure 13.2 SuperHyway Bus to PCI Local Bus Access To access to the PCI memory address space, use the PCI memory bank register (PCIMBR) and PCI memory bank mask register (PCIMBMR). These registers should have an address space ranging from 16 Mbytes to 512 Mbytes. PCI addresses can be allocated to by software. The PCIC supports burst transfers to memory transfer. Consecutive accesses with the SuperHyway load 32-byte or SuperHyway store 32-byte command result in a burst transfer of 32-byte or more (64-byte, 96-byte, etc.). The PCI memory spaces are allocated from H'FD00 0000 to H'FDFF FFFF for PCI memory space 0 (16 Mbytes), H'1000 0000 to H'13FF FFFF for PCI memory space 1 (Area 4, 64 Mbytes, selection of the PCIC, DDRIF and LBSC spaces), and H'C000 0000 to H'DFFF FFFF for PCI memory space 2 (512 Mbytes, available only in 32-bit address extended mode). Address translation from SuperHyway bus to PCI local bus The lower 15 bits ([17:3]) of a SuperHyway bus address are sent without translation.
Rev. 1.00 Oct. 01, 2007 Page 530 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
For PCI memory space 0 accesses, bits 23 to 18 of a SuperHyway bus address are controlled by PCI memory bank mask register 0 (PCIMBMR0). Note: In the following items and figures, "SH" means the SuperHyway bus of this LSI and "PCI" means the PCI local bus. * PCIMBMR0 [23:18] B'1111 11: PCI address [23:18] = SH address [23:18] * PCIMBMR0 [23:18] B'0111 11: PCI address [23:18] = PCIMBR0 [23], SH address [22:18] * PCIMBMR0 [23:18] B'0000 01: PCI address [23:18] = PCIMBR0 [23:19], SH address [18] * PCIMBMR0 [23:18] B'0000 00: PCI address [23:18] = PCIMBR0 [23:18] The upper eight bits ([31:24]) of a SuperHyway bus address are replaced with bits 31 to 24 in PCI memory bank register 0 (PCIMBR0).
31 24 23 SH address
18 17
0 PCI address
31
24 23
18 17
0
mask 31 24 23 PCIMBMR0 18 17 0 PCIMBR0 31 24 23 PMSBA0 18 17 0
MSBAM0
Figure 13.3 SuperHyway Bus to PCI Local Bus Address Translation (PCI Memory Space 0) For PCI memory space 1 accesses, bits 25 to 18 of a SuperHyway address are controlled by PCI memory bank mask register 1 (PCIMBMR1). * PCIMBMR1 [25:18] B'11 1111 11: PCI address [25:18] = SH address [25:18] * PCIMBMR1 [25:18] B'01 1111 11: PCI address [25:18] = PCIMBR1 [25], SH address [24:18] * PCIMBMR1 [25:18] B'00 0000 01: PCI address [25:18] = PCIMBR1 [25:19], SH address [18] * PCIMBMR1 [25:18] B'00 0000 00: PCI address [25:18] = PCIMBR1 [25:18] The upper six bits ([31:26]) of a SuperHyway bus address are replaced with bits 31 to 26 in PCI memory bank register 1 (PCIMBR1).
Rev. 1.00 Oct. 01, 2007 Page 531 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
31 26 25
SH address
18 17
0
PCI address
31
26 25
18 17
0
mask
31 26 25
PCIMBMR1
18 17
0
PCIMBR1
31
26 25
PMSBA1
18 17
0
MSBAM1
Figure 13.4 SuperHyway Bus to PCI Local Bus Address Translation (PCI Memory Space 1) For PCI memory space 2 accesses, bits 28 to 18 of a SuperHyway address are controlled by the PCI memory bank mask register 2 (PCIMBMR2). * PCIMBMR2 [28:18] B'1 1111 1111 11: PCI address [28:18] = SH address [28:18] * PCIMBMR2 [28:18] B'0 1111 1111 11: PCI address [28:18] = PCIMBR2 [28], SH address [27:18] * PCIMBMR2 [28:18] B'0 0000 0000 01: PCI address [28:18] = PCIMBR2 [28:19], SH address [18] * PCIMBMR2 [28:18] B'0 0000 0000 00: PCI address [28:18] = PCIMBR2[28:18] The upper three bits ([31:29]) of a SuperHyway bus address are replaced with bits 31 to 29 in PCI memory bank register 2 (PCIMBR2).
31 29 28
SH address
18 17
0
PCI address
31
29 28
18 17
0
mask
31 29 28
PCIMBMR2
18 17
0
PCIMBR2
31
29 28
PMSBA2
18 17
0
MSBAM2
Figure 13.5 SuperHyway Bus to PCI Local Bus Address Translation (PCI Memory Space 2)
Rev. 1.00 Oct. 01, 2007 Page 532 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(3)
Accessing PCI I/O Space
Access within the size of 4-byte. Burst I/O transfers are not supported. The PCI I/O address space is allocated from H'FD20 0000 to H'FE3F FFFF (2 Mbytes). Address translation from SuperHyway bus to PCI local bus The lower 15 bits ([17:3]) of a SuperHyway bus address are sent without translation. Bits 20 to 18 of a SuperHyway bus address are controlled by the PCI I/O bank mask register (PCIIOBMR). Note: In the following item and figure, "SH" means the SuperHyway bus of this LSI and "PCI" means the PCI local bus. * * * * PCIIOMR0 [20:18] B'111: PCI address [20:18] = SH address [20:18] PCIIOMR0 [20:18] B'011: PCI address [20:18] = PCIIOBR [20], SH address [19:18] PCIIOMR0 [20:18] B'001: PCI address [20:18] = PCIIOBR [20:19], SH address [18] PCIIOMR0 [20:18] B'000: PCI address [20:18] = PCIIOBR [20:18]
The upper 11 bits ([31:21]) of a SuperHyway bus address are replaced with bits 31 to 21 in the PCI I/O bank register (PCIIOBR).
31 SH address
21 20 18 17
0 PCI address
31
29 28
18 17
0
11111110001
mask 31 PCIIOBMR 21 20 18 17 IOBAM 0 PCIIOBR 31 29 28 PIOSBA 18 17 0
Figure 13.6 SuperHyway Bus to PCI Local Bus Address Translation (PCI I/O)
Rev. 1.00 Oct. 01, 2007 Page 533 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
(4)
Accessing Internal Registers of this LSI
All internal registers, that is, PCIECR, PCI configuration registers, and PCI local registers are accessible from the CPU. 4-byte, 2-byte, and byte transmission are supported. (5) Endian
The PCIC of this LSI supports both the big endian and little endian formats. Since PCI local bus is inherently little endian, the PCIC supports both byte swapping and non-byte swapping. The endian format is specified by the setting of the TBS bit in the PCI control register (PCICR) at a reset. Note: In the following figures, "SH" means the SuperHyway bus of this LSI and "PCI" means the PCI local bus. "MSByte" means the most significant byte and "LSByte" means the least significant byte.
Rev. 1.00 Oct. 01, 2007 Page 534 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
1. Little Endian
MSByte LSByte
SH data
A'
B'
C'
D'
A
B
C
D
Buffer data
A'
B'
C'
D'
A
B
C
D
PCI Address[2] = 1
PCI Address[2] = 0
PCI data
A
31
B
C
D
0
2. Big Endian
MSByte LSByte
SH data
A
B
C
D
A'
B'
C'
D'
Buffer data
A
B
C
D
A'
B'
C'
D'
PCI Address[2] = 0
PCI Address[2] = 1
PCI data
A
31
B
C
D
0
Note: PCI Address [2]: AD[2] (address)
Figure 13.7 Endian Conversion from SuperHyway Bus to PCI Local bus (Non-Byte Swapping: TBS = 0)
Rev. 1.00 Oct. 01, 2007 Page 535 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
1. Little Endian
MSByte LSByte
SH data
A'
B'
C'
D'
A
B
C
D
Buffer data
A'
B'
C'
D'
A
B
C
D
PCI Address[2] = 1
PCI Address[2] = 0 PCI data A
31
B
C
D
0
2. Big Endian SH data
MSByte
LSByte
D
C
B
A
D'
C'
B'
A'
Buffer data
A'
B'
C'
D'
A
B
C
D
PCI Address[2] = 1
PCI Address[2] = 0 PCI data A
31
B
C
D
0
Note: PCI Address [2]: AD[2] (address)
Figure 13.8 Endian Conversion from SuperHyway Bus to PCI Local bus (Byte Swapping: TBS = 1)
Rev. 1.00 Oct. 01, 2007 Page 536 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
13.4.4
Target Access
This section describes how the PCIC of this LSI is accessed by an external PCI local bus master when the PCIC is used in both the host bus bridge and normal modes. (1) Accessing This LSI Address Space
Accesses to the address space of this LSI by an external PCI bus master are described here.
PCI local bus address space (4 Gbytes) H'0000 0000 Memory base 0 SuperHyway bus address space (4 Gbytes) H'0000 0000
Local address space 0 (base 0) Memory base 1 Local address space 1 (base 1)
I/O space (4 Mbytes) H'FFFF FFFF PCI I/O space
H'FE00 0000
H'FE3F FFFF
H'FFFF FFFF
I/O base 1
Figure 13.9 PCI local bus to SuperHyway bus Memory Map
Rev. 1.00 Oct. 01, 2007 Page 537 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
To access the address space of this LSI, use the PCI memory base address register (PCIMBAR0/1), PCI local space register (PCILSR0/1), and PCI local address register (PCILAR0/1). The address spaces are mapped by software. The PCIC includes two memory mapping registers. Setting these two registers enables the use of two spaces. The size of these address spaces are selectable from 1 Mbyte to 512 Mbytes by setting the PCI local space register (PCILSR0/1). Single longword and burst transfers are supported for the memory data transfer to a PCI target. A certain range of the address space on the PCI local bus corresponds to the local address space on the SuperHyway bus. The local address space 0 is controlled by the PCIMBAR0, PCILSR0 and PCILAR0. And the local address space 1 is controlled by the PCIMBAR1, PCILSR1 and PCILAR1. Figure 13.10 shows the method of accessing the local address space. The PCIMBAR0/1 indicates the starting address of the memory space used by the PCI device. The PCILAR0/1 specifies the starting address of the local address space 0/1. The PCILSR0/1 expresses the size of the memory used by the PCI device. Address translation from PCI local bus to SuperHyway bus For the PCIMBAR0/1 and PCILAR0/1, the more significant address bits that are higher than the memory size set in the PCILSR0/1 becomes valid. The more significant address bits of the PCIMBAR0/1 and the same field line bits of the PCI local bus address output from an external PCI device are compared for the purpose of determining whether the access is made to the PCIC. When the addresses correspond, the access to the PCIC is recognized, and a local address is generated from the more significant address bits of the PCILAR0/1 and the less significant bits of the PCI local bus address output from the external PCI device. The PCI command is executed for this local address. If the more significant address bits of the PCI local bus address output from the external PCI device does not correspond with the more significant address bits of the PCIMBAR0/1, the PCIC does not respond to the PCI command. Note: In the following figures, "SH" means the SuperHyway bus of this LSI and "PCI" means the PCI local bus.
Rev. 1.00 Oct. 01, 2007 Page 538 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
31 2928 PCI address
2019
0 SH address
31 2928
2019
0
compare
31 29 28 PCIMBAR0/1
2019
0 PCILAR0/1
31
2928 LAR
2019
0
MBA (upper)
31 2928 PCILSR0/1 0 0 0 001
2019 100
10 0 0/1
Figure 13.10 PCI Local Bus to SuperHyway Bus Address Translation (Local Address Space 0/1) When all the MBARE bits in PCILSR0/1 are 0, the PCI local bus address is sent to the SuperHyway bus without translation. Data prefetching for memory read commands is supported. When a PCI burst read is performed, 8 bytes, or 32 bytes of data block is prefetched. (this depends on the settings of the PFE and PFCS bits in PCICR). (2) Accessing PCIC I/O Space
Allocate a 256-byte area to the I/O address space. Address translation from PCI local bus to SuperHyway bus The lower 8 bits ([7:0]) are sent to the SuperHyway bus without translation. When bits 31 to 8 of a PCI local bus address match bits 31 to 8 in a PCI I/O base address register (PCIIBAR), the upper 24 bits of a PCI local bus address are replaced with H'FE04 01.
Rev. 1.00 Oct. 01, 2007 Page 539 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
31 PCI Address
87
0 SH address
31 H'FE04 01
87
0
compare
31 PCIIBAR IOB (upper)
87
0
Figure 13.11 PCI Local Bus to SuperHyway Bus Address Translation (PCIC I/O Space) (3) Accessing PCIC Registers
Configuration Registers: Access the configuration registers using an offset from the PCI configuration register space base address with the configuration read or write command. Only a single access which size should be under longword is performed. If a burst transfer is attempted, it is terminated to end the transaction. Local Registers: Access the local registers using an offset from a PCI local register space base address with the I/O read or I/O write command. Only a single longword access is performed. If a burst transfer is attempted, it is terminated to end the transaction. Control Register (PCIECR): Do not read or write access to the PCIECR from the PCI local bus. (4) Access to this LSI Address Space
Memory Space: Refer to Section 13.4.4 (1), Accessing This LSI Address Space. Area 0 to area 2 and area 4 to area 6 and DDR-SDRAM space on this LSI address space can be accessed. On-chip IO Space: Do not read or write access to the on-chip IO space using memory read or memory write command via PCI local bus. The operation of this read/write is not guaranteed.
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Section 13 PCI Controller (PCIC)
(5)
Exclusive Access
The lock access on the PCI bus is supported. When the PCI local bus is locked, the PCIC is accessible from the device that activates the LOCK signal. SuperHyway bus resource lock does not occur. (Another on-chip module can access the PCIC during a lock transfer.) (6) Endian
This LSI supports both the big and little endian formats. Since the PCI local bus is inherently little endian, the PCIC supports both byte swapping and non-byte swapping. The endian format is specified by the setting of the TBS bit in the PCI control register (PCICR). Note: In the following figures, "MSByte" means the most significant byte and "LSByte" means the least significant byte.
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Section 13 PCI Controller (PCIC)
1. Little Endian 31 PCI data
A
B C
D
PCI Address[2] = 0
0
PCI Address[2] = 1
Buffer data
A'
B'
C'
D'
A
B
C
D
MSByte SH data
A'
B'
C'
D'
A
B C
D
LSByte
2. Big Endian
31 PCI data
A
B C
D
0
PCI Address[2] = 1
PCI Address[2] = 0
Buffer data
A
B
C
D
A'
B'
C'
D'
MSByte
SH data
A
B
C
D
A'
B' C'
D'
LSByte
Note: PCI Address [2]: AD[2] (address)
Figure 13.12 Endian Conversion from PCI Local Bus to SuperHyway bus (Non-Byte Swapping: TBS = 0)
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Section 13 PCI Controller (PCIC)
1. Little Endian
31
PCI data
0
B C
D
PCI Address[2] = 0
A
PCI Address[2] = 1
Buffer data
A'
B'
C'
D'
D
B
C
D
MSByte
SH data
LSByte
A'
B'
C'
D'
A
B C
D
2. Big Endian
31
PCI data
0
B C
D
PCI Address[2] = 1
A
PCI Address[2] = 0
Buffer data
D
C
B
A
D'
C'
B'
A'
MSByte
SH data
LSByte
D
C
B
A
D'
C' B'
A'
Note: PCI Address [2]: AD[2] (address)
Figure 13.13 Endian Conversion from PCI Local Bus to SuperHyway bus (Non-Byte Swapping: TBS = 1)
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Section 13 PCI Controller (PCIC)
(7)
Cache Coherency
The PCIC supports cache snoop function. When the PCIC functions as a target device, cache coherency is guaranteed for accesses from a master device connected to a PCI bus in both the host bus bridge mode and normal mode. When accessing this LSI cacheable area, set the cache snoop registers: the PCI cache snoop control registers (PCICSCR0 and PCICSCR1) and PCI cache snoop address register (PCICSAR0 and PCICSAR1). Usage Notes * Up to 2 conditions can be set as snoop address. Address comparison is logical OR of setting 2 conditions. * When using this function, execute memory read or write after flush/purge request issued to the CPU cache in the access of cache hit. It reduces PCI bus transfer speed and CPU performance. * When using this function, do not use the prefetch function. (Do not set PFE bit in the PCICR to 1.) * Do not use this function when the CPU is sleep state. If cache hit occurs in sleep state, it becomes an error access on the SuperHyway bus, and memory read or memory write does not execute. Specify the SNPMD bit in the PCICSCR to 00 before the CPU enters sleep mode. To keep the coherency before and after the CPU sleep, cache purge should be executed before sleep instruction executed. * Do not use ether of the following functions and the cache shoop function simultaneously. Debug function using an emulator (Disable this function when using an emulator). L memory or memory mapped cache access from the DMAC.
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Section 13 PCI Controller (PCIC)
Set
PCI address
Cache snoop control register
SuperHyway address
Cache snoop address register
compare
Hit
No hit
issue the flush/purge
Issue the read/write
issue the read/write
Figure 13.14 Cache Flush/Purge Execution Flow for PCI local Bus to SuperHyway Bus
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Section 13 PCI Controller (PCIC)
13.4.5 (1)
Host Bus Bridge Mode
PCI Host bus bridge Mode Operation
The PCIC supports a subset of the PCI Local Bus Specification Revision 2.2 and can be connected to a device with a PCI bus interface. While the PCIC is set in host bus bridge mode, or while set in normal mode, operation differs according to whether or not bus parking is performed, and whether or not the PCI bus arbiter function is enabled or not. In host bus bridge mode, the AD, CBE, PAR signal lines are driven by the PCIC when transfers are not being performed on the PCI bus. When the PCIC subsequently starts transfers as master, these signal lines continue to be driven until the end of the address phase. The arbiter in the PCIC and the REQ and GNT between PCIC are connected internally. Here, pins REQ0/REQOUT, REQ1, REQ2, and REQ3 function as the REQ inputs from the external masters 0 to 3. Similarly, GNT0/GNTIN, GNT1, GNT2, and GNT3 function as the GNT outputs to external masters 0 to 3. Including the PCIC, arbitration of up to five masters is possible. (2) Configuration Space Access
The PCIC supports configuration mechanism #1. The PCI PIO address register (PCIPAR) and PCI PIO data register (PCIPDR) correspond to the configuration address register and configuration data register, respectively. When PCIPDR is read from or written to after PCIPAR has been set, a configuration cycle is issued on a PCI bus. For a type 0 transfer, bits 10 to 2 of the configuration address register are sent without translation and bits 31 to 11 are translated so that these bits can be used as the IDSEL signal. Bit 16 of the AD signal is driven to 1 and the other bits are made 0 by setting the device number to 0. Bit 17 of the AD signal is driven to 1 and the other bits are made 0 by setting the device number to 1. Similarly, setting the device number to 2 drives bit 18 of the AD signal to 1 and setting the device number to 3 drives bit 19 of the AD signal to 0. Bit 31 of the AD signal is driven to 1 and the other bits are made 0 by setting the device number to 16. For details, refer to "PCI Local Bus Specification Revision 2.2, section 3.2.2.3 Configuration Space Decoding".
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Section 13 PCI Controller (PCIC)
31 30 Configuration address register (PCIPAR)
24 23 BN
16 15 DN
11 10 FN
87 CRA
21 00
0
Reserved CCIE
PCI local bus address (AD31 to AD0)
Only one '1' 31
00000 16 15 11 10 87
00 21 0
Figure 13.15 Address Generation for Type 0 Configuration Access In configuration accesses, a PCI master abort (no device connected) will not cause an interrupt. Configuration writes will end normally. Configuration reads will return a value of 0. (3) Special Cycle Generation
When the PCIC operates as the host device, a special cycle is generated by setting H'8000 FF00 in the PCIPAR and writing to the PCIPDR. (4) Arbitration
In host bus bridge mode, the PCI bus arbiter in the PCIC is activated. The PCIC supports four external masters (i.e., four REQ and GNT pairs). If use of the bus is simultaneously requested by more than one device, the bus is granted to the device with the highest priority. The PCI bus arbiter supports two modes to determine the priority of devices: fixed priority and pseudo-round-robin. The mode is selected by the BMAM bit in PCICR. Fixed Priority: When the BMAM bit in PCICR is cleared to 0, the priorities of devices are fixed the following default values. PCIC > device 0 > device 1 > device 2 > device 3 The PCIC always gains use of the bus over other devices. Pseudo-Round-Robin: When the BMAM bit in PCICR is set to 1, the most recently granted device is assigned the lowest priority. The initial priority is the same as the fixed priority mode.
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Section 13 PCI Controller (PCIC)
After device 1 has claimed and granted the bus, and transferred data, the priority is as follows: PCIC > device 0 > device 2 > device 3 > device 1 Then, after the PCIC has claimed and granted the bus, and transferred data, the priority is changed to: Device 0 > device 2 > device 3 > device 1 > PCIC After device 3 has claimed and granted the bus, and transferred data, the priority is changed to: Device 0 > device 2 > device 1 > PCIC > device 3 In host bus bridge mode, bus parking is always controlled by the PCIC. (5) Interrupts
* 10 interrupts are available (these signals are connected to the INTC of this LSI) * Interrupts are enabled/disabled and their priority levels are specified by the INTC of this LSI * When the PCIC operates normal mode, INTA output is available to the host device on the PCI bus. The INTA pin is specified assert or negate by the IOCS bit in the PCICR. Table 13.6 Interrupt Priority
Signal PCISERR PCIINTA PCIINTB PCIINTC PCIINTD PCIEER PCIPWD3 PCIPWD2 PCIPWD1 PCIPWD0 Interrupt Source SERR assertion detected in host bus bridge mode PCI interrupt A (INTA) detected in host bus bridge mode PCI interrupt B (INTB) detected in host bus bridge mode PCI interrupt C (INTC) detected in host bus bridge mode PCI interrupt D (INTD) detected in host bus bridge mode Error on PCI bus occurs and reflected in PCIIR and PCIAINT. The interrupt can be masked. Power state transition to D3 caused by PCIPINT. The interrupt can be masked. Power state transition to D2 caused by PCIPINT. The interrupt can be masked. Power state transition to D1 caused by PCIPINT. The interrupt can be masked. Power state transition to D0 caused by PCIPINT. The interrupt can be masked. Low Priority High
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Section 13 PCI Controller (PCIC)
The PCIC can store the error information on the PCI bus. If an error occurs, the error address is stored in the PCI error address information register (PCIAIR), the types of transfer and command information are stored in the PCI error command information register. And then if the PCIC operates host bus bridge mode, the bus master information is stored in the PCI error bus master information register. Error information is stored only one information. This causes only to store the first occurred error information, and not to store after second error information. The error information is initialized by a power-on reset. 13.4.6 Normal mode
When operating in normal mode, the PCI bus arbitration function in the PCIC is disabled and PCI bus arbitration is performed according to the specifications of the externally connected PCI bus arbiter. In normal mode, the master performs bus parking is decided by the grant signal that asserted from the external bus arbiter. If the master that performing bus parking is different from the next transaction master, the bus will be high-impedance state for minimum one clock cycle before the address phase. In normal mode, the GNT0/GNTIN pin is used for the grant input signal to the PCIC, and the REQ0/REQOUT pin is used for the request output signal from the PCIC. 13.4.7 Power Management
The PCIC supports PCI power management revision 1.1. Supported features are shown below. * Support for the PCI power management control configuration register. * Support for the power-down/restore request interrupts from hosts on the PCI bus. There are seven configuration registers for PCI power management control. PCI capabilities pointer register shows the address offset of the configuration registers for power management. In the PCIC, this offset is fixed at CP = H'40. PCI capability ID (PCICID), next item pointer (PCINIP), power management capability (PCIPMC), power management control/status (PCIPMCSR), PMCSR bridge support extension (PCIPMCSRBSE) and power consumption/dissipation (PCIPCDD) are power management registers. They support four states: power state D0 (normal) power state D1 (bus idle) power state D2 (clock stop) and power state D3 (power down mode). Figure 13.16 shows the PCI local bus power down state transition.
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Section 13 PCI Controller (PCIC)
D0 (normal)
D2 (clock stop)
D1 (bus idle)
D3 (power down)
Figure 13.16 PCI Local Bus Power Down State Transition The PCIC detects when the power state (PS) bit of the PCI power management control/status register changes (when it is written to from an external PCI device), and issues a power management interrupt. To control the power management interrupts, there are the PCI power management interrupt register (PCIPINT) and PCI power management interrupt mask register (PCIPINTM). Of the power management interrupts, the power state D0 interrupt (PCIPWD0) detects a transition from the power state D1/D2/D3 to D0, while power state D1 interrupt (PCIPWD1) detects a transition from the power state D0 to D1, while power state D2 interrupt (PCIPWD2) detects a transition from the power state D0/D1 to D2, while power state D3 interrupt (PCIPWD3) detects a transition from the power state D0/D1/D2 to D3. Interrupt masks can be set for each interrupt. No power state D0 interrupt is generated at a power-on reset. The following cautions should be noted when the PCIC is operating in normal mode and a power down interrupt is received from the host: In PCI power management, the PCI local bus clock stops within a minimum of 16 clocks after the host device has instructed a transition to power state D3. After detecting a power state D3 interrupt, do not, therefore, attempt to read or write to local registers and configuration registers that can be accessed from the SuperHyway bus and PCI local bus access (I/O and memory spaces). Because these accesses operate using the PCI local bus clock, the cycle for these accesses will not be completed if the clock stops and may be hung-up on the SuperHyway bus. 13.4.8 PCI Local Bus Basic Interface
The PCIC of this LSI conforms to the PCI local bus specification revision 2.2 stipulations and can be connected to a device with a PCI local bus interface. The following figures show the timing for each operation mode.
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Section 13 PCI Controller (PCIC)
(1)
Master Read/Write Cycle Timing
Figures13.17 is an example of a single-write cycle in host bus bridge mode. Figure 13.18 is an example of a single read cycle in host bus bridge mode. Figure 13.19 is an example of a burst write cycle in normal mode. And Figure 13.20 is an example of a burst read cycle in normal mode. Note that the response speed of DEVSEL and TRDY differs according to the connected target device. In host bus bridge mode, master accesses always use single read/write cycles. The issuing of configuration transfers is only possible in host bus bridge mode.
PCICLK AD[31:0] PAR CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQ GNT Com Addr D0 AP BE0 DP0
[Legend] Addr: PCI space address AP: Address parity Com: Command
Dn: nth data DPn: nth data parity BEn: nth data byte enable
Figure 13.17 Master Write Cycle in Host Bus Bridge Mode (Single)
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Section 13 PCI Controller (PCIC)
PCICLK AD[31:0]
PAR
CBE[3:0] (C/BE[3:0]) Com
Addr
AP
BE0
D0
DP0
PCIFRAME
IRDY
DEVSEL
TRDY
LOCK IDSEL
REQ GNT
[Legend] Addr: PCI space address AP: Address parity Com: Command
Dn: nth data DPn: nth data parity BEn: nth data byte enable
Figure 13.18 Master Read Cycle in Host Bus Bridge Mode (Single)
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Section 13 PCI Controller (PCIC)
PCICLK AD[31:0]
PAR
CBE[3:0] (C/BE[3:0])
Addr
D0
D1
DP0
Dn
DPn-1 DPn
AP Com
BE0
BE1
BEn
PCIFRAME
IRDY
DEVSEL
TRDY
LOCK IDSEL
REQ GNT
[Legend] Addr: PCI space address AP: Address parity Com: Command
Dn: nth data DPn: nth data parity BEn: nth data byte enable
Figure 13.19 Master Write Cycle in Normal Mode (Burst)
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Section 13 PCI Controller (PCIC)
PCICLK AD[31:0]
PAR
CBE[3:0] (C/BE[3:0])
Addr
D0
D1
DP0
Dn
DPn-1 DPn
AP Com
BE0
BE1
BEn
PCIFRAME
IRDY
DEVSEL
TRDY
LOCK IDSEL
REQ GNT
[Legend] Addr: PCI space address AP: Address parity Com: Command
Dn: nth data DPn: nth data parity BEn: nth data byte enable
Figure 13.20 Master Read Cycle in Normal Mode (Burst)
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Section 13 PCI Controller (PCIC)
(2)
Target Read/Write Cycle Timing
The PCIC responds to target memory burst read accesses from an external master by retries until 8 longword (32-bit) data are prepared in the PCIC's internal FIFO. That is, it always responds to the first target burst read with a retry. For a single read access, the PCIC reaponds as soon as the data is prepared. Also, when a target memory write access is made, the content of the data is guaranteed until the write data is completely written to the local memory if reading the target write data immediately after write access. Only single transfers are supported in the case of target accesses of the configuration space and I/O space. If there is a burst access request, the external master is disconnected on completion of the first transfer. Note that the DEVSEL response speed is fixed at 2 clocks (Medium) in the case of target access to the PCIC. Figure 13.21 shows an example target single read cycle in normal mode. Figure 13.22 shows an example target single write cycle in normal mode. Figure 13.23 is an example of a target burst read cycle in host bus bridge mode. And figure 13.24 is an example of a target burst write cycle in host bus bridge mode.
Rev. 1.00 Oct. 01, 2007 Page 555 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
PCICLK AD[31:0]
PAR
CBE[3:0] (C/BE[3:0])
Com
Addr
D0
AP
BE0
DP0
PCIFRAME
IRDY
DEVSEL
TRDY STOP
Disconnect
LOCK IDSEL
Locked
At configuration access
REQOUT GNTIN
[Legend] Addr: PCI space address AP: Address parity Com: Command
Dn: nth data DPn: nth data parity BEn: nth data byte enable
Figure 13.21 Target Read Cycle in Normal Mode (Single)
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Section 13 PCI Controller (PCIC)
PCICLK AD[31:0] PAR CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY STOP
Disconnect Com Addr
D0 AP BE0 DP0
LOCK IDSEL
Locked
At configuration access
REQOUT GNTIN [Legend] Addr: PCI space address AP: Address parity Com: Command
Dn: nth data DPn: nth data parity BEn: nth data byte enable
Figure 13.22 Target Write Cycle in Normal Mode (Single)
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Section 13 PCI Controller (PCIC)
PCICLK AD[31:0]
PAR
CBE[3:0] (C/BE[3:0])
Com
Addr
D0
D1
Dn
DPn-1 DPn
AP
BE0
DP0
BE1
BEn
PCIFRAME
IRDY
DEVSEL
TRDY STOP
Disconnect
LOCK IDSEL
REQ GNT
[Legend] Addr: PCI space address AP: Address parity Com: Command
Locked
Dn: nth data DPn: nth data parity BEn: nth data byte enable
Figure 13.23 Target Memory Read Cycle in Host Bus Bridge Mode (Burst)
Rev. 1.00 Oct. 01, 2007 Page 558 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
PCICLK AD[31:0] PAR CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY STOP
Disconnect Com Addr
D0 AP BE0 DP0
D1
Dn
DPn-1 DPn
BE1
BEn
LOCK IDSEL REQ GNT
Locked
[Legend] Addr: PCI space address AP: Address parity Com: Command
Dn: nth data DPn: nth data parity BEn: nth data byte enable
Figure 13.24 Target Memory Write Cycle in Host Bus Bridge Mode (Burst)
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Section 13 PCI Controller (PCIC)
(3)
Address/Data Stepping Timing
By writing 1 to the SC bit in PCICMD, a wait (stepping) of one clock can be inserted when the PCIC is driving the AD bus. As a result, the PCIC drives the AD bus over 2 clocks. This function can be used when there is a heavy load on the PCI bus and the AD bus does not achieve the stipulated logic level in one clock. When the PCIC operates as the host bus bridge mode, it is recommended to use this function for the issuance of configuration transfers. Figure 13.25 is an example of burst memory write cycle with stepping. Figure 13.26 is an example of target burst read cycle with stepping.
PCICLK AD[31:0]
PAR
CBE[3:0] (C/BE[3:0])
Addr
AP
D0
DP0
D1
Dn
DPn-1 DPn
Com
BE0
BE1
BEn
PCIFRAME
IRDY
DEVSEL
TRDY
[Legend] Addr: PCI space address AP: Address parity Com: Command
Dn: nth data DPn: nth data parity BEn: nth data byte enable
Figure 13.25 Master Write Cycle in Host Bus Bridge Mode (Burst, with stepping)
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Section 13 PCI Controller (PCIC)
PCICLK AD[31:0] PAR CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY [Legend] Addr: PCI space address AP: Address parity Com: Command Com Addr AP BE0 D0 DP0 BE1 D1 Dn DPn-1 BEn DPn
Dn: nth data DPn: nth data parity BEn: nth data byte enable
Figure 13.26 Target Memory Read Cycle in Host Bus Bridge Mode (Burst, with stepping)
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Section 13 PCI Controller (PCIC)
13.5
13.5.1
Usage Notes
Notes on PCIC Target Reading
When the PCIC is used in target mode and all the three conditions below are satisfied, data may be lost during a PCIC target read. 1. PFCS bit in PCICR = 1 (32-byte pre-fetch enabled) 2. FTO bit in PCICR = 1 (TRDY control enabled) 3. PFE bit in PCICR = 1 (pre-fetch enabled) For target reading in target mode, at least one of the above three conditions must be cancelled. 13.5.2 Notes on Host Mode
When the PCIC is used while all the five conditions below are satisfied, REQn (n = 3 to 1) with the lowest priority is masked, thus disabling correct transfers via the PCI bus, which leads to unstable operation of the PCI bus system. 1. Host mode (MD6 = high) 2. PCI bus master arbitration mode is set to fixed mode (BMAM bit in PCICR = 0) 3. In addition to this LSI (with the PCIC in host mode), two or more external PCI devices that can be a bus master are connected to the PCI bus. 4. Among the above external devices, there is at least one device (REQm) that does not execute REQ negation and FRAME assertion simultaneously when a single transaction is requested (single or burst transfer). 5. There is an external device (REQn; n > m) that can be a bus master with a priority lower than the priority of the external device (REQm) satisfying condition 4 above.
PCICLK REQm GNTm FRAME
Figure 13.27 Timing Example of Device (REQm) Not Executing REQ Negation and FRAME Assertion Simultaneously
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Section 13 PCI Controller (PCIC)
To prevent a device that does not execute REQ negation and FRAME assertion simultaneously (figure 13.27) from being a bus master, preventive measure 1 or 2 below should be taken. 1. Use pseudo-round-robin mode. Pseudo-round-robin mode should be set (BMAM bit in PCICR = 1) as the PCI bus arbitration scheme. 2. Assign the lowest priority level to the relevant device. When there is only one device that does not execute REQ negation and FRAME assertion simultaneously, the device should be connected to the REQn and GNTn with the lowest priority. However, if none of the external devices connected to the PCI has such negation/assertion timing or if none of the external devices with such negation/assertion timing can be a bus master, the above preventive measures are not required.
Rev. 1.00 Oct. 01, 2007 Page 563 of 1956 REJ09B0256-0100
Section 13 PCI Controller (PCIC)
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Section 14 Direct Memory Access Controller (DMAC)
Section 14 Direct Memory Access Controller (DMAC)
This LSI includes the direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules.
14.1
Features
* Six channels (four channels can receive an external request: channel 0 to 3) * 4-Gbyte physical address space * Data transfer unit is selectable: Byte, word (2 bytes), longword (4 bytes), 16 bytes, and 32 bytes * Maximum transfer count: 16,777,216 transfers * Address mode: Dual address mode * Transfer requests: External request (channel 0 to 3), on-chip peripheral module request (channel 0 to 5), or auto request can be selected. The following modules can issue an on-chip peripheral module request. CMT, SCIF0, SCIF1, SCIF2, HAC, USBF, SSI0 to SSI3, MMCIF, SIM, SIOF0 to SIOF2, STIF0 and STIF1 * Selectable bus modes: Cycle steal mode (normal mode and intermittent mode) or burst mode can be selected. * Selectable channel priority levels: The channel priority levels are selectable between fixed mode and round-robin mode. * Interrupt request: An interrupt request can be generated to the CPU after half of the transfers ended, all transfers ended, or an address error occurred. * External request detection: There are following four types of DREQn input detection. (n = 0 to 3) Low level detection (Initial value) High level detection Rising edge detection Falling edge detection
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Section 14 Direct Memory Access Controller (DMAC)
* Active levels for both the DMA transfer request acceptance signal (DACKn) and DMA transfer end signal (TENDn) can be set. (n = 0 to 3) Figure 14.1 shows the block diagram of the DMAC.
DMAC channels 0 to 5
On-chip memory On-chip peripheral module Peripheral bus controller Iteration control Register control Start-up control SARm DARm TCRm CHCRm DMAOR0 DMARS0-2 Request priority control SARBn DARBn TCRBn Bus interface DREQ0 to DREQ3 DACK0 to DACK3 TEND0 to TEND3 Local bus state controller
DMA transfer request signal DMA transfer end signal DMINT0 to DMINT5 Interrupt controller DMAE
External ROM External RAM External I/O
DDR-SDRAM interface
PCI controller
[Legend] CHCRm: DARBn: DARm: DMAE: DMAOR : DMA channel control register DMA destination address register B DMA destination address register DMA Address error interrupt request DMA operation register DMARS0 to DMARS2: DMINTm: SARBn: SARm: TCRBn: TCRm: DMA extended resource selectors 0 to 2 DMA transfer end/half-end interrupt request from channel m* DMA source address register B DMA source address register DMA transfer count register B DMA transfer count register
m: n: Note:
0,1,2,3,4,5 for channels 0 to 5 0,1,2,3 for channels 0 to 5 * The half-end interrupt request is available in channels 0 to 3.
Figure 14.1 Block Diagram of DMAC
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SuperHyway bus
Section 14 Direct Memory Access Controller (DMAC)
14.2
Input/Output Pins
The external pins for the DMAC are described below. Table 14.1 lists the configuration of the pins that are connected to external device. The DMAC has pins for four channels (channel 0 to 3) for external bus use. The input/output pins of channel 1 are divided in two groups: normal I/O group and mirror I/O group. The input/output operations of pins in two groups are always the same. The pin select register of the GPIO is used to select the Channel 1 pins. Table 14.1 Pin Configuration
Channel 0 Pin Name Function DREQ0*
1
I/O Input
Description DMA transfer request input from external device to channel 0
DMA transfer request DMA transfer request acknowledge DMA transfer end notification DMA transfer request DMA transfer request acknowledge DMA transfer end notification
DACK0*2
Output Strobe output from channel 0 to external device which has output, regarding DMA transfer request Output DMA transfer end output from channel 0 to external device Input DMA transfer request input from external device to channel 1
TEND0* 1
2
Normal DREQ1*1 I/O Pins DACK1*2
Output Strobe output from channel 1 to external device which has output, regarding DMA transfer request Output DMA transfer end output from channel 1 to external device Input DMA transfer request input from external device to channel 1
TEND1* Miller I/O Pins
2
DREQ1M*1 DMA transfer request DACK1M*2 DMA transfer request acknowledge TEND1M*2 DMA transfer end notification
Output Strobe output from channel 1 to external device which has output, regarding DMA transfer request Output DMA transfer end output from channel 1 to external device
Rev. 1.00 Oct. 01, 2007 Page 567 of 1956 REJ09B0256-0100
Section 14 Direct Memory Access Controller (DMAC)
Channel 2
Pin Name Function DREQ2*
1
I/O Input Output
Description DMA transfer request input from external device to channel 2 Strobe output from channel 2 to external device which has output, regarding DMA transfer request DMA transfer end output from channel 2 to external device DMA transfer request input from external device to channel 3 Strobe output from channel 3 to external device which has output, regarding DMA transfer request DMA transfer end output from channel 3 to external device
DMA transfer request DMA transfer request acknowledge DMA transfer end notification DMA transfer request DMA transfer request acknowledge DMA transfer end notification
DACK2*2
TEND2* 3
2
Output Input Output
DREQ3*1 DACK3*2
TEND3*
2
Output
Notes: 1. The initial value is detected at low level. 2. The initial value is low active.
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Section 14 Direct Memory Access Controller (DMAC)
14.3
Register Descriptions
Table 14.2 shows the configuration of registers of the DMAC. Table 14.3 shows the state of registers in each processing mode. Table 14.2 Register Configuration of DMAC
Channel Name 0 DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0 1 DMA source address register 1 DMA destination address register 1 DMA transfer count register 1 DMA channel control register 1 2 DMA source address register 2 DMA destination address register 2 DMA transfer count register 2 DMA channel control register 2 3 DMA source address register 3 DMA destination address register 3 DMA transfer count register 3 DMA channel control register 3 0 to 5 4 DMA operation register DMA source address register 4 DMA destination address register 4 DMA transfer count register 4 DMA channel control register 4 5 DMA source address register 5 DMA destination address register 5 DMA transfer count register 5 DMA channel control register 5 Abbrev. SAR0 DAR0 TCR0 CHCR0 SAR1 DAR1 TCR1 CHCR1 SAR2 DAR2 TCR2 CHCR2 SAR3 DAR3 TCR3 CHCR3 DMAOR SAR4 DAR4 TCR4 CHCR4 SAR5 DAR5 TCR5 CHCR5 R/W R/W R/W R/W P4 Address H'FF60 8020 H'FF60 8024 H'FF60 8028 Area 7 Address H'1F60 8020 H'1F60 8024 H'1F60 8028 H'1F60 802C H'1F60 8030 H'1F60 8034 H'1F60 8038 H'1F60 803C H'1F60 8040 H'1F60 8044 H'1F60 8048 H'1F60 804C H'1F60 8050 H'1F60 8054 H'1F60 8058 H'1F60 805C H'1F60 8060 H'1F60 8070 H'1F60 8074 H'1F60 8078 H'1F60 807C H'1F60 8080 H'1F60 8084 H'1F60 8088 H'1F60 808C Access Size*3 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 32 32 32 32 32 32 32 32
R/W*1 H'FF60 802C R/W R/W R/W R/W* R/W R/W R/W
1
H'FF60 8030 H'FF60 8034 H'FF60 8038 H'FF60 803C H'FF60 8040 H'FF60 8044 H'FF60 8048
R/W*1 H'FF60 804C R/W R/W R/W R/W* R/W* R/W R/W R/W R/W* R/W R/W R/W R/W*
1 1 1
H'FF60 8050 H'FF60 8054 H'FF60 8058 H'FF60 805C H'FF60 8060 H'FF60 8070 H'FF60 8074 H'FF60 8078 H'FF60 807C H'FF60 8080 H'FF60 8084 H'FF60 8088 H'FF60 808C
2
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Section 14 Direct Memory Access Controller (DMAC)
Access Size*3 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16
Channel Name 0 DMA source address register B0
Abbrev. SARB0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
P4 Address H'FF60 8120 H'FF60 8124 H'FF60 8128 H'FF60 8130 H'FF60 8134 H'FF60 8138 H'FF60 8140 H'FF60 8144 H'FF60 8148 H'FF60 8150 H'FF60 8154 H'FF60 8158 H'FF60 9000 H'FF60 9004 H'FF60 9008
Area 7 Address H'1F60 8120 H'1F60 8124 H'1F60 8128 H'1F60 8130 H'1F60 8134 H'1F60 8138 H'1F60 8140 H'1F60 8144 H'1F60 8148 H'1F60 8150 H'1F60 8154 H'1F60 8158 H'1F60 9000 H'1F60 9004 H'1F60 9008
DMA destination address register B0 DARB0 DMA transfer count register B0 1 DMA source address register B1 TCRB0 SARB1
DMA destination address register B1 DARB1 DMA transfer count register B1 2 DMA source address register B2 TCRB1 SARB2
DMA destination address register B2 DARB2 DMA transfer count register B2 3 DMA source address register B3 TCRB2 SARB3
DMA destination address register B3 DARB3 DMA transfer count register B3 0, 1 2, 3 4, 5 DMA extended resource selector 0 DMA extended resource selector 1 DMA extended resource selector 2 TCRB3 DMARS0 DMARS1 DMARS2
Note:
1. Writing 0 after read 1 of HE or TE bit of CHCR is possible to clear the flag. 2. Writing 0 after read 1 of AE or NMIF bit of DMAOR is possible to clear the flag. 3. Accessing with other access sizes is prohibited.
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Section 14 Direct Memory Access Controller (DMAC)
Table 14.3 State of Registers in Each Operating Mode
Channel 0 Abbreviation SAR0 DAR0 TCR0 CHCR0 1 SAR1 DAR1 TCR1 CHCR1 2 SAR2 DAR2 TCR2 CHCR2 3 SAR3 DAR3 TCR3 CHCR3 0 to 5 4 DMAOR SAR4 DAR4 TCR4 CHCR4 5 SAR5 DAR5 TCR5 CHCR5 0 SARB0 DARB0 TCRB0 Power-on Reset Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined H'4000 0000 H'0000 Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined Manual Reset Sleep Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined H'4000 0000 H'0000 Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Stand by Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
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Section 14 Direct Memory Access Controller (DMAC)
Channel 1
Abbreviation SARB1 DARB1 TCRB1
Power-on Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'0000 H'0000 H'0000
Manual Reset Sleep Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'0000 H'0000 H'0000 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Stand by Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
2
SARB2 DARB2 TCRB2
3
SARB3 DARB3 TCRB3
0, 1 2, 3 4, 5
DMARS0 DMARS1 DMARS2
14.3.1
DMA Source Address Registers (SAR0 to SAR5)
SAR is 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. To transfer data in word or in longword units, specify the address with word or longword address boundary. When transferring data in 16-byte or in 32-byte units, a 16-byte or 32-byte boundary must be set for the source address value. The initial value is undefined.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 SAR -- R/W 15 -- R/W -- R/W 14 -- R/W -- R/W 13 -- R/W -- R/W 12 -- R/W -- R/W 11 -- R/W -- R/W 10 -- R/W -- R/W 9 -- R/W -- R/W 8 SAR -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 23 22 21 20 19 18 17 16
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Section 14 Direct Memory Access Controller (DMAC)
14.3.2
DMA Source Address Registers (SARB0 to SARB3)
SARB is 32-bit readable/writable registers that specify the source address of a DMA transfer that is set in SAR again in repeat/reload mode. Data to be written from the CPU to SAR is also written to SARB. To set SARB address that differs from SAR address, write data to SARB after SAR. To transfer data in word or in longword units, specify the address with word or longword address boundary. When transferring data in 16-byte or in 32-byte units, a 16-byte or 32-byte boundary must be set for the source address value. The initial value is undefined.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- R/W 15 -- R/W 30 -- R/W 14 -- R/W 29 -- R/W 13 -- R/W 28 -- R/W 12 -- R/W 27 -- R/W 11 -- R/W 26 -- R/W 10 -- R/W 25 -- R/W 9 -- R/W 24 -- R/W 8 -- R/W 23 -- R/W 7 -- R/W 22 -- R/W 6 -- R/W 21 -- R/W 5 -- R/W 20 -- R/W 4 -- R/W 19 -- R/W 3 -- R/W 18 -- R/W 2 -- R/W 17 -- R/W 1 -- R/W 16 -- R/W 0 -- R/W
SARB
SARB
14.3.3
DMA Destination Address Registers (DAR0 to DAR5)
DAR is 32-bit readable/writable registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the next destination address. To transfer data in word or in longword units, specify the address with word or longword address boundary. When transferring data in 16-byte or in 32-byte units, a 16-byte or 32-byte boundary must be set for the destination address value. The initial value is undefined.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- R/W 15 -- R/W 30 -- R/W 14 -- R/W 29 -- R/W 13 -- R/W 28 -- R/W 12 -- R/W 27 -- R/W 11 -- R/W 26 -- R/W 10 -- R/W 25 -- R/W 9 -- R/W 24 DAR -- R/W 8 DAR -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 23 22 21 20 19 18 17 16
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Section 14 Direct Memory Access Controller (DMAC)
14.3.4
DMA Destination Address Registers (DARB0 to DARB3)
DARB is 32-bit readable/writable registers that specify the destination address of a DMA transfer that is set in DAR again in repeat/reload mode. Data to be written from the CPU to DAR is also written to DARB. To set DARB address that differs from DAR address, write data to DARB after DAR. To transfer data in word or in longword units, specify the address with word or longword address boundary. When transferring data in 16-byte or in 32-byte units, a 16-byte or 32-byte boundary must be set for the source address value. The initial value is undefined.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- R/W 15 30 -- R/W 14 29 -- R/W 13 28 -- R/W 12 27 -- R/W 11 26 -- R/W 10 25 -- R/W 9 24 -- R/W 8 23 -- R/W 7 22 -- R/W 6 21 -- R/W 5 20 -- R/W 4 19 -- R/W 3 18 -- R/W 2 17 -- R/W 1 16 -- R/W 0
DARB
DARB -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W
14.3.5
DMA Transfer Count Registers (TCR0 to TCR5)
TCR is 32-bit readable/writable registers that specify the DMA transfer count. The number of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers indicate the remaining transfer count. The upper eight bits of TCR are always read as 0, and the write value should always be 0. The initial value is undefined.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- R/W 15 -- R/W 30 -- R/W 14 -- R/W 29 -- R/W 13 -- R/W 28 -- R/W 12 -- R/W 27 -- R/W 11 -- R/W 26 -- R/W 10 -- R/W 25 -- R/W 9 -- R/W 24 TCR -- R/W 8 TCR -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 23 22 21 20 19 18 17 16
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Section 14 Direct Memory Access Controller (DMAC)
14.3.6
DMA Transfer Count Registers (TCRB0 to TCRB3)
TCRB is 32-bit readable/writable registers. Data to be written from the CPU to TCR is also written to TCRB. While the HE function is used, TCRB are used as the initial value hold registers to detect HE. Also, TCRB specify the number of DMA transfers which are set in TCR in repeat mode. TCRB specify the number of DMA transfers and are used as transfer count counters in reload mode. In reload mode, the lower 16 bits operate as transfer count counters, values of SAR and DAR are updated after the value of the lower 16 bits became 0, and then the value of the upper 16 bits of TCRB are loaded to the lower 16 bits. In upper 16 bits, set the number of transfers which starts reloading. In reload mode, the same number of transfers should be set in both upper and lower 16 bits. Also, set the HIE bit in CHCR to 0 and do not use the HE function. The initial value of TCRB is undefined.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- R 15 -- R/W 30 -- R 14 -- R/W 29 -- R 13 -- R/W 28 -- R 12 -- R/W 27 -- R 11 -- R/W 26 -- R 10 -- R/W 25 -- R 9 -- R/W 24 -- R 8 -- R/W 23 -- R/W 7 -- R/W 22 -- R/W 6 -- R/W 21 -- R/W 5 -- R/W 20 -- R/W 4 -- R/W 19 -- R/W 3 -- R/W 18 -- R/W 2 -- R/W 17 -- R/W 1 -- R/W 16 -- R/W 0 -- R/W
TCRB
TCRB
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Section 14 Direct Memory Access Controller (DMAC)
14.3.7
DMA Channel Control Registers (CHCR0 to CHCR5)
CHCR is 32-bit readable/writable registers that control the DMA transfer mode.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 LCKN 0 R 15 0 R/W 1 R/W 14 0 R/W 0 R 13 0 R/W 0 R 12 0 R/W 0 R/W 11 0 R/W 29 28 27 26 RPT[2:0] 0 R/W 10 0 R/W 0 R/W 9 0 R/W 0 R 8 0 R/W 25 24 23 DO 0 R/W 7 DL 0 R/W 0 R 6 DS 0 R/W 22 21 20 19 HE 18 HIE 17 AM 0 R/W 1 TE 16 AL 0 R/W 0
DE
DVMD TS[2]
0 R/W 5 TB 0 R/W
0 0 0 R/W R/(W)* R/W 4 0 R/W 3 0 R/W 2 IE
DM[1:0]
SM[1:0]
RS[3:0]
TS[1:0]
0 0 0 R/W R/(W)* R/W
Note: Writing 0 is possible to clear the flag.
Bit 31
Bit Name --
Initial Value 0
R/W R
Descriptions Reserved This bit is always read as 0. The write value should always be 0.
30
LCKN
1
R/W
Bus Lock Signal Disable Specifies whether enable or disable the bus lock signal output when a load instruction is output in dual transfer mode. This bit is effective in cycle steal mode, and should be cleared to 0 in burst mode. To disable the bus lock signal, the bus request from the bus master other than the DMAC could be received, and so improve the bus usage efficiency in total system. 0: Bus lock signal output enabled 1: Bus lock signal output disabled
29, 28
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 14 Direct Memory Access Controller (DMAC)
Bit 27 to 25
Bit Name RPT[2:0]
Initial Value 000
R/W R/W
Descriptions DMA Setting Renewal Specify These bits are enabled in CHCR0 to CHCR3. 000: Normal mode 001: Repeat mode SAR/DAR/TCR used as repeat area 010: Repeat mode DAR/TCR used as repeat area 011: Repeat mode SAR/TCR used as repeat mode 100: Reserved (setting prohibited) 101: Reload mode SAR/DAR/TCR used as reload area 110: Reload mode DAR/TCR used as reload area 111: Reload mode SAR/TCR used as reload area
24
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
23
DO
0
R/W
DMA Overrun Selects whether DREQ is detected by overrun 0 or by overrun 1. This bit is valid only in CHCR0 to CHCR3. 0: Detects DREQ by overrun 0 1: Detects DREQ by overrun 1
22
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
21
DVMD
0
R/W
Division Transfer Mode Specification Specifies the execution of the DMA transfer in 16-byte units between the on-chip peripheral module STIF and the external memory. When the STIF is used, always write 1 to this bit. When the STIF is not used, always write 0 to this bit.
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Section 14 Direct Memory Access Controller (DMAC)
Bit 20
Bit Name TS2
Initial Value 0
R/W R/W
Descriptions DMA Transfer Size Specify With TS1 and TS0, this bit specifies the DMA transfer size. When the transfer source or transfer destination is a register of an on-chip peripheral module with a transfer size set, a proper transfer size for the register should be set. For the transfer source or destination address specified by SAR or DAR, an address boundary should be set according to the transfer data size. TS[2:0] 000: Byte units transfer 001: Word (2-byte) units transfer 010: Longword (4-byte) units transfer 011: 16-byte units transfer 100: 32-byte units transfer Other than above: Setting prohibited
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Section 14 Direct Memory Access Controller (DMAC)
Bit 19
Bit Name HE
Initial Value 0
R/W
Descriptions
R/(W)* Half End Flag After HIE (bit 18) is set to 1 and the number of transfers become half of TCR (1 bit shift to right) which is set before transfer starts, HE becomes 1. This bit is set to 1 when the TCR value is equal to (TCR set before transfer)/2: TCR value is set to even number of times (TCR set before transfer -1)/2: TCR value is set to odd number of times 8,388,608 (H'0080 0000): TCR value is set to the maximum number of times (H'0000 0000) The HE bit is not set when transfers are ended by an NMI interrupt or address error, or by clearing the DE bit or the DME bit in DMAOR before the number of transfers is decreased to half of the TCR value set preceding the transfer. The HE bit is kept set when the transfer ends by an NMI interrupt or address error, or clearing the DE bit (bit 0) or the DME bit in DMAOR after the HE bit is set to 1. To clear the HE bit, write 0 after reading 1 in the HE bit. This bit is valid only in CHCR0 to CHCR3. 0: During the DMA transfer or DMA transfer has been interrupted TCR > (TCR set before transfer)/2 [Clearing condition] Writing 0 after HE = 1 is read. 1: TCR * (TCR set before transfer)/2
18
HIE
0
R/W
Half End Interrupt Enable Specifies whether an interrupt request is generated to the CPU when the number of transfers is decreased to half of the TCR value set preceding the transfer. When the HIE bit is set to 1 and the HE bit is set, an interrupt request is generated to the CPU. Clear this bit to 0 while reload mode is set. This bit is valid in CHCR0 to CHCR3. 0: Half end Interrupt disabled 1: Half end Interrupt enabled
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Section 14 Direct Memory Access Controller (DMAC)
Bit 17
Bit Name AM
Initial Value 0
R/W R/W
Descriptions Acknowledge Mode Selects whether DACK is output in data read cycle or in data write cycle. This bit is valid only in CHCR0 to CHCR3. 0: DACK output in read cycle 1: DACK output in write cycle
16
AL
0
R/W
Acknowledge Level Specifies whether the DACK signal output is high active or low active. This bit is valid only in CHCR0 to CHCR3. 0: Low-active output of DACK and TEND 1: High-active output of DACK and TEND
15, 14
DM[1:0]
00
R/W
Destination Address Mode Specify whether the DMA destination address is incremented, decremented, or left fixed. 00: Fixed destination address 01: Destination address is incremented +1 in byte units transfer +2 in word units transfer +4 in longword units transfer +16 in 16-byte units transfer +32 in 32-byte units transfer 10: Destination address is decremented -1 in byte units transfer -2 in word units transfer -4 in longword units transfer Setting prohibited in 16/32-byte units transfer 11: Setting prohibited
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Section 14 Direct Memory Access Controller (DMAC)
Bit 13, 12
Bit Name SM[1:0]
Initial Value 00
R/W R/W
Descriptions Source Address Mode Specify whether the DMA source address is incremented, decremented, or left fixed. 00: Fixed source address 01: Source address is incremented +1 in byte units transfer +2 in word units transfer +4 in longword units transfer +16 in 16-byte units transfer +32 in 32-byte units transfer 10: Source address is decremented -1 in byte units transfer -2 in word units transfer -4 in longword units transfer Setting prohibited in 16/32-byte units transfer 11: Setting prohibited
11 to 8
RS[3:0]
0000
R/W
Resource Select Specify which transfer requests will be sent to the DMAC. The changing of transfer request source should be done in the state that the DMA enable bit (DE) is cleared to 0. 0000: External request, dual address mode 0100: Auto request 1000: Selected by DMA extended resource selector (for on-chip modules) Other than above: Setting prohibited Note: External request specification is valid only in CHCR0 to CHCR3. None of the external request can be selected in CHCR4 and CHCR5.
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Section 14 Direct Memory Access Controller (DMAC)
Bit 7 6
Bit Name DL DS
Initial Value 0 0
R/W R/W R/W
Descriptions DREQ Level and DREQ Edge Select Specify the detecting method of the DREQ pin input and the detecting level. These bits are valid only in CHCR0 to CHCR3. In channels 0 to 3, also, if the transfer request source is specified as an on-chip peripheral module or if an autorequest is specified, these bits are invalid. 00: DREQ detected at low level 01: DREQ detected at falling edge 10: DREQ detected at high level 11: DREQ detected at rising edge
5
TB
0
R/W
Transfer Bus Mode Specifies the bus mode when DMA transfers data. 0: Cycle steal mode 1: Burst mode Burst mode cannot be used when the on-chip peripheral module is the transfer request source.
4, 3 2
TS[1:0] IE
00 0
R/W R/W
DMA Transfer Size Specify See the description of TS[2] (bit 20). Interrupt Enable Specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when the TE bit is set to 1. 0: Interrupt request is disabled. 1: Interrupt request is enabled.
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Section 14 Direct Memory Access Controller (DMAC)
Bit 1
Bit Name TE
Initial Value 0
R/W
Descriptions
R/(W)* Transfer End Flag Shows that DMA transfer ends. The TE bit is set to 1 when data transfer ends when TCR becomes to 0. The TE bit is not set to 1 in the following cases. * * DMA transfer ends due to an NMI interrupt or DMA address error before TCR is cleared to 0. DMA transfer is ended by clearing the DE bit and DME bit in DMAOR.
To clear the TE bit, the TE bit should be written to 0 after reading 1. Even if the DE bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: During the DMA transfer or DMA transfer has been interrupted [Clearing condition] Writing 0 after TE = 1 read 1: DMA transfer ends by the specified count (TCR = 0) 0 DE 0 R/W DMA Enable Enables or disables the DMA transfer. In auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this time, all of the bits TE, NMIF, and AE in DMAOR must be 0. In an external request or peripheral module request, DMA transfer starts if DMA transfer request is generated by the devices or peripheral modules after setting the bits DE and DME to 1. In this case, however, all of the bits TE, NMIF, and AE must be 0, which is the same as in the case of auto request mode. Clearing the DE bit to 0 can terminate the DMA transfer. 0: DMA transfer disabled 1: DMA transfer enabled To abort the DMA transfer in on-chip peripheral module request mode, clear the DE bit to 0 while the DMA request from the corresponding peripheral module is cleared. Note: * Writing 0 is possible to clear the flag.
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Section 14 Direct Memory Access Controller (DMAC)
14.3.8
DMA Operation Register (DMAOR)
DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register shows the DMA transfer status. DMAOR is a common register for channel 0 to 5.
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R/W 12 0 R/W 11 0 R 10 0 R 9 0 R/W 8 0 R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 AE 1 0
CMS[1:0]
PR[1:0]
NMIF DME
0 0 0 R/(W)*R/(W)* R/W
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Descriptions Reserved These bits are always read as 0. The write value should always be 0.
13, 12
CMS[1:0]
00
R/W
Cycle Steal Mode Select Select either normal mode or intermittent mode in cycle steal mode. It is necessary that all channel bus modes are set to cycle steal mode to make valid intermittent mode. 00: Normal mode 01: Setting prohibited 10: Intermittent mode 16 Executes one DMA transfer in each of 16 clocks of an external bus clock. 11: Intermittent mode 64 Executes one DMA transfer in each of 64 clocks of an external bus clock.
11, 10
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 14 Direct Memory Access Controller (DMAC)
Bit 9, 8
Bit Name PR[1:0]
Initial Value 00
R/W R/W
Descriptions Priority Mode 1, 0 Select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 01: CH0 > CH2 > CH3 > CH1 > CH4 > CH5 10: Setting prohibited 11: Round-robin mode
7 to 3
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
2
AE
0
R/(W)* Address Error Flag Indicates that an address error occurred during DMA transfer. This bit is set under following conditions: * * * The value set in SAR or DAR does not match to the transfer size boundary. The transfer source or transfer destination is invalid space. The transfer source or transfer destination is in module stop mode
If this bit is set, DMA transfer is disabled even if the DE bit in CHCR and the DME bit in DMAOR are set to 1. 0: No DMAC address error [Clearing condition] Writing AE = 0 after AE = 1 read 1: DMAC address error occurs
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Section 14 Direct Memory Access Controller (DMAC)
Bit 1
Bit Name NMIF
Initial Value 0
R/W
Descriptions
R/(W)* NMI Flag Indicates that an NMI interrupt occurred. If this bit is set, DMA transfer is disabled even if the DE bit in CHCR and the DME bit in DMAOR are set to 1. When the NMI is input, the DMA transfer in progress can be done in at least one transfer unit. When the DMAC is not in operational, the NMIF bit is set to 1 even if the NMI interrupt was input. 0: No NMI interrupt [Clearing condition] Writing NMIF = 0 after NMIF = 1 read 1: NMI interrupt occurs Note: DMA transfer is stopped when an NMI interrupt is input. After returning from the NMI interrupt routine, set all channels again, and then start the DMA transfer.
0
DME
0
R/W
DMA Master Enable Enables or disables DMA transfers on all channels. If the DME bit and the DE bit in CHCR are set to 1, transfer is enabled. In this time, all of the bits TE in CHCR, NMIF, and AE in DMAOR must be 0. If this bit is cleared during transfer, transfers in all channels are terminated. 0: Disables DMA transfers on all channels 1: Enables DMA transfers on all channels Note: To abort the DMA transfer when the on-chip peripheral module request mode is set for any of the channels specified by DMAOR (channel 0 to 5), clear the DE bit to 0 while the DMA transfer request from the corresponding peripheral module is cleared.
Note:
*
Writing 0 is possible to clear the flag.
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Section 14 Direct Memory Access Controller (DMAC)
14.3.9
DMA Extended Resource Selectors (DMARS0 to DMARS2)
DMARS is 16-bit readable/writable registers that specify the DMA transfer sources from peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies for channels 2 and 3, and DMARS2 specifies for channels 4 and 5. This register can set the transfer request of CMT, SCIF0 to SCIF2. HAC, USBF, SSI0 to SSI3, MMCIF, SIM, SIOF0 to SIOF2, STIF0, AND STIF1. When MID/RID other than the values listed in table 14.4 is set, the operation of this LSI is not guaranteed. The transfer request from DMARS is valid only when the resource select bits RS[3:0] has been set to B'1000 for CHCR0 to CHCR5 registers. Otherwise, even if DMARS has been set, transfer request source is not accepted. * DMARS0
Bit: Initial value: R/W: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W C1MID[5:0] C1RID[1:0] C0MID[5:0] C0RID[1:0]
Bit 15 to 10 9, 8 7 to 2 1, 0
Bit Name
Initial Value
R/W R/W R/W R/W R/W
Descriptions Transfer request module ID for DMA channel 1 (MID) See table 14.4. Transfer request register ID for DMA channel 1 (RID) See table 14.4. Transfer request module ID for DMA channel 0 (MID) See table 14.4 Transfer request register ID for DMA channel 0 (RID) See table 14.4.
C1MID[5:0] 000000 C1RID[1:0] 00 C0MID[5:0] 000000 C0RID[1:0] 00
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Section 14 Direct Memory Access Controller (DMAC)
* DMARS1
Bit: Initial value: R/W: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W C3MID[5:0] C3RID[1:0] C2MID[5:0] C2RID[1:0]
Bit 15 to 10 9, 8 7 to 2 1, 0
Bit Name
Initial Value
R/W R/W R/W R/W R/W R/W
Descriptions Transfer request module ID for DMA channel 3 (MID) See table 14.4. Transfer request register ID0 for DMA channel 3 (RID) See table 14.4. Transfer request module ID for DMA channel 2 (MID) See table 14.4. Transfer request register ID for DMA channel 2 (RID) See table 14.4.
C3MID[5:0] 000000 C3RID[1:0] 00 C2MID[5:0] 000000 C2RID[1:0] 00
* DMARS2
Bit: Initial value: R/W: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W C5MID[5:0] C5RID[1:0] C4MID[5:0] C4RID[1:0]
Bit 15 to 10 9, 8 7 to 2 1, 0
Bit Name
Initial Value
R/W R/W R/W R/W R/W
Descriptions Transfer request module ID for DMA channel 5 (MID) See table 14.4. Transfer request register ID for DMA channel 5 (RID) See table 14.4. Transfer request module ID for DMA channel 4 (MID) See table 14.4. Transfer request register ID for DMA channel 4 (RID) See table 14.4.
C5MID[5:0] 000000 C5RID[1:0] 00 C4MID[5:0] 000000 C4RID[1:0] 00
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Section 14 Direct Memory Access Controller (DMAC)
Table 14.4 Transfer Request Sources
Peripheral Module CMT channel 0 CMT channel 1 CMT channel 2 CMT channel 3 CMT channel 4 SCIF0 Setting Value for One Channel (MID and RID) H'03 H'07 H'0B H'0F H'13 H'21 H'22 SCIF1 H'29 H'2A SCIF2 H'41 H'42 HAC H'45 H'46 USBF H'51 H'52 SSI0 SSI1 SSI2 SSI3 MMCIF SIM H'73 H'77 H'83 H'87 H'93 H'A1 H'A2 MID B'0000 00 B'0000 01 B'0000 10 B'0000 11 B'0001 00 B'0010 00 B'0010 00 B'0010 10 B'0010 10 B'0100 00 B'0100 00 B'0100 01 B'0100 01 B'0101 00 B'0101 00 B'0111 00 B'0111 01 B'1000 00 B'1000 01 B'10 01 00 B'1010 00 B'1010 00 RID B'11 B'11 B'11 B'11 B'11 B'01 B'10 B'01 B'10 B'01 B'10 B'01 B'10 B'01 B'10 B'11 B'11 B'11 B'11 B'11 B'01 B'10 Function Transmit Receive Transmit Receive Transmit Receive Transmit Receive Transmit Receive Transmit and Receive Transmit and Receive Transmit and Receive Transmit and Receive Transmit and Receive Transmit Receive
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Section 14 Direct Memory Access Controller (DMAC)
Peripheral Module SIOF0
Setting Value for One Channel (MID and RID) H'B1 H'B2
MID B'1011 00 B'1011 00 B'1011 01 B'1011 01 B'1100 00 B'1100 00 B'1101 00 B'1101 01
RID B'01 B'10 B'01 B'10 B'01 B'10 B'11 B'11
Function Transmit Receive Transmit Receive Transmit Receive Transmit and Receive Transmit and Receive
SIOF1
H'B5 H'B6
SIOF2
H'C1 H'C2
STIF0 STIF1
H'D3 H'D7
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Section 14 Direct Memory Access Controller (DMAC)
14.4
Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. In bus mode, burst mode or cycle steal mode can be selected. 14.4.1 DMA Transfer Requests
DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by external devices or on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. The request mode is selected in the bits RS[3:0] in CHCR0 to CHCR5, and DMARS0 to DMARS2. (1) Auto-Request Mode
When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits in CHCR0 to CHCR5 and the DME bit in DMAOR are set to 1, the transfer begins so long as the AE and NMIF bits in DMAOR are all 0. (2) External Request Mode
In this mode, a transfer is performed at the request signal (DREQ0 to DREQ3) of an external device. This mode is valid only in channel 0 to 3. In this mode, the RS[3:0] bits in CHCRn (n = 0 to 3) should be B'0000. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at the DREQ input. Table 14.5 Setting External Request Mode with RS bit
CHCR RS[3] RS[2] 0 0 RS[1] RS[0] Address Mode 0 0 Dual Address Mode Transfer Source Any Transfer Destination Any
Choose to detect DREQ by either the edge or level of the signal input with the DL bit and DS bit in CHCRn (n = 0 to 3) as shown in table 14.6. The source of the transfer request does not have to be the data transfer source or destination.
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Section 14 Direct Memory Access Controller (DMAC)
Table 14.6 Selecting External Request Detection with DL, DS Bits
CHCRn (n=0 to 3) DL 0 DS 0 1 1 0 1 Detection of External Request Low level detection (initial value; DREQ) Falling edge detection High level detection Rising edge detection
When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK. * Overrun 0: Transfer is aborted after the same number of transfer has been performed as requests. * Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests plus 1) times. The DO bit in CHCR selects this overrun 0 or overrun 1. Table 14.7 Selecting External Request Detection with DO Bit
CHCR DO 0 1 External Request Overrun 0 (initial value) Overrun 1
(3)
On-Chip Peripheral Module Request Mode
In this mode, a transfer is performed at the transfer request signal of an on-chip peripheral module. Transfer request signals comprise the transmit data empty transfer request and receive data full transfer request from the SCIF0 to SCIF2, HAC USBF, SSI0 to SSI3, MMCIF, SIM, SIOF0 to SIOF2, STIF0, and STIF1 set by DMARS0/1/2, and transfer requests from the CMT. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon the input of a transfer request signal.
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Section 14 Direct Memory Access Controller (DMAC)
When a transmit data empty transfer request of the SCIF0 is set as the transfer request, the transfer destination must be the SCIF0's transmit data register. Likewise, when receive data full transfer request of the SCIF0 is set as the transfer request, the transfer source must be the SCIF0's receive data register. These conditions also apply to the SCIF1, SCIF2, HAC USBF, SSI0 to SSI3, MMCIF, SIM, SIOF0 to SIOF2, STIF0, and STIF1. Table 14.8 Selecting On-Chip Peripheral Module Request Modes with Bits RS[3:0]
CHCR RS[3:0] 1000 DMARS MID 000000 000001 000010 000011 000100 001000 RID 11 11 11 11 11 01 10 001010 01 10 010000 01 10 010001 01 10 010100 01 10 011100 11 DMA Transfer DMA Transfer Request Source Request Signal CMT channel 0 CMT channel 1 CMT channel 2 CMT channel 3 CMT channel 4 SCI F0 transmitter SCIF0 receiver SCI F1 transmitter SCIF1 receiver SCIF2 transmitter SCIF2 receiver HAC transmitter HAC receiver USB transmitter USB receiver SSI0 transmitter SSI0 receiver Compare-match transfer request Compare-match transfer request Compare-match transfer request Compare-match transfer request Compare-match transfer request TXI (transmit FIFO data empty interrupt) RXI (receive FIFO data full interrupt) TXI (transmit FIFO data empty interrupt) RXI (receive FIFO data full interrupt) TXI (transmit FIFO data empty interrupt) RXI (receive FIFO data full interrupt) Bus Mode Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal
Source Any Any Any Any Any Any SCFRDR0 Any SCFRDR1 Any SCFRDR2
Destination Any Any Any Any Any SCFTDR0 Any SCFTDR1 Any SCFTDR2 Any HACPCML, HACPCMR Any EPDR Any SSIRDR
Transmit data empty request Any Receive data is not read HACPCML, HACPCMR
Transmit data empty request Any Receive data full request Transmit mode : DMRQ = 1 (Transmit data empty request) Receive mode : DMRQ = 1 (Receive data is not read) EPDR Any
11
SSIRDR
Any
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Section 14 Direct Memory Access Controller (DMAC) CHCR RS[3:0] 1000 DMARS MID 011101 RID 11 DMA Transfer DMA Transfer Request Source Request Signal SSI1 transmitter SSI1 receiver SSI2 transmitter SSI2 receiver SSI3 transmitter SSI3 receiver MMCIF data part transmit MMCIF data part receive 101000 01 10 101100 01 10 101101 01 10 110000 01 10 110100 11 11 110101 11 11 SIM transmitter SIM receiver SIOF0 transmitter SIOF0 receiver SIOF1 transmitter SIOF1 receiver SIOF2 transmitter SIOF2 receiver STIF0 transmitter STIF0 receiver STIF1 transmitter STIF1 receiver Transmit mode : DMRQ = 1 (Transmit data empty request) Receive mode : DMRQ = 1 (Receive data is not read) Transmit mode : DMRQ = 1 (Transmit data empty request) Receive mode : DMRQ = 1 (Receive data is not read) Transmit mode : DMRQ = 1 (Transmit data empty request) Receive mode : DMRQ = 1 (Receive data is not read) FIFO data write request FIFO data read request TXT (transmit data empty) RXI (receive data full) TXI (transmit FIFO data empty) RXI (receive data full) TXI1 (transmit FIFO data empty) RXI (receive FIFO data empty) TXI (transmit FIFO data empty) RXI (receive FIFO data full) FIFO data write request FIFO data read request FIFO data write request FIFO data read request
Source Any
Destination SSITDR
Bus Mode Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal
11 100000 11
SSIRDR Any
Any SSITDR
11 100001 11
SSIRDR Any
Any SSITDR
11 100100 11
SSIRDR Any DR Any SCRDR Any SIRDR0 Any SIRDR1 Any SIRDR2 Any STI0FIFO0 Any STI0FIFO1
Any DR Any SCTDR Any SITDR0 Any SITDR1 Any SITDR2 Any STI0FIFO0 Any STI0FIFO1 Any
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Section 14 Direct Memory Access Controller (DMAC)
14.4.2
Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it transfers data according to a predetermined priority. Two modes (fixed mode and round-robin mode) are selected by the bits PR[1:0] in DMAOR. (1) Fixed Mode
In this mode, the priority levels among the channels remain fixed. There are two kinds of fixed modes as follows: * CH0 > CH1 > CH2 > CH3 > CH4 > CH5 * CH0 > CH2 > CH3 > CH1 > CH4 > CH5 These are selected by the bits PR[1:0] in DMAOR (2) Round-Robin Mode
In round-robin mode each time data of one transfer unit (word, byte, longword, 16-byte, or 32byte unit) is transferred on one channel, the priority is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority. The round-robin mode operation is shown in figure 14.2. The priority of round-robin mode is CH0 > CH1 > CH2 > CH3 > CH4 > CH5 immediately after reset. When round-robin mode is specified, do not mix the cycle steal mode and the burst mode in multiple channels' bus modes.
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Section 14 Direct Memory Access Controller (DMAC)
(1) When channel 0 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 CH1 > CH2 > CH3 > CH4 > CH5 > CH0 Channel 0 becomes bottom priority
Priority order after transfer
(2) When channel 1 transfers Channel 1 becomes bottom priority. The priority of channel 0, which was higher than channel 1, is also shifted.
Initial priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5
Priority order after transfer
CH2 > CH3 > CH4 > CH5 > CH0 > CH1
(3) When channel 2 transfers CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Channel 2 becomes bottom priority. The priority of channels 0 and 1, which were higher than channel 2, are also shifted. If immediately after there is a request to transfer channel 5 only, channel 5 becomes bottom priority and the priority of channels 3 and 4, which were higher than channel 5, are also shifted.
Initial priority order
Priority order after transfer
CH3 > CH4 > CH5 > CH0 > CH1 > CH2
Post-transfer priority order when there is an CH0 > CH1 > CH2 > CH3 > CH4 > CH5 immediate transfer request to channel 5 only
(4) When channel 5 transfers Initial priority order Priority order after transfer CH0 > CH1 > CH2 > CH3 > CH4 > CH5 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Priority order does not change.
Figure 14.2 Round-Robin Mode
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Section 14 Direct Memory Access Controller (DMAC)
Figure 14.3 shows how the priority changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 0 and 3. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 becomes lowest priority. 5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. When the channel 1 transfer ends, channel 1 becomes lowest priority. 7. The channel 3 transfer begins. 8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority.
Transfer request Waiting channel(s) DMAC operation Channel priority
(1) Channels 0 and 3
(3) Channel 1 3 (2) Channel 0 transfer start Priority order changes 0>1>2>3>4>5
1,3 (4) Channel 0 transfer ends
1>2>3>4>5>0
(5) Channel 1 transfer starts 3 (6) Channel 1 transfer ends Priority order changes 2>3>4>5>0>1
(7) Channel 3 transfer starts None (8) Channel 3 transfer ends
Priority order changes
4>5>0>1>2>3
Figure 14.3 Changes in Channel Priority in Round-Robin Mode
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Section 14 Direct Memory Access Controller (DMAC)
14.4.3
DMA Transfer Types
DMA transfer type is dual address mode transfer. A data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. (1) Dual Address Modes
In dual address mode, both the transfer source and destination are accessed by an address. The source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 14.4, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle.
DMAC SAR DAR Memory
Address bus
Data bus
Transfer source module Transfer destination module
Data buffer
The SAR value is an address, data is read from the transfer source module, and the data is temporarily stored in the DMAC. First bus cycle DMAC SAR Memory
Address bus
DAR
Data bus
Transfer source module Transfer destination module
Data buffer
The DAR value is an address and the value stored in the data buffer in the DMAC is written to the transfer destination module. Second bus cycle
Figure 14.4 Data Flow of Dual Address Mode
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Section 14 Direct Memory Access Controller (DMAC)
Auto request, external request, and on-chip peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. CHCR can specify whether the DACK is output in read cycle or write cycle. Figure 14.5 shows an example of DMA transfer timing in dual address mode.
CLKOUT
A25 to A0
Transfer source address
Transfer destination address
CSn
D31 to D0
RD WE DACK (Active-low)
Data read cycle (1st cycle)
Data write cycle (2nd cycle)
Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn.
Figure 14.5 Example of DMA Transfer Timing in Dual Address Mode (Source: Ordinary Memory, Destination: Ordinary Memory)
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Section 14 Direct Memory Access Controller (DMAC)
(2)
Bus Modes
There are two bus modes: cycle steal mode and burst mode. Select the mode in the TB and LCKN bits in CHCR. And cycle steal mode has normal and intermittent modes that are specified by the CMS bits in DMAOR. * Cycle-Steal Mode Normal mode1 (DMAOR.CMS = 00, CHCR.LCKN = 0, CHCR.TB = 0) In cycle-steal normal mode, the SuperHyway bus mastership is given to another bus master after a one-transfer unit (byte, word, longword, 16-byte, or 32-byte unit) DMA transfer. When the next transfer request occurs, the DMAC issues the next transfer request, the bus mastership is obtained from the other bus master and a transfer is performed for onetransfer unit. When that transfer ends, the bus mastership is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. In cycle-steal normal mode, transfer areas are not affected regardless of settings of the transfer request source, transfer source, and transfer destination. Figure 14.6 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer conditions shown in the figure are:
DREQ Bus mastership returned to CPU once SuperHyway bus cycle
CPU
CPU
CPU
DMAC DMAC
CPU
DMAC
DMAC
CPU
Read/Write
Read/Write
Figure 14.6 DMA Transfer Timing Example in Cycle-Steal Normal Mode 1 (DREQ Low Level Detection) Normal mode 2 (DMAOR.CMS = 00, CHCR.LCKN = 1, CHCR.TB = 0) In cycle steal normal mode 2, the DMAC does not keep the SuperHyway bus mastership, is to obtain the bus mastership in every one transfer unit of read or write cycle. Figure 14.7 shows an example of DMA transfer timing in cycle steal normal mode 2.
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Section 14 Direct Memory Access Controller (DMAC)
DREQ Busmastership retured to CPU once
SuperHyway bus cycle
CPU
CPU
CPU
DMAC Read
CPU
DMAC Write
CPU
DMAC Read
CPU
DMAC Write
CPU
Figure 14.7 DMA Transfer Timing Example in Cycle-Steal Normal Mode 2 (DREQ Low Level Detection) Intermittent mode 16 (DMAOR.CMS = 10, CHCR.LCKN = 0 or 1, CHCR.TB = 0), intermittent mode 64 (DMAOR.CMS = 11, CHCR.LCKN = 0 or 1, CHCR.TB = 0) In intermittent mode of cycle steal, the DMAC returns the SuperHyway bus mastership to other bus master whenever a one-transfer unit (byte, word, longword, or 16-byte or 32-byte unit) is complete. If the next transfer request occurs after that, the DMAC issues the next transfer request after waiting for 16 or 64 clocks in Bck count, and obtains the bus mastership from other bus master. The DMAC then transfers data of one-transfer unit and returns the bus mastership to other bus master. These operations are repeated until the transfer end condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA transfer than cycle-steal normal mode. When the DMAC issues again the transfer request, DMA transfer can be postponed in case of entry updating due to cache miss. This intermittent mode can be used for all transfer section; transfer request source, transfer source, and transfer destination. The bus modes, however, must be cycle steal mode in all channels. Figure 14.8 shows an example of DMA transfer timing in cycle steal intermittent mode. Transfer conditions shown in the figure are:
DREQ More than 16 or 64 Bck (depends on DMAOR.CMS settings)
SuperHyway bus cycle
CPU
CPU
CPU DMAC DMAC
Read/Write
CPU
CPU
DMAC DMAC
Read/Write
CPU
Figure 14.8 Example of DMA Transfer Timing in Cycle Steal Intermittent Mode (DREQ Low Level Detection)
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Section 14 Direct Memory Access Controller (DMAC)
* Burst Mode (LCKN = 0, TB = 1) In burst mode, once the DMAC obtains the SuperHyway bus mastership, the transfer is performed continuously without releasing the bus mastership until the transfer end condition is satisfied. In external request mode with level detection of the DREQ pin, however, when the DREQ pin is not active, the bus mastership passes to the other bus master after the DMAC transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. Burst mode cannot be used when the on-chip peripheral module is the transfer request source. Figure 14.9 shows DMA transfer timing in burst mode.
DREQ
SuperHyway bus cycle
CPU
CPU
CPU
DMAC DMAC DMAC DMAC DMAC DMAC Read Write Read Write Read Write
CPU
Figure 14.9 DMA Transfer Timing Example in Burst Mode (DREQ Low Level Detection) (3) DMA Transfer Matrix
Table 14.10 shows the DMA transfer matrix in auto-request mode and table 14.11 shows the DMA transfer matrix in external request mode, and table 14.12 shows the on-chip peripheral module request.
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Section 14 Direct Memory Access Controller (DMAC)
Table 14.9 DMA Transfer Matrix in Auto-Request Mode (all channels)
Transfer Destination On-chip peripheral 1 LBSC space DDRIF space PCIC space module* Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Transfer Source LBSC space DDRIF space PCIC space On-chip peripheral 1 module* L RAM
L RAM Yes Yes Yes Yes Yes
[Legend] Yes: Transfer is available. Note: 1. When the transfer source or destination is on-chip peripheral module register, the transfer size should be the same value of its access size.
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Section 14 Direct Memory Access Controller (DMAC)
Table 14.10 DMA Transfer Matrix in External Request Mode (only channels 0 to 3)
Transfer Destination On-chip peripheral 1 module* Yes Yes*3 Yes*3 Yes Yes
Transfer Source LBSC space DDRIF space PCIC space On-chip peripheral 1 module* L RAM
LBSC space DDRIF space PCIC space Yes Yes*3 Yes*3 Yes Yes Yes* No Yes*5 Yes*2 Yes*2
2
L RAM Yes Yes*3 Yes*3 Yes Yes
Yes*
2
Yes*4 Yes*5 Yes*2 Yes*2
[Legend] Yes: Transfer is available. No: Transfer is not available. Notes: 1. When the transfer source or destination is on-chip peripheral module register, the transfer size should be the same value of its access size. 2. Transfer is available when the AM bit in CHCR is cleared to 0. 3. Transfer is available when the AM bit in CHCR is set to 1. 4. Transfer is available when the AM bit in CHCR is set to 1 and the destination address of the PCIC is H'FD00 0000 to H'FDFF FFFF (PCI memory space 0). 5. Transfer is available when the AM bit in CHCR is cleared to 0 and the source address of the PCIC is H'FD00 0000 to H'FDFF FFFF (PCI memory space 0). 6. Transfer is available when the source or destination, or both the source and destination address of the PCIC is H'FD00 0000 to H'FDFF FFFF (PCI memory space 0). When the transfer source address is H'FD00 0000 to H'FDFF FFFF, the AM bit in CHCR is cleared to 0, when the transfer destination address is H'FD00 0000 to H'FDFF FFFF the AM bit in CHCR is set to 1.
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Section 14 Direct Memory Access Controller (DMAC)
Table 14.11 DMA Transfer Matrix in On-Chip Peripheral module Request Mode
Transfer Destination On-chip peripheral 1 module* Yes Yes Yes Yes Yes
Transfer Source LBSC space DDRIF space PCIC space On-chip peripheral 1 module* L RAM
LBSC space DDRIF space PCIC space No No No Yes No No No No Yes No No No No Yes No
L RAM No No No Yes No
[Legend] Yes: Transfer is available. No: Transfer is not available. Note: 1. When the transfer source or the destination is an on-chip peripheral module, the transfer size should be the same value of its register access size. The transfer source or the transfer destination should be a register of request source in on-chip peripheral module request mode. This transfer is available only cycle steal mode, and when the transfer request source is an on-chip peripheral module, the transfer is available in channel 0 to 5.
(4)
Bus Mode and Channel Priority
When the priority is set in fixed mode (CH0 > CH1) and channel 1 is transferring in burst mode, if there is a transfer request to channel 0 with a higher priority, the transfer of channel 0 will begin immediately. At this time, if channel 0 is also operating in burst mode, the channel 1 transfer will continue after the channel 0 transfer has completely finished. When channel 0 is in cycle steal mode, channel 0 with a higher priority performs the transfer of one transfer unit and the channel 1 transfer is continuously performed without releasing the bus mastership. The bus mastership will then switch between the two in the order channel 0, channel 1, channel 0, and channel 1. This example is shown in figure 14.9. When multiple channels are operating in burst modes, the channel with the highest priority is executed first. When DMA transfer is executed in the multiple channels, the bus mastership will not be given to the bus master until all competing burst transfers are complete.
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Section 14 Direct Memory Access Controller (DMAC)
CPU
DMA CH1
DMA CH1
DMA CH0
DMA CH1
DMA CH0
DMA CH1
DMA CH1
CPU
DMA CH1 Burst mode CH0 transfer source
DMA CH0 and CH1 Burst mode
DMA CH1 Burst mode
CH1 transfer source
Priority: CH0 > CH1 CH0: Cycle steal mode CH1: Burst mode
Figure 14.10 Bus State when Multiple Channels are Operating In round-robin mode, the priority changes according to the specification shown in figure 14.2. However, the channel in cycle steal mode cannot be mixed with the channel in burst mode. 14.4.4 DMA Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation register (DMAOR), and DMA extended resource selectors (DMARS) are set, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) 2. When a transfer request occurs while transfer is enabled, the DMAC transfers one transfer unit of data (depending on the TS0 and TS1 settings). In auto request mode, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented for each transfer. The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfer have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit in CHCR or the DME bit in DMAOR is changed to 0. Figure 14.11 shows a flowchart of this procedure.
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Section 14 Direct Memory Access Controller (DMAC)
Start Initial settings (SAR, DAR, TCR, CHCR, DMAOR, SARB, DARB, TCRB, DMARS)
DE, DME = 1 and TE, AE, NMIF = 0?
No
Yes
*1 *3
Transfer request occurs? Yes
*2
No
*4
Bus mode, DREQ detection system, transfer request mode
Transfer (1 transfer unit); TCR - 1 TCR, SAR, and DAR updated Reload mode: TCR[7:0] TCRBL
*6
Reload mode?
Yes No
TCR[7:0] = 0?
No
Yes
SARB/DARB load *5 TCR[23:16] TCR[7:0] load *6
TCR = 0?
No
Yes
TE = 1
No
TCR = TCRB/2?
Yes
DEI interrupt request (IE = 1)
Yes
HE = 1, DEI interrupt request (HIE = 1)
Repeat mode?
NMIF = 1 or AE = 1 or DE = 0 or DME = 0?
No
No
NMIF = 1 or AE =1 or DE = 0 or DME = 0?
SARB/DARB load TCRB TCR load
Yes
*5
Yes
No
HIE = 0 or HE = 1?
Yes
No
Normal end
Transfer end
Notes: 1. In repeat mode, a transfer request is acceptted with TE =1 when HIE = 1 and HE = 0 (half end interrupt is enable and clear the HE to 0 after HE is set to 1). 2. In auto-request mode, transfer starts when bits NMIF, AE, and TE are all 0 or bits TE and HIE are 1 and HE is 0 (in repeat mode), and bits DE and DME are set to 1. 3. DREQ is level detection (external requesrt) in burst mode or cycle-steral mode. 4. DREQ is edge detection (external request) or auto request in burst mode. 5. Loading to SAR and DAR differs according to the operating conditions in each mode.
Figure 14.11 DMA Transfer Flowchart
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Section 14 Direct Memory Access Controller (DMAC)
14.4.5
Repeat Mode Transfer
In a repeat mode transfer, a DMA transfer is repeated without specifying the transfer settings every time before executing a transfer. Using a repeat mode transfer with the half end function allows a double buffer transfer executed virtually. Following processing can be executed effectively by using a repeat mode transfer. As an example, operation of receiving voice data from the VOICE CODEC and compressing it is explained. In the following example, processing of compressing 40-word voice data every data reception is explained. In this case, it is assumed that voice data is received by means of SIOF. DMAC settings Set address of the SIOF receive data register in SAR Set address of an internal memory data store area in DAR Set TCR to H'50 (80 times) Satisfy the following settings of CHCR Bits RPT[2:0] = B'010: Repeat mode (use DAR as a repeat area) Bit HIE = B'1: TCR/2 interrupt generated Bits DM[1:0] = B'01: DAR incremented Bits SM[1:0] = B'00: SAR fixed Bit IE = B'1: Interrupt enabled Bit DE = B'1: DMA transfer enabled * Set such as bits TB and TS[2:0] according to use conditions * Set bits CMS[1:0] and PR[1:0] in DMAOR according to use conditions and set the DME bit to B'1 2. Voice data is received and then transferred by SIOF/DMAC 3. TCR is decreased to half of its initial value and an interrupt is generated After reading CHCR to confirm that the HE bit is set to 1 by an interrupt processing, clear the HE bit to 0 and compress 40-word voice data from the address set in DAR. 4. TCR is cleared to 0 and an interrupt is generated After reading CHCR to confirm that the TE bit is set to 1 by an interrupt processing, clear the TE bit to 0 and compress 40-word voice data from the address set in DAR + 40. After this operation, the value of DARB is copied to DAR in DMAC and initialized, and the value of TCRB is copied to TCR and initialized to 80. 1. * * * *
Rev. 1.00 Oct. 01, 2007 Page 608 of 1956 REJ09B0256-0100
Section 14 Direct Memory Access Controller (DMAC)
5. Hereafter, steps 2 and 4 are repeated until the DME or DE bit is cleared to 0, or an NMI interrupt is generated. Note that if the HE bit is not cleared in the procedure 3 or if the TE bit is not cleared in the procedure 4, then the transfer is stopped according to the condition of both the HE and the TE bits are set to 1. As explained above, a repeat mode transfer enables sequential voice compression by changing buffer for storing data received consequentially and a data buffer for processing signals alternately. 14.4.6 Reload Mode Transfer
In a reload mode transfer, according to the settings of bits RPT[2:0] in CHCR, the value set in SARB/DARB is set to SAR/DAR and the value of bits TCRB[23:16] is set in bits TCRB[7:0] at each transfer set in the bits TCRB[7:0], and the transfer is repeated until TCR becomes 0 without specifying the transfer settings again. A reload mode transfer is effective when repeating data transfer with specific area. Figure 14.12 shows the operation of reload mode transfer.
DMAC
Bits RPT[2:0]
CHCR
Transfer request
TCR
SHwy bus
Transfer counter TCRB Reload counter Reload signal Reload controller SARB/DARB SAR/DAR
Figure 14.12 Reload Mode Transfer When a reload mode transfer is executed, TCRB is used as a reload counter. Set TCRB according to section 14.3.6, DMA Transfer Count Registers (TCRB0 to TCRB3).
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Section 14 Direct Memory Access Controller (DMAC)
14.4.7
DREQ Pin Sampling Timing
Figures 14.13 to 14.16 show the sample timing of the DREQ input in each bus mode, respectively.
CKOUT Bus cycle DREQ (Rising edge) DRAK (Low-active) DACK (Low-active) : Non-sensitive period Acceptance started
CPU
DMAC
CPU
1st acceptance
2nd acceptance
Figure 14.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
CLKOUT Bus cycle DREQ (Overrun 0, Low-level) DRAK (Low-active) DACK (Low-active) Acceptance started CPU DMAC CPU
1st acceptance
2nd acceptance
CLKOUT Bus cycle DREQ (Overrun 1, Low-level) DRAK (Low-active) DACK (Low-active) Acceptance started : Non-sensitive period CPU DMAC CPU
1st acceptance
2nd acceptance
Figure 14.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
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Section 14 Direct Memory Access Controller (DMAC)
CLKOUT
Bus cycle DREQ (Rising edge) DRAK (Low-active) DACK (Low-active) : Non-sensitive period
CPU
Burst acceptance
DMAC
DMAC
Figure 14.15 Example of DREQ Input Detection in Burst Mode Edge Detection
CLKOUT Bus cycle DREQ (Overrun 0, Low-level) DRAK (Low-active) DACK (Low-active) CPU DMAC
1st acceptance
2nd acceptance
Acceptance started
CLKOUT Bus cycle DREQ (Overrun 1, Low-level) DRAK (Low-active) DACK (Low-active) : Non-sensitive period CPU DMAC DMAC
1st acceptance
2nd acceptance
3rd acceptance
Acceptance started
Acceptance started
Figure 14.16 Example of DREQ Input Detection in Burst Mode Level Detection
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Section 14 Direct Memory Access Controller (DMAC)
Figure 14.17 shows the timing of the TEND output.
CLKOUT Last DMA transfer Bus cycle DMAC CPU DMAC CPU CPU
DREQ DACK (Active-high) TEND (Active-high)
Figure 14.17 DMA Transfer End Signal (Cycle Steal Mode Level Detection) Note that the DACK output and TEND output are divided to align the data when an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external device is accessed in word units. This example is shown in figure 14.18.
Rev. 1.00 Oct. 01, 2007 Page 612 of 1956 REJ09B0256-0100
Section 14 Direct Memory Access Controller (DMAC)
T1
T2
Taw
T1
T2
CLKOUT
Address
CS
RD
Data
WEn
DACKn (Active-low) TENDn (Active-low)
WAIT
Note: TEND is asserted during the last transfer unit of the DMA transfer. When the transfer unit is divided into several bus cycles and CS is negated between bus cycles, TEND is also divided.
Figure 14.18 Example of BSC Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
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Section 14 Direct Memory Access Controller (DMAC)
14.5
Usage Notes
Pay attentions to the following notes when the DMAC is used. 14.5.1 Module Stop
While DMAC is in operation, modules should not be stopped by setting MSTPCR (transition to the module standby state). When modules are stopped, transfer contents cannot be guaranteed. 14.5.2 Address Error
When a DMA address error is occurred, after execute the following procedure, and then start a transfer. 1. Dummy read for the below listed registers. BCR (LBSC) PCIECR (PCIC) MIM (DDRIF) INTCB3 (INTC) 2. Issue the SYNCO instruction. 3. Set registers of all channels again. If the AE bit in DMAOR is set to 1, channels 0 to 5 should be set again. 14.5.3 Notes on Burst Mode Transfer
During a burst mode transfer, following operation should not be executed until the transfer of corresponding channel has completed. * Frequency should not be changed. * Transition to sleep mode should not be made.
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Section 14 Direct Memory Access Controller (DMAC)
14.5.4
DACK and TEND Output Divisions
The DACK and TEND output are divided to align the data unit like the CSn output when a DMA transfer unit is divided with multiple bus cycles, for example when an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external device is accessed in word units, and the CSn output is negated between these bus cycles. 14.5.5 CS Output Settings and Transfer Size Larger than External Bus Width
When one DMA transfer is performed by multiple bus cycles*1, the CSn output should be set not to negate between bus cycles*2. For detail of settings, refer to tables 11.9 to 11.14. If set the CSn output is negated between bus cycles, the DREQ signal is not sampled correctly and malfunction may occur. Notes: 1. When a DMA transfer is performed with larger transfer size than the bus width. For example, performing the 16-/32-byte transfer to the 8-/16-/32-bit bus width LBSC space, longword (32-bit) transfer to the 8-/16-bit bus width LBSC space, or word (16bit) transfer to the 8-bit bus width LBSC space. Note that except for a 32-bit access to the MPX interface. This access generates only one bus cycle (burst). 2. When the CSn output is negated between bus cycles, then the DACK output is also negated between bus cycles (DACK output is also divided). 14.5.6 DACK and TEND Assertion and DREQ Sampling
The DACK and TEND signals may be asserted ceaselessly during two or more times DMA transfer when the DREQ level detection with overrun 1 and the DREQ edge detection. In this case, the DMA transfer is suspended and do not perform correctly, to avoid this insert one or more idle cycle between the DMA transfer. The transfer source is the LBSC space and the DACK and TEND are output during the read cycle: (1) Set B'001 to B'111 (i.e., other than 000) to the IWRRD bits in CSnBCR (2) Set B'001 to B'111 (i.e., other than 000) to the IWRRS bits in CSnBCR
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Section 14 Direct Memory Access Controller (DMAC)
The transfer destination is the LBSC space and the DACK and TEND are output during the write cycle: (1) Set B'001 to B'111 (i.e., other than 000) to the IWW bits in CSnBCR
Note: * The transfer source is the LBSC space and the DACK is output during the read cycle or the transfer destination is the LBSC space and the DACK is output during the write cycle. And then specifies no idle cycle (CSnBCR.IWRRD, IWRRS, IWW are cleared to B'000). Note that the case that both the transfer source and the transfer destination are the LBSC spaces, does not apply this. Tables 14.12 to 14.15 show the number of the bus cycles generated in each DMA transfer and the register settings for the LBSC space. With these settings, CSn is not negated even if multiple bus cycles are generated. Note that, in the following settings, when either the transfer source or the transfer destination is the LBSC space, to avoid the DACK is asserted ceaselessly during between the two or more times DMA transfer, set B'001 to B'111 to the IWRRD, IWRRS or IWW bits in CSnBCR. In this setting, if the 16-byte DMA transfer is performed, multiple bus cycles are generated and the CSn is negated between bus cycles, the DREQ signal is not sampled correctly and malfunction may occur.
Rev. 1.00 Oct. 01, 2007 Page 616 of 1956 REJ09B0256-0100
Section 14 Direct Memory Access Controller (DMAC)
Table 14.12 Register Setting for SRAM, Burst ROM, Byte Control SRAM Interface.
Register Setting of CSn is not negated Bus Width [bit] 8 DMA Transfer Access Size Byte Word Longword 16-Byte 32-Byte 16 Byte Word Longword 16-Byte 32-Byte 32 Byte Word Longword 16-Byte 32-Byte Bus Cycle Number 1 2 4 16 32 1 1 2 8 16 1 1 1 4 8 CSnBCR.IWRRD, IWRRS or IWW Any Any Any B'000 Any Any Any Any B'000 Any Any Any Any B'000 Any CSnWCR.ADS and ADH Any B'000 B'000 B'000 B'000 Any Any B'000 B'000 B'000 Any Any Any B'000 B'000
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Section 14 Direct Memory Access Controller (DMAC)
Table 14.13 Register Setting for PCMCIA Interface
Bus Width [bit] 8 DMA Transfer Access Size Byte Word Longword 16-Byte 32-Byte 16 Byte Word Longword 16-Byte 32-Byte Bus Cycle Number 1 2 4 16 32 1 1 2 8 16 Register Setting of CSn is not negated CSnWCR.ADS and ADH Any Any Any B'000 Any Any Any Any B'000 Any
Table 14.14 Register Setting for MPX Interface (Read Access)
Bus Width [bit] 32 DMA Transfer Access Size Byte Word Longword 16-Byte 32-Byte Bus Cycle Number 1 1 1 4 1 Register Setting of CSn is not negated CSnWCR.ADS and ADH Any Any Any Impossible (Negated) Any
Table 14 15 Register Settings for MPX Interface (Write Access)
Bus Width [bit] 32 DMA Transfer Access Size Byte Word Longword 16-Byte 32-Byte Bus Cycle Number 1 1 1 4 1 Register Setting of CSn is not negated CSnBCR.IWW Any Any Any B'000 Any CSnWCR.IW[1:0] Any Any Any B'11 to B'01 Any
Rev. 1.00 Oct. 01, 2007 Page 618 of 1956 REJ09B0256-0100
Section 14 Direct Memory Access Controller (DMAC)
14.5.7
DMA Transfer to DMAC Prohibited
Do not perform DMA transfer with the DMAC register specified as the transfer source or transfer destination. 14.5.8 NMI Interrupt
When an NMI interrupt occurs, the DMA transfer is stopped. After returning from the NMI interrupt routine, set all channels again, and then restart the DMA transfer.
Rev. 1.00 Oct. 01, 2007 Page 619 of 1956 REJ09B0256-0100
Section 14 Direct Memory Access Controller (DMAC)
Rev. 1.00 Oct. 01, 2007 Page 620 of 1956 REJ09B0256-0100
Section 15 External CPU Interface (EXCPU)
Section 15 External CPU Interface (EXCPU)
The DDR-SDRAM space in this LSI and internal registers of this LSI can be accessed by a CPU externally connected to the LSI (hereinafter, simply referred to as "external CPU"). Access by an external CPU is implemented using the MPX protocol.
15.1
Features
* Control of access from an external CPU An external CPU is able to access the DDR-SDRAM space and internal registers of this LSI. The MPX protocol is used for access from an external CPU. The SH7750 Group and the SH7751 Group can be connected as the external CPU via the buses of the SH7750 Group and the SH7751 Group. Figure 15.1 shows a block diagram of the EXCPU.
External CPU interface (EXCPU)
SuperHyway(SHwy) bus
SuperHyway bus interface controller
External CPU interface controller
EX_CS0 EX_CS1 EX_RDWR EX_FRAME EX_AD31 to EX_AD0
Registers
EX_SIZE2 to EX_SIZE0 EX_RDY EX_INT
Figure 15.1 EXCPU Block Diagram
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Section 15 External CPU Interface (EXCPU)
15.2
Input/Output Pins
Table 15.1 shows the pin configuration of the EXCPU. Table 15.1 Pin Configuration
Pin Name EX_CS0 EX_CS1 EX_BS EX_FRAME EX_RDWR EX_SIZE2 to EX_SIZE0 Symbol Chip select 0 Chip select 1 Bus cycle start Access cycle Read/write Access size I/O Input Input Input Input Input Input Description Indicates access to the DDR-SDRAM space Indicates access to an internal register of this LSI Indicates an address phase Indicates an access cycle period Indicates whether it is data write or read Indicates the access size Note: These pins are used in the SH7750 Group. In the SH7751 Group, pins D31 to D29 act as access size signals. Address/data Input/ output During an address phase, signals on EX_AD25 to EX_AD0 are input as an address During a data phase, signals on EX_AD25 to EX_AD0 are input as data EX_RDY EX_INT MD10 Ready External CPU interrupt Mode control Output Output Input Wait state request signal Interrupt signal External CPU connection select
EX_AD0 EX_AD31
Rev. 1.00 Oct. 01, 2007 Page 622 of 1956 REJ09B0256-0100
Section 15 External CPU Interface (EXCPU)
15.3
Register Descriptions
Table 15.2 shows the EXCPU register configuration. Table 15.3 shows the register states in each operating mode. Table 15.2 Register Configuration
Register Name External CPU control register External CPU memory space select register External CPU output interrupt control register Abbreviation EXCCTRL R/W R/W Area P4 Address H'FE40 000C H'FE40 0010 H'FE40 0014 Area 7 Address H'1E40 000C H'1E40 0010 H'1E40 0014 Access Size 32 32 32
EXCMSETR R/W EXCINOR R/W
Table 15.3 Register States in Each Operating Mode
Register Name External CPU control register External CPU memory space select register External CPU output interrupt control register Abbreviation EXCCTRL EXCMSETR EXCINOR Power-On Reset Manual Reset Sleep Standby Retained Retained Retained
H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained H'0000 0000 H'0000 0000 Retained
Rev. 1.00 Oct. 01, 2007 Page 623 of 1956 REJ09B0256-0100
Section 15 External CPU Interface (EXCPU)
15.3.1
External CPU Control Register (EXCCTRL)
EXCCTRL indicates whether an external CPU is connected and sets the type of the external CPU.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R 0
EXC SEL
15
-
0 R
14
-
0 R
13
-
0 R
-
12
11
-
0 R
10
-
0 R
-
0 R
9
-
0 R
8
-
0 R
7
-
0 R
6
-
0 R
5
-
0 R
4
-
0 R
3
-
0 R
2
1
EXC CD
Initial value: R/W:
0 R
R
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 2
1
EXCMD
Undefined* R
External CPU Connection Indicator Indicates the state of the MD10 pin. 0: External CPU is not connected 1: External CPU is connected
0
EXCSEL
0
R/W
External CPU Type Selects the type of the CPU to be connected 0: SH7751 Group 1: SH7750 Group
Note: The initial value depends on the state of the MD10 pin.
Rev. 1.00 Oct. 01, 2007 Page 624 of 1956 REJ09B0256-0100
Section 15 External CPU Interface (EXCPU)
15.3.2
External CPU Memory Space Select Register (EXCMSETR)
EXCMSETR sets the base address used when the internal memory space of this LSI is accessed by the external CPU.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
Initial value: R/W: Bit:
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
Initial value: R/W:
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R 0 R/W
EXCMSET[3:0] 0 R/W 0 R/W 0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 4
3 to 0
EXCMSET 0000
R/W
Internal Memory Space Base Address These bits set the base address of the memory space used for access to the internal memory by the external CPU. The address of the memory space to be accessed is comprised as follows: 31st and 30th bits: Fixed at B'01 29 to 26th bits: EXCMSET[3:0] 25 to 0th bits: Access address from the external CPU The address range of the memory space accessible to the external CPU is from H'4000 0000 to H'7FFF FFFF.
Rev. 1.00 Oct. 01, 2007 Page 625 of 1956 REJ09B0256-0100
Section 15 External CPU Interface (EXCPU)
15.3.3
External CPU Interrupt Output Control Register (EXCINOR)
EXCINOR is used to generate an interrupt to the external CPU from this LSI.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
Initial value: R/W: Bit:
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXC INO
-
Initial value: R/W:
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 1
0
EXCINI
0
R/W
Notification of Interrupt to External CPU 1: Asserts the EX_INT pin to generate an interrupt to the external CPU 0: Negates the EX_INT pin to clear an interrupt to the external CPU
Rev. 1.00 Oct. 01, 2007 Page 626 of 1956 REJ09B0256-0100
Section 15 External CPU Interface (EXCPU)
15.4
Operation
With this LSI, a CPU externally connected to the LSI (an external CPU) is allowed to access the DDR-SDRAM space or internal registers of the LSI by using the MPX protocol. The external CPU becomes ready to access the space in this LSI after this sequence: an access request (BREQ) from the external CPU is accepted by the LBSC, the local bus is released, and an access acknowledgement (BACK) is returned to the external CPU. The EXCPU determines whether the access is to the DDR-SDRAM space or to an internal register according to the CS signals (EX_CS0, EX_CS1) from the external CPU and performs processing for the respective access. In the case of access to the DDR-SDRAM space, the EXCPU implements access to the DDRSDRAM space in this LSI by converting the signal from the external CPU from the MPX protocol to the SuperHyway bus protocol. In this process, data alignment conversion is performed with the same endian as this LSI according to the access size from the external CPU. (1) Space Accessible to the External CPU
The DDR-SDRAM space and internal registers of this LSI are accessible to the external CPU. The space to be accessed is selected as shown below using the CS signals. * EX_CS0: * EX_CS1: DDR-SDRAM space (64 Mbytes) Internal registers of this LSI
For DDR-SDRAM space access, however, the size of the space that can be accessed by the external CPU is 64 Mbytes while the entire DDR-SDRAM space in this LSI is 512 Mbytes. So, access to the entire DDR-SDRAM space from the external CPU is enabled by the window method. To access the entire DDR-SDRAM space in this LSI, first designate a 64-Mbyte access space by the EXCMSETR register of the EXCPU, and then create an access to the DDR-SDRAM space.
Rev. 1.00 Oct. 01, 2007 Page 627 of 1956 REJ09B0256-0100
Section 15 External CPU Interface (EXCPU)
(2)
Data Alignment Conversion for the External CPU
For the external CPU, the EXCPU performs data alignment conversion with the same endian as this LSI. This conversion supports both big endian, where the upper byte is placed at the smaller address, and little endian, where the lower byte is placed at the smaller address. Endian selection is done at a power-on reset by means of an external pin. Table 15.4 Access and Data Alignment for Little Endian
EX_AD31 to EX_AD24 Byte access to address 0 Byte access to address 1 Byte access to address 2 Byte access to address 3 Byte access to address 4 Byte access to address 5 Byte access to address 6 Byte access to address 7 Word access to address 0 Word access to address 2 Word access to address 4 Word access to address 6 Longword access to address 0 Longword access to address 4 Data 15 to data 8 Data 31 to data 24 Data 31 to data 24 Data 7 to data 0 Data 23 to data 16 Data 23 to data 16 Data 15 to data 8 Data 15 to data 8 Data 7 to data 0 Data 7 to data 0 Data 15 to data 8 Data 7 to data 0 Data 15 to data 8 Data 7 to data 0 Data 7 to data 0 Data 15 to data 8 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 EX_AD23 to EX_AD16 EX_AD15 to EX_AD8 EX_AD7 to EX_AD0 Data 7 to data 0
Rev. 1.00 Oct. 01, 2007 Page 628 of 1956 REJ09B0256-0100
Section 15 External CPU Interface (EXCPU)
Table 15.5 Access and Data Alignment for Big Endian
EX_AD31 to EX_AD24 Byte access to address 0 Byte access to address 1 Byte access to address 2 Byte access to address 3 Byte access to address 4 Byte access to address 5 Byte access to address 6 Byte access to address 7 Word access to address 0 Word access to address 2 Word access to address 4 Word access to address 6 Longword access to address 0 Longword access to address 4 Data 31 to data 24 Data 31 to data 24 Data 23 to data 16 Data 23 to data 16 Data 15 to data 8 Data 7 to data 0 Data 15 to data 8 Data 15 to data 8 Data 15 to data 8 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 Data 15 to data 8 Data 7 to data 0 Data 15 to data 8 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 Data 7 to data 0 EX_AD23 to EX_AD16 EX_AD15 to EX_AD8 EX_AD7 to EX_AD0
Rev. 1.00 Oct. 01, 2007 Page 629 of 1956 REJ09B0256-0100
Section 15 External CPU Interface (EXCPU)
(3)
Timing Charts of External CPU Access
External CPU access through the EXCPU is done through handshaking of the access request (BREQ) and access acknowledge (BACK) signals. Figures 15.2 and 15.3 show the access timing of the EXCPU and external CPU.
Read access CLKOUT BREQ BACK EX_CS0 EX_BS EX_FRAME EX_RDWR EX_AD [31:0] EX_RDY Write access CLKOUT BREQ BACK EX_CS0 EX_BS EX_FRAME EX_RDWR EX_AD [31:0] EX_RDY Low A0 D0 High A0 D0
Figure 15.2 External CPU Access (Single Access)
Rev. 1.00 Oct. 01, 2007 Page 630 of 1956 REJ09B0256-0100
Section 15 External CPU Interface (EXCPU)
Read access CLKOUT BREQ BACK EX_CS0 EX_BS EX_FRAME
EX_RDWR EX_AD[31:0] High
A0
D0
D1
D5
D6
D7
EX_RDY
Write access CLKOUT BREQ BACK EX_CS0 EX_BS EX_FRAME EX_RDWR EX_AD[31:0] EX_RDY
Low
A0
D0
D1
D6
D7
Figure 15.3 External CPU Access (Burst Access) (4) Configuration of Connection to the External CPU
Figure 15.4 shows the configuration of the connection between the external CPU and this LSI.
Rev. 1.00 Oct. 01, 2007 Page 631 of 1956 REJ09B0256-0100
Section 15 External CPU Interface (EXCPU)
This LSI SH7750/7751 MD10 EXCPU BS BS/EX_BS
CS*
CS2/EX_CS1
CS*
CS1/EX_CS0
RD/FRAME
RD/FRAME/EX_FRAME
RDWR
RDWR/EX_RDWR D31/EX_AD31 to D0/EX_AD0
DATA31 to DATA0
DATA31 to DATA29
A25/EX_SIZE2 to A23/EX_SIZE0
RDY
RDY/EX_RDY
EX_INT
BSREQ BSACK
BREQ BACK
LBSC
Figure 15.4 Configuration of Connection with External CPU
Rev. 1.00 Oct. 01, 2007 Page 632 of 1956 REJ09B0256-0100
Section 16 Clock Pulse Generator (CPG)
Section 16 Clock Pulse Generator (CPG)
The CPG generates clocks provided to the on-chip peripheral modules and external bus interface of this LSI, and controls the power-down mode function. The CPG consists of an oscillator, PLL circuits, frequency dividers, and control circuits.
16.1
Features
* Clocks used for LSI internal operation Generates the CPU clock (Ick) used by the CPU, FPU, cache, and TLB, SHwy clock (SHck) used by the SuperHyway, and peripheral clocks (Pck0, Pck1) supplied to the peripheral modules. * Clocks supplied to outside modules Generates the bus clock (Bck) used by the external bus interface and the memory clocks (DDRck) used by the DDR interface. * Clock modes Either a crystal resonator or an externally input clock can be selected as the CPG clock input. The combination of the division ratios for the CPU clock, SHwy clock, bus clock, peripheral clock, and DDR-memory clock after a power-on reset can be selected from two clock operating modes. * Power-down mode control The clock can be stopped for sleep mode and software standby mode, and specific modules can be stopped in module standby mode.
Rev. 1.00 Oct. 01, 2007 Page 633 of 1956 REJ09B0256-0100
Section 16 Clock Pulse Generator (CPG)
A block diagram of the CPG is shown in figure 16.1.
PLL cicuit 3 x
Divider 2 1/4
DDR clock DDRck0 DDRck90 DDRck180 DDRck270
PLL circuit 2 x1
CLKOUT
Divider 1 XTAL
Crystal oscillator
Bus clock Bck CPU clock Ick SHwy clock SHck Pwripheral clock Pck0 Pck1
PLL circuit 1 16
EXTAL
1/4 1/6 1/8 1/12 1/16 1/24
MD8
MD2
MD1
MD0
Clock frequency controller
Clock controller
FRQCR
STBCR
PLLCR
MSTPCR
Bus interface
Peripheral bus [Legend] FRQCR STBCR MSTPCR PLLCR
Frequency control register Standby control register Module stop register PLL control register
Note : Refer to section 18, Power-Down Mode, for detaiis on STBCR and MSTPCR.
Figure 16.1 Block Diagram of CPG
Rev. 1.00 Oct. 01, 2007 Page 634 of 1956 REJ09B0256-0100
Section 16 Clock Pulse Generator (CPG)
The functions of the blocks in the CPG are as follows. (1) PLL Circuit 1
PLL circuit 1 multiples the frequency of the crystal oscillator or the clock input from the EXTAL pin by the ratio of x16. The multiplication ratio is selected by the combination of mode control pins MD0, MD1, and MD2. (2) PLL Circuit 2
PLL circuit 2 aligns the phases of the bus clock (Bck) and the clock signal output from the CLKOUT pin that is used by the external peripheral interface. (3) Crystal Oscillator
The crystal oscillator is a clock pulse generator used when a crystal resonator is connected to the XTAL or EXTAL pin. The crystal oscillator can be enabled by the MD8 pin setting. (4) Divider 1
Divider 1 generates the CPU clock (Ick), SHwy clock (SHck), peripheral module clocks (Pck0, Pck1), and bus clock (Bck). The division ratio is selected by the combination of mode control pins MD0, MD1, and MD2. (5) Frequency Control Register (FRQCR)
The frequency control register is a read-only register that depends on the combination of mode control pins MD0, MD1, and MD2. (6) PLL Circuit 3
PLL circuit 3 multiples the frequency of the SHwy clock (SHck) by the ratio of x4. (7) Divider 2
Divider 2 generates the DDR-memory clocks (DDRck0, DDRck90, DDRck180, and DDRck270). (8) PLL Control Register (PLLCR)
The PLL control register has control bits assigned for enabling or disabling the CLKOUT pin output.
Rev. 1.00 Oct. 01, 2007 Page 635 of 1956 REJ09B0256-0100
Section 16 Clock Pulse Generator (CPG)
(9)
Module Stop Registers 0, 1(MSTPCR0 and MSTPCR1)
The module stop registers have control bits for running/stopping the individual peripheral modules. (10) Standby Control Register (STBCR) The standby control register has bits for controlling the power-down modes.
16.2
Input/Output Pins
Table 16.1 lists the CPG pin configuration. Table 16.1 Pin Configuration and Functions of CPG
Pin Name MD0 MD1 MD2 MD8 Function I/O Description Sets the clock operating mode after a power-on reset.
Mode control pins 0, Input 1, 2 Input (Clock operating Input mode) Mode control pin 8 (Clock input mode) Input
Selects the use of the crystal resonator. MD8 = low: External clock is input from the EXTAL pin. MD8 = high: Crystal resonator is connected to the EXTAL and XTAL pins.
XTAL EXTAL CLKOUT Note:
Clock pins
Output Input Output
A crystal resonator is connected. A crystal resonator is connected, or an external clock is input. Used as an external bus clock output pin.
For the guaranteed AC timing of the CLKOUT pin, refer to the section on electrical characteristics. Pay attention to the relationship between the input frequency of the crystal oscillator and the multiplication ratio.
Rev. 1.00 Oct. 01, 2007 Page 636 of 1956 REJ09B0256-0100
Section 16 Clock Pulse Generator (CPG)
16.3
Clock Operating Mode
Table 16.2 shows the relationship between the mode control pin (MD0, MD1, and MD2) combinations and the clock operating mode after a power-on reset. Table 16.2 Clock Operating Modes
Clock operating mode 0 External pin combination*1 EXTAL PLL PLL PLL frequency 2 3 (MHz) Ick
Clock generated by CPG
Initial value
MD2 MD1 MD0 1 0 0 0 ON
SHck Bck Pck0 Pck1 DDRck of FRQCR 4 2 2 1 4 H'1013 0035
ON OFF 25 to 33.1 Frequency 8 ratio*2 Max. frequency
266 133
66.6 66.6
33.3
133
Notes: 1. Mode pin (MD0, MD1, and MD2) combinations other than above are prohibited. 2. The ratio of the frequency of each clock to that of the crystal oscillator or the clock input from the EXTAL pin.
Rev. 1.00 Oct. 01, 2007 Page 637 of 1956 REJ09B0256-0100
Section 16 Clock Pulse Generator (CPG)
16.4
Register Descriptions
Table 16.3 shows the CPG register configuration. Table 16.4 shows the register states in each operating mode. Table 16.3 Register Configuration
Register Name Frequency control register PLL control register Abbreviation FRQCR PLLCR R/W R R/W Area P4 Address H'FFC8 0000 H'FFC8 0024 Area 7 Address H'1FC8 0000 H'1FC8 0024 Access Size 32 32
Table 16.4 Register States in Each Operating Mode
Register Name Frequency control register PLL control register Abbrevia- Power-On tion Reset FRQCR PLLCR Manual Reset Standby Retained Retained Sleep Retained Retained
H'1013 0035 Retained H'0000 0001 Retained
Rev. 1.00 Oct. 01, 2007 Page 638 of 1956 REJ09B0256-0100
Section 16 Clock Pulse Generator (CPG)
16.4.1
Frequency Control Register (FRQCR)
FRQCR is a 32-bit read-only register used to confirm the division ratios for the CPU clock (Ick), SHwy clock (SHck), peripheral clocks (Pck0, Pck1), and the bus clock (Bck) after a power-on reset. For the frequency ratios, refer to table 16.2, Clock Operating Modes. This register can be accessed only in longwords. Operation cannot be guaranteed if this register is written to. FRQCR is only initialized by a power-on reset caused by the PRESET pin or watchdog timer overflow.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 1 R/W 12 0 R/W 27 0 R/W 11 0 R/W 26 0 R/W 10 0 R/W 25 0 R/W 9 0 R/W 24 0 R/W 8 0 R/W 23 0 R 7 0 R 0 R 0 R 6 22 21 CFC[2:0] 0 R 5 P0FC[2:0] 1 R 1 R/W 1 R/W 4 20 19 0 R/W 3 0 R/W 1 R/W 0 R/W 2 18 17 BFC[2:0] 1 R/W 1 P1FC[2:0] 0 R/W 1 R/W 1 R/W 0 16
Bit 31 to 28 27 to 23 22 to 20
Bit Name -- -- CFC[2:0]
Initial Value 0001 All 0 001
R/W R R R
Description Reserved These bits are read as B'0001. Reserved These bits are always read as all 0. CPU Clock (Ick) and SHwy Clock (SHck) Frequency Division Ratios CFC[2:0] 001: Ick x1/2 SHck x1/4
19 18 to 16 15 to 7 6 to 4
-- BFC[2:0] -- P0FC[2:0]
0 011 All 0 011
R R R R
Reserved This bit is always read as 0. Bus Clock 0 (Bck) Frequency Division Ratio 011: x1/8 Reserved These bits are always read as all 0. Peripheral Clock 0 (Pck0) Frequency Division Ratio 011: x1/8
Rev. 1.00 Oct. 01, 2007 Page 639 of 1956 REJ09B0256-0100
Section 16 Clock Pulse Generator (CPG)
Bit 3 2 to 0
Bit Name --
Initial Value 0
R/W R R
Description Reserved This bit is always read as 0. Peripheral Clock 1 (Pck1) Frequency Division Ratio 101: x1/16
P1FC[2:0] 101
Rev. 1.00 Oct. 01, 2007 Page 640 of 1956 REJ09B0256-0100
Section 16 Clock Pulse Generator (CPG)
16.4.2
PLL Control Register (PLLCR)
PLLCR is a 32-bit readable/writable register that enables or disables clock output from the CLKOUT pin. PLLCR can be accessed only in longwords.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
Initial value: R/W: Bit: 0 R 15
-
0 R 14
-
0 R 13
-
0 R 12
-
0 R 11
-
0 R 10
-
0 R 9
-
0 R 8
-
0 R 7
-
0 R 6
-
0 R 5
-
0 R 4
-
0 R 3
-
0 R 2
-
0 R 1
-
0 R 0
-
Initial value: R/W:
0 R
-
1 R
-
1 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
CKOFF CKONE
0 R/W
1 R/W
Bit 31 to 15
Initial Bit Name Value -- All 0
R/W R
Description Reserved The write value should be the same as the initial values.
14, 13
--
All 1
R
Reserved The write value should be the same as the initial values.
12 to 2
--
All 0
R
Reserved The write value should be the same as the initial values.
1
CKOFF
0
R/W
CLKOUT Output Stop 0: Clock is output from the CLKOUT pin. 1: Clock is not output from the CLKOUT pin. (The pin level is low.)
0
CKONE
1
R/W
Clock Output Enable Selects whether to output clock from the CLKOUT pin or tie the CLKOUT pin to a low level during software standby mode. 0: Tied to a low level 1: Clock is output
Note:
*
Depends on the clock operating mode that is selected by the MD0 to MD2 pin settings.
Rev. 1.00 Oct. 01, 2007 Page 641 of 1956 REJ09B0256-0100
Section 16 Clock Pulse Generator (CPG)
16.5
(1)
Notes on Board Design
Notes on Using Crystal Resonator
Place the crystal resonator and capacitors as close as possible to the EXTAL and XTAL pins. Do not allow any signal lines to cross the EXTAL or XTAL line to prevent induction from interfering with correct oscillation.
Crystal resonator
CL1
CL2
Recommended values CL1 = CL2 = 0-33 pF R=0
Avoid crossing signal lines
R
EXTAL SH7763
XTAL
Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer.
Figure 16.2 Notes on Using Crystal Resonator (2) Notes on Inputting External Clock via EXTAL Pin
Make no connection to the XTAL pin.
Rev. 1.00 Oct. 01, 2007 Page 642 of 1956 REJ09B0256-0100
Section 16 Clock Pulse Generator (CPG)
(3)
Notes on Using PLL or DLL Oscillator Circuit
Separate VDD-PLL and VSS-PLL from the other VDD and VSS lines at the board power supply source, and insert resistors RCB and bypass capacitors CPB near the pins for noise filtering. VDD-DLL and VSS-DLL should be set to the same level as the VDD and VSS levels, respectively.
RCB1 VDD-PLL1 CPB11 0.1F VSS-PLL1
RCB2
CPB12 1F
4.7
Recommended values: RCB1 = RCB2 = RCB3 = 4.7 CPB11 = CPB21 = CPB31 = 0.1F CPB12 = CPB22 = CPB32 = 1F
VDD-PLL2
CPB21 CPB22
1F
4.7
SH7763
0.1F
VSS-PLL2
RCB3
VDD-PLL3
CPB31 0.1F CPB32
1F
4.7
1.25V
VSS-PLL3
Figure 16.3 Notes on Using PLL or DLL Oscillator Circuit
Rev. 1.00 Oct. 01, 2007 Page 643 of 1956 REJ09B0256-0100
Section 16 Clock Pulse Generator (CPG)
Rev. 1.00 Oct. 01, 2007 Page 644 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
Section 17 Watchdog Timer and Reset (WDT)
The reset and watchdog timer (WDT) control circuit comprises the reset control unit and WDT control unit which control the power-on reset sequence and a reset for on-chip peripheral modules and external devices. The WDT is a one-channel timer which can be used as the watchdog timer or interval timer.
17.1
Features
* WDT monitors a system crash using a timer counting at specified intervals. * WDT supports the watchdog timer mode and the interval timer mode. * WDT generates an internal reset when a WDT overflow occurs in watchdog timer mode. A power-on reset or a manual reset can be selectable. * WDT generates the interval timer interrupt when counter overflow occurs in interval timer mode. * The maximum time until the watchdog timer overflows is approximately 21 seconds (when the peripheral clock Pck0 is 50 MHz). * Writing to WDT-related registers is not normally allowed. A specified code in the upper bits of write data enables writing to the registers.
Rev. 1.00 Oct. 01, 2007 Page 645 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
Figure 17.1 is a system block diagram.
Watchdog timer and Reset
PRESET
MRESET
Reset control circuit
Internal reset request
CPG
2 STATUS[1:0]
Interrupt control circuit
INTC
Internal reset request
WDTCSR
WDTCNT
Comparator
WDTBCNT
Comparator
Peripheral clock
WDTST
Count-up signal
[Legend] WDTBCNT: WDTBST: WDTCNT: WDTCSR: WDTST:
WDTBST
Watchdog timer base counter Watchdog timer base stop time register Watchdog timer counter Watchdog timer control/status register Watchdog timer stop time register
Figure 17.1 System Block Diagram
Rev. 1.00 Oct. 01, 2007 Page 646 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
17.2
Input/Output Pins
Table 17.1 shows the pin configuration of the reset control unit. Table 17.1 Pin Configuration
Pin name PRESET MRESET STATUS1* STATUS0* Function Power-on reset input Manual reset input Processing state 1 Processing state 0 I/O Input Input Output Description Power-on reset occurs at low-level Manual reset occurs at low-level Indicate the processor's operating status STATUS1 High High Low Low Note: * These pins are multiplexed with other function pins. STATUS0 High Low High Low Operating Status Reset Sleep mode Standby mode Normal operation
Rev. 1.00 Oct. 01, 2007 Page 647 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
17.3
Register Descriptions
Table 17.2 shows the registers of the reset and watchdog timer. Table 17.3 shows the register state in each operating mode. Table 17.2 Register Configuration
Register Name Watchdog timer stop time register Watchdog timer control/status register Watchdog timer base stop time register Watchdog timer counter Watchdog timer base counter Abbreviation R/W WDTST WDTCSR WDTBST WDTCNT WDTBCNT R/W R/W R/W R R P4 Address H'FFCC 0000 H'FFCC 0004 H'FFCC 0008 H'FFCC 0010 H'FFCC 0018 Area 7 Address H'1FCC 0000 H'1FCC 0004 H'1FCC 0008 H'1FCC 0010 H'1FCC 0018 Access Size 32 32 32 32 32
Table 17.3 Register State in Each Operating Mode
Power-on Power-on Reset by Manual Reset by Abbreviation PRESET Pin WDT/H-UDI Reset WDTST WDTCSR WDTBST WDTCNT WDTBCNT H'0000 0000 Retained H'0000 0000 Retained H'0000 0000 Retained H'0000 0000 Retained H'0000 0000 Retained Retained Retained Retained Retained Retained
Register Name Watchdog timer stop time register Watchdog timer control/status register Watchdog timer base stop time register Watchdog timer counter Watchdog timer base counter
Sleep Retained Retained Retained Retained Retained
Standby Retained Retained Retained Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 648 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
17.3.1
Watchdog Timer Stop Time Register (WDTST)
WDTST is a readable/writable 32-bit register that specifies the time until a watchdog timer overflows. The time until WDTCNT overflows becomes the minimum value when set H'001 to the bits 11 to 0, and the maximum value when set H'000 to the bits 11 to 0. Use a longword access to write to the WDTST, with H'5A in the bits 31 to 24. The reading value of bits 31 to 24 is always H'00.
Bit: 31 30 29 28 27 26 25 24 23 0 R/W 10 0 R/W 9 0 R/W 8 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
(Given code) Initial value: R/W: Bit: 0 R/W 15 Initial value: R/W: 0 R 0 R/W 14 0 R 0 R/W 13 0 R 0 R/W 12 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 11
WDTST 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 31 to 24
Bit Name (Given code)
Initial Value H'00
R/W R/W
Description Reserved (Given code for writing) These bits are always read as H'00. To write to this register, the write value must be H'5A.
23 to 12
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
11 to 0
WDTST
All 0
R/W
Counter value
Rev. 1.00 Oct. 01, 2007 Page 649 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
17.3.2
Watchdog Timer Control/Status Register (WDTCSR)
WDTCSR is a readable/writable 32-bit register that comprises the timer mode-selecting bit and overflow flags. Use a longword access to write to the WDTCSR, with H'A5 in the bits 31 to 24. The reading value of bits 31 to 24 is always H'00.
Bit: 31 30 29 28 27 26 25 24 23 0 R/W 10 0 R 0 R/W 9 0 R 0 R/W 8 0 R 0 R 7
TME
22 0 R 6
21 0 R 5
20 0 R 4
19 0 R 3
18 0 R 2 0 R
17 0 R 1 0 R
16 0 R 0 0 R
(Given code)
Initial value: R/W: Bit:
0 R/W 15
0 R/W 14 0 R
0 R/W 13 0 R
0 R/W 12 0 R
0 R/W 11 0 R
WT/IT RSTS WOVF IOVF
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 24
Bit Name (Given code)
Initial Value H'00
R/W R/W
Description Reserved (Given code for writing) These bits are always read as H'00. To write to this register, the write value must be H'A5.
23 to 8
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
7
TME
0
R/W
Timer Enable Specifies starting and stopping of timer operation. 0: Stops counting up 1: Starts counting up
6
WT/IT
0
R/W
Timer Mode Select Specifies whether the WDT is used as a watchdog timer or interval timer. Up counting may not be performed correctly if this bit is modified while the WDT is running. 0: Interval timer mode 1: Watchdog timer mode
Rev. 1.00 Oct. 01, 2007 Page 650 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
Bit 5
Bit Name RSTS
Initial Value 0
R/W R/W
Description Reset Select Specifies the kind of reset to be performed when WDTCNT overflows in watchdog timer mode. This setting is ignored in interval timer mode. 0: Power-on reset 1: Manual reset
4
WOVF
0
R/W
Watchdog Timer Overflow Flag Indicates that WDTCNT has overflowed in watchdog timer mode. This flag is not set in interval timer mode. 0: An overflow has not occurred 1: An overflow on WDTCNT has occurred
3
IOVF
0
R/W
Interval Timer Overflow Flag Indicates that WDTCNT has overflowed in interval timer mode. This flag is not set in watchdog timer mode. 0: An overflow has not occurred 1: An overflow on WDTCNT has occurred
2 to 0
R
All 0
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 651 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
17.3.3
Watchdog timer Base Stop Time Register (WDTBST)
WDTBST is a readable/writable 32-bit register that clears WDTBCNT. Use a longword access to clear the WDTBCNT, with H'A5 in the bits 31 to 24. The reading value of bits WDTBST is always H'0000 0000.
Bit:
31
30
29
28
27
26
25
24
23
(Given code) Initial value: PCI R/W:
-
0 R
22
-
0 R
21
-
0 R
20
-
0 R
19
-
0 R
18
-
0 R
17
-
0 R
16
-
0
0 R/W
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
R/W
R
Bit:
-
0 R
15
14
-
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
Initial value: PCI R/W:
R
Bit 31 to 24
Bit Name (Given code)
Initial Value R/W
R/W H'00
Description Reserved (Given code for writing) These bits are always read as H'00. To write to this register, the write value must be H'55.
23 to 0
R
All 0
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 652 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
17.3.4
Watchdog Timer Counter (WDTCNT)
WDTCNT is a 32-bit read-only register that comprises 12-bit watchdog timer counter and counts up on the WDTBCNT overflow signal. When WDTCNT overflows, a reset is generated in watchdog timer mode, or an interrupt is generated in interval timer mode. Writing to WDTCNT is invalid.
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 0 R 0 R 0 R 0 R 0 R 27 0 R 11 26 0 R 10 25 0 R 9 24 0 R 8 23 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
WDTCNT 0 R 0 R 0 R 0 R 0 R 0 R 0 R
17.3.5
Watchdog Timer Base Counter (WDTBCNT)
WDTBCNT is a 32-bit read-only register that comprises 18-bit counter and counts up on the peripheral clock (Pck0). When WDTBCNT overflows, WDTCNT is counted up and WDTBCNT is cleared to 0 Writing to WDTCNT is invalid.
Bit: 31 Initial value: R/W:
Bit:
30 0 R
14
29 0 R
13
28 0 R
12
27 0 R
11
26 0 R
10
25 0 R
9
24 0 R
8
23 0 R
7
22 0 R
6
21 0 R
5
20 0 R
4
19
18
17 WDTBCNT
16
0 R
15
0 R
3
0 R
2
0 R
1
0 R
0
WDTBCNT Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Rev. 1.00 Oct. 01, 2007 Page 653 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
17.4
17.4.1
Operation
Reset request
Power-on reset and manual reset are available. These sources are follows. (1) Power-on reset
1. Reset sources * Input low level via PRESET pin. * The WDTCNT overflows when the WT/IT bit in the WDTCSR is 1, and the RSTS bit is 0. * The H-UDI reset occurs (For details, see section 42, User Debugging Interface (H-UDI)). 2. Branch destination address: H'A000 0000 3. Operation in branch Exception code H'000 is set in the EXPEVT register. The VBR and SR registers are initialized, and the program branches to PC =H'A000 0000. By initialization, the VBR register is set to H'0000 0000. In the SR register, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the IMASK3 to IMASK0 bits (interrupt mask level) are set to B'1111. The CPU and the peripheral modules are also initialized. For details, see the register descriptions in each section. When the power is turned on, be sure to input a low level to the PRESET pin. The TRST pin should also be brought low level to initialize the H-UDI.
Power_on_reset() { EXPEVT = H'0000 0000; VBR = H'0000 0000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A000 0000; }
Rev. 1.00 Oct. 01, 2007 Page 654 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
(2) 1. * * *
Manual reset Reset sources Input low level via MRESET pin. When a general exception other than a user break occurs while the BL bit is set to 1 in SR When the WDTCNT overflows while the WT/IT bit and the RSTS bit are set to 1 in WTCSR.
2. Branch destination address: H'A000 0000 3. Operation in branch Exception code H'020 is set in the EXPEVT register. The VBR and SR registers are initialized, and the program branches to PC =H'A000 0000. By initialization, the VBR register is set to H'0000 0000. In the SR register, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the IMASK3 to IMASK0 bits (interrupt mask level) are set to B'1111. The CPU and the peripheral modules are also initialized. For details, see the register descriptions in each section.
Manual_reset() { EXPEVT = H'0000 0020; VBR = H'0000 0000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A000 0000; }
17.4.2
Using watchdog timer mode
1. Set the WDTCNT overflow interval value in WDTST. 2. Set the WT/IT bit in WDTCSR to 1, select the type of reset with the RSTS bit. 3. When the TME bit in WDTCSR is set to 1, the WDT count starts.
Rev. 1.00 Oct. 01, 2007 Page 655 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
4. During operation in watchdog timer mode, clear to the WDTCNT or WDTBCNT periodically so that WDTCNT does not overflow. See section 17.4.5, Clearing WDT Counter for WDT counter clear method. 5. When the WDTCNT overflows, the WDT sets the WOVF flag in WDTCSR to 1, and generates a reset of the type specified by the RSTS bit. After reset operation, the WDTCNT and WDTBCNT continue counting again. 17.4.3 Using Interval timer mode
When the WDT is operating in interval timer mode, an interval timer interrupt is generated each time the counter overflows. This enables interrupts to be generated at fixed intervals. 1. 2. 3. 4. Set the WDTCNT overflow time in WDTST. Clear the WT/IT bit in WDTCSR to 0. When the TME bit in WDTCSR is set to 1, the WDT count starts. When the WDTCNT overflows, the WDT sets the IOVF flag in WDTCSR to 1, and sends an interval timer interrupt (ITI) request to INTC. The counter continues counting. Time for WDT Overflow
17.4.4
Figure 17.2 shows a WDT counting up operation. In interval timer mode, the WDT continues counting even after the WDTCNT overflow. In watchdog timer mode, the WDT clears the WDTCNT and WDTBCNT and start counting again after reset operation.
Rev. 1.00 Oct. 01, 2007 Page 656 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
WDTCNT value Setting value of WDTST
Interval timer mode: Clear counter when overflowed
WDT mode: Clear counter after reset operation
Counting up with overflow signal of WDTBCNT H'0000 0000 Time
WDTBCNT value H'0003 FFFF
Clear counter when overflowed
Counting up with Pck
Interval timer mode
H'0000 0000 Start counting up TME WOVF, IOVF Reset (internal) Set flag
WDT mode Time
Figure 17.2 WDT Counting Up Operation
Rev. 1.00 Oct. 01, 2007 Page 657 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
WDTBCNT is an 18-bit up-counter operated on the peripheral clock0 (Pck0). WDTBCNT is cleared when H'55 is set to the bits 31 to 24 in WDTBST. If the peripheral clock frequency is 66.6 MHz, the WDTBCNT overflow time is approximately 3.932 ms (= 2^18 [bit] x 1/66.6 [MHz]). WDTCNT is a 12-bit counter, starts count up operation when overflow occurs in WDTBCNT. The time until WDTCNT overflows becomes the maximum value when H'000 is set to WDTST. Where the peripheral clock frequency is 66.6 MHz, the maximum overflow time is approximately 16.105 s (= 2^12 [bit] x 3.932 [ms]). And the time until WDTCNT overflows becomes the minimum value when H'5A000001 is set to WDTST. The minimum overflow time is approximately 3.932 ms (= 2^1 [bit] x 3.932 [ms]). 17.4.5 Clearing WDT Counter
Writing H'55 to WDTBST with longword access clears WDTBCNT and writing the overflow setting value to WDTST clears WDTCNT.
Rev. 1.00 Oct. 01, 2007 Page 658 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
17.5
17.5.1
Status Pin Change Timing during Reset
Power-On Reset by PRESET
A power-on reset is to initialize the on-chip PLL circuit when this LSI goes to the power-on reset state by the PERSET pin low level input and then it is necessary to ensure the synchronization settling time of the PLL circuit. Therefore, do not input high level to the PRESET pin during the PLL synchronization settling time. The PLL synchronization settling time is the total value of the PLL1 synchronization settling time and the PLL2 synchronization settling time. After the PRESET pin input level is changed from low level to high level, the reset state is continued during the reset holding time in the LSI. The reset holding time is 20 clock cycles of the EXTAL pin input clock and thereafter equal to or more than 45 clock cycles of the peripheral clock (Pck0). The STATUS [1:0] pins output timing that indicates the reset state is asynchronous, and that indicates a normal operation is synchronous with the peripheral clock (Pck0) and asynchronous with both the EXTAL pin input clock and the CLKOUT pin input clock. (1) Turning On Power Supply
When turning on power supply, the PRESET pin input level should be low level. And the TRST pin input level should be low level to initialize the H-UDI.
Rev. 1.00 Oct. 01, 2007 Page 659 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
EXTAL input CLKOUT output VDD
PRESET input TRST input STATUS[1:0] output HH (reset) LL (normal)
EXTAL input stabilization time
PLL oscillation Reset holding settling time time
Figure 17.3 STATUS Output during Power-on
Rev. 1.00 Oct. 01, 2007 Page 660 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
(2)
PRESET input during normal operation
It is necessary to ensure the PLL oscillation settling time when the PRESET input during normal operation.
EXTAL input
CLKOUT output
PRESET input
STATUS[1:0] output
LL (normal)
HH (reset)
LL (normal)
PLL oscillation settling time
Reset holding time
Figure 17.4 STATUS Output by Reset input during Normal Operation (3) PRESET input during Sleep Mode
It is necessary to ensure the PLL oscillation time when power-on reset generates by the PRESET pin low revel input during sleep mode.
EXTAL input
CLKOUT output PRESET input
STATUS[1:0] output
HL (sleep)
HH (reset)
LL (normal)
PLL oscillation settling time
Reset holding time
Figure 17.5 STATUS Output by Reset input during Sleep Mode
Rev. 1.00 Oct. 01, 2007 Page 661 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
17.5.2
Power-On Reset by Watchdog Timer Overflow
The power-on reset time (watchdog timer reset holding time) by the watchdog timer overflowed is 3774 clock cycles of the EXTAL pin input clock and thereafter equal to or more than 45 clock cycles of the peripheral clock (Pck0). The transition time from the watchdog timer overflowed to the power-on reset state (watchdog timer reset setup time) is 1 clock cycle of the EXTAL input clock and thereafter equal to or more than 5 clock cycles of the peripheral clock (Pck0). The STATUS [1:0] pins output timing that indicates the reset state or a normal operation is asynchronous with both the EXTAL pin input clock and the CLKOUT pin input clock because the STATUS [1:0] pins output timing is synchronous with the peripheral clock (Pck0). (1) Power-On Reset by Watchdog timer Overflowed in Normal Operation
EXTAL input
CLKOUT output
WDT overflow signal
STATUS[1:0] output
LL (normal)
HH (reset)
LL (normal)
WDT reset stabilization time
WDT reset holding time
Figure 17.6 STATUS Output by Watchdog timer overflow Power-On Reset during Normal Operation
Rev. 1.00 Oct. 01, 2007 Page 662 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
(2)
Power-On Reset by Watchdog timer Overflowed in Sleep Mode
EXTAL input
CLKOUT output
WDT overflow signal
STATUS[1:0] output
HH (reset)
LL (normal)
WDT reset stabilization time
WDT reset holding time
Figure 17.7 STATUS Output by Watchdog timer overflow Power-On Reset during Sleep Mode
Rev. 1.00 Oct. 01, 2007 Page 663 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
17.5.3
Manual Reset by Watchdog Timer Overflow
The manual reset time (watchdog timer manual reset holding time) by the watchdog timer overflowed is equal to or more than 3774 clock cycles of the EXTAL pin input clock. The transition time from watchdog timer overflowed to manual reset state (watchdog timer reset setup time) is 1 clock cycle of the EXTAL input and thereafter equal to or more than 5 clock cycles of the peripheral clock (Pck0). The STATUS [1:0] pins output timing that indicates the reset state or a normal operation is asynchronous with both the EXTAL pin input clock and the CLKOUT pin input clock because the STATUS [1:0] pins output timing is synchronous with the peripheral clock (Pck0). (1) Manual Reset by Watchdog timer Overflowed in Normal Operation
EXTAL input
CLKOUT output
WDT overflow signal
MRESETOUT output
STATUS[1:0] output
HH (reset)
LL (normal)
WDT reset stabilization time
Manual reset holding time
Figure 17.8 STATUS Output by Watchdog timer overflow Manual Reset during Normal Operation
Rev. 1.00 Oct. 01, 2007 Page 664 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
(2)
Manual Reset by Watchdog timer Overflowed in Sleep Mode
EXTAL input
CLKOUT output
WDT overflow signal
STATUS[1:0] output
HL (sleep)
HH (reset)
LL (normal)
WDT reset stabilization time
WDT reset holding time
Figure 17.9 STATUS Output by Watchdog timer overflow Manual Reset during Sleep Mode
Rev. 1.00 Oct. 01, 2007 Page 665 of 1956 REJ09B0256-0100
Section 17 Watchdog Timer and Reset (WDT)
Rev. 1.00 Oct. 01, 2007 Page 666 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
Section 18 Power-Down Mode
In power-down modes, operations of the CPU and some of the on-chip peripheral modules are stopped to reduce power consumption.
18.1
Features
* Supports sleep mode and module standby mode * Supports RTC power supply backup mode where the power supply for only the RTC is held and other power supplies are turned off * Supports DDR-SDRAM power supply backup mode where the power supply for only the 2.5V power supplied modules are held and other power supplies are turned off 18.1.1 Types of Power-Down Modes
The types and functions of power-down modes are as shown below. * * * * * Sleep mode Software standby mode Module standby mode RTC power supply backup mode DDR-SDRAM power supply backup mode
Rev. 1.00 Oct. 01, 2007 Page 667 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
Table 18.1 lists the states of the CPU and on-chip peripheral modules in each mode. Table 18.1 States in Power-Down Modes
State PowerDown Mode Sleep Transition Condition SLEEP instruction executed with STBY = 0 in STBCR SLEEP instruction executed with STBY = 1 in STBCR CPG Run CPU On-Chip Memory RTC On-Chip Peripheral Module Others Run Pin Held DDRSDRAM
6
S1 S0 Cancellation *7 1 *7 0
Retained Run Halt (register contents retained)
AR or SR* - Interrupt - Power-on reset - Manual reset
Software standby
Halt*8 Halt Run Halt (register (contents contents retained) retained) Run Run Run
Halt
Hi-Z
Undefined - NMI or IRQ (refresh not - Power-on performed) reset - Manual reset
0
1
Module standby
Corresponding Run bit in MSTPCR0/ MSTPCR1 set to 1 XRTCSTBI pin Halt driven low
Selected modules halt
Held
AR or SR*6 Clear 0 corresponding bit in MSTPCR0/ MSTPCR1 to 0 Undefined Power-on (refresh not reset performed) 0
0
RTC power supply backup *2*3 DDRSDRAM power supply backup *1*3
Halt
Halt
Run
Halt
Hi-Z*4
1
See section 18.7, DDR-SDRAM Power Supply Backup.
Halt
Halt
Halt
Halt
Halt
Undefined*5 SR*6
Power-on reset
0
0
Power-on PRESET pin reset driven low Manual reset
Initial Initial state state Initial state
Initial state Initial state
Counter Initial state Initial state Initial state retained Counter WDT, Held retained GPIO, and debugging interface are held Run Run Run Initial state
1 1
1 1
MRESET pin Held driven low or software reset
Normal operation
Run
Run
Run
Run
0
0
Notes: 1. Because power supplies (1.2 V and 3.3 V) other than the 2.5-V power supply are stopped in DDR-SDRAM power supply backup mode, all modules, except for pads of the DDRIF module, are halted and their register information is not retained. 2. Because power supplies (1.2 V, 2.5 V, and 3.3 V) other than the RTC power supply are stopped in RTC power supply backup mode, all modules other than the RTC module are halted and their register information is not retained. 3. To enter both RTC and DDR-SDRAM power supply backup modes, satisfy the transition conditions for both of them.
Rev. 1.00 Oct. 01, 2007 Page 668 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
4. 5. 6. 7. 8.
Hi-Z state, except for the RTC module interface pins Undefined, except for DDR-SDRAM interface pins AR: auto-refresh: SR: self-refresh S1 and S0 are the output states on the STATUS1 and STATUS0 pins, respectively. Although the clock supply to the internal circuitry is stopped, the clock output on the CLKOUT pin continues if the CKONE bit in PLLCR of the CPG is set to 1.
18.2
Input/Output Pins
Table 18.2 lists the pin configuration related to power-down modes. Table 18.2 Pin Configuration
Pin Name STATUS1 STATUS0 Function Processing state 1 Processing state 0 I/O Output Output Description These pins indicate the operating state of this LSI. STATUS[1:0] H, H: H, L: L, H: L, L: XRTCSTB1 RTC standby Input Operating state Power-on reset or manual reset Sleep mode Software standby or RTC power supply backup mode Normal operation
When this pin goes low, the LSI enters RTC power supply backup mode.
Rev. 1.00 Oct. 01, 2007 Page 669 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
18.3
Register Descriptions
Table 18.3 shows the register configuration for power-down modes. Table 18.4 shows the register states in each operating mode. Table 18.3 Register Configuration
Register Name Standby control register Module stop register 0 Module stop register 1 Abbreviation R/W STBCR MSTPCR0 MSTPCR1 R/W R/W R/W Area P4 Address H'FFC8 0020 H'FFC8 0030 H'FFC8 0038 Area 7 Address H'1FC8 0020 H'1FC8 0030 H'1FC8 0038 Access Size 32 32 32
Table 18.4 Register States in Each Operating Mode
Register Name Standby control register Module stop register 0 Module stop register 1 Power-On Abbreviation Reset STBCR MSTPCR0 MSTPCR1 H'0000 0000 H'0000 0000 H'0000 0000 Manual Reset Retained Retained Retained Sleep Retained Retained Retained Standby Retained Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 670 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
18.3.1
Standby Control Register (STBCR)
STBCR is a 32-bit readable/writable register that selects a power-down mode to be entered after a SLEEP instruction is executed. STBCR can be accessed only in longwords.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit:
-
0 R 14
-
0 R 13
-
0 R 12
-
0 R 11
-
0 R 10
-
0 R 9
-
0 R 8
-
0 R 7
STBY
-
0 R 6
-
0 R 5
-
0 R 4
-
0 R 3
-
0 R 2
-
0 R 1
-
0 R 0
0 R 15
-
Initial value: R/W:
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
0 R
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 8
7
STBY
0
R/W
Standby Selects whether to enter sleep mode or software standby mode after a SLEEP instruction is executed. 0: Sleep mode 1: Software standby mode
6 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 671 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
18.3.2
Module Stop Register 0 (MSTPCR0)
MSTPCR0 is a 32-bit readable/writable register that can individually start or stop the module assigned to each bit. MSTPCR0 can be accessed only in longwords.
Bit: 31 -- Initial value: R/W: Bit: 0 R
15
30 -- 0
R
14 -- 0 R
29 -- 0 R
13
28 -- 0 R
12
27 -- 0 R
11
26 -- 0 R
10
25 -- 0 R
9
24 -- 0 R
8
23 -- 0 R
7
22 -- 0 R
6
21
--
20 -- 0 R
4
19
--
18
--
17
--
16
--
0 R
5
0 R
3
0 R
2
0 R
1
0 R
0
LCDC
--
0 R
--
0 R
--
0 R
--
0 R
--
0 R
--
0 R
--
0 R
--
0 R
--
0 R
--
0 R
--
0 R
--
0 R
--
0 R
--
0 R
Initial value: 0 R/W: R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15
LCDC
0
R/W
LCDC Module Stop Bit When set to 1, the clock supply to the LCDC module is halted. 0: LCDC operates 1: Clock supply to LCDC is halted
14 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 672 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
18.3.3
Module Stop Register 1 (MSTPCR1)
MSTPCR1 is a 32-bit readable/writable register that can individually start or stop the module assigned to each bit. MSTPCR1 can be accessed only in longwords.
Bit: 31 -- Initial value: R/W: Bit: 0
R
15
30 PCC 0 R/W
14
29
28
27
26
25
24
23
22 IIC1 0 R/W
6
21
20
19
18
17
16
HAC STIF1 STIF0 SSI3 SSI2 SSI1 SSI0 0 R/W
13
IIC0 SIOF2 SIOF1 SIOF0 SCIF2 SCIF1 0 R/W
5
0 R/W
12
0 R/W
11
0 R/W
10
0 R/W
9
0 R/W
8
0 R/W
7
0 R/W
4
0 R/W
3
0 R/W
2
0 R/W
1
0 R/W
0
SCIF0 SIM
ADC
0 R/W
DAC
0 R/W
CMT TMU1 TMU0 TPU
0 R/W 0 R/W 0 R/W 0 R/W
--
0 R
--
0 R
--
0 R
--
0 R
MMC
0 R/W
--
0 R
--
0 R
--
0 R
Initial value: 0 R/W: R/W
0 R/W
Bit 31
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
30
PCC
0
R/W
PCC Module Stop Bit When set to 1, the clock supply to the PCC module is halted. 0: PCC operates 1: Clock supply to PCC is halted
29
HAC
0
R/W
HAC Module Stop Bit When set to 1, the clock supply to the HAC module is halted. 0: HAC operates 1: Clock supply to HAC is halted
Rev. 1.00 Oct. 01, 2007 Page 673 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
Bit 28
Bit Name STIF1
Initial Value 0
R/W R/W
Description STIF1 Module Stop Bit When set to 1, the clock supply to the STIF1 module is halted. 0: STIF1 operates 1: Clock supply to STIF1 is halted
27
STIF0
0
R/W
STIF0 Module Stop Bit When set to 1, the clock supply to the STIF0 module is halted. 0: STIF0 operates 1: Clock supply to STIF0 is halted
26
SSI3
0
R/W
SSI3 Module Stop Bit When set to 1, the clock supply to the SSI3 module is halted. 0: SSI3operates 1: Clock supply to SSI3 is halted
25
SSI2
0
R/W
SSI2 Module Stop Bit When set to 1, the clock supply to the SSI2 module is halted. 0: SSI2 operates 1: Clock supply to SSI2 is halted
24
SSI1
0
R/W
SSI1 Module Stop Bit When set to 1, the clock supply to the SSI1 module is halted. 0: SSI1 operates 1: Clock supply to SSI1 is halted
23
SSI0
0
R/W
SSI0 Module Stop Bit When set to 1, the clock supply to the SSI0 module is halted. 0: SSI0 operates 1: Clock supply to SSI0 is halted
Rev. 1.00 Oct. 01, 2007 Page 674 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
Bit 22
Bit Name IIC1
Initial Value 0
R/W R/W
Description IIC1 Module Stop Bit When set to 1, the clock supply to the IIC1 module is halted. 0: IIC1 operates 1: Clock supply to IIC1 is halted
21
IIC0
0
R/W
IIC0 Module Stop Bit When set to 1, the clock supply to the IIC0 module is halted. 0: IIC0 operates 1: Clock supply to IIC0 is halted
20
SIOF2
0
R/W
SIOF2 Module Stop Bit When set to 1, the clock supply to the SIOF2 module is halted. 0: SIOF2 operates 1: Clock supply to SIOF2 is halted
19
SIOF1
0
R/W
SIOF1 Module Stop Bit When set to 1, the clock supply to the SIOF1 module is halted. 0: SIOF1 operates 1: Clock supply to SIOF1 is halted
18
SIOF0
0
R/W
SIOF0 Module Stop Bit When set to 1, the clock supply to the SIOF0 module is halted. 0: SIOF0 operates 1: Clock supply to SIOF0 is halted
17
SCIF2
0
R/W
SCIF2 Module Stop Bit When set to 1, the clock supply to the SCIF2 module is halted. 0: SCIF2 operates 1: Clock supply to SCIF2 is halted
Rev. 1.00 Oct. 01, 2007 Page 675 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
Bit 16
Bit Name SCIF1
Initial Value 0
R/W R/W
Description SCIF1 Module Stop Bit When set to 1, the clock supply to the SCIF1 module is halted. 0: SCIF1 operates 1: Clock supply to SCIF1 is halted
15
SCIF0
0
R/W
SCIF0 Module Stop Bit When set to 1, the clock supply to the SCIF0 module is halted. 0: SCIF0 operates 1: Clock supply to SCIF0 is halted
14
SIM
0
R/W
SIM Module Stop Bit When set to 1, the clock supply to the SIM module is halted. 0: SIM operates 1: Clock supply to SIM is halted
13
ADC
0
R/W
ADC Module Stop Bit When set to 1, the clock supply to the ADC module is halted. 0: ADC operates 1: Clock supply to ADC is halted
12
DAC
0
R/W
DAC Module Stop Bit When set to 1, the clock supply to the DAC module is halted. 0: DAC operates 1: Clock supply to DAC is halted
11
CMT
0
R/W
CMT Module Stop Bit When set to 1, the clock supply to the CMT module is halted. 0: CMT operates 1: Clock supply to CMT is halted
Rev. 1.00 Oct. 01, 2007 Page 676 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
Bit 10
Bit Name TMU1
Initial Value 0
R/W R/W
Description TMU1 Module Stop Bit When set to 1, the clock supply to the TMU1 module is halted. 0: TMU1 operates 1: Clock supply to TMU1 is halted
9
TMU0
0
R/W
TMU0 Module Stop Bit When set to 1, the clock supply to the TMU0 module is halted. 0: TMU0 operates 1: Clock supply to TMU0 is halted
8
TPU
0
R/W
TPU Module Stop Bit When set to 1, the clock supply to the TPU module is halted. 0: TPU operates 1: Clock supply to TPU is halted
7 to 4
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
3
MMC
0
R/W
MMC Module Stop Bit When set to 1, the clock supply to the MMC module is halted. 0: MMC operates 1: Clock supply to MMC is halted
2 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Note: When writing to a certain bit in MSTPCR1, read all values in MSTPCR1 first and rewrite the certain bit, then return the renewed values back to MSTPCR1.
Rev. 1.00 Oct. 01, 2007 Page 677 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
18.4
18.4.1
Sleep Mode
Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of the CPU registers remain unchanged. On-chip peripheral modules continue to operate, and the clock output on the CLKOUT pin also continues. In sleep mode, a high level is output to the STATUS1 pin and a low level to the STATUS0 pin. 18.4.2 Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRQ/IRL[7:0], or on-chip peripheral module interrupt) or a reset. Interrupts are accepted in sleep mode even when the BL bit in SR is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction. (1) Canceling with Interrupt
When an NMI, IRQ/IRL[7:0], or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. A code indicating the interrupt source is set in INTEVT. (2) Canceling with Reset
Sleep mode is canceled by a power-on reset caused by the RESET pin or watchdog timer overflow or a manual reset. Note: If an NMI interrupt is used to cancel sleep mode while the LCD is used, the NMIFL bit in the NMIFCR register is set to 1 by the interrupt. This disables the LCD to access to the VRAM used for the display data storage (DDR_SDRAM in area 3). Moreover, as the LCDC continues to output data stored in the line buffer to the LCD panel data pin, the LCD display will be stopped if the line buffer becomes empty. Accordingly, an NMI interrupt should be disabled and the NMIFL bit should be cleared to 0 before the line buffer becomes empty.
Rev. 1.00 Oct. 01, 2007 Page 678 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
18.5
18.5.1
Software Standby Mode
Transition to Software Standby Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 1 causes a transition from the program execution state to software standby mode. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. However, the clock output from the CLKOUT pin continues when the CKONE bit in the PLLCR register of the CPG is set to 1. When the CKONE bit is 0, a low level is output from the CLKOUT pin. The contents of the CPU and cache registers remain unchanged. Some registers of the on-chip peripheral modules are initialized. The procedure for a transition to software standby mode is as follows: 1. Set the STBY bit in STBCR to 1. 2. Execute the SLEEP instruction. 3. Software standby mode is entered and the clocks within the LSI are halted. The output on the STATUS0 pin goes high. All modules should be stopped before the above procedure is executed.
18.5.2
Canceling Software Standby Mode
Software standby mode is canceled by an interrupt (NMI or IRQ/IRL) or a reset. (1) Canceling with Interrupt
When an NMI or IRQ, occurs, software standby mode is canceled and the STATUS0 pin goes low. Thereafter, interrupt exception handling is executed and a code indicating the interrupt source is set in INTEVT. After branching to the interrupt service routine, clear the STBY bit in the STBCR register back to 0. Since interrupts are accepted in software standby mode even when the BL bit in SR is 1, save SPC and SSR to the stack before executing the SLEEP instruction if necessary. Immediately after an interrupt is detected, the clock output on the CLKOUT pin may be unstable until software standby mode is canceled.
Rev. 1.00 Oct. 01, 2007 Page 679 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
18.6
18.6.1
Module Standby Mode
Transition to Module Standby Mode
Setting the bits in the module stop register to 1 halts the clock supply to the corresponding on-chip peripheral modules. This function can be used to reduce power consumption in normal mode. Modules in module standby mode keep the state immediately before the transition to the module standby mode. The registers retain their contents before the module is halted, and the external pins also hold their states before halted. At waking up from the module standby state, operation starts from the condition immediately before the module was halted. 18.6.2 Canceling Module Standby Mode
The module standby mode can be canceled by clearing the respective bit in the module stop register to 0 or by a power-on reset.
Rev. 1.00 Oct. 01, 2007 Page 680 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
18.7
18.7.1
DDR-SDRAM Power Supply Backup
Control of Self-Refresh and Initialization
To preserve the contents of the DDR-SDRAM with battery backup, make sure that the DDRSDRAM is in the self-refresh mode before turning off the system power supply. When the system power supply is turned on, initialization of the DDR-SDRAM or cancellation of the self-refresh mode must be performed according to whether the DDR-SDRAM has been in self-refresh mode or has not been initialized. For DDR-SDRAM, both a transition to and a cancellation of the selfrefresh mode are done by issuing a command. (1) RMODE Bit
Bit 33 in the MIM register. The initial value is 0. Setting this bit to 1 after setting the DRE bit in MIM to 1 causes the DDRIF to start the sequence for a transition to the self-refresh mode. For details, see section 12.5.5 (1), Self-Refresh Mode. (2) Bits SMS2 to SMS0
Bits 2 to 0 in the SCR register. These bits are used to assert the M_CKE signal (high) by setting SMS = B'011 when canceling the self-refresh mode with the DESL command. (3) M_BKPRST Signal
To prevent the M_CKE signal from being unstable when turning on or off the LSI power supply, the M_BKPRST signal must be input in synchronization with turning the LSI power supply on or off. The M_BKPRST signal must be kept low while the system power supply is turned off.
Rev. 1.00 Oct. 01, 2007 Page 681 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
Transition to self-refresh mode completed
System power supply turned off
System power Power-on supply reset turned on canceled
M_CKE asserted by SMS bits in SCR
PRESET
Delay time of LSI internal reset
DDRIF reset VDD (1.2 V, 3.3 V) M_CKE
M_BKPRST
Figure 18.1 DDR-SDRAM Interface Operation when Turning System Power Supply On/Off 18.7.2 DDR-SDRAM Backup Sequence when Turning Off System Power Supply
The sequence when the system power supply is turned off is shown below. Figure 18.2 shows the sequence of entering the self-refresh mode and turning off the system power supply. 1. Confirm that all transactions of the DDRIF caused by on-chip peripheral modules are completed. 2. Issue the all bank precharge command (PREALL) with bits SMS2 to SMS0 in SCR by software. Activated banks will be closed. After that, issue the auto-refresh command (REFA) with bits SMS2 to SMS0 in SCR to perform CBR refresh on all rows. 3. Specify the DRE and RMODE bits in the MIM register of the DDRIF to put the SDRAM into the self-refresh mode. At this time, keep the DCE bit set to 1. The DDRIF automatically issues a self-refresh command and drives the M_CKE signal low. After that, the DDR-SDRAM will automatically enter the power-down mode. 4. The SELFS bit in MIM is set to 1. 5. Drive the M_BKPRST pin from high to low. The M_CKE output will be unstable immediately after the system power supply is turned off. Therefore, before turning off the system power supply, use the M_BKPRST signal, which is a signal outside the LSI, to keep the M_CKE signal input of the DDR-SDRAM low until the power-on reset is canceled (figure 18.1). 6. Turn off the system power supply (1.2 V and 3.3 V).
Rev. 1.00 Oct. 01, 2007 Page 682 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
After the system power supply is turned on, the M_CKE output may remain unstable until the clock is supplied after the LSI power supply has become stable. Therefore, use the M_BKPRST signal to keep the M_CKE signal input of the DDR-SDRAM low until the power-on reset is canceled.
Time Processing SELFS Command M_CKE High REFA/NOP SDRAM State Performs auto-refresh at regular intervals
1.
Confirm that all transactions of DDRIF caused by on-chip peripheral modules are completed
2.
Set SCR to issue PREALL and REFA commands
Low PREALL REFA
Enters idle state after refreshing once
3.
Set MIM to issue self-refresh command
Low
Performs self-refresh
4.
Set MIM: SELFS = 1
REFS
5.
Drive M_BKPRST from high to low
High
6.
Turn off system power supply
Figure 18.2 Sequence for Turning Off System Power Supply after Entering Self-Refresh Mode
Rev. 1.00 Oct. 01, 2007 Page 683 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
18.8
18.8.1
RTC Power Supply Backup
Transition to RTC Power Supply Backup Mode
When entering the RTC power supply backup mode with the VDD power supply (1.2 V) turned off, the VDD power supply should be turned off while the XRTCSTBI signal is held low. By turning off the VDD power supply, the currents that might be generated in the VDD (1.2 V) operating region can be eliminated to reduce power consumption. If the clock has been supplied from the 32.768-Hz crystal, the RTC continues counting of its second to year counters while the VDD (1.2 V) power supply is turned off. 18.8.2 Canceling RTC Power Supply Backup Mode
The RTC power supply backup mode is canceled by a power-on reset. Even when any interrupt condition is satisfied in the RTC power supply backup mode, the interrupt-generating condition will be canceled by the power-on reset. RTC power supply backup mode can be canceled in the following steps. 1. Turn on the VDD power supply (1.2 V) while holding the PRESET signal low. 2. Since the VDD-RTC (3.3 V), which is exclusively used for the RTC, is supplied, drive the XRTCSTBI signal high only after the power-on oscillation stabilization time has elapsed after the VDD (1.2 V) becomes stable. This is to prevent the LSI from being damaged by the transient current. 3. Hold the PRESET signal low until the RTC is reset by the power-on reset, and then cancel the power-on reset. Table 18.5 shows the configuration of the pins related to RTC power supply backup mode. Table 18.5 Pin Configuration
Pin Name XRTCSTBI Function RTC standby I/O Input Description When this pin goes low, the LSI enters RTC power supply backup mode.
Rev. 1.00 Oct. 01, 2007 Page 684 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
System power supply turned off VDD-RTC
System power supply turned on High-level RTC battery backup state
VDD RTC standby XRTCSTBI Power-on reset canceled PRESET
(1) (1) Oscillation stabilization time at power-on (2) Reset delay time at the RTC
(2)
Figure 18.3 Sequence for Turning VDD Power Supply (1.2 V) On/Off
18.9
18.9.1
STATUS Pin Signal Change Timing
Timing at Reset
Refer to section 17.5, Status Pin Change Timing during Reset. 18.9.2 (1) Timing at Sleep Mode Cancellation
When an Interrupt Occurs in Sleep Mode
Figure 18.4 shows the timing of signal changes on the STATUS pins.
Interrupt request
CLKOUT
IRQOUT output
STATUS[1:0] output
LL (Normal operation)
HL (sleep)
LL (Normal operation)
Figure 18.4 STATUS Output when an Interrupt Occurs in Sleep Mode
Rev. 1.00 Oct. 01, 2007 Page 685 of 1956 REJ09B0256-0100
Section 18 Power-Down Mode
Rev. 1.00 Oct. 01, 2007 Page 686 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
Section 19 Timer Unit (TMU)
This LSI includes an on-chip 32-bit timer unit (TMU), which has six channels (channels 0 to 5).
19.1
Features
The TMU has the following features. * Auto-reload type 32-bit down-counter provided for each channel * Input capture function provided in channel 2 * Selection of rising edge or falling edge as external clock input edge when external clock is selected or input capture function is used for each channel * 32-bit timer constant register for auto-reload use, readable/writable at any time, and 32-bit down-counter provided for each channel * Selection of seven counter input clocks: External clock (TMU_TCLK) for channel 0 to 2 only, RTC clock (RTCCLK) and five peripheral clocks (Pck0/4, Pck0/16, Pck0/64, Pck0/256, and Pck0/1024) (Pck0 is the peripheral clock0) for each channel. * Two interrupt sources One underflow source (each channel) and one input capture source (channel 2)
Rev. 1.00 Oct. 01, 2007 Page 687 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
Figure 19.1 shows a block diagram of the TMU.
RESET, STBY etc. TUNI0, 1, 3, 4, and 5 Pck/4, Pck/16, Pck/64* TCLK RTCCLK TUNI2 TUNI2
TMU operation controller
Prescaler
TCLK controller
To each channel
To channels 0 to 2
TOCR TSTR
Channel 0, 1, 3, 4, 5
Channel 2
Counter
Interrupt controller
Counter
Interrupt controller
TCR
TCOR
TCNT
TCR2
TCOR2
TCNT2
TCPR2
Bus interface
Peripheral bus
Note: * Internal signals with 1/4, 1/16, or 1/64 of the Pck frequency and supplied to the on-chip peripheral modules. [Legend] TSTR: TCOR: TCNT: TCR: TCPR2:
Timer start register Timer constant register Timer counter Timer control register Input capture register 2 (only in channel 2)
Figure 19.1 Block Diagram of TMU
Rev. 1.00 Oct. 01, 2007 Page 688 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
19.2
Input/Output Pins
Table 19.1 shows the TMU pin configuration. Table 19.1 Pin Configuration
Pin Name TMU_TCLK Function Clock input I/O Input Description Channel 0, 1 and 2 external clock input pin/channel 2 input capture control input pin
Rev. 1.00 Oct. 01, 2007 Page 689 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
19.3
Register Descriptions
Table 19.2 shows register configuration. Table 19.3 shows the register states in each operating mode. Table 19.2 Register Configuration
Channel 0,1,2 Common 0 Register Name Timer output control register Timer start register 0 Timer constant register 0 Timer counter 0 Timer control register 0 1 Timer constant register 1 Timer counter 1 Timer control register 1 2 Timer constant register 2 Timer counter 2 Timer control register 2 Input capture register 2 3,4,5 Common 3 Timer start register 1 Timer constant register 3 Timer counter 3 Timer control register 3 4 Timer constant register 4 Timer counter 4 Timer control register 4 5 Timer constant register 5 Timer counter 5 Timer control register 5 Abbrev. R/W TOCR TSTR0 TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 TCPR2 TSTR1 TCOR3 TCNT3 TCR3 TCOR4 TCNT4 TCR4 TCOR5 TCNT5 TCR5 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P4 Address H'FFD8 0000 H'FFD8 0004 H'FFD8 0008 H'FFD8 000C H'FFD8 0010 H'FFD8 0014 H'FFD8 0018 H'FFD8 001C H'FFD8 0020 H'FFD8 0024 H'FFD8 0028 H'FFD8 002C H'FFD8 8004 H'FFD8 8008 H'FFD8 800C H'FFD8 8010 H'FFD8 8014 H'FFD8 8018 H'FFD8 801C H'FFD8 8020 H'FFD8 8024 H'FFD8 8028 Area 7 Address H'1FD8 0000 H'1FD8 0004 H'1FD8 0008 H'1FD8 000C H'1FD8 0010 H'1FD8 0014 H'1FD8 0018 H'1FD8 001C H'1FD8 0020 H'1FD8 0024 H'1FD8 0028 H'1FD8 002C H'1FD8 8004 H'1FD8 8008 H'1FD8 800C H'1FD8 8010 H'1FD8 8014 H'1FD8 8018 H'1FD8 801C H'1FD8 8020 H'1FD8 8024 H'1FD8 8028 Size 8 8 32 32 16 32 32 16 32 32 16 32 8 32 32 16 32 32 16 32 32 16
Rev. 1.00 Oct. 01, 2007 Page 690 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
Table 19.3 Register States in Each Operating Mode
Channel 0,1,2 Common 0
Register Name Timer output control register Timer start register 0 Timer constant register 0 Timer counter 0 Timer control register 0
Abbrev. TOCR TSTR0 TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 TCPR2 TSTR1 TCOR3 TCNT3 TCR3 TCOR4 TCNT4 TCR4 TCOR5 TCNT5 TCR5
Power-on Reset H'00 H'00 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000
Manual Reset Sleep H'00 H'00 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
1
Timer constant register 1 Timer counter 1 Timer control register 1
2
Timer constant register 2 Timer counter 2 Timer control register 2 Input capture register 2
H'XXXX XXXX H'XXXX XXXX Retained H'00 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000 H'00 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
3,4,5 Common 3
Timer start register 1 Timer constant register3 Timer counter 3 Timer control register 3
4
Timer constant register 4 Timer counter 4 Timer control register 4
5
Timer constant register 5 Timer counter 5 Timer control register 5
Note:
*
After exiting hardware standby mode, this LSI enters the power-on reset state caused by the PRESET pin.
Rev. 1.00 Oct. 01, 2007 Page 691 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
19.3.1
Timer Output Control Register (TOCR)
TOCR is an 8-bit read-only register that specifies whether external pin TMU_TCLK is used as the external clock or input capture control input pin.
BIt: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 TCOE 0 R/W
Bit 7 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
TCOE
0
R/W
Timer Clock Pin Control (TCOE) Specifies whether timer clock pin (TMU_TCLK) is used as the external clock or input capture control input pin. 0: TMU_TCLK is used as external clock input or input capture control input pin. 1: Invalid
Rev. 1.00 Oct. 01, 2007 Page 692 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
19.3.2
Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that specifies whether TCNT in each channel is operated or stopped. * TSTR0
BIt: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0 STR2 STR1 STR0 0 R/W 0 R/W 0 R/W
Bit 7 to 3
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2
STR2
0
R/W
Counter Start 2 Specifies whether TCNT2 is operated or stopped. 0: TCNT2 count operation is stopped 1: TCNT2 performs count operation
1
STR1
0
R/W
Counter Start 1 Specifies whether TCNT1 is operated or stopped. 0: TCNT1 count operation is stopped 1: TCNT1 performs count operation
0
STR0
0
R/W
Counter Start 0 Specifies whether TCNT0 is operated or stopped. 0: TCNT0 count operation is stopped 1: TCNT0 performs count operation
Rev. 1.00 Oct. 01, 2007 Page 693 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
* TSTR1
BIt: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0 STR5 STR4 STR3 0 R/W 0 R/W 0 R/W
Bit 7 to 3
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2
STR5
0
R/W
Counter Start 5 Specifies whether TCNT5 is operated or stopped. 0: TCNT5 count operation is stopped 1: TCNT5 performs count operation
1
STR4
0
R/W
Counter Start 4 Specifies whether TCNT4 is operated or stopped. 0: TCNT4 count operation is stopped 1: TCNT4 performs count operation
0
STR3
0
R/W
Counter Start 3 Specifies whether TCNT3 is operated or stopped. 0: TCNT3 count operation is stopped 1: TCNT3 performs count operation
Rev. 1.00 Oct. 01, 2007 Page 694 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
19.3.3
Timer Constant Register (TCORn) (n = 0 to 5)
The TCOR registers are 32-bit readable/writable registers. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: R/W: BIt:
1 R/W 15
1 R/W 14
1 R/W 13
1 R/W 12
1 R/W 11
1 R/W 10
1 R/W 9
1 R/W 8
1 R/W 7
1 R/W 6
1 R/W 5
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
19.3.4
Timer Counter (TCNTn) (n = 0 to 5)
The TCNT registers are 32-bit readable/writable registers. Each TCNT counts down on the input clock selected by the TPSC2 to TPSC0 bits in TCR. When a TCNT counter underflows while counting down, the UNF flag is set in TCR of the corresponding channel. At the same time, the TCOR value is set in TCNT, and the count-down operation continues from the set value.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: R/W: BIt:
1 R/W 15
1 R/W 14
1 R/W 13
1 R/W 12
1 R/W 11
1 R/W 10
1 R/W 9
1 R/W 8
1 R/W 7
1 R/W 6
1 R/W 5
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Rev. 1.00 Oct. 01, 2007 Page 695 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
19.3.5
Timer Control Registers (TCRn) (n = 0 to 5)
The TCR registers are 16-bit readable/writable registers. Each TCR selects the count clock, specifies the edge when an external clock is selected, and controls interrupt generation when the flag indicating TCNT underflow is set to 1. TCR2 is also used for input capture control and control of interrupt generation in the event of input capture. * TCR0, TCR1, TCR3, TCR4 and TCR5
BIt: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 UNF 0 R/W 7 -- 0 R 6 -- 0 R 5 4 3 2 1 0
UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
* TCR2
BIt: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 8 7 6 5 4 3 2 1 0 ICPF UNF ICPE1 ICPE0 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit Bit Name 15 to 10 --
Initial Value All 0
R/W R
9
ICPF*1
0
R/W
8
UNF
0
R/W
Description Reserved These bits are always read as 0. The write value should always be 0. Input Capture Interrupt Flag Status flag, provided in channel 2 only, which indicates the occurrence of input capture. 0: Input capture has not occurred [Clearing condition] When 0 is written to ICPF 1: Input capture has occurred [Setting condition] When input capture occurs*2 Underflow Flag Status flag that indicates the occurrence of TCNT underflow. 0: TCNT has not underflowed [Clearing condition] When 0 is written to UNF 1: TCNT has underflowed [Setting condition] When TCNT underflows*2
Rev. 1.00 Oct. 01, 2007 Page 696 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
Bit 7 6
Bit Name ICPE1* ICPE0*
1 1
Initial Value 0 0
R/W R/W R/W
Description Input Capture Control These bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used. The CKEG bits specify whether the rising edge or falling edge of the TCLK pin is used to set the TCNT2 value in TCPR2. The TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is 0. When the ICPF bit is 1, TCPR2 is not set in the event of input capture. 00: Input capture function is not used. 01: Setting prohibited 10: Input capture function is used, but interrupt due to input capture (TICPI2) is not enabled. Data transfer request is sent to the DMAC in the event of input capture. 11: Input capture function is used, and interrupt due to input capture (TICPI2) is enabled.
5
UNIE
0
R/W
Underflow Interrupt Control Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1, indicating TCNT underflow. 0: Interrupt due to underflow (TUNI) is disabled 1: Interrupt due to underflow (TUNI) is enabled
4 3
CKEG1 CKEG0
0 0
R/W R/W
Clock Edge 1 and 0 These bits select the external clock input edge when an external clock is selected or the input capture function is used. 00: Count/input capture register set on rising edge 01: Count/input capture register set on falling edge 1X: Count/input capture register set on both rising and falling edges
Rev. 1.00 Oct. 01, 2007 Page 697 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
Bit 2 1 0
Bit Name TPSC2 TPSC1 TPSC0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Timer Prescaler 2 to 0 These bits select the TCNT count clock. 000: Counts on Pck0/4 001: Counts on Pck0/16 010: Counts on Pck0/64 011: Counts on Pck0/256 100: Counts on Pck0/1024 101: Setting prohibited 110: Counts on on-chip RTC output clock (RCTCLK) 111: Counts on external clock (TCLK) *
3
Notes: X: Don't care 1. Reserved bit in channel 0 or 1 (initial value is 0, and can only be read). 2. Writing 1 does not change the value; the previous value is retained. 3. Do not set in channels 3, 4, and 5
19.3.6
Input Capture Register 2 (TCPR2)
TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in channel 2. The input capture function is controlled by means of the ICPE and CKEG bits in TCR2. When input capture occurs, the TCNT2 value is copied into TCPR2. The value is set in TCPR2 only when the ICPF bit in TCR2 is 0.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: R/W: BIt:
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: R/W:
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
Rev. 1.00 Oct. 01, 2007 Page 698 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
19.4
Operation
Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). Each TCNT performs count-down operation. The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function. 19.4.1 Counter Operation
When one of bits STR0 to STR2 in TSTR is set to 1, the TCNT for the corresponding channel starts counting. When TCNT underflows, the UNF flag in TCR is set. If the UNIE bit in TCR is set to 1 at this time, an interrupt request is sent to the CPU. At the same time, the value is copied from TCOR into TCNT, and the count-down continues (auto-reload function). (1) Example of Count Operation Setting Procedure
Figure 19.2 shows an example of the count operation setting procedure.
Rev. 1.00 Oct. 01, 2007 Page 699 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
Select operation
(1) Select the count clock with the TPSC2 to TPSC0 bits in TCR. When the external clock (TCLK) is selected, specify the external clock edge with the CKEG1 and CKEG0 bits in TCR. (2) Specify whether an interrupt is to be generated on TCNT underflow with the UNIE bit in TCR. (3) When the input capture function is used, set the ICPE bits in TCR, including specification of whether the interrupt function is to be used. (4) Set a value in TCOR.
Select count clock
(1)
Underflow interrupt generation setting
(2)
Input capture interrupt generation setting
(3)
Timer constant register setting
(5) Set the initial value inTCNT. (4) (6) Set the STR bit to 1 in TSTR to start the count.
Set initial timer counter value
(5)
Start count
Note:
(6)
When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt enabled state is set without clearing the flag, another interrupt will be generated.
Figure 19.2 Example of Count Operation Setting Procedure
Rev. 1.00 Oct. 01, 2007 Page 700 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
(2)
Auto-Reload Count Operation
Figure 19.3 shows the TCNT auto-reload operation.
TCNT value TCOR
TCOR value set in TCNT on underflow
H'0000 0000
Time
STR0 to STR5
UNF
Figure 19.3 TCNT Auto-Reload Operation (3) TCNT Count Timing
* Operating on internal clock Any of five count clocks (Pck0/4, Pck0/16, Pck0/64, Pck0/256, or Pck0/1024) scaled from the peripheral clock can be selected as the count clock by means of the TPSC2 to TPSC0 bits in TCR. Figure 19.4 shows the timing in this case.
Pck
Internal clock
TCNT
N+1
N
N-1
Figure 19.4 Count Timing when Operating on Internal Clock
Rev. 1.00 Oct. 01, 2007 Page 701 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
* Operating on external clock In channels 0, 1, and 2, the external clock pin (TCLK) input can be selected as the timer clock by means of the TPSC2 to TPSC0 bits in TCR. The detected edge (rising, falling, or both edges) can be selected with the CKEG1 and CKEG0 bits in TCR. Figure 19.5 shows the timing for both-edge detection.
Pck
External clock input pin
TCNT N+1 N N-1
Figure 19.5 Count Timing when Operating on External Clock * Operating on on-chip RTC output clock The on-chip RTC output clock can be selected as the timer clock by means of the TPSC2 to TPSC0 bits in TCR. Figure 19.6 shows the timing for both-edge detection.
RTC output clock
TCNT
N+1
N
N-1
Figure 19.6 Count Timing when Operating on on-chip RTC output Clock
Rev. 1.00 Oct. 01, 2007 Page 702 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
19.4.2
Input Capture Function
Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1. Use bits TPSC2 to TPSC0 in TCR to set an internal clock as the timer operating clock. 2. Use bits IPCE1 and IPCE0 in TCR to specify use of the input capture function, and whether interrupts are to be generated when this function is used. 3. Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the TCLK pin is to be used to set the TCNT value in TCPR2. When input capture occurs, the TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is 0. A new DMAC transfer request is not generated until processing of the previous request is finished. Figure 19.7 shows the operation timing when the input capture function is used (with TCLK rising edge detection).
TCNT value TCOR TCOR value set in TCNT on underflow
H'0000 0000 TCLK
Time
TCPR2
TCNT value set
TICPI2
Figure 19.7 Operation Timing when Using Input Capture Function
Rev. 1.00 Oct. 01, 2007 Page 703 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
19.5
Interrupts
There are seven TMU interrupt sources: underflow interrupts and the input capture interrupt when the input capture function is used. Underflow interrupts are generated on each of the channels, and input capture interrupts on channel 2 only. An underflow interrupt request is generated (for each channel) when both the UNF bit and the interrupt enable bit (UNIE) for that channel are set to 1. When the input capture function is used and an input capture request is generated, an interrupt is requested if the ICPF bit in TCR2 is 1 and the input capture control bits (ICPE1 and ICPE0) in TCR2 are both set to 11. The TMU interrupt sources are summarized in Table 19.4. Table 19.4 TMU Interrupt Sources
Channel 0 1 2 Interrupt Source TUNI0 TUNI1 TUNI2 TICPI2 3 4 5 TUNI3 TUNI4 TUNI5 Description Underflow interrupt 0 Underflow interrupt 1 Underflow interrupt 2 Input capture interrupt 2 Underflow interrupt 3 Underflow interrupt 4 Underflow interrupt 5
Rev. 1.00 Oct. 01, 2007 Page 704 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
19.6
19.6.1
Usage Notes
Register Writes
When writing to a TMU register, timer count operation must be stopped by clearing the start bit (STR5 to STR0) for the relevant channel in TSTR. Note that TSTR can be written to, and the UNF and ICPF bits in TCR can be cleared while the count is in progress. When the flags (UNF and ICPF) are cleared while the count is in progress, make sure not to change the values of bits other than those being cleared. 19.6.2 Reading from TCNT
Reading from TCNT is performed synchronously with the timer count operation. Note that when the timer count operation is performed simultaneously with reading from a register, the synchronous processing causes the TCNT value before the count-down operation to be read as the TCNT value. 19.6.3 External Clock Frequency
Ensure that the external clock (TMU_TCLK) frequency for channels 0, 1 and 2 does not exceed Pck0/4.
Rev. 1.00 Oct. 01, 2007 Page 705 of 1956 REJ09B0256-0100
Section 19 Timer Unit (TMU)
Rev. 1.00 Oct. 01, 2007 Page 706 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Section 20 16-Bit Timer Pulse Unit (TPU)
This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises four 16-bit timer channels.
20.1
Features
* Maximum 4-pulse output A total of 16 timer general registers (TGRA to TGRD x 4 ch.) are provided (four each for channels). TGRA can be set as an output compare register. TGRB, TGRC, and TGRD for each channel can also be used as timer counter clearing registers. TGRC and TGRD can also be used as buffer registers. * Selection of four counter input clocks for channels 0 and 1, and of six counter input clocks for channels 2 and 3. * The following operations can be set for each channel: Waveform output at compare match: Selection of 0, 1, or toggle output Counter clear operation: Counter clearing possible by compare match PWM mode: Any PWM output duty can be set Maximum of 4-phase PWM output possible * Buffer operation settable for each channel Automatic rewriting of output compare register possible * Phase counting mode settable independently for each of channels 2, and 3 Two-phase encoder pulse up/down-count possible * An interrupt request for each channel For channels 0 and 1, compare match interrupts and overflow interrupts can be requested independently For channels 2, and 3, compare match interrupts, overflow interrupts, and underflow interrupts can be requested independently Table 20.1 lists the functions of the TPU.
Rev. 1.00 Oct. 01, 2007 Page 707 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Table 20.1 TPU Functions
Item Count clock Channel 0 Pck0/1 Pck0/4 Pck0/16 Pck0/64 General registers General registers/ buffer registers Output pins Counter clear function Compare 0 output match output 1 output Toggle output TGR0A TGR0B TGR0C TGR0D TPU_TO0 TGR compare match Channel 1 Pck0/1 Pck0/4 Pck0/16 Pck0/64 TGR1A TGR1B TGR1C TGR1D TPU_TO1 TGR compare match Channel 2 Pck0/1 Pck0/4 Pck0/16 Pck0/64 TPU_TI2A TPU_TI2B TGR2A TGR2B TGR2C TGR2D TPU_TO2 TGR compare match Channel 3 Pck0/1 Pck0/4 Pck0/16 Pck0/64 TPU_TI3A TPU_TI3B TGR3A TGR3B TGR3C TGR3D TPU_TO3 TGR compare match
PWM mode Phase counting mode Buffer operation Interrupt sources 5 sources * * Compare match Overflow 5 sources * * Compare match Overflow 6 sources * * * Compare match Overflow Underflow 6 sources * * * Compare match Overflow Underflow
[Legend] : Possible : Not possible Note: TPU_TI2B and TPU_TI3B are used as count clocks only in phase counting mode.
Rev. 1.00 Oct. 01, 2007 Page 708 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Figure 20.1 shows a block diagram of the TPU.
Pck0
Divider
Pck0/1 Pck0/4 Pck0/16 Pck0/64
Clock selection
Edge selection
Counter up Output control
TPU_TO0
Channel 0
Note 1 clear
TGRA Comparator
TGRC TGRD
Channel 1
Same as channel 0
Selecter
TGRB
Buffer
TPU_TO1
selector
Clock selection
Edge selection
Counter up Output control
TPU_TO2
TPU_TI2A TPU_TI2B
Phase comparison down clear Note 1
Channel 2
TGRA
Comparator
TGRC TGRD
Selector
TGRB
Buffer
Note 1: Output disabled Initial value 0, 1 Compare match 0, 1, toggle
TPU_TI3A TPU_TI3B
Channel 3
Same as channel 2
TPU_TO3
Figure 20.1 Block Diagram of TPU
Rev. 1.00 Oct. 01, 2007 Page 709 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.2
Input/Output Pins
Table 20.2 summarizes the TPU related external pins. Table 20.2 TPU Pin Configurations
Channel 0 1 2 Name Output compare match 0 Output compare match 1 Output compare match 2A Clock input 2A Clock input 2B 3 Output compare match 3A Clock input 3A Clock input 3B Pin Name TPU_TO0 TPU_TO1 TPU_TO2 TPU_TI2A TPU_TI2B TPU_TO3 TPU_TI3A TPU_TI3B I/O Function
Output TGR0A output compare output/PWM output pin Output TGR1A output compare output/PWM output pin Output TGR2A output compare output/PWM output pin Input Input External clock channel 2A input pin /channel 2 counting mode A phase input Channel 2 counting mode B phase input
Output TGR3A output compare output/PWM output pin Input Input External clock channel 3A input pin /channel 3 counting mode A phase input Channel 3 counting mode B phase input
Rev. 1.00 Oct. 01, 2007 Page 710 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.3
Register Descriptions
Table 20.3 shows the TPU register configuration. Table 20.4 shows the register state in each operating mode. Table 20.3 Register Configuration
Register Name Timer start register Timer control register_0 Timer mode register_0 Timer I/O control register_0 Abbreviation TSTR TCR_0 TMDR_0 TIOR_0 R/W R/W R/W R/W R/W R/W R/W R R R R R R/W R/W R/W R/W R/W R R R R R R/W R/W R/W Area P4 Address* H'FFE2 8000 H'FFE2 8010 H'FFE2 8014 H'FFE2 8018 Area 7 Address* H'1FE2 8000 H'1FE2 8010 H'1FE2 8014 H'1FE2 8018 Access Size 16 16 16 16
Timer interrupt enable register_0 TIER_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1
H'FFE2 801C H'1FE2 801C 16 H'FFE2 8020 H'FFE2 8024 H'FFE2 8028 H'1FE2 8020 H'1FE2 8024 H'1FE2 8028 16 16 16
H'FFE2 802C H'1FE2 802C 16 H'FFE2 8030 H'FFE2 8034 H'FFE2 8050 H'FFE2 8054 H'FFE2 8058 H'1FE2 8030 H'1FE2 8034 H'1FE2 8050 H'1FE2 8054 H'1FE2 8058 16 16 16 16 16
Timer interrupt enable register_1 TIER_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer general register C_1 Timer general register D_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 TSR_1 TCNT_1 TGRA_1 TGRB_1 TGRC_1 TGRD_1 TCR_2 TMDR_2 TIOR_2
H'FFE2 805C H'1FE2 805C 16 H'FFE2 8060 H'FFE2 8064 H'FFE2 8068 H'1FE2 8060 H'1FE2 8064 H'1FE2 8068 16 16 16
H'FFE2 806C H'1FE2 806C 16 H'FFE2 8070 H'FFE2 8074 H'FFE2 8090 H'FFE2 8094 H'FFE2 8098 H'1FE2 8070 H'1FE2 8074 H'1FE2 8090 H'1FE2 8094 H'1FE2 8098 16 16 16 16 16
Rev. 1.00 Oct. 01, 2007 Page 711 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Register Name Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Timer general register C_2 Timer general register D_2 Timer control register_3 Timer mode register_3 Timer I/O control register_3 Timer interrupt enable register_3 Timer status register_3 Timer counter_3 Timer general register A_3 Timer general register B_3 Timer general register C_3 Timer general register D_3 Note: *
Abbreviation TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TGRC_2 TGRD_2 TCR_3 TMDR_3 TIOR_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3
R/W R/W R/W R R R R R R/W R/W R/W R/W R/W R R R R R
Area P4 Address*
Area 7 Address*
Access Size
H'FFE2 809C H'1FE2 809C 16 H'FFE2 80A0 H'1FE2 80A0 H'FFE2 80A4 H'1FE2 80A4 H'FFE2 80A8 H'1FE2 80A8 16 16 16
H'FFE2 80AC H'1FE2 80AC 16 H'FFE2 80B0 H'1FE2 80B0 H'FFE2 80B4 H'1FE2 80B4 16 16
H'FFE2 80D0 H'1FE2 80D0 16 H'FFE2 80D4 H'1FE2 80D4 16 H'FFE2 80D8 H'1FE2 80D8 16 H'FFE2 80DC H'1FE2 80DC 16 H'FFE2 80E0 H'1FE2 80E0 H'FFE2 80E4 H'1FE2 80E4 H'FFE2 80E8 H'1FE2 80E8 16 16 16
H'FFE2 80EC H'1FE2 80EC 16 H'FFE2 80F0 H'FFE2 80F4 H'1FE2 80F0 H'1FE2 80F4 16 16
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
Rev. 1.00 Oct. 01, 2007 Page 712 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Table 20.4 Register State in Each Operating Mode
Register Name Timer start register Timer control register_0 Timer mode register_0 Timer I/O control register_0 Abbreviation TSTR TCR_0 TMDR_0 TIOR_0 Power-On Manual Reset Reset H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Timer interrupt enable register_0 TIER_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1
Timer interrupt enable register_1 TIER_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer general register C_1 Timer general register D_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 TSR_1 TCNT_1 TGRA_1 TGRB_1 TGRC_1 TGRD_1 TCR_2 TMDR_2 TIOR_2
Timer interrupt enable register_2 TIER_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 TSR_2 TCNT_2 TGRA_2 TGRB_2
Rev. 1.00 Oct. 01, 2007 Page 713 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Register Name Timer general register C_2 Timer general register D_2 Timer control register_3 Timer mode register_3 Timer I/O control register_3 Timer interrupt enable register_3 Timer status register_3 Timer counter_3 Timer general register A_3 Timer general register B_3 Timer general register C_3 Timer general register D_3
Abbreviation TGRC_2 TGRD_2 TCR_3 TMDR_3 TIOR_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3
Power-On Manual Reset Reset H'FFFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'FFFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 714 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.3.1
Timer Control Registers (TCR)
The TCR registers are 16-bit registers that control the TCNT channels. The TPU has four TCR registers, one for each of channels 0 to 3. The TCR registers are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or module standby. TCR register settings should be made only when TCNT operation is stopped.
Bit: 15
14
0 R
13
0 R
12
0 R
11
0 R
10
0 R
9
0 R
8
0 R
7
6
CCLR[2:0]
5
4
3
2
1
TPSC[2:0]
0
CKEG[1:0] 0 R/W 0 R/W
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R R/W
Description Reserved These bits are always read as 0 and cannot be modified. Counter Clear These bits select the TCNT counter clearing source. 000: TCNT clearing disabled 001: TCNT cleared by TGRA compare match 010: TCNT cleared by TGRB compare match 011: Reserved (setting prohibited) 100: TCNT clearing disabled 101: TCNT cleared by TGRC compare match 110: TCNT cleared by TGRD compare match 111: Reserved (setting prohibited)
15 to 8 7 to 5
CCLR[2:0] 000
Rev. 1.00 Oct. 01, 2007 Page 715 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Bit 4, 3
Bit Name
Initial Value
R/W R/W
Description Clock Edge These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). If phase counting mode is used this setting is ignored. 00: Count at rising edge 01: Count at falling edge 1X: Count at both edges* [Legend] X: Don't care Note: * If Pck0/1 is selected for the input clock, operation is disabled.
CKEG[1:0] 00
2 to 0
TPSC[2:0] 000
R/W
Time Prescaler These bits select the TCNT counter clock. The clock source can be selected independently for each channel. Table 20.5 shows the clock sources that can be set for each channel. For more in formation on count clock selection, see table 20.6.
Table 20.5 TPU Clock Sources
Internal Clock Channel 0 1 2 3 [Legend] : Setting Blank : No setting Pck0/1 Pck0/4 Pck0/16 Pck0/64 External Clock TPU_TI2A TPU_TI3A
Rev. 1.00 Oct. 01, 2007 Page 716 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Table 20.6 TPSC[2:0] (1)
Channel 0 TPSC[2] 0 TPSC[1] 0 TPSC[0] 0 1 1 0 1 1 * * Description Internal clock: counts on Pck0/1 Internal clock: counts on Pck0/4 Internal clock: counts on Pck0/16 Internal clock: counts on Pck0/64 Reserved (setting prohibited) (Initial value)
Table 20.6 TPSC[2:0] (2)
Channel 1 TPSC[2] 0 TPSC[1] 0 TPSC[0] 0 1 1 0 1 1 * * Description Internal clock: counts on Pck0/1 Internal clock: counts on Pck0/4 Internal clock: counts on Pck0/16 Internal clock: counts on Pck0/64 Reserved (setting prohibited) (Initial value)
Table 20.6 TPSC[2:0] (3)
Channel 2 TPSC2 0 TPSC1 0 TPSC0 0 1 1 0 1 1 0 0 1 1 * Description Internal clock: counts on Pck0/1 Internal clock: counts on Pck0/4 Internal clock: counts on Pck0/16 Internal clock: counts on Pck0/64 External clock: counts on TPU_TI2A pin input Reserved (setting prohibited) (Initial value)
Rev. 1.00 Oct. 01, 2007 Page 717 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Table 20.6 TPSC[2:0] (4)
Channel 3 TPSC2 0 TPSC1 0 TPSC0 0 1 1 0 1 1 0 0 1 1 Note: * Don't care * Description Internal clock: counts on Pck0/1 Internal clock: counts on Pck0/4 Internal clock: counts on Pck0/16 Internal clock: counts on Pck0/64 External clock: counts on TPU_TI3A pin input Reserved (setting prohibited) (Initial value)
Rev. 1.00 Oct. 01, 2007 Page 718 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.3.2
Timer Mode Registers (TMDR)
The TMDR registers are 16-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has four TMDR registers, one for each channel. The TMDR registers are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or module standby. TMDR register settings should be made only when TCNT operation is stopped.
Bit: 15
14
0 R
13
0 R
12
0 R
11
0 R
10
0 R
9
0 R
8
0 R
7
0 R
6
5
4
BFA 0 R/W
3
0 R
2
1
MD[2:0]
0
BFWT BFB 0 R/W 0 R/W
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0 0
R/W R R/W
Description Reserved These bits are always read as 0 and cannot be modified. Buffer Write Timing Specifies TGRA and TGRB update timing when TGRC and TGRD are used as a compare match buffer. When TGRC and TGRD are not used as a compare match buffer register, this bit does not function. 0: TGRA and TGRB are rewritten at compare match of each register. 1: TGRA and TGRB are rewritten in counter clearing.
15 to 7 6 BFWT
5
BFB
0
R/W
Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation*
4
BFA
0
R/W
Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation
Rev. 1.00 Oct. 01, 2007 Page 719 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Bit 3 2 to 0
Bit Name MD[2:0]
Initial Value 0 000
R/W R R/W
Description Reserved This bit is always read as 0 and cannot be modified. Modes These bits are used to set the timer operating mode. 000: Normal operation 001: Reserved (setting prohibited) 010: PWM mode 011: Reserved (setting prohibited) 100: Phase counting mode 1 101: Phase counting mode 2 110: Phase counting mode 3 111: Phase counting mode 4
Note:
*
Operation when setting (BFWT, BFB, BFA) = (1, 1, 0) is the same as when setting (BFWT, BFB, BFA) = (1, 0, 1). However, when the BFB bit is set to 1 (TGRB and TGRD used together for buffer operation), the setting of (BFWT, BFB, BFA) = (1, 1, 1) should be made. In this case, the value set in TGRA should also be set in TGRC because TGRA and TGRC are also used together for buffer operation.
Rev. 1.00 Oct. 01, 2007 Page 720 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.3.3
Timer I/O Control Registers (TIOR)
The TIOR registers are 16-bit registers that control the TPU_TO pin. The TPU has four TIOR registers, one for each channel. The TIOR registers are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or module standby. TIOR register settings should be made only when TCNT operation is halted. Care is required since TIOR is affected by the TMDR setting. If the counting operation is halted, the initial value set by this register is output from the TPU_TO pin.
Bit:
15
14
0 R
13
0 R
12
0 R
11
0 R
10
0 R
9
0 R
8
0 R
7
0 R
6
0 R
5
0 R
4
0 R
3
0 R
2
1
IOA[2:0]
0
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0 000
R/W R R/W
Description Reserved These bits are always read as 0 and cannot be modified. I/O Control Bits IOA3 to IOA0 specify the functions of TGRA and the TPU_TO pin. For details, see table 20.7.
15 to 3 2 to 0 IOA[2:0]
Rev. 1.00 Oct. 01, 2007 Page 721 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Table 20.7 IOA[2:0]
Channels IOA[2] IOA[1] IOA[0] Description 0 to 3 0 0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 This setting is invalid in PWM mode. Always 1 output Initial output is 1 output for TPU_TO pin 0 output at TGRA compare match 1 output at TGRA compare match* Toggle output at TGRA compare match* Always 0 output (Initial value) Initial output is 0 output for TPU_TO pin 0 output at TGRA compare match* 1 output at TGRA compare match Toggle output TGRA at compare match*
Rev. 1.00 Oct. 01, 2007 Page 722 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.3.4
Timer Interrupt Enable Registers (TIER)
The TIER registers are 16-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has four TIER registers, one for each channel. The TIER registers are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode or module standby.
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TC1EU TC1EV TG1ED TG1EC TG1EB TG1EA
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value 0 0
R/W R R/W
Description Reserved These bits are always read as 0 and cannot be modified. Underflow Interrupt Enable Enables or disables interrupt requests by the TCFU bit when the TCFU bit in TSR is set to 1 in phase counting mode of channels 2, and 3 (TCNT underflow). In channels 0 and 1, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests by TCFU disabled 1: Interrupt requests by TCFU enabled
15 to 6 5 TC1EU
4
TC1EV
0
R/W
Overflow Interrupt Enable Enables or disables interrupt requests by the TCFV bit when the TCFV bit in TSR is set to 1 (TCNT overflow). 0: Interrupt requests by TCFV disabled 1: Interrupt requests by TCFV enabled
3
TG1ED
0
R/W
TGR Interrupt Enable D Enables or disables interrupt requests by the TGFD bit when the TGFD bit in TSR is set to (TCNT and TGRD compare match). 0: Interrupt requests by TGFD disabled 1: Interrupt requests by TGFD enabled
Rev. 1.00 Oct. 01, 2007 Page 723 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Bit 2
Bit Name TG1EC
Initial Value 0
R/W R/W
Description TGR Interrupt Enable C Enables or disables interrupt requests by the TGFC bit when the TGFC bit in TSR is set to 1 (TCNT and TGRC compare match). 0: Interrupt requests by TGFC disabled 1: Interrupt requests by TGFC enabled
1
TG1EB
0
R/W
TGR Interrupt Enable B Enables or disables interrupt requests by the TGFB bit when the TGFB bit in TSR is set to 1 (TCNT and TGRB compare match). 0: Interrupt requests by TGFB disabled 1: Interrupt requests by TGFB enabled
0
TG1EA
0
R/W
TGR Interrupt Enable A Enables or disables interrupt requests by the TGFA bit when the TGFA bit in TSR is set to 1 (TCNT and TGRA compare match). 0: Interrupt requests by TGFA disabled 1: Interrupt requests by TGFA enabled
Rev. 1.00 Oct. 01, 2007 Page 724 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.3.5
Timer Status Registers (TSR)
The TSR registers are 16-bit registers that indicate the status of each channel. The TPU has four TSR registers, one for each channel. The TSR registers are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode or module standby mode.
Bit: 15
14
0 R
13
0 R
12
0 R
11
0 R
10
0 R
9
0 R
8
0 R
7
TCFD 0 R
6
0 R
5
4
3
2
1
0
TCFU TCFV TGFD TGFC TGFB TGFA 0 0 0 0 0 0 R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value R/W All 0 0 R R
Description Reserved These bits are always read as 0 and cannot be modified. Count Direction Flag Status flag that shows the direction in which TCNT counts in phase counting mode of channels 2, and 3. In channels 0 and 1, bit 7 is reserved. It is always read as 0 and cannot be modified. 0: TCNT counts down 1: TCNT counts up
15 to 8 7 TCFD
6 5
TCFU
0 0
R
Reserved This bit is always read as 0 and cannot be modified.
R/(W)* Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 2, and 3 are set to phase counting mode. In channels 0 and 1, bit 5 is reserved. It is always read as 0 and cannot be modified. [Clearing condition] (Initial value) When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF)
Rev. 1.00 Oct. 01, 2007 Page 725 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Bit 4
Bit Name TCFV
Initial Value R/W 0
Description
R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000)
3
TGFD
0
R/(W)* Compare Flag D Status flag that indicates the occurrence of TGRD compare match. [Clearing conditions] When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] When TCNT = TGRD
2
TGFC
0
R/(W)* Compare Flag C Status flag that indicates the occurrence of TGRC compare match. [Clearing conditions] When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] When TCNT = TGRC
1
TGFB
0
R/(W)* Compare Flag B Status flag that indicates the occurrence of TGRB compare match. [Clearing conditions] When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] When TCNT = TGRB
Rev. 1.00 Oct. 01, 2007 Page 726 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Bit 0
Bit Name TGFA
Initial Value R/W 0
Description
R/(W)* Output Compare Flag A Status flag that indicates the occurrence of TGRA compare match. [Clearing conditions] When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] When TCNT = TGRA
Note:
*
Only 0 can be written, to clear the flag.
20.3.6
Timer Counters (TCNT)
The TCNT registers are 16-bit counters. The TPU has four TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset. The TCNT counters are not initialized in standby mode, sleep mode, or module standby. 20.3.7 Timer General Registers (TGR)
The TGR registers are 16-bit registers. The TPU has 16 TGR registers, four each for channels 0 and 3. TGRC and TGRD can also be designated for operation as buffer registers*. The TGR registers are initialized to H'FFFF by a reset. These registers are not initialized in standby mode, sleep mode, or module standby. Note: * TGR buffer register combinations are TGRA--TGRC and TGRB--TGRD.
Rev. 1.00 Oct. 01, 2007 Page 727 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.3.8
Timer Start Register (TSTR)
TSTR is a 16-bit readable/writable register that selects TCNT operation/stoppage for channels 0 to 3. TSTR is initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or module standby.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
CST3
2
CST2
1
CST1
0
CST0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0 0 0 0 0
R/W R R/W R/W R/W R/W
Description Reserved These bits are always read as 0 and cannot be modified. Counter Start These bits select operation or stoppage for TCNT. 0: TCNTn count operation is stopped) 1: TCNTn performs count operation n = 3 to 0
15 to 4 3 2 1 0 CST3 CST2 CST1 CST0
Rev. 1.00 Oct. 01, 2007 Page 728 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.4
20.4.1
Operation
Overview
Operation in each mode is outlined below. (1) Normal Operation
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. (2) Buffer Operation
When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR. For update timing from a buffer register, rewriting on compare match occurrence or on counter clearing can be selected. (3) PWM Mode
In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the setting of each TGR register. (4) Phase Counting Mode
In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input from the external clock input pins (TPU_TI2A and TPU_TI2B, or TPU_TI3A and TPU_TI3B) in channels 2, and 3. When phase counting mode is set, the corresponding TI pin functions as the clock pin, and TCNT performs up/down-counting. This can be used for two-phase encoder pulse input.
Rev. 1.00 Oct. 01, 2007 Page 729 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.4.2 (1)
Basic Functions
Counter Operation
When one of bits CST[0:3] is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. (a) Example of count operation setting procedure
Figure 20.2 shows an example of the count operation setting procedure.
Operation selection
Select counter clock
[1]
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Periodic counter
Free-running counter
Select counter clearing source
[2]
[2] For periodic counter operation, select the TGRA to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR.
Select output compare register
[3]
[3] Designate the output compare register by means of TIOR.
Set period
[4]
[4] Set the periodic counter cycle in the TGRA. Set external pin function [5] [5] Set the external pin function in pin function controller (PFC).
Set external pin function
[5]
Start count
[6]
Start count
[6]
[6] Set the CST bit in TSTR to 1 to start the counter operation.
Figure 20.2 Example of Counter Operation Setting Procedure
Rev. 1.00 Oct. 01, 2007 Page 730 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
(b)
Free-running count operation and periodic count operation
Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. After overflow, TCNT starts counting up again from H'0000. Figure 20.3 illustrates free-running counter operation.
TCNT value H'FFFF
H'0000
Time
CST bit
TCFV
Figure 20.3 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. After a compare match, TCNT starts counting up again from H'0000.
Rev. 1.00 Oct. 01, 2007 Page 731 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
Figure 20.4 illustrates periodic counter operation.
TCNT value TGR
Counter cleared by TGRA compare match
H'0000
Time
CST bit
Flag cleared by software
TGFA
Figure 20.4 Periodic Counter Operation (2) Waveform Output by Compare Match
The TPU can perform 0, 1, or toggle output from the corresponding output pin (TPU_TO pin) using TGRA compare match. (a) Example of setting procedure for waveform output by compare match
Figure 20.5 shows an example of the setting procedure for waveform output by compare match.
[1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TPU_TO pin until the first compare match occurs. [2] Set the timing for compare match generation in TGRA. [3] Set the external pin function in pin function controller (PFC). [4] Set the CST bit in TSTR to 1 to start the count operation.
Start count [4]
Output selection
Select waveform output mode
[1]
Set output timing
[2]
Set external pin function
[3]

Figure 20.5 Example of Setting Procedure for Waveform Output by Compare Match
Rev. 1.00 Oct. 01, 2007 Page 732 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
(b)
Examples of waveform output operation
Figure 20.6 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
TCNT value
H'FFFF
TGRA
H'0000
No change No change
Time
TPU_TO pin (1 output) TPU_TO pin (0 output)
No change No change
Figure 20.6 Example of 0 Output/1 Output Operation Figure 20.7 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by compare match A.
TCNT value
Counter cleared by TGRB compare match
H'FFFF TGRB TGRA H'0000
Toggle output Time
TPU_TO pin
Figure 20.7 Example of Toggle Output Operation
Rev. 1.00 Oct. 01, 2007 Page 733 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.4.3
Buffer Operation
Buffer operation, enables TGRC and TGRD to be used as buffer registers. Table 20.8 shows the register combinations used in buffer operation. Table 20.8 Register Combinations in Buffer Operation
Timer General Register TGRA TGRB Buffer Register TGRC TGRD
When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. For update timing from a buffer register, rewriting on compare match occurrence or on counter cleaning can be selected. This operation is illustrated in figure 20.8.
Counter cleaning signal BFWT bit Timer general register
Compare match signal
Buffer register
Comparator
TCNT
Figure 20.8 Compare Match Buffer Operation
Rev. 1.00 Oct. 01, 2007 Page 734 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
(1)
Example of Buffer Operation Setting Procedure
Figure 20.9 shows an example of the buffer operation setting procedure.
Buffer operation
[1] Designate TGR for buffer operation with bits BFA and BFB in TMDR.
[1]
Set buffer operation
[2] Set rewriting timing from the buffer register with bit BFWT in TMDR. [3] Set the external pin function in pin function controller (PFC). [4] Set the CST bit in TSTR to 1 to start the count operation.
Set rewriting timing
[2]
Set external pin function
[3]
Start count
[4]

Figure 20.9 Example of Buffer Operation Setting Procedure
Rev. 1.00 Oct. 01, 2007 Page 735 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
(2)
Example of Buffer Operation
Figure 20.10 shows an operation example in which PWM mode has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A (TPU_TO pin), and 0 output at counter clearing. Rewriting timing from the buffer register is set at counter clearing. As buffer operation has been set, when compare match A occurs the output changes. When counter clearing occurs by TGRB, the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details of PWM modes, see section 20.4.4, PWM Modes.
TCNT value TGRB N (TGRB+1) N (B) N (A) Time
TGRA H'0000 TGRC
N (A)
N (B)
N (TGRB+1)
TGRA
N (A)
N (B)
N (TGRB+1)
TPU_TO pin
Figure 20.10 Example of Buffer Operation
Rev. 1.00 Oct. 01, 2007 Page 736 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.4.4
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, or 1, output can be selected as the output level in response to compare match of each TGRA. Designating TGRB compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. PWM output is generated from the TPU_TO pin using TGRB as the period register and TGRA as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a period register compare match, the output value of each pin is the initial value set in TIOR. Set TIOR so that the initial output and an output value by compare match are different. If the same levels or toggle outputs are selected, operation is disabled. Conditions of duty 0% and 100% are shown below. * Duty 0% : The set value of the period register (TGRB) is TGRA + 1 for the duty register (TGRA). * Duty 100% : The set value of the duty register (TGRA) is 0.
In PWM mode 1, a maximum 4-phase PWM output is possible.
Rev. 1.00 Oct. 01, 2007 Page 737 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
(1)
Example of PWM Mode Setting Procedure
Figure 20.11 shows an example of the PWM mode setting procedure.
PWM mode
Select counter clock
[1]
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGRB to be used as the TCNT clearing source. [3] Use TIOR to select the initial value and output value. [4] Set the period in TGRB, and set the duty in TGRA. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the external pin function in pin function controller (PFC). [7] Set the CST bit in TSTR to 1 to start the count operation.
Select counter clearing source
[2]
Select waveform output level
[3]
Set period
[4]
Set PWM mode
[5]
Set external pin function
[6]
Start count
[7]

Figure 20.11 Example of PWM Mode Setting Procedure
Rev. 1.00 Oct. 01, 2007 Page 738 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
(2)
Examples of PWM Mode Operation
Figure 20.12 shows an example of PWM mode operation. In this example, TGRB compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRA output value. In this case, the value set in TGRB is used as the period, and the value set in TGRA as the duty.
TCNT value TGRB
Counter cleared by TGRB compare match
TGRA
H'0000
Time
TPU_TO pin
Figure 20.12 Example of PWM Mode Operation (1) Figure 20.13 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
TCNT TGRA=0
2
0
1
2
0
TGRA=1 TGRA=2 TGRA=3
Rewrite timing for TGRA Period: TGRB=2
Figure 20.13 Examples of PWM Mode Operation (2)
Rev. 1.00 Oct. 01, 2007 Page 739 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.4.5
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 2, and 3. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and compare match and interrupt functions can be used. The previous set value (initial output value set before the timer was started in phase counting mode) is output from the TPU_TO pin in TIOR. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 20.9 shows the correspondence between external clock pins and channels. Table 20.9 Phase Counting Mode Clock Input Pins
External Clock Pins Channels When channel 2 is set to phase counting mode When channel 3 is set to phase counting mode A-Phase TPU_TI2A TPU_TI3A B-Phase TPU_TI2B TPU_TI3B
Rev. 1.00 Oct. 01, 2007 Page 740 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
(1)
Example of Phase Counting Mode Setting Procedure
Figure 20.14 shows an example of the phase counting mode setting procedure.
Phase counting mode
[1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the external pin function in pin function controller (PFC). [3] Set the CST bit in TSTR to 1 to start the count operation.
Select phase counting mode
[1]
Set external pin function
[2]
Start count
[3]

Figure 20.14 Example of Phase Counting Mode Setting Procedure
Rev. 1.00 Oct. 01, 2007 Page 741 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
(2)
Examples of Phase Counting Mode Operation
In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1
Figure 20.15 shows an example of phase counting mode 1 operation, and table 20.10 summarizes the TCNT up/down-count conditions.
TPU_TI2A (channel 2) TPU_TI3A (channel 3) TPU_TI2B (channels 2) TPU_TI3B (channels 3)
TCNT value Up-count Down-count
Time
Figure 20.15 Example of Phase Counting Mode 1 Operation Table 20.10 Up/Down-Count Conditions in Phase Counting Mode 1
TPU_TI2A (Channel 2) TPU_TI3A (Channel 3) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count TPU_TI2B (Channel 2) TPU_TI3B (Channel 3) Operation Up-count
Rev. 1.00 Oct. 01, 2007 Page 742 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
(b)
Phase counting mode 2
Figure 20.16 shows an example of phase counting mode 2 operation, and table 20.11 summarizes the TCNT up/down-count conditions.
TPU_TI2A (Channel 2) TPU_TI3A (Channel 3)
TPU_TI2B (Channel 2) TPU_TI3B (Channel 3)
TCNT value
Up-count Down-count
Time
Figure 20.16 Example of Phase Counting Mode 2 Operation Table 20.11 Up/Down-Count Conditions in Phase Counting Mode 2
TPU_TI2A (Channel 2) TPU_TI3A (Channel 3) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count Up-count Don't care TPU_TI2B (Channel 2) TPU_TI3B (Channel 3) Operation Don't care
Rev. 1.00 Oct. 01, 2007 Page 743 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
(c)
Phase counting mode 3
Figure 20.17 shows an example of phase counting mode 3 operation, and table 20.12 summarizes the TCNT up/down-count conditions.
TPU_TI2A (channel 2) TPU_TI3A (channel 3) TPU_TI2B (channel 2) TPU_TI3B (channel 3)
TCNT value
Up-count
Down-count
Time
Figure 20.17 Example of Phase Counting Mode 3 Operation Table 20.12 Up/Down-Count Conditions in Phase Counting Mode 3
TPU_TI2A (Channel 2) TPU_TI3A (Channel 3) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Up-count Down-count Don't care TPU_TI2B (Channel 2) TPU_TI3B (Channel 3) Operation Don't care
Rev. 1.00 Oct. 01, 2007 Page 744 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
(d)
Phase counting mode 4
Figure 20.18 shows an example of phase counting mode 4 operation, and table 20.13 summarizes the TCNT up/down-count conditions.
TPU_TI2A (channel 2) TPU_TI3A (channel 3)
TPU_TI2B (channel 2) TPU_TI3B (channel 3)
TCNT value Down-count
Up-count
Time
Figure 20.18 Example of Phase Counting Mode 4 Operation Table 20.13 Up/Down-Count Conditions in Phase Counting Mode 4
TPU_TI2A (Channel 2) TPU_TI3A (Channel 3) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Don't care Down-count Don't care TPU_TI2B (Channel 2) TPU_TI3B (Channel 3) Operation Up-count
Rev. 1.00 Oct. 01, 2007 Page 745 of 1956 REJ09B0256-0100
Section 20 16-Bit Timer Pulse Unit (TPU)
20.5
Usage Notes
Note that the kinds of operation and contention described below can occur during TPU operation. (1) Input Clock Restrictions
The input clock pulse width must be at least 2 states in the case of single-edge detection, and at least 3 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 2 states, and the pulse width must be at least 3 states. Figure 20.19 shows the input clock conditions in phase counting mode.
Overlap TPU_TCLKA (TPU_TCLKC)
TPU_TCLKB (TPU_TCLKD)
Phase Phase differdifference Overlap ence
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 2 states or more : 3 states or more Pulse width
Figure 20.19 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev. 1.00 Oct. 01, 2007 Page 746 of 1956 REJ09B0256-0100
Section 21 Compare Match Timer (CMT)
Section 21 Compare Match Timer (CMT)
This LSI includes a 32-bit compare match timer (CMT) of five channels (channel 0 to channel 4).
21.1
Features
* 16 bits/32 bits can be selected. * Each channel is provided with an auto-reload up counter. * All channels are provided with 32-bit constant registers and 32-bit up counters that can be written or read at any time. * Allows selection among three counter input clocks for channel 0 to channel 4: Peripheral clock (Pck0): 1/8, 1/32, and 1/128 * One-shot operation and free-running operation are selectable. * Allows selection of compare match or overflow for the interrupt source. * Generate a DMA transfer request when compare match or overflow occurs in channels 0 to 4. * Module standby mode can be set.
Rev. 1.00 Oct. 01, 2007 Page 747 of 1956 REJ09B0256-0100
Section 21 Compare Match Timer (CMT)
Figure 21.1 shows a block diagram of the CMT.
CMSTR Pck0
CMT
Pre-scaller
CH0
CMCNT_0
CMCOR_0
CMCSR_0
Interrupt control
Internal interrupt DMA transfer
Pre-scaller
CH1
CMCNT_1
CMCOR_1
CMCSR_1
Interrupt control
Internal interrupt DMA transfer
Pre-scaller
CH2
CMCNT_2
CMCOR_2
CMCSR_2
Interrupt control
Internal interrupt DMA transfer
Pre-scaller
CH3
CMCNT_3
CMCOR_3
CMCSR_3
Interrupt control
Internal interrupt DMA transfer
Pre-scaller
CH4
CMCNT_4
CMCOR_4
CMCSR_4
Interrupt control
Internal interrupt DMA transfer
[Legend] CMSTR: Compare match timer start register CMCSR: Compare match timer control/status register
CMCNT: Compare match timer counter CMCOR: Compare match timer constant register
Figure 21.1 Block Diagram of CMT
Rev. 1.00 Oct. 01, 2007 Page 748 of 1956 REJ09B0256-0100
Peripheral bus
Section 21 Compare Match Timer (CMT)
21.2
Register Descriptions
Table 21.2 shows the CMT register configuration. Table 21.3 shows the register state in each operating mode. Table 21.1 Register Configuration
Register Name Compare match timer start register Abbreviation R/W CMSTR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Area P4 Address* Area 7 Address* Access Size
H'FFE2 0000 H'1FE2 0000 16 H'FFE2 0010 H'1FE2 0010 16 H'FF20 0014 H'1F20 0014 32 H'FF20 0018 H'1F20 0018 32 H'FFE2 0020 H'1FE2 0020 16 H'FF20 0024 H'1F20 0024 32 H'FF20 0028 H'1F20 0028 32 H'FFE2 0030 H'1FE2 0030 16 H'FF20 0034 H'1F20 0034 32 H'FF20 0038 H'1F20 0038 32 H'FFE2 0040 H'1FE2 0040 16 H'FF20 0044 H'1F20 0044 32 H'FF20 0048 H'1F20 0048 32 H'FFE2 0050 H'1FE2 0050 16 H'FF20 0054 H'1F20 0054 32 H'FF20 0058 H'1F20 0058 32
Compare match timer control/status CMCSR_0 register_0 Compare match timer counter_0 Compare match timer constant register_0 CMCNT_0 CMCOR_0
Compare match timer control/status CMCSR_1 register_1 Compare match timer counter_1 Compare match timer constant register_1 CMCNT_1 CMCOR_1
Compare match timer control/status CMCSR_2 register_2 Compare match timer counter_2 Compare match timer constant register_2 CMCNT_2 CMCOR_2
Compare match timer control/status CMCSR_3 register_3 Compare match timer counter_3 Compare match timer constant register_3 CMCNT_3 CMCOR_3
Compare match timer control/status CMCSR_4 register_4 Compare match timer counter_4 Compare match timer constant register_4 Note: * CMCNT_4 CMCOR_4
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
Rev. 1.00 Oct. 01, 2007 Page 749 of 1956 REJ09B0256-0100
Section 21 Compare Match Timer (CMT)
Table 21.2 Register State in Each Operating Mode
Register Name Compare match timer start register Compare match timer control/status register_0 Compare match timer counter_0 Compare match timer constant register_0 Compare match timer control/status register_1 Compare match timer counter_1 Compare match timer constant register_1 Compare match timer control/status register_2 Compare match timer counter_2 Compare match timer constant register_2 Compare match timer control/status register_3 Compare match timer counter_3 Compare match timer constant register_3 Compare match timer control/status register_4 Compare match timer counter_4 Compare match timer constant register_4 Power-On Abbreviation Reset CMSTR CMCSR_0 CMCNT_0 CMCOR_0 CMCSR_1 CMCNT_1 CMCOR_1 CMCSR_2 CMCNT_2 CMCOR_2 CMCSR_3 CMCNT_3 CMCOR_3 CMCSR_4 CMCNT_4 CMCOR_4 H'0000 H'0000 H'0000 0000 H'FFFF FFFF H'0000 H'0000 0000 H'FFFF FFFF H'0000 H'0000 0000 H'FFFF FFFF H'0000 H'0000 0000 H'FFFF FFFF H'0000 H'0000 0000 H'FFFF FFFF Manual Reset H'0000 H'0000 Sleep Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
H'0000 0000 Retained H'FFFF FFFF Retained H'0000 Retained
H'0000 0000 Retained H'FFFF FFFF Retained H'0000 Retained
H'0000 0000 Retained H'FFFF FFFF Retained H'0000 Retained
H'0000 0000 Retained H'FFFF FFFF Retained H'0000 Retained
H'0000 0000 Retained H'FFFF FFFF Retained
Rev. 1.00 Oct. 01, 2007 Page 750 of 1956 REJ09B0256-0100
Section 21 Compare Match Timer (CMT)
21.2.1
Compare Match Timer Start Register (CMSTR)
CMSTR is a 16-bit register that selects whether the compare match timer counter (CMCNT) is operated or halted.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
STR[4:0]
1
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 5
4 to 0
STR[4:0]
All 0
R/W
Count Start Selects whether to operate or halt the compare match timer counter for each channel (CMCNT_4 to CMCNT_0). 0: CMCNTn count operation halted 1: CMCNTn count operation n: 4 to 0 (corresponds to each channel)
Rev. 1.00 Oct. 01, 2007 Page 751 of 1956 REJ09B0256-0100
Section 21 Compare Match Timer (CMT)
21.2.2
Compare Match Timer Control/Status Register (CMCSR)
CMCSR is a 16-bit register that indicates the occurrence of compare matches, enables interrupts and DMA transfer request, and sets the counter input clocks. Do not change bits other than bits CMF and OVF during the compare match timer counter (CMCNT) operation.
Bit:
15
CMF
14
OVF
13
12
11
10
9
CMS
8
CMM
7
6
5
4
3
2
1
CKS[2:0]
0
CMR[1:0]
0 Initial value: 0 R/W: R/(W)* R/(W)*
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R
0 R
0 R/W
0 R/W
0 R
0 R/W
0 R/W
0 R/W
Bit 15
Bit Name CMF
Initial Value 0
R/W
1
Description
R/(W)* Compare Match Flag This flag indicates whether or not values of the compare match timer counter (CMCNT) and compare match timer constant register (CMCOR) have matched. Software cannot write 1 to the bit. When one-shot is selected for the counter operation, counting resumes by clearing this bit. 0: CMCNT and CMCOR values have not matched [Clearing condition] * Write 0 to CMF after reading CMF=1 1: CMCNT and CMCOR values have matched
14
OVF
0
R/(W)*1 Overflow Flag This flag indicates whether or not the compare match timer counter (CMCNT) has overflowed and been cleared to 0. Software cannot write 1 to this bit. 0: CMCNT has not overflowed [Clearing condition] * Write 0 to OVF after reading OVF=1 1: CMCNT has overflowed
Rev. 1.00 Oct. 01, 2007 Page 752 of 1956 REJ09B0256-0100
Section 21 Compare Match Timer (CMT)
Bit
Initial Bit Name Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13 to 10
9
CMS
0
R/W
Compare Match Timer Counter Size Selects whether the compare match timer counter (CMCNT) is used as a 16-bit counter or a 32-bit counter. This setting becomes the valid size for the compare match timer constant register (CMCOR). 0: Operates as a 32-bit counter 1: Operates as a 16-bit counter
8
CMM
0
R/W
Compare Match Mode Selects one-shot operation or free-running operation of the counter. 0: One-shot operation 1: Free-running operation
7, 6
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
5, 4
CMR[1:0] 00
R/W
Compare Match Request Selects enable or disable for a DMA transfer request or internal interrupt request in a compare match. 00: Disables a DMA transfer request and internal interrupt request 01: Enables DMA transfer request 10: Enables an internal interrupt request 11: Setting prohibited
3
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 753 of 1956 REJ09B0256-0100
Section 21 Compare Match Timer (CMT)
Bit 2 to 0
Initial Bit Name Value CKS[2:0] All 0
R/W R/W
Description Clock Select These bits select the clock input to CMCNT. When the STRn (n: 4 to 0) bit in CMSTR is set to 1, CMCNT begins incrementing with the clock selected by these bits. 000: Pck0/8 001: Pck0/32 010: Pck0/128 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
Note:
*
Only 0 can be written to clear the flag.
21.2.3
Compare Match Timer Counter (CMCNT)
CMCNT is a 32-bit register that is used as an up-counter. A counter operation is set by the compare match timer control/status register (CMCSR). Therefore, set CMCSR first, before starting a channel operation corresponding to the compare match timer start register (CMSTR). When the 16-bit counter operation is selected by the CMS bit, bits 15 to 0 of this register become valid. When the register should be written to, write the data that is added H'0000 to the upper half in a 32-bit operation. The contents of this register are initialized to H'00000000. 21.2.4 Compare Match Timer Constant Register (CMCOR)
CMCOR is a 32-bit register that sets the compare match period with CMCNT for each channel. When the 16-bit counter operation is selected by the CMS bit in CMCSR, bits 15 to 0 of this register become valid. When the register should be written to, write the data that is added H'0000 to the upper half in a 32-bit operation. An overflow is detected when CMCNT is cleared to 0 and this register is H'FFFFFFFF. The contents of this register are initialized to H'FFFFFFFF.
Rev. 1.00 Oct. 01, 2007 Page 754 of 1956 REJ09B0256-0100
Section 21 Compare Match Timer (CMT)
21.3
21.3.1
Operation
Counter Operation
The CMT starts the operation of the counter by writing a 1 to the STRn bit in CMSTR of a channel that has been selected for operation. Complete all of the settings before starting the operation. Do not change the register settings other than by clearing flag bits. The counter operates in one of two ways. * One-Shot Operation One-shot operation is selected by setting the CMM bit in CMCSR to 0. When the value in CMCNT matches the value in CMCOR, the value in CMCNT is cleared to H'00000000 and the CMF bit in CMCSR is set to 1. Counting by CMCNT stops after it has been cleared. To detect an overflow interrupt, set the value in CMCOR to H'FFFFFFFF. When the value in CMCNT matches the value in CMCOR, CMCNT is cleared to H'00000000 and bits CMF and OVF in CMCSR are set to 1.
Value in CMCNT CMCOR
H'00000000 Time CMF = 1 OVF = 1 (When an overflow is detected)
Figure 21.2 Counter Operation (One-Shot Operation) * Free-Running Operation Free-running operation is selected by setting the CMM bit in CMCSR to 1. When the value in CMCNT matches the value in CMCOR, CMCNT is cleared to H'00000000 and the CMF bit in CMCSR is set to 1. CMCNT resumes counting-up after it has been cleared. To detect an overflow interrupt, set CMCOR to H'FFFFFFFF. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'00000000 and bits CMF and OVF in CMCSR are set to 1.
Rev. 1.00 Oct. 01, 2007 Page 755 of 1956 REJ09B0256-0100
Section 21 Compare Match Timer (CMT)
Value in CMCNT
CMCOR
H'00000000 Time
CMF=1 OVF=1 (When an overflow is detected)
Figure 21.3 Counter Operation (Free-Running Operation) 21.3.2 Counter Size
In this module, the size of the counter is selectable as either 16 or 32 bits. This is selected by the CMS bit in CMCSR. When the 16-bit size is selected, use a 32-bit value which has H'0000 as its upper half to set CMCOR. To detect an overflow interrupt, the value must be set to H'0000FFFF. 21.3.3 Timing for Counting by CMCNT
In this module, the clock for the counter can be selected from among the following: * For channels 0 to 4: Peripheral clock (Pck0): 1/8, 1/32, or 1/128
The clock for the counter is selected by bits CKS2 to CKS0 in CMCSR. CMCNT is incremented at the rising edge of the selected clock.
Rev. 1.00 Oct. 01, 2007 Page 756 of 1956 REJ09B0256-0100
Section 21 Compare Match Timer (CMT)
21.3.4
DMA Transfer Requests and Internal Interrupt Requests to CPU
The setting of bits CMR1 and CMR0 in CMCSR selects the sending of a request for a DMA transfer or for an internal interrupt to the CPU at a compare match. A DMA transfer request has different specifications according to the CMT channel as described below. 1. For channels 0 and 1, a single DMA transfer request is output at a compare match. 2. For channels 2 to 4, a DMA transfer request continues until the amount of data transferred has reached the value set in the DMAC, and the output of the request then automatically stops. To clear the interrupt request, the CMF bit should be set to 0. Set the CMF bit to 0 in the handling routine for the CMT interrupt. 21.3.5 Compare Match Flag Set Timing (All Channels)
The CMF bit in CMCSR is set to 1 by the compare match signal generated when CMCOR and CMCNT match. The compare match signal is generated upon the final state of the match (timing at which the CMCNT value is updated to H'0000). Consequently, after CMCOR and CMCNT match, a compare match signal will not be generated until a CMCNT counter clock is input. Figure 21.4 shows the set timing of the CMF bit.
Peripheral operating clock (Pck0)
Counter clock
N+1 clock
CMCNT
N
0
CMCOR
N
Compare match signal and interrupt signal
Figure 21.4 CMF Set Timing
Rev. 1.00 Oct. 01, 2007 Page 757 of 1956 REJ09B0256-0100
Section 21 Compare Match Timer (CMT)
Rev. 1.00 Oct. 01, 2007 Page 758 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
Section 22 Realtime Clock (RTC)
This LSI includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillator for use by the RTC.
22.1
Features
The RTC has the following features. * Clock and calendar functions (BCD display) Counts seconds, minutes, hours, day-of-week, days, months, and years. * 1 to 64 Hz timer (binary display) The 64 Hz counter register indicates a state of 64 Hz to 1 Hz within the RTC frequency divider * Start/stop function * 30-second adjustment function * Alarm interrupts Comparison with second, minute, hour, day-of-week, day, month, or year can be selected as the alarm interrupt condition * Periodic interrupts An interrupt period of 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds can be selected * Carry interrupt Carry interrupt function indicating a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read * Automatic leap year adjustment
Rev. 1.00 Oct. 01, 2007 Page 759 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.1.1
Block Diagram
Figure 22.1 shows a block diagram of the RTC.
RTC clock output
ATI PRI CUI
Reset
16.384 kHz
Prescaler
32.768 kHz
RTC crystal oscillator
RTC operation control unit
128 kHz RCR1 RCR2
Counter unit
R64CNT
Interr upt control unit
RCR3
RSECCNT
RMINCNT
RHRCNT
RDAYCNT
RWKCNT
RMONCNT
RYRCNT
RSECAR
RMINAR
RHRAR
RDAYAR To registers
RWKAR
RMONAR
RYRAR
Bus interface
Internal peripheral module bus
Figure 22.1 Block Diagram of RTC
Rev. 1.00 Oct. 01, 2007 Page 760 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.2
Input/Output Pins
Table 22.1 shows the RTC pins. Table 22.1 RTC Pins
Pin Name RTC oscillator crystal pin RTC oscillator crystal pin Dedicated RTC power supply Dedicated RTC GND pin RTC standby Note: * Abbreviation EXTAL2 XTAL2 Vdd-RTC Vss-RTC XRTCSTBI I/O Input Output -- -- Input Function Connects crystal to RTC oscillator Connects crystal to RTC oscillator RTC oscillator power supply pin* RTC oscillator GND pin* RTC standby
Power must be supplied to the RTC power supply pins even when the RTC is not used.
Rev. 1.00 Oct. 01, 2007 Page 761 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.3
Register Descriptions
Table 22.2 shows the RTC register configuration. Table 22.3 shows the register state in each operating mode. Table 22.2 Register Configuration
Register Name 64 Hz counter Second counter Minute counter Hour counter Day-of-week counter Day counter Month counter Year counter Second alarm register Minute alarm register Hour alarm register Day-of-week alarm register Day alarm register Month alarm register RTC control register 1 RTC control register 2 RTC control register 3 Year alarm register Note: * Abbreviation R/W R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 RCR3 RYRAR R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Area P4 Address* H'FFF8 0000 H'FFF8 0004 H'FFF8 0008 H'FFF8 000C H'FFF8 0010 H'FFF8 0014 H'FFF8 0018 H'FFF8 001C H'FFF8 0020 H'FFF8 0024 H'FFF8 0028 H'FFF8 002C H'FFF8 0030 H'FFF8 0034 H'FFF8 0038 H'FFF8 003C H'FFF8 0050 H'FFF8 0054 Area 7 Address* H'1FF8 0000 H'1FF8 0004 H'1FF8 0008 H'1FF8 000C H'1FF8 0010 H'1FF8 0014 H'1FF8 0018 H'1FF8 001C H'1FF8 0020 H'1FF8 0024 H'1FF8 0028 H'1FF8 002C H'1FF8 0030 H'1FF8 0034 H'1FF8 0038 H'1FF8 003C H'1FF8 0050 H'1FF8 0054 Access Size 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 16
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
Rev. 1.00 Oct. 01, 2007 Page 762 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
Table 22.3 Register State in Each Operating Mode
Name 64 Hz counter Second counter Minute counter Hour counter Day-of-week counter Day counter Month counter Year counter Abbreviation R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined* Undefined* Undefined*
1 1
Power-On Manual Reset Reset Counts Counts Counts Counts Counts Counts Counts Counts
1 1
Sleep Counts Counts Counts Counts Counts Counts Counts Counts
Standby Counts Counts Counts Counts Counts Counts Counts Counts
Counts Counts Counts Counts Counts Counts Counts Counts
Second alarm register RSECAR Minute alarm register Hour alarm register Day-of-week alarm register Day alarm register Month alarm register RMINAR RHRAR RWKAR RDAYAR RMONAR
Initialized* Retained Initialized* Retained Initialized* Retained Initialized*1 Retained Initialized*1 Retained Initialized* Retained Initialized Initialized Initialized Retained Initialized
2 1 1
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
1
Undefined*1 Undefined*1 Undefined* H'00* H'09* H'00 Undefined
3 4 1
RTC control register 1 RCR1 RTC control register 2 RCR2 RTC control register 3 RCR3 Year alarm register Notes: 1. 2. 3. 4. RYRAR
Initialized* Retained Retained Retained Retained Retained Retained Retained Retained
The ENB bit in each register is initialized. Bits other than the RTCEN bit and START bit are initialized. The value of the CF bit, CRF bit and AF bit is undefined. The value of the PEF bit is undefined.
Rev. 1.00 Oct. 01, 2007 Page 763 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.4
22.4.1
Register Descriptions
64 Hz Counter (R64CNT)
R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider. If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7 (CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read. In this case, the read value is not valid, and so R64CNT must be read again after first writing 0 to the CF bit in RCR1 to clear it. When the RESET bit or ADJ bit in RTC control register 2 (RCR2) is set to 1, the RTC frequency divider is initialized and R64CNT is initialized to H'00. R64CNT is not initialized by a power-on or manual reset. Bit 7 is always read as 0 and cannot be modified.
Bit: 7 -- Initial value: R/W: 0 R 6 1 Hz -- R 5 2 Hz -- R 4 4 Hz -- R 3 2 1 0
8 Hz 16 Hz 32 Hz 64 Hz -- R -- R -- R -- R
22.4.2
Second Counter (RSECCNT)
RSECCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded second value in the RTC. It counts on the carry (transition of the R64CNT.1Hz bit from 1 to 0) generated once per second by the 64 Hz counter. The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RSECCNT is not initialized by a power-on or manual reset. Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0.
Bit: 7 -- Initial value: R/W: 0 R 6 5 4 3 2 1 0
10-second units -- R/W -- R/W -- R/W -- R/W
1-second units -- R/W -- R/W -- R/W
Rev. 1.00 Oct. 01, 2007 Page 764 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.4.3
Minute Counter (RMINCNT)
RMINCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the second counter. The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RMINCNT is not initialized by a power-on or manual reset. Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0.
Bit: 7 -- Initial value: R/W: 0 R 6 5 4 3 2 1 0
10-minute units -- R/W -- R/W -- R/W -- R/W
1-minute units -- R/W -- R/W -- R/W
22.4.4
Hour Counter (RHRCNT)
RHRCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded hour value in the RTC. It counts on the carry generated once per hour by the minute counter. The setting range is decimal 00 to 23. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RHRCNT is not initialized by a power-on or manual reset. Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always be 0.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 4 3 2 1 0
10-hour units -- R/W -- R/W -- R/W
1-hour units -- R/W -- R/W -- R/W
Rev. 1.00 Oct. 01, 2007 Page 765 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.4.5
Day-of-Week Counter (RWKCNT)
RWKCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day-of-week value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 0 to 6. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RWKCNT is not initialized by a power-on or manual reset. Bits 7 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0
Day-of-week code -- R/W -- R/W -- R/W
Day-of-week code Day of week
0 Sun
1 Mon
2 Tue
3 Wed
4 Thu
5 Fri
6 Sat
Rev. 1.00 Oct. 01, 2007 Page 766 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.4.6
Day Counter (RDAYCNT)
RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 01 to 31. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RDAYCNT is not initialized by a power-on or manual reset. The setting range for RDAYCNT depends on the month and whether the year is a leap year, so care is required when making the setting. Taking the year counter (RYRCNT) value as the year, leap year calculation is performed according to whether or not the value is divisible by 400, 100, and 4. Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always be 0.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 4 3 2 1 0
10-day units -- R/W -- R/W -- R/W
1-day units -- R/W -- R/W -- R/W
Rev. 1.00 Oct. 01, 2007 Page 767 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.4.7
Month Counter (RMONCNT)
RMONCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded month value in the RTC. It counts on the carry generated once per month by the day counter. The setting range is decimal 01 to 12. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RMONCNT is not initialized by a power-on or manual reset. Bits 7 to 5 are always read as 0. A write to these bits is invalid, but the write value should always be 0.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4
10-month unit
3
2
1
0
1-month units -- R/W -- R/W -- R/W -- R/W
-- R/W
22.4.8
Year Counter (RYRCNT)
RYRCNT is a 16-bit readable/writable register used as a counter for setting and counting the BCD-coded year value in the RTC. It counts on the carry generated once per year by the month counter. The setting range is decimal 0000 to 9999. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RYRCNT is not initialized by a power-on or manual reset.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1000-year units Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W
100-year units -- R/W -- R/W -- R/W -- R/W
10-year units -- R/W -- R/W -- R/W -- R/W
1-year units -- R/W -- R/W -- R/W
Rev. 1.00 Oct. 01, 2007 Page 768 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.4.9
Second Alarm Register (RSECAR)
RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared with the RSECCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RSECAR is initialized to 0 by a power-on reset. The other fields in RSECAR are not initialized by a power-on or manual reset.
Bit: 7 ENB Initial value: R/W: 0 R/W 6 5 4 3 2 1 0
10-second units -- R/W -- R/W -- R/W -- R/W
1-second units -- R/W -- R/W -- R/W
22.4.10 Minute Alarm Register (RMINAR) RMINAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded minute value counter, RMINCNT. When the ENB bit is set to 1, the RMINAR value is compared with the RMINCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RMINAR is initialized by a power-on reset. The other fields in RMINAR are not initialized by a power-on or manual reset.
Bit: 7 ENB Initial value: R/W: 0 R/W 6 5 4 3 2 1 0
10-minute units -- R/W -- R/W -- R/W -- R/W
1-minute units -- R/W -- R/W -- R/W
Rev. 1.00 Oct. 01, 2007 Page 769 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.4.11 Hour Alarm Register (RHRAR) RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with the RHRCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 00 to 23 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RHRAR is initialized by a power-on reset. The other fields in RHRAR are not initialized by a power-on or manual reset. Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0.
Bit: 7 ENB Initial value: R/W: 0 R/W 6 -- 0 R 5 4 3 2 1 0
10-hour units -- R/W -- R/W -- R/W
1-hour units -- R/W -- R/W -- R/W
22.4.12 Day-of-Week Alarm Register (RWKAR) RWKAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded day-of-week value counter, RWKCNT. When the ENB bit is set to 1, the RWKAR value is compared with the RWKCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 0 to 6 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RWKAR is initialized by a power-on reset. The other fields in RWKAR are not initialized by a power-on or manual reset.
Rev. 1.00 Oct. 01, 2007 Page 770 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
Bits 6 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0.
Bit: 7 ENB Initial value: R/W: 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0
Day-of-week code -- R/W -- R/W -- R/W
Day-of-week code Day of week
0 Sun
1 Mon
2 Tue
3 Wed
4 Thu
5 Fri
6 Sat
22.4.13 Day Alarm Register (RDAYAR) RDAYAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCDcoded day value counter, RDAYCNT. When the ENB bit is set to 1, the RDAYAR value is compared with the RDAYCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 01 to 31 + ENB bit. The RTC will not operate normally if any other value is set. The setting range for RDAYAR depends on the month and whether the year is a leap year, so care is required when making the setting. The ENB bit in RDAYAR is initialized by a power-on reset. The other fields in RDAYAR are not initialized by a power-on or manual reset. Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0.
Bit: 7 ENB Initial value: R/W: 0 R/W 6 -- 0 R 5 4 3 2 1 0
10-day units -- R/W -- R/W -- R/W
1-day units -- R/W -- R/W -- R/W
Rev. 1.00 Oct. 01, 2007 Page 771 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.4.14 Month Alarm Register (RMONAR) RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCDcoded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is compared with the RMONCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 01 to 12 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RMONAR is initialized by a power-on reset. The other fields in RMONAR are not initialized by a power-on or manual reset. Bits 6 and 5 are always read as 0. A write to these bits is invalid, but the write value should always be 0.
Bit: 7 ENB Initial value: R/W: 0 R/W 6 -- 0 R 5 -- 0 R 4
10-month unit
3
2
1
0
1-month units -- R/W -- R/W -- R/W -- R/W
-- R/W
22.4.15 RTC Control Register 1 (RCR1) RCR1 is an 8-bit readable/writable register containing a carry flag and alarm flag, plus flags to enable or disable interrupts for these flags. The CIE and AIE bits are initialized to 0 by a power-on or manual reset; the value of bits other than CIE and AIE is undefined.
Bit: 7 CF Initial value: R/W: -- R/W 6 -- -- R 5 -- -- R 4 CIE 0 R/W 3 AIE 0 R/W 2 -- -- R 1 -- -- R 0 AF -- R/W
Rev. 1.00 Oct. 01, 2007 Page 772 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
Bit 7
Bit Name CF
Initial Value Undefined
R/W R/W
Description Carry Flag This flag is set to 1 on generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read. The count register value read at this time is not guaranteed, and so the count register must be read again. 0: No second counter carry, or 64 Hz counter carry when 64 Hz counter is read [Clearing condition] When 0 is written to CF 1: Second counter carry, or 64 Hz counter carry when 64 Hz counter is read [Setting conditions] Generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read When 1 is written to CF
6 to 5
--
Undefined
R
Reserved The initial value of these bits is undefined. A write to these bits is invalid, but the write value should always be 0.
4
CIE
0
R/W
Carry Interrupt Enable Flag Enables or disables interrupt generation when the carry flag (CF) is set to 1. 0: Carry interrupt is not generated when CF flag is set to 1 1: Carry interrupt is generated when CF flag is set to 1
3
AIE
0
R/W
Alarm Interrupt Enable Flag Enables or disables interrupt generation when the alarm flag (AF) is set to 1. 0: Alarm interrupt is not generated when AF flag is set to 1 1: Alarm interrupt is generated when AF flag is set to 1
2 to 1
--
Undefined
R
Reserved The initial value of these bits is undefined. A write to these bits is invalid, but the write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 773 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
Bit 0
Bit Name AF
Initial Value Undefined
R/W R/W
Description Alarm Flag Set to 1 when the alarm time set in those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1 matches the respective counter values. 0: Alarm registers and counter values do not match (Initial value) [Clearing condition] When 0 is written to AF 1: Alarm registers and counter values match* [Setting condition] When alarm registers in which the ENB bit is set to 1 and counter values match* Note: * Writing 1 does not change the value.
22.4.16 RTC Control Register 2 (RCR2) RCR2 is an 8-bit readable/writable register used for periodic interrupt control, 30-second adjustment, and frequency divider RESET and RTC count control. RCR2 is basically initialized to H'09 by a power-on reset, except that the value of the PEF bit is undefined. In a manual reset, bits other than RTCEN and START are initialized, while the value of the PEF bit is undefined. In standby mode RCR2 is not initialized, and retains its current value.
Bit: 7
PEF
6
5
PES[2:0]
4
3
2
1
0
RTCEN ADJ
RESET START
Initial value: R/W:
-- R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
1 R/W
Rev. 1.00 Oct. 01, 2007 Page 774 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
Bit 7
Bit Name PEF
Initial Value Undefined
R/W R/W
Description Periodic Interrupt Flag Indicates interrupt generation at the interval specified by bits PES2-PES0. When this flag is set to 1, a periodic interrupt is generated. 0: Interrupt is not generated at interval specified by bits PES2-PES0 [Clearing condition] When 0 is written to PEF 1: Interrupt is generated at interval specified by bits PES2-PES0 [Setting conditions] Generation of interrupt at interval specified by bits PES2-PES0 When 1 is written to PEF
6 to 4
PES[2:0]
All 0
R/W
Periodic Interrupt Enable These bits specify the period for periodic interrupts. 000: No periodic interrupt generation 001: Periodic interrupt generated at 1/256-second intervals 010: Periodic interrupt generated at 1/64-second intervals 011: Periodic interrupt generated at 1/16-second intervals 100: Periodic interrupt generated at 1/4-second intervals 101: Periodic interrupt generated at 1/2-second intervals 110: Periodic interrupt generated at 1-second intervals 111: Periodic interrupt generated at 2-second intervals
3
RTCEN
1
R/W
Oscillator Enable Controls the operation of the RTC's crystal oscillator. 0: RTC crystal oscillator is halted 1: RTC crystal oscillator is operated
Rev. 1.00 Oct. 01, 2007 Page 775 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
Bit 2
Bit Name ADJ
Initial Value 0
R/W R/W
Description 30-Second Adjustment Used for 30-second adjustment. When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute. The frequency divider circuits (RTC prescaler and R64CNT) are also reset at this time. This bit always returns 0 if read. 0: Normal clock operation 1: 30-second adjustment performed
1
RESET
0
R/W
Reset The frequency divider circuits are initialized by writing 1 to this bit. When 1 is written to the RESET bit, the frequency divider circuits (RTC prescaler and R64CNT) are reset and the RESET bit is automatically cleared to 0 (i.e. does not need to be written with 0). 0: Normal clock operation 1: Frequency divider circuits are reset
0
START
1
R/W
Start Bit Stops and restarts counter (clock) operation. 0: Second, minute, hour, day, day-of-week, month, and year counters are stopped* 1: Second, minute, hour, day, day-of-week, month, and year counters operate normally* Note: * The 64 Hz counter continues to operate unless stopped by means of the RTCEN bit.
Rev. 1.00 Oct. 01, 2007 Page 776 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.4.17 RTC Control Register (RCR3) and Year-Alarm Register (RYRAR) RCR3 and RYRAR are readable/writable registers. RYRAR is the alarm register for the RTC's BCD-coded year-value counter RYRCNT. When the YENB bit of RCR3 is set to 1, the RYRCNT value is compared with the RYRAR value. Comparison between the counter and the alarm register only takes place with the alarm registers in which the ENB and YENB bits are set to 1. The alarm flag of RCR1 is only set to 1 when the respective values all match. The setting range of RYRAR is decimal 0000 to 9999, and normal operation is not obtained if a value beyond this range is set here. RCR3 is initialized by a power-on reset, but RYRAR will not be initialized by a power-on or manual reset. Bits 6 to 0 of RCR3 are always read as 0. A write to these bits is invalid. If a value is written to these bits, it should always be 0. * RCR3
Bit: 7
YENB
6 -- 0 R
5 -- 0 R
4 -- 0 R
3 -- 0 R
2 -- 0 R
1 -- 0 R
0 -- 0 R
Initial value: R/W:
-- R/W
* RYRAR
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1000 years Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W
100 years -- R/W -- R/W -- R/W -- R/W
10 years -- R/W -- R/W -- R/W -- R/W
1 year -- R/W -- R/W -- R/W
Rev. 1.00 Oct. 01, 2007 Page 777 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.5
Operation
Examples of the use of the RTC are shown below. 22.5.1 Time Setting Procedures
Figure 22.2 shows examples of the time setting procedures.
Set RCR2.RESET to 1. Clear RCR2.START to 0.
Stop clock Reset frequency divider
Set second/minute/hour/day/ day-of-week/month/year
In any order.
Start clock operation (a) Setting time after stopping clock
Set RCR2.START to 1.
Clear carry flag
Clear RCR1.CF to 0 (Write 1 to RCR1.AF so that alarm flag is not cleared). Set RYRCNT first and RSECCNT last.
Write to counter register
Yes
Carry flag = 1? No
Read RCR1 register and check CF bit.
(b) Setting time while clock is running
Figure 22.2 Examples of Time Setting Procedures The procedure for setting the time after stopping the clock is shown in figure 22.2 (a). The programming for this method is simple, and it is useful for setting all the counters, from second to year. The procedure for setting the time while the clock is running is shown in figure 22.2 (b). This method is useful for modifying only certain counter values (for example, only the second data or hour data). If a carry occurs during the write operation, the write data is automatically updated and there will be an error in the set data. The carry flag should therefore be used to check the write status. If the carry flag (RCR1.CF) is set to 1, the write must be repeated. The interrupt function can also be used to determine the carry flag status.
Rev. 1.00 Oct. 01, 2007 Page 778 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.5.2
Time Reading Procedures
Figure 22.3 shows examples of the time reading procedures.
Disable carry interrupts
Clear RCR1.CIE to 0.
Clear carry flag
Clear RCR1.CF to 0 (Write 1 to RCR1.AF so that alarm flag is not cleared).
Read counter register
Yes
Carry flag = 1? No
Read RCR1 register and check CF bit.
(a) Reading time without using interrupts
Clear carry flag
Enable carry interrupts
Set RCR1.CIE to 1. Clear RCR1.CF to 0 (Write 1 to RCR1.AF so that alarm flag is not cleared).
Clear carry flag
Read counter register
Yes
Interrupt generated? No
Disable carry interrupts
Clear RCR1.CIE to 0.
(b) Reading time using interrupts
Figure 22.3 Examples of Time Reading Procedures If a carry occurs while the time is being read, the correct time will not be obtained and the read must be repeated. The procedure for reading the time without using interrupts is shown in figure 22.3 (a), and the procedure using carry interrupts in figure 22.3 (b). The method without using interrupts is normally used to keep the program simple.
Rev. 1.00 Oct. 01, 2007 Page 779 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.5.3
Alarm Function
The use of the alarm function is illustrated in figure 22.4.
Clock running
Disable alarm interrupts
Clear RCR1.AIE to prevent erroneous interrupts.
Set alarm time
Clear alarm flag
Be sure to reset the flag as it may have been set during alarm time setting. Set RCR1.AIE to 1.
Enable alarm interrupts
Monitor alarm time
(Wait for interrupt or check alarm flag)
Figure 22.4 Example of Use of Alarm Function An alarm can be generated by the second, minute, hour, day-of-week, day, month, or year value, or a combination of these. Write 1 to the ENB bit in the alarm registers involved in the alarm setting, and set the alarm time in the lower bits. Write 0 to the ENB bit in registers not involved in the alarm setting. When the counter and the alarm time match, RCR1.AF is set to 1. Alarm detection can be confirmed by reading this bit, but normally an interrupt is used. If 1 has been written to RCR1.AIE, an alarm interrupt is generated in the event of alarm, enabling the alarm to be detected.
Rev. 1.00 Oct. 01, 2007 Page 780 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
22.6
Interrupts
There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts. An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1. A periodic interrupt request (PRI) is generated when the periodic interrupt enable bits (PES2- PES0) in RCR2 are set to a value other than 000 and the periodic interrupt flag (PEF) is set to 1. A carry interrupt request (CUI) is generated when the carry flag (CF) in RCR1 is set to 1 while the carry interrupt enable bit (CIE) is also set to 1.
22.7
22.7.1
Usage Notes
Register Initialization
After powering on and making the RCR1 register settings, reset the frequency divider (by setting RCR2.RESET to 1) and make initial settings for all the other registers. 22.7.2 Crystal Oscillator Circuit
Crystal oscillator circuit constants (recommended values) are shown in table 22.4, and the RTC crystal oscillator circuit in figure 22.5. Table 22.4 Crystal Oscillator Circuit Constants (Recommended Values)
fosc 32.768 kHz Cin 10-22 pF Cout 10-22 pF
Rev. 1.00 Oct. 01, 2007 Page 781 of 1956 REJ09B0256-0100
Section 22 Realtime Clock (RTC)
This LSI
Rf
VDD-RTC
VSS-RTC
EXTAL2
RD XTAL2
Noise filter
C RTC
XTAL C in C out
R RTC 3.3 V
Notes: 1. Select either the Cin or Cout side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2. Built-in resistance value Rf (typ. value) = 10 M, RD (typ. value) = 400 k 3. Cin and Cout values include floating capacitance due to the wiring. Take care when using a solidearth board. 4. The crystal oscillation stabilization time depends on the mounted circuit constants, floating capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip. (Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins.) 6. Ensure that the crystal resonator connection pin (EXTAL2 and XTAL2) wiring is routed as far away as possible from other power lines (except GND) and signal lines. 7. Insert a noise filter in the RTC power supply.
Figure 22.5 Example of Crystal Oscillator Circuit Connection 22.7.3 Interrupt source and request generating order
If it occurs two or three interrupt source of alarm interrupts(ATI), periodic interrupts(PFI), and carry interrupts(CUI) at the same time, RTC generates interrupt request as the order of table 22.5. Table 22.5 Interrupt source and request generating order
Interrupt request generating order Interrupt source ATI, PFI and CUI ATI and PFI PFI and CUI ATI and CUI Fast PFI PFI PFI CUI CUI ATI CUI ATI ATI -- -- --
Rev. 1.00 Oct. 01, 2007 Page 782 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Section 23 Gigabit Ethernet Controller (GETHER)
This LSI has an on-chip Gigabit Ethernet controller (GETHER) conforming to the Ethernet or the IEEE802.3 MAC (Media Access Control) layer standard. Connecting a physical-layer LSI (PHYLSI) complying with this standard enables the GETHER to perform transmission and reception of Ethernet/IEEE802.3 frames. The LSI has two MAC layer interface ports (hereafter referred to as port 0 and port 1), both of which can be made to perform transmission and reception independently. The GETHER can transfer the transmitted or received Ethernet frame data to and from the transmit/receive buffer in the memory at high speed using a dedicated direct memory access controller (E-DMAC). The GETHER also has an on-chip TSU (Transfer Switching Unit) which controls transferring, allowing mutual transfer of data between MAC layer controllers of ports 0 and 1.
23.1
Features
* MAC (Media Access Control) function Constructs/deconstructs data frames (frame format conforming to IEEE802.3, 2000 Edition) Supports transfer at 10, 100, and 1000 Mbps Supports full-duplex and half-duplex modes Two channels (GETHER0 and GETHER1) Flow control conforming to IEEE802.3x Supports three PHY interfaces conforming to IEEE802.3 GMII (Gigabit Media Independent Interface) MII (Media Independent Interface) RMII (Reduced Media Independent Interface) Upward protocol support (checksum) function * Switching unit for data transfer between channels (relay FIFO: 6 Kbytes) * E-DMAC (Direct Memory Access Controller for Ethernet controller) function Data transfer between GETHER and external/internal memory Four channels 32-byte burst transfer Supports single-frame/single-descriptor operation and single-frame/multi-descriptor (multibuffer) operation Transfer data width: 32 bits
Rev. 1.00 Oct. 01, 2007 Page 783 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Transmit/receive FIFO (for transmission: 2 Kbytes, for reception: 8 Kbytes) Figure 23.1 shows the configuration of the GETHER.
SuperHyway (SHwy) bridge bus
GETHER E-DMAC0 DMA transfer processing Descriptor access E-DMAC1 DMA tansfer processing Descriptor access
Receive FIFO Transmit FIFO (Port 0) (Port 0)
Receive FIFO Transmit FIFO (Port 1) (Port 1)
TSU CAM entry tables
Relay FIFO (Port 0 Port 1) Relay FIFO (Port 0 Port 1)
Transfer processing CAM control
Transfer processing CAM control
E-MAC-0 (Port 0) Receive processing unit Transmit processing unit
E-MAC-1 (Port 1) Receive processing unit Transmit processing unit
PHY interface
PHY interface
GMII/MII RMII conversion
GMII/MII RMII conversion
RMII PHY-0
GMII/MII
RMII PHY-1
GMII/MII
Figure 23.1 Configuration of GETHER
Rev. 1.00 Oct. 01, 2007 Page 784 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.2
Input/Output Pins
Table 23.1 lists the pin configuration of the GETHER. Table 23.1 Pin Configuration
Name Transmit clock Port 0 Abbreviation ET0_TX-CLK I/O Input Function ET0_TX-EN, ET0_ETXD3 to ET0_ETXD0, ET0_TX-ER timing reference signal Indicates that transmit data is ready on ET0_ETXD3 to ET0_ETXD0 4-bit MII transmit data or lower four bits of GMII transmit data Upper four bits of GMII transmit data Collision detection signal Notifies PHY-LSI of error during transmission ET0_RX-DV, ET0_ERXD3 to ET0_ERXD0, ET0_RX-ER timing reference signal Indicates that valid receive data is on ET0_ERXD3 to ET0_ERXD0 4-bit MII receive data or lower four bits of GMII receive data (MII and GMII) Upper four bits of GMII receive data Identifies error state occurred during data reception Carrier detection signal Reference clock signal for information transfer via ET0_MDIO Bidirectional signal for exchange of management information between STA and PHY
Transmit enable MII/GMII transmit data GMII transmit data Collision detection Transmit error Receive clock
ET0_TX-EN ET0_ETXD3 to ET0_ETXD0
Output Output
GET0_ETXD7 to Output GET0_ETXD4 ET0_COL ET0_TX-ER ET0_RX-CLK Input Output Input
Receive data valid MII/GMII receive data GMII receive data Receive error Carrier detection Management data clock Management data I/O
ET0_RX-DV ET0_ERXD3 to ET0_ERXD0
Input Input
GET0_ERXD7 to Input GET0_ERXD4 ET0_RX-ER ET0_CRS ET0_MDC ET0_MDIO Input Input Output I/O
Rev. 1.00 Oct. 01, 2007 Page 785 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name RMII management data clock RMII management data I/O RMII management data clock (mirror 0 pin) RMII management data I/O (mirror 0 pin) RMII management data clock (mirror 1 pin) RMII management data I/O (mirror 1 pin) Link status Wake-On-LAN PHY interrupt GMII transmit clock RMII carrier detection RMII receive error RMII receive data RMII receive data RMII transmit enable
Port 0
Abbreviation RMII0_MDC
I/O Output
Function Reference clock signal for information transfer via RMII0_MDIO in RMII mode Bidirectional signal for exchange of management information between STA and PHY in RMII mode Reference clock signal for information transfer via RMII0M0_MDIO in RMII mode (mirror 0 pin) Bidirectional signal for exchange of management information between STA and PHY in RMII mode (mirror 0 pin) Reference clock signal for information transfer via RMII0M1_MDIO in RMII mode (mirror 1 pin) Bidirectional signal for exchange of management information between STA and PHY in RMII mode (mirror 1 pin) Inputs link status from PHY-LSI Signal indicating reception of Magic Packet Interrupt signal from PHY Transmit signal timing reference signal in GMII mode Carrier detection signal in RMII mode Identifies error state occurred during data reception in RMII mode 2-bit receive data in RMII mode 2-bit receive data in RMII mode Indicates that transmit data is ready on RMII0_TXD0 and RMII0_TXD1 in RMII mode
RMII0_MDIO
I/O
RMII0M0_MDC
Output
RMII0M0_MDIO
I/O
RMII0M1_MDC
Output
RMII0M1_MDIO
I/O
ET0_LINKSTA ET0_WOL ET0_PHY-INT
Input Output Input
GET0_GTX-CLK Output RMII0_CRS_DV RMII0_RX_ER RMII0_RXD0 RMII0_RXD1 RMII0_TXD_EN Input Input Input Input Output
Rev. 1.00 Oct. 01, 2007 Page 786 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name RMII transmit data RMII transmit data Transmit clock
Port 0
Abbreviation RMII0_TXD0 RMII0_TXD1
I/O Output Output Input
Function 2-bit transmit data in RMII mode 2-bit transmit data in RMII mode ET1_TX-EN, ET1_ETXD3 to ET1_ETXD0, ET1_TX-ER timing reference signal ET1_RX-DV, ET1_ERXD3 to ET1_ERXD0, ET1_RX-ER timing reference signal Indicates that transmit data is ready on ET1_ETXD3 to ET1_ETXD0 4-bit MII transmit data or lower four bits of GMII transmit data Upper four bits of GMII transmit data Notifies PHY-LSI of error during transmission Indicates that valid receive data is on ET1_ERXD3 to ET1_ERXD0 4-bit MII receive data or lower four bits of GMII receive data (MII and GMII) Upper four bits of GMII receive data Identifies error state occurred during data reception Carrier detection signal Collision detection signal Reference clock signal for information transfer via ET1_MDIO Bidirectional signal for exchange of management information between STA and PHY Reference clock signal for information transfer via RMII1_MDIO in RMII mode
1
ET1_TX-CLK
Receive clock
ET1_RX-CLK
Input
Transmit enable MII/GMII transmit data GMII transmit data Transmit error Receive data valid MII/GMII receive data GMII receive data Receive error Carrier detection Collision detection Management data clock Management data I/O RMII management data clock
ET1_TX-EN ET1_ETXD3 to ET1_ETXD0
Output Output
GET1_ETXD7 to Output GET1_ETXD4 ET1_TX-ER ET1_RX-DV ET1_ERXD3 to ET1_ERXD0 Output Input Input
GET1_ERXD7 to Input GET1_ERXD4 ET1_RX-ER ET1_CRS ET1_COL ET1_MDC ET1_MDIO Input Input Input Output I/O
RMII1_MDC
Output
Rev. 1.00 Oct. 01, 2007 Page 787 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name RMII management data I/O Link status Wake-On-LAN PHY interrupt GMII transmit clock RMII carrier detection RMII receive error RMII receive data RMII receive data RMII transmit enable RMII transmit data RMII transmit data RMII carrier detection (mirror pin) RMII receive error (mirror pin) RMII receive data (mirror pin) RMII receive data (mirror pin) RMII transmit enable (mirror pin)
Port 1
Abbreviation RMII1_MDIO
I/O I/O
Function Bidirectional signal for exchange of management information between STA and PHY in RMII mode Inputs link status from PHY-LSI Signal indicating reception of Magic Packet Interrupt signal from PHY Transmit signal timing reference signal in GMII mode Carrier detection signal in RMII mode Identifies error state occurred during data reception in RMII mode 2-bit receive data in RMII mode 2-bit receive data in RMII mode Indicates that transmit data is ready on RMII1_TXD0 and RMII1_TXD1 in RMII mode 2-bit transmit data in RMII mode 2-bit transmit data in RMII mode Carrier detection signal in RMII mode (mirror pin) Identifies error state occurred during data reception in RMII mode (mirror pin) 2-bit receive data in RMII mode (mirror pin) 2-bit receive data in RMII mode (mirror pin) Indicates that transmit data is ready on RMII1_TXD0 and RMII1_TXD1 in RMII mode (mirror pin)
ET1_LINKSTA ET1_WOL ET1_PHY-INT GET1_GTX-CLK RMII1_CRS_DV RMII1_RX_ER RMII1_RXD0 RMII1_RXD1 RMII1_TXD_EN
Input Output Input Output Input Input Input Input Output
RMII1_TXD0 RMII1_TXD1
Output Output
RMII1M_CRS_DV Input
RMII1M_RX_ER RMII1M_RXD0 RMII1M_RXD1
Input Input Input
RMII1M_TXD_EN Output
Rev. 1.00 Oct. 01, 2007 Page 788 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name
Port
Abbreviation RMII1M_TXD0 RMII1_TXD1
I/O
Function
RMII transmit 1 data (mirror pin) RMII transmit data (mirror pin) 125-MHz reference clock 50-MHz reference clock Note: *
Output 2-bit transmit data in RMII mode(mirror pin) Output 2-bit transmit data in RMII mode (mirror pin) Input Input Transmit clock generation signal in GMII mode Transmit clock generation signal in RMII mode
Common REF125CK Common REF50CK
MII signal conforming to IEEE802.3u
Rev. 1.00 Oct. 01, 2007 Page 789 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3
Register Descriptions
Table 23.2 shows the configuration of registers of the GETHER. Table 23.3 shows the state of registers in each processing mode. The last number of the abbreviation of a register, except for registers related to the CAM entry tables, corresponds to the number of the two Ethernet interface ports (port 0 or port 1). Some numbers have been omitted in the text. Table 23.2 Register Configuration
Name Software reset register E-MAC mode register E-MAC status register
E-MAC interrupt permission register Abbreviation
R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
P4 Area Address H'FEE0 1800 H'FEE0 0500 H'FEE0 0510 H'FEE0 0518 H'FEE0 0520 H'FEE0 05C0 H'FEE0 05C8 H'FEE0 0508 H'FEE0 0528 H'FEE0 052C H'FEE0 0700 H'FEE0 0708 H'FEE0 0710 H'FEE0 0740 H'FEE0 0748 H'FEE0 0750 H'FEE0 0758 H'FEE0 0760 H'FEE0 0768
Area 7 Address H'1EE0 1800 H'1EE0 0500 H'1EE0 0510 H'1EE0 0518 H'1EE0 0520 H'1EE0 05C0 H'1EE0 05C8 H'1EE0 0508 H'1EE0 0528 H'1EE0 052C H'1EE0 0700 H'1EE0 0708 H'1EE0 0710 H'1EE0 0740 H'1EE0 0748 H'1EE0 0750 H'1EE0 0758 H'1EE0 0760 H'1EE0 0768
Access Size
ARSTR ECMR0 ECSR0 ECSIPR0 PIR0 MAHR0 MALR0 RFLR0 PSR0 PIPR0 TROCR0 CDCR0 LCCR0 CEFCR0 FRECR0 TSFRCR0 TLFRCR0
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
PHY interface register MAC address high register MAC address low register Receive frame length register PHY status register PHY_INT polarity register
Transmit retry over counter register
Delayed collision detect counter register Lost carrier counter register CRC error frame receive counter register
Frame receive error counter register
Too-short frame receive counter register Too-long frame receive counter register
Residual-bit frame receive counter RFCR0 register
Carrier extension loss counter register CERCR0
Rev. 1.00 Oct. 01, 2007 Page 790 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name Carrier extension error counter register Multicast address frame receive counter register Automatic PAUSE frame register Manual PAUSE frame register Automatic PAUSE frame retransmit count register PAUSE frame transmit counter register PAUSE frame receive counter register GETHER mode register
Burst cycle count upper-limit register
Abbreviation
R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W
P4 Area Address H'FEE0 0770 H'FEE0 0778 H'FEE0 0554 H'FEE0 0558 H'FEE0 0564 H'FEE0 055C H'FEE0 0560 H'FEE0 05B0 H'FEE0 05B4 H'FEE0 0D00 H'FEE0 0D10 H'FEE0 0D18 H'FEE0 0D20 H'FEE0 0D2C H'FEE0 0DC0 H'FEE0 0DC8 H'FEE0 0D08 H'FEE0 0D28 H'FEE0 0F00 H'FEE0 0F08 H'FEE0 0F10 H'FEE0 0F40 H'FEE0 0F48 H'FEE0 0F50 H'FEE0 0F58
Area 7 Address H'1EE0 0770 H'1EE0 0778 H'1EE0 0554 H'1EE0 0558 H'1EE0 0564 H'1EE0 055C H'1EE0 0560 H'1EE0 05B0 H'1EE0 05B4 H'1EE0 0D00 H'1EE0 0D10 H'1EE0 0D18 H'1EE0 0D20 H'1EE0 0D2C H'1EE0 0DC0 H'1EE0 0DC8 H'1EE0 0D08 H'1EE0 0D28 H'1EE0 0F00 H'1EE0 0F08 H'1EE0 0F10 H'1EE0 0F40 H'1EE0 0F48 H'1EE0 0F50 H'1EE0 0F58
Access Size
CEECR0 MAFCR0 APR0 MPR0 TPAUSER0 PFTCR0 PFRCR0 GECMR0 BCULR0 ECMR1 ECSR1 ECSIPR1 PIR1 PIPR1 MAHR1 MALR1 RFLR1 PSR1 TROCR1 CDCR1 LCCR1 CEFCR1 FRECR1 TSFRCR1 TLFRCR1
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
E-MAC mode register E-MAC status register
E-MAC interrupt permission register
PHY interface register PHY_INT polarity register MAC address high register MAC address low register Receive frame length register PHY status register
Transmit retry over counter register
Delayed collision detect counter register Lost carrier counter register CRC error frame receive counter register
Frame receive error counter register
Too-short frame receive counter register Too-long frame receive counter register
Rev. 1.00 Oct. 01, 2007 Page 791 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name
Abbreviation
R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W
P4 Area Address H'FEE0 0F60 H'FEE0 0F68 H'FEE0 0F70 H'FEE0 0F78 H'FEE0 0D54 H'FEE0 0D58 H'FEE0 0D64 H'FEE0 0D5C H'FEE0 0D60 H'FEE0 0DB0 H'FEE0 0DB4 H'FEE0 1804 H'FEE0 1810 H'FEE0 1814 H'FEE0 1818 H'FEE0 1820 H'FEE0 1824 H'FEE0 1828 H'FEE0 182C H'FEE0 1830 H'FEE0 1834
Area 7 Address H'1EE0 0F60 H'1EE0 0F68 H'1EE0 0F70 H'1EE0 0F78 H'1EE0 0D54 H'1EE0 0D58 H'1EE0 0D64 H'1EE0 0D5C H'1EE0 0D60 H'1EE0 0DB0 H'1EE0 0DB4 H'1EE0 1804 H'1EE0 1810 H'1EE0 1814 H'1EE0 1818 H'1EE0 1820 H'1EE0 1824 H'1EE0 1828 H'1EE0 182C H'1EE0 1830 H'1EE0 1834
Access Size
Residual-bit frame receive counter RFCR1 register
Carrier extension loss counter register CERCR1
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Carrier extension error counter register Multicast address frame receive counter register Automatic PAUSE frame register Manual PAUSE frame register Automatic PAUSE frame retransmit count register PAUSE frame transmit counter register PAUSE frame receive counter register GETHER mode register
Burst cycle count upper-limit register
CEECR1 MAFCR1 APR1 MPR1 TPAUSER1 PFTCR1 PFRCR1 GECMR1 BCULR1
TSU counter reset register
TSU_CTRST R/W R/W R/W R/W
Relay enable register (Port 0 to 1) TSU_FWEN0 Relay enable register (Port 1 to 0) TSU_FWEN1 Relay FIFO size select register Relay FIFO overflow alert set register (port 0) Relay FIFO overflow alert set register (port 1) Transmit/relay priority control mode register (port 0) Transmit/relay priority control mode register (port 1) TSU_FCM
TSU_BSYSL0 R/W TSU_BSYSL1 R/W TSU_PRISL0 TSU_PRISL1
R/W R/W
Receive/relay function set register TSU_FWSL0 R/W (port 0 to 1) Receive/relay function set register TSU_FWSL1 R/W (port 1 to 0)
Rev. 1.00 Oct. 01, 2007 Page 792 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name
Relay function set register (common)
Abbreviation TSU_FWSLC
R/W R/W
P4 Area Address H'FEE0 1838 H'FEE0 1840 H'FEE0 1844 H'FEE0 1850 H'FEE0 1854 H'FEE0 1848 H'FEE0 184C H'FEE0 1858 H'FEE0 185C H'FEE0 1860 H'FEE0 1864 H'FEE0 1870 H'FEE0 1874 H'FEE0 1878 H'FEE0 187C H'FEE0 1900 H'FEE0 1908 H'FEE0 1910 H'FEE0 1918 H'FEE0 1920 H'FEE0 1928 H'FEE0 1930 H'FEE0 1938 H'FEE0 1940 H'FEE0 1948 H'FEE0 1950 H'FEE0 1958 H'FEE0 1960
Area 7 Address H'1EE0 1838 H'1EE0 1840 H'1EE0 1844 H'1EE0 1850 H'1EE0 1854 H'1EE0 1848 H'1EE0 184C H'1EE0 1858 H'1EE0 185C H'1EE0 1860 H'1EE0 1864 H'1EE0 1870 H'1EE0 1874 H'1EE0 1878 H'1EE0 187C H'1EE0 1900 H'1EE0 1908 H'1EE0 1910 H'1EE0 1918 H'1EE0 1920 H'1EE0 1928 H'1EE0 1930 H'1EE0 1938 H'1EE0 1940 H'1EE0 1948 H'1EE0 1950 H'1EE0 1958 H'1EE0 1960
Access Size
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Qtag addition/deletion set register TSU_QTAG0 R/W (port 0 to 1) Qtag addition/deletion set register TSU_QTAG1 R/W (port 1 to 0) Relay status register
Relay status interrupt mask register
TSU_FWSR
TSU_FWINMK
R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W
Added Qtag value set register (port 0 to 1) Added Qtag value set register (port 1 to 0) VLANtag set register (port 0) VLANtag set register (port 1) CAM entry table busy register CAM entry table enable register CAM entry table POST1 register CAM entry table POST2 register CAM entry table POST3 register CAM entry table POST4 register CAM entry table 0H register CAM entry table 1H register CAM entry table 2H register CAM entry table 3H register CAM entry table 4H register CAM entry table 5H register CAM entry table 6H register CAM entry table 7H register CAM entry table 8H register CAM entry table 9H register CAM entry table 10H register CAM entry table 11H register CAM entry table 12H register
TSU_ADQT0 TSU_ADQT1 TSU_VTAG0 TSU_VTAG1
TSU_ADSBSY
TSU_TEN TSU_POST1 TSU_POST2 TSU_POST3 TSU_POST4
TSU_ADRH0 R/W TSU_ADRH1 R/W TSU_ADRH2 R/W TSU_ADRH3 R/W TSU_ADRH4 R/W TSU_ADRH5 R/W TSU_ADRH6 R/W TSU_ADRH7 R/W TSU_ADRH8 R/W TSU_ADRH9 R/W
TSU_ADRH10 TSU_ADRH11 TSU_ADRH12
R/W R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 793 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name CAM entry table 13H register CAM entry table 14H register CAM entry table 15H register CAM entry table 16H register CAM entry table 17H register CAM entry table 18H register CAM entry table 19H register CAM entry table 20H register CAM entry table 21H register CAM entry table 22H register CAM entry table 23H register CAM entry table 24H register CAM entry table 25H register CAM entry table 26H register CAM entry table 27H register CAM entry table 28H register CAM entry table 29H register CAM entry table 30H register CAM entry table 31H register CAM entry table 0L register CAM entry table 1L register CAM entry table 2L register CAM entry table 3L register CAM entry table 4L register CAM entry table 5L register CAM entry table 6L register CAM entry table 7L register CAM entry table 8L register CAM entry table 9L register CAM entry table 10L register CAM entry table 11L register
Abbreviation TSU_ADRH13 TSU_ADRH14 TSU_ADRH15 TSU_ADRH16 TSU_ADRH17 TSU_ADRH18 TSU_ADRH19 TSU_ADRH20 TSU_ADRH21 TSU_ADRH22 TSU_ADRH23 TSU_ADRH24 TSU_ADRH25 TSU_ADRH26 TSU_ADRH27 TSU_ADRH28 TSU_ADRH29 TSU_ADRH30 TSU_ADRH31
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
P4 Area Address H'FEE0 1968 H'FEE0 1970 H'FEE0 1978 H'FEE0 1980 H'FEE0 1988 H'FEE0 1990 H'FEE0 1998 H'FEE0 19A0 H'FEE0 19A8 H'FEE0 19B0 H'FEE0 19B8 H'FEE0 19C0 H'FEE0 19C8 H'FEE0 19D0 H'FEE0 19D8 H'FEE0 19E0 H'FEE0 19E8 H'FEE0 19F0 H'FEE0 19F8 H'FEE0 1904 H'FEE0 190C H'FEE0 1914 H'FEE0 191C H'FEE0 1924 H'FEE0 192C H'FEE0 1934 H'FEE0 193C H'FEE0 1944 H'FEE0 194C H'FEE0 1954 H'FEE0 195C
Area 7 Address H'1EE0 1968 H'1EE0 1970 H'1EE0 1978 H'1EE0 1980 H'1EE0 1988 H'1EE0 1990 H'1EE0 1998 H'1EE0 19A0 H'1EE0 19A8 H'1EE0 19B0 H'1EE0 19B8 H'1EE0 19C0 H'1EE0 19C8 H'1EE0 19D0 H'1EE0 19D8 H'1EE0 19E0 H'1EE0 19E8 H'1EE0 19F0 H'1EE0 19F8 H'1EE0 1904 H'1EE0 190C H'1EE0 1914 H'1EE0 191C H'1EE0 1924 H'1EE0 192C H'1EE0 1934 H'1EE0 193C H'1EE0 1944 H'1EE0 194C H'1EE0 1954 H'1EE0 195C
Access Size
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
TSU_ADRL0 R/W TSU_ADRL1 R/W TSU_ADRL2 R/W TSU_ADRL3 R/W TSU_ADRL4 R/W TSU_ADRL5 R/W TSU_ADRL6 R/W TSU_ADRL7 R/W TSU_ADRL8 R/W TSU_ADRL9 R/W
TSU_ADRL10 TSU_ADRL11
R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 794 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name CAM entry table 12L register CAM entry table 13L register CAM entry table 14L register CAM entry table 15L register CAM entry table 16L register CAM entry table 17L register CAM entry table 18L register CAM entry table 19L register CAM entry table 20L register CAM entry table 21L register CAM entry table 22L register CAM entry table 23L register CAM entry table 24L register CAM entry table 25L register CAM entry table 26L register CAM entry table 27L register CAM entry table 28L register CAM entry table 29L register CAM entry table 30L register CAM entry table 31L register
Transmit frame counter register (port 0) (normal transmission only)
Abbreviation TSU_ADRL12 TSU_ADRL13 TSU_ADRL14 TSU_ADRL15 TSU_ADRL16 TSU_ADRL17 TSU_ADRL18 TSU_ADRL19 TSU_ADRL20 TSU_ADRL21 TSU_ADRL22 TSU_ADRL23 TSU_ADRL24 TSU_ADRL25 TSU_ADRL26 TSU_ADRL27 TSU_ADRL28 TSU_ADRL29 TSU_ADRL30 TSU_ADRL31
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R
P4 Area Address H'FEE0 1964 H'FEE0 196C H'FEE0 1974 H'FEE0 197C H'FEE0 1984 H'FEE0 198C H'FEE0 1994 H'FEE0 199C H'FEE0 19A4 H'FEE0 19AC H'FEE0 19B4 H'FEE0 19BC H'FEE0 19C4 H'FEE0 19CC H'FEE0 19D4 H'FEE0 19DC H'FEE0 19E4 H'FEE0 19EC H'FEE0 19F4 H'FEE0 19FC H'FEE0 1880 H'FEE0 1884
Area 7 Address H'1EE0 1964 H'1EE0 196C H'1EE0 1974 H'1EE0 197C H'1EE0 1984 H'1EE0 198C H'1EE0 1994 H'1EE0 199C H'1EE0 19A4 H'1EE0 19AC H'1EE0 19B4 H'1EE0 19BC H'1EE0 19C4 H'1EE0 19CC H'1EE0 19D4 H'1EE0 19DC H'1EE0 19E4 H'1EE0 19EC H'1EE0 19F4 H'1EE0 19FC H'1EE0 1880 H'1EE0 1884
Access Size
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
TXNLCR0 TXALCR0
Transmit frame counter register (port 0) (normal and erroneous transmission) Receive frame counter register (port 0) (normal reception only)
Receive frame counter register (port 0) (normal and erroneous reception)
RXNLCR0 RXALCR0
R R R R
H'FEE0 1888 H'FEE0 188C H'FEE0 1890 H'FEE0 1894
H'1EE0 1888 H'1EE0 188C H'1EE0 1890 H'1EE0 1894
32 32 32 32
Relay frame counter register (port 1 to FWNLCR0 0) (normal relay only) Relay frame counter register (port 1 to FWALCR0 0) (normal and erroneous relay)
Rev. 1.00 Oct. 01, 2007 Page 795 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name
Transmit frame counter register (port 1) (normal transmission only)
Abbreviation
R/W R R
P4 Area Address H'FEE0 18A0 H'FEE0 18A4
Area 7 Address H'1EE0 18A0 H'1EE0 18A4
Access Size
TXNLCR1 TXALCR1
32 32
Transmit frame counter register (port 1) (normal and erroneous transmission) Receive frame counter register (port 1) (normal reception only)
RXNLCR1
R R R R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
H'FEE0 18A8 H'FEE0 18AC H'FEE0 18B0 H'FEE0 18B4 H'FEE0 0000 H'FEE0 0400 H'FEE0 0408 H'FEE0 0410 H'FEE0 0010 H'FEE0 0030 H'FEE0 0428 H'FEE0 0430 H'FEE0 0438 H'FEE0 0440 H'FEE0 0448 H'FEE0 0450 H'FEE0 0458 H'FEE0 0034 H'FEE0 0038
H'1EE0 18A8 H'1EE0 18AC H'1EE0 18B0 H'1EE0 18B4 H'1EE0 0000 H'1EE0 0400 H'1EE0 0408 H'1EE0 0410 H'1EE0 0010 H'1EE0 0030 H'1EE0 0428 H'1EE0 0430 H'1EE0 0438 H'1EE0 0440 H'1EE0 0448 H'1EE0 0450 H'1EE0 0458 H'1EE0 0034 H'1EE0 0038
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Receive frame counter register (port 1) RXALCR1 (normal and erroneous reception)
Relay frame counter register (port FWNLCR1 0 to 1) (normal relay only)
Relay frame counter register (port 0 to FWALCR1 1) (normal and erroneous relay)
E-DMAC start register E-DMAC mode register
EDSR0 EDMR0
E-DMAC transmit request register EDTRR0 E-DMAC receive request register Transmit descriptor list start address register Receive descriptor list start address register E-MAC/E-DMAC status register E-MAC/E-DMAC status interrupt permission register Transmit/receive status copy enable register Receive missed-frame counter register Transmit FIFO threshold register FIFO depth register EDRRR0 TDLAR0 RDLAR0 EESR0 EESIPR0 TRSCER0 RMFCR0 TFTR0 FDR0
Receiving method control register RMCR0 Receive descriptor fetch address register Receive descriptor finished address register RDFAR0 RDFXR0
Rev. 1.00 Oct. 01, 2007 Page 796 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name
Receive descriptor final flag register
Abbreviation R/W
P4 Area Address H'FEE0 003C H'FEE0 0014 H'FEE0 0018 H'FEE0 001C H'FEE0 0468 H'FEE0 0460 H'FEE0 0800 H'FEE0 0C00 H'FEE0 0C08 H'FEE0 0C10 H'FEE0 0810 H'FEE0 0830 H'FEE0 0C28 H'FEE0 0C30 H'FEE0 0C38 H'FEE0 0C40 H'FEE0 0C48 H'FEE0 0C50 H'FEE0 0C58 H'FEE0 0834 H'FEE0 0838 H'FEE0 083C H'FEE0 0814
Area 7 Address H'1EE0 003C H'1EE0 0014 H'1EE0 0018 H'1EE0 001C H'1EE0 0468 H'1EE0 0460 H'1EE0 0800 H'1EE0 0C00 H'1EE0 0C08 H'1EE0 0C10 H'1EE0 0810 H'1EE0 0830 H'1EE0 0C28 H'1EE0 0C30 H'1EE0 0C38 H'1EE0 0C40 H'1EE0 0C48 H'1EE0 0C50 H'1EE0 0C58 H'1EE0 0834 H'1EE0 0838 H'1EE0 083C H'1EE0 0814
Access Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
RDFFR0 TDFAR0 TDFXR0 TDFFR0 FCFTR0 RPADIR0 EDSR1 EDMR1
R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transmit descriptor fetch address register Transmit descriptor finished address register
Transmit descriptor final flag register Overflow alert FIFO threshold register Receive data padding insert register
E-DMAC start register E-DMAC mode register
E-DMAC transmit request register EDTRR1 E-DMAC receive request register Transmit descriptor list start address register Receive descriptor list start address register E-MAC/E-DMAC status register E-MAC/E-DMAC status interrupt permission register Transmit/receive status copy enable register Receive missed-frame counter register Transmit FIFO threshold register FIFO depth register EDRRR1 TDLAR1 RDLAR1 EESR1 EESIPR1 TRSCER1 RMFCR1 TFTR1 FDR1
Receiving method control register RMCR1 Receive descriptor fetch address register Receive descriptor finished address register
Receive descriptor final flag register
RDFAR1 RDFXR1 RDFFR1 TDFAR1
Transmit descriptor fetch address register
Rev. 1.00 Oct. 01, 2007 Page 797 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name
Transmit descriptor finished address register Transmit descriptor final flag register
Abbreviation
R/W R/W R/W R/W R/W
P4 Area Address H'FEE0 0818 H'FEE0 081C H'FEE0 0C68 H'FEE0 0C60
Area 7 Address H'1EE0 0818 H'1EE0 081C H'1EE0 0C68 H'1EE0 0C60
Access Size
TDFXR1 TDFFR1
32 32 32 32
Overflow alert FIFO threshold register FCFTR1 Receive data padding insert register
RPADIR1
Table 23.3 Register States in Each Operating Mode
Name Software reset register E-MAC mode register E-MAC status register E-MAC interrupt permission register PHY interface register MAC address high register MAC address low register Receive frame length register PHY status register PHY_INT polarity register Transmit retry over counter register
Delayed collision detect counter register Abbreviation
Power-On Manual Reset Reset
Sleep
Standby
ARSTR ECMR0 ECSR0 ECSIPR0 PIR0 MAHR0 MALR0 RFLR0 PSR0 PIPR0 TROCR0 CDCR0 LCCR0
H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'0000000x H'0000000x Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained
Lost carrier counter register
CRC error frame receive counter register CEFCR0
Frame receive error counter register FRECR0
Too-short frame receive counter register Too-long frame receive counter register Residual-bit frame receive counter register Carrier extension loss counter register Carrier extension error counter register
TSFRCR0 TLFRCR0 RFCR0 CERCR0 CEECR0 MAFCR0
Multicast address frame receive counter register
Rev. 1.00 Oct. 01, 2007 Page 798 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name Automatic PAUSE frame register Manual PAUSE frame register Automatic PAUSE frame retransmit count register
PAUSE frame transmit counter register PAUSE frame receive counter register
Abbreviation Reset
Power-On Manual Reset
Sleep
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
APR0 MPR0
H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained
TPAUSER0 H'00000000 H'00000000 Retained PFTCR0 PFRCR0 GECMR0
H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'0000000x H'0000000x Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained
GETHER mode register
Burst cycle count upper-limit register BCULR0 E-MAC mode register E-MAC status register E-MAC interrupt permission register PHY interface register PHY_INT polarity register MAC address high register MAC address low register Receive frame length register PHY status register Transmit retry over counter register
Delayed collision detect counter register
ECMR1 ECSR1 ECSIPR1 PIR1 PIPR1 MAHR1 MALR1 RFLR1 PSR1 TROCR1 CDCR1 LCCR1
Lost carrier counter register
CRC error frame receive counter register CEFCR1
Frame receive error counter register FRECR1
Too-short frame receive counter register Too-long frame receive counter register
TSFRCR1 TLFRCR1 RFCR1 CERCR1 CEECR1 MAFCR1 APR1 MPR1
Residual-bit frame receive counter register
Carrier extension loss counter register Carrier extension error counter register
Multicast address frame receive counter register Automatic PAUSE frame register Manual PAUSE frame register
Rev. 1.00 Oct. 01, 2007 Page 799 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name Automatic PAUSE frame retransmit count register
PAUSE frame transmit counter register PAUSE frame receive counter register
Abbreviation
Power-On Manual Reset Reset
Sleep
Standby
TPAUSER1 PFTCR1 PFRCR1 GECMR1 BCULR1
H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained
GETHER mode register Burst cycle count upper-limit register TSU counter reset register Relay enable register (Port 0 to 1) Relay enable register (Port 1 to 0) Relay FIFO size select register
TSU_CTRST H'00000000 H'00000000 Retained Retained
TSU_FWEN0 TSU_FWEN1 H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained
TSU_FCM
Relay FIFO overflow alert set register TSU_BSYSL0 H'0000003F H'0000003F Retained Retained (port 0) Relay FIFO overflow alert set register TSU_BSYSL1 H'0000003F H'0000003F Retained Retained (port 1) Transmit/relay priority control mode register (port 0) Transmit/relay priority control mode register (port 1) Receive/relay function set register (port 0 to 1) Receive/relay function set register (port 1 to 0)
TSU_PRISL0 TSU_PRISL1 H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained
TSU_FWSL0 H'00000000 H'00000000 Retained Retained TSU_FWSL1 H'00000000 H'00000000 Retained Retained
H'00000000 H'00000000 Retained Retained
Relay function set register (common) TSU_FWSLC Qtag addition/deletion set register (port 0 to 1) Qtag addition/deletion set register (port 1 to 0) Relay status register Relay status interrupt mask register
TSU_QTAG0 H'00000000 H'00000000 Retained Retained TSU_QTAG1 H'00000000 H'00000000 Retained Retained TSU_FWSR H'00000000 H'00000000 Retained Retained
TSU_FWINMK H'00000000 H'00000000 Retained Retained
Added Qtag value set register (port 0 to 1) TSU_ADQT0 H'81000000 H'81000000 Retained Retained Added Qtag value set register (port 1 to 0) TSU_ADQT1 H'81000000 H'81000000 Retained Retained
VLANtag set register (port 0) VLANtag set register (port 1)
TSU_VTAG0 H'00000000 H'00000000 Retained Retained TSU_VTAG1 H'00000000 H'00000000 Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 800 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name CAM entry table busy register CAM entry table enable register CAM entry table POST1 register CAM entry table POST2 register CAM entry table POST3 register CAM entry table POST4 register CAM entry table 0H register CAM entry table 1H register CAM entry table 2H register CAM entry table 3H register CAM entry table 4H register CAM entry table 5H register CAM entry table 6H register CAM entry table 7H register CAM entry table 8H register CAM entry table 9H register CAM entry table 10H register CAM entry table 11H register CAM entry table 12H register CAM entry table 13H register CAM entry table 14H register CAM entry table 15H register CAM entry table 16H register CAM entry table 17H register
Abbreviation
Power-On Manual Reset Reset
Sleep
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
TSU_ ADSBSY TSU_TEN
TSU_POST1 TSU_POST2 TSU_POST3 TSU_POST4 TSU_ADRH0 TSU_ADRH1 TSU_ADRH2 TSU_ADRH3 TSU_ADRH4 TSU_ADRH5 TSU_ADRH6 TSU_ADRH7 TSU_ADRH8 TSU_ADRH9
H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained
TSU_ ADRH10 TSU_ ADRH11 TSU_ ADRH12 TSU_ADRH13 TSU_ ADRH14 TSU_ ADRH15 TSU_ ADRH16 TSU_ ADRH17
Rev. 1.00 Oct. 01, 2007 Page 801 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name CAM entry table 18H register CAM entry table 19H register CAM entry table 20H register CAM entry table 21H register CAM entry table 22H register CAM entry table 23H register CAM entry table 24H register CAM entry table 25H register CAM entry table 26H register CAM entry table 27H register CAM entry table 28H register CAM entry table 29H register CAM entry table 30H register CAM entry table 31H register CAM entry table 0L register CAM entry table 1L register CAM entry table 2L register CAM entry table 3L register CAM entry table 4L register CAM entry table 5L register CAM entry table 6L register
Abbreviation Reset
Power-On Manual Reset
Sleep
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
TSU_ ADRH18 TSU_ ADRH19 TSU_ ADRH20 TSU_ ADRH21 TSU_ ADRH22 TSU_ ADRH23 TSU_ ADRH24 TSU_ ADRH25 TSU_ ADRH26 TSU_ ADRH27 TSU_ ADRH28 TSU_ ADRH29 TSU_ ADRH30 TSU_ ADRH31
H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained
TSU_ADRL0 H'00000000 H'00000000 Retained TSU_ADRL1 H'00000000 H'00000000 Retained TSU_ADRL2 H'00000000 H'00000000 Retained TSU_ADRL3 H'00000000 H'00000000 Retained TSU_ADRL4 H'00000000 H'00000000 Retained TSU_ADRL5 H'00000000 H'00000000 Retained TSU_ADRL6 H'00000000 H'00000000 Retained
Rev. 1.00 Oct. 01, 2007 Page 802 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name CAM entry table 7L register CAM entry table 8L register CAM entry table 9L register CAM entry table 10L register CAM entry table 11L register CAM entry table 12L register CAM entry table 13L register CAM entry table 14L register CAM entry table 15L register CAM entry table 16L register CAM entry table 17L register CAM entry table 18L register CAM entry table 19L register CAM entry table 20L register CAM entry table 21L register CAM entry table 22L register CAM entry table 23L register
Abbreviation Reset
Power-On Manual Reset
Sleep
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
TSU_ADRL7 H'00000000 H'00000000 Retained TSU_ADRL8 H'00000000 H'00000000 Retained TSU_ADRL9 H'00000000 H'00000000 Retained
TSU_ ADRL10 TSU_ ADRL11 TSU_ ADRL12 TSU_ ADRL13 TSU_ ADRL14 TSU_ ADRL15 TSU_ ADRL16 TSU_ ADRL17 TSU_ ADRL18 TSU_ ADRL19 TSU_ ADRL20 TSU_ ADRL21 TSU_ ADRL22 TSU_ ADRL23
H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained
Rev. 1.00 Oct. 01, 2007 Page 803 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name CAM entry table 24L register CAM entry table 25L register CAM entry table 26L register CAM entry table 27L register CAM entry table 28L register CAM entry table 29L register CAM entry table 30L register CAM entry table 31L register
Abbreviation Reset
Power-On Manual Reset
Sleep
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
TSU_ ADRL24 TSU_ ADRL25 TSU_ ADRL26 TSU_ ADRL27 TSU_ ADRL28 TSU_ ADRL29 TSU_ ADRL30 TSU_ ADRL31
H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained
Transmit frame counter register (port TXNLCR0 0) (normal transmission only)
Transmit frame counter register (port 0) (normal and erroneous transmission)
TXALCR0 RXNLCR0 RXALCR0 FWNLCR0 FWALCR0
Receive frame counter register (port 0) (normal reception only) Receive frame counter register (port 0) (normal and erroneous reception) Relay frame counter register (port 1 to 0) (normal relay only) Relay frame counter register (port 1 to 0) (normal and erroneous relay)
Transmit frame counter register (port TXNLCR1 1) (normal transmission only)
Transmit frame counter register (port 1) (normal and erroneous transmission)
TXALCR1 RXNLCR1 RXALCR1
Receive frame counter register (port 1) (normal reception only) Receive frame counter register (port 1) (normal and erroneous reception)
Rev. 1.00 Oct. 01, 2007 Page 804 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name Relay frame counter register (port 0 to 1) (normal relay only) Relay frame counter register (port 0 to 1) (normal and erroneous relay) E-DMAC start register E-DMAC mode register E-DMAC transmit request register E-DMAC receive request register Transmit descriptor list start address register Receive descriptor list start address register E-MAC/E-DMAC status register E-MAC/E-DMAC status interrupt permission register Transmit/receive status copy enable register
Receive missed-frame counter register
Abbreviation Reset
Power-On Manual Reset
Sleep
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
FWNLCR1 FWALCR1 EDSR0 EDMR0 EDTRR0 EDRRR0 TDLAR0 RDLAR0 EESR0 EESIPR0 TRSCER0 RMFCR0 TFTR0 FDR0 RMCR0 RDFAR0 RDFXR0 RDFFR0
H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'001F00FF H'001F00FF Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained
Transmit FIFO threshold register FIFO depth register Receiving method control register
Receive descriptor fetch address register
Receive descriptor finished address register Receive descriptor final flag register
Transmit descriptor fetch address register TDFAR0
Transmit descriptor finished address register Transmit descriptor final flag register
TDFXR0 TDFFR0
Overflow alert FIFO threshold register FCFTR0 Receive data padding insert register E-DMAC start register E-DMAC mode register RPADIR0 EDSR1 EDMR1
Rev. 1.00 Oct. 01, 2007 Page 805 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Name E-DMAC transmit request register E-DMAC receive request register Transmit descriptor list start address register Receive descriptor list start address register E-MAC/E-DMAC status register E-MAC/E-DMAC status interrupt permission register Transmit/receive status copy enable register Receive missed-frame counter register Transmit FIFO threshold register FIFO depth register Receiving method control register Receive descriptor fetch address register Receive descriptor finished address register Receive descriptor final flag register Transmit descriptor fetch address register Transmit descriptor finished address register Transmit descriptor final flag register
Abbreviation Reset
Power-On Manual Reset
Sleep
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
EDTRR1 EDRRR1 TDLAR1 RDLAR1 EESR1 EESIPR1 TRSCER1 RMFCR1 TFTR1 FDR1 RMCR1 RDFAR1 RDFXR1 RDFFR1 TDFAR1 TDFXR1 TDFFR1
H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'001F00FF H'001F00FF Retained H'00000000 H'00000000 Retained
Overflow alert FIFO threshold register FCFTR1 Receive data padding insert register RPADIR1
Rev. 1.00 Oct. 01, 2007 Page 806 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.1
Software Reset Register (ARSTR)
ARSTR resets all blocks (E-MAC, TSU, and E-DMAC) in the GETHER. By writing 1 to the ARST bit in this register, a software reset is issued to all blocks of the GETHER (for 256 cycles of external bus clock Bck). The ARST bit is always read as 0. While a software reset is issued, register access to all blocks of the GETHER is prohibited.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARST
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
Bit 31 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
ARST
0
R/W
Software Reset When 1 is written to this bit, a software reset is issued to all blocks of the GETHER (for 256 cycles of external bus clock Bck). Writing 0 does not affect this bit. This bit is always read as 0. While a software reset is issued, register access to all blocks of the GETHER is prohibited. The following registers are not initialized by a software reset. TSU_ADRH0 to TSU_ADRH31, TSU_ADRL0 to TSU_ADRL31, TXNLCR0, TXNLCR1, TXALCR0, TXALCR1, RXNLCR0, RXNLCR1, RXALCR0, RXALCR1, FWNLCR0, FWNLCR1, FWALCR0, FWALCR1 When relay operations from the E-MAC-1 to E-MAC-0 or from the E-MAC-0 to E-MAC-1 are enabled, a reset must be issued using this bit. A software reset issued by the SWRT and SWRR bits in EDMR does not reset the transfer switching unit (TSU) performing data transfer between the E-MAC-1 and E-MAC-0.
Rev. 1.00 Oct. 01, 2007 Page 807 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.2
E-MAC Mode Register (ECMR)
ECMR is a 32-bit readable/writable register that specifies the operating mode of the GETHER. The settings in this register are normally made in the initialization process following a reset. The operating mode setting must not be changed while the transmitting and receiving functions are enabled. To switch the operating mode, return the E-MAC and E-DMAC to their initial states by means of the SWRT and SWRR bits in EDMR before making settings again.
Bit: 31
30
29
28
27
26
TRCCM
25
24
23
RCSC
22
21
DPAD
20
RZPF
19
ZPF
18
PFR
17
RXF
16
TXF
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R
0 R
0 R/W
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
15
14
13
MCT
12
11
10
9
MPDE
8
7
6
RE
5
TE
4
3
ILB
2
1
DM
0
PRM
Initial value: R/W:
0 R
0 R
0 R/W
0 R
0 R
0 R
0 R/W
0 R
0 R
0 R/W
0 R/W
0 R
0 R/W
0 R
0 R/W
0 R/W
Bit 31 to 27
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
26
TRCCM
0
R/W
Counter Clear Mode Sets the method for clearing the counter register. Refer to the description of each register. 0: Cleared to 0 by writing H'11111111 to the relevant register 1: Cleared to 0 when the relevant register is read
25, 24
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 808 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 23
Bit Name RCSC
Initial Value 0
R/W R/W
Description Checksum Calculation Specifies whether to perform automatic calculation (hardware calculation) of the checksum of the receive frame data unit. 0: Checksum is not automatically calculated 1: Checksum is automatically calculated Note that the checksum calculation of a frame with a VLAN tag is not supported.
22
0
R
Reserved This bit is always read as 0. The write value should always be 0.
21
DPAD
0
R/W
Data Padding 0: Padding is inserted to data less than 60 bytes so it is transmitted as 60-byte data 1: Padding is not inserted to data less than 60 bytes and it is transmitted without changes
20
RZPF
0
R/W
PAUSE Frame Reception with TIME = 0 0: Reception of a PAUSE frame whose TIME parameter value is 0 is disabled 1: Reception of a PAUSE frame whose TIME parameter value is 0 is enabled
Rev. 1.00 Oct. 01, 2007 Page 809 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 19
Bit Name ZPF
Initial Value 0
R/W R/W
Description PAUSE Frame Usage with TIME = 0 Enable/Lost Carrier Error Detection Enable. PAUSE Frame Usage with TIME = 0 Enable (In fullduplex mode) 0: Control of a PAUSE frame whose TIME parameter value is 0 is disabled. The next frame is not transmitted until the time specified by the Timer value has elapsed. If a PAUSE frame whose time specified by the Timer value is 0 is received, that PAUSE frame is discarded. 1: Control of a PAUSE frame whose TIME parameter value is 0 is enabled. When the data size in the receive FIFO becomes smaller than the FCFTR setting before the time specified by the Timer value elapses, an automatic PAUSE frame with a Timer value of 0 is transmitted. On receiving a PAUSE frame with a Timer value of 0, the transmission wait state is canceled. Lost carrier Error Detection Enable (In half-duplex mode) 0: A lost carrier error is checked during frame transmission. 1: A lost carrier error is not checked during frame transmission Lost carrier error detection can be enabled only when the time period from the EX_TX_EN signal activation (high-active) to the ET_CRS = 1 detection is 63BT* or less. If the time period from the EX_TX_EN signal activation (high-active) to the ET_CRS = 1 detection is greater than 63BT*, or if the ET_CRS signal timing is undefined, this bit should not be cleared to 0. Note*: 1BT = 1ns (1000Mbps), 1BT = 10ns (100bps), 1BT = 100nS (10Mbps)
18
PFR
0
R/W
PAUSE Frame Receive Mode 0: PAUSE frame is not transferred to E-DMAC 1: PAUSE frame is transferred to E-DMAC
Rev. 1.00 Oct. 01, 2007 Page 810 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 17
Bit Name RXF
Initial Value 0
R/W R/W
Description Operating Mode for Receiving Port Flow Control 0: PAUSE frame detection is disabled 1: Flow control for the receiving port is enabled
16
TXF
0
R/W
Operating Mode for Transmitting Port Flow Control 0: Flow control for the transmitting port is disabled (Automatic PAUSE frame is not transmitted) 1: Flow control for the transmitting port is enabled (Automatic PAUSE frame is transmitted as required)
15, 14
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
13
MCT
0
R/W
Multicast Address Frame Receive Mode 0: Frames other than the multicast address set by the CAM entry table 0 to 31 (H/L) registers are received. However, if the on-chip CAM entry table reference is disabled, all multicast address frames are received. 1: Only the multicast address set by the CAM entry table 0 to 31 (H/L) registers is received.
12 to 10
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9
MPDE
0
R/W
Magic Packet Detection Enable Enables or disables Magic Packet detection by hardware to allow activation from the Ethernet. 0: Magic Packet detection is not enabled 1: Magic Packet detection is enabled
8, 7
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 811 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 6
Bit Name RE
Initial Value 0
R/W R/W
Description Reception Enable If a switch is made from receiving function enabled (RE = 1) to disabled (RE = 0) while a frame is being received, the receiving function will be enabled until reception of the corresponding frame is completed. 0: Receiving function is disabled 1: Receiving function is enabled
5
TE
0
R/W
Transmission Enable If a switch is made from transmitting function enabled (TE = 1) to disabled (TE = 0) while a frame is being transmitted, the transmitting function will be enabled until transmission of the corresponding frame is completed. 0: Transmitting function is disabled 1: Transmitting function is enabled
4
0
R
Reserved This bit is always read as 0. The write value should always be 0.
3
ILB
0
R/W
Internal Loop Back Mode Specifies loopback mode in the GETHER. 0: Normal data transmission/reception is performed 1: Data loopback is performed inside the E-MAC in the GETHER when DM = 1
2
0
R
Reserved This bit is always read as 0. The write value should always be 0.
1
DM
0
R/W
Duplex Mode Specifies the GETHER transfer method. 0: Half-duplex transfer is specified 1: Full-duplex transfer is specified
Rev. 1.00 Oct. 01, 2007 Page 812 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 0
Bit Name PRM
Initial Value 0
R/W R/W
Description Promiscuous Mode Setting this bit enables all Ethernet frames to be received. All Ethernet frames means all receivable frames, irrespective of differences or enabled/disabled status (destination address, broadcast address, multicast bit, etc.). 0: GETHER performs normal operation 1: GETHER performs promiscuous mode operation
Note: All bits, except for TE and RE, should be changed while the transmitting function is disabled (TE = 0) and the receiving function is disabled (RE = 0).
Rev. 1.00 Oct. 01, 2007 Page 813 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.3
E-MAC Status Register (ECSR)
ECSR is a 32-bit readable/writable register that indicates the status in the E-MAC. This status can be notified to the CPU by interrupts. When 1 is written to the PFROI, LCHNG, MPD, and ICD bits, the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that generate interrupts, the interrupt can be enabled or disabled by the corresponding bit in ECSIPR. Writing 1 or 0 to the PHYI bit does not change its value. The interrupts generated due to this status register are indicated in each ECI bit in EESR of the EDMAC0 for port 0 and the E-DMAC1 for port 1.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICD
PFROI PHYI LCHNG MPD
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R
0 R/W
0 R/W
0 R/W
Bit 31 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
4
PFROI
0
R/W
PAUSE Frame Retransmit Retry Over Indicates whether the retransmit count for retransmitting a PAUSE frame when flow control is enabled has exceeded the retransmit upper-limit set in the automatic PAUSE frame retransmit count register (TPAUSER). 0: PAUSE frame retransmit count has not exceeded the upper limit 1: PAUSE frame retransmit count has exceeded the upper limit
Rev. 1.00 Oct. 01, 2007 Page 814 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 3
Bit Name PHYI
Initial Value 0
R/W R
Description ET_PHY-INT Interrupt Indicates the state of the ET_PHY-INT pin input from the PHY-LSI. 0: ET_PHY-INT pin is not asserted 1: ET_PHY-INT pin is asserted The signal polarity of the ET_PHY-INT pin can be set by PIPR.
2
LCHNG
0
R/W
Link Signal Change Indicates that the ET_LNKSTA signal input from the PHY-LSI has changed from high to low or low to high. However, signal changes may be detected at the timing at which the ET_LNKSTA function was selected using PACR of the GPIO. To check the current Link state, refer to the LMON bit in the PHY status register (PSR). 0: Change in the ET_LNKSTA signal has not been detected 1: Change in the ET_LNKSTA signal has been detected (high to low or low to high)
1
MPD
0
R/W
Magic Packet Detection Indicates that a Magic Packet has been detected on the line. 0: Magic Packet has not been detected 1: Magic Packet has been detected
0
ICD
0
R/W
Illegal Carrier Detection Indicates that the PHY-LSI has detected an illegal carrier on the line. If a change in the signal input from the PHY-LSI occurs in a period shorter than the software recognition period, the correct information may not be obtained. Refer to the timing specification for the PHY-LSI used. 0: PHY-LSI has not detected an illegal carrier on the line 1: PHY-LSI has detected an illegal carrier on the line
Rev. 1.00 Oct. 01, 2007 Page 815 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.4
E-MAC Interrupt Permission Register (ECSIPR)
ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PFRO PHYIP LCHN GIP MPDIP ICDIP IP
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
4
PFROIP
0
R/W
PAUSE Frame Retransmit Interrupt Enable 0: Interrupt notification by the PFROI bit is disabled 1: Interrupt notification by the PFROI bit is enabled
3
PHYIP
0
R/W
ET_PHY-INT Pin Interrupt Enable 0: Interrupt notification by the PHYI bit is disabled 1: Interrupt notification by the PHYI bit is enabled
2
LCHNGIP
0
R/W
LINK Signal Change Interrupt Enable 0: Interrupt notification by the LCHNG bit is disabled 1: Interrupt notification by the LCHNG bit is enabled
1
MPDIP
0
R/W
Magic Packet Detect Interrupt Enable 0: Interrupt notification by the MPD bit is disabled 1: Interrupt notification by the MPD bit is enabled
0
ICDIP
0
R/W
Illegal Carrier Detect Interrupt Enable 0: Interrupt notification by the ICD bit is disabled 1: Interrupt notification by the ICD bit is enabled
Rev. 1.00 Oct. 01, 2007 Page 816 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.5
PHY Interface Register (PIR)
PIR is a 32-bit readable/writable register that provides a means of accessing the PHY-LSI internal registers via the GMII/MII/RMII.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
MDI
2
MDO
1
MMD
0
MDC
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
R
0 R/W
0 R/W
0 R/W
Bit 31 to 4
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
3 2
MDI MDO
Undefined R
GMII/MII/RMII Management Data-In Indicates the level of the ET_MDIO pin. GMII/MII/RMII Management Data-Out Outputs the value set in this bit from the ET_MDIO pin when the MMD bit is 1.
0
R/W
1
MMD
0
R/W
GMII/MII/RMII Management Mode Specifies the data read/write direction with respect to the GMII/MII/RMII. 0: Read direction is specified 1: Write direction is specified
0
MDC
0
R/W
GMII/MII/RMII Management Data Clock Outputs the value set in this bit from the ET_MDC pin and supplies the GMII/MII/RMII with the management data clock. For the method of accessing the GMII/MII/RMII registers, see section 23.5.4, Accessing MII Registers.
Rev. 1.00 Oct. 01, 2007 Page 817 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.6
MAC Address High Register (MAHR)
MAHR is a 32-bit readable/writable register that specifies the upper 32 bits of the 48-bit MAC address. The settings in this register are normally made in the initialization process after a reset. The MAC address setting must not be changed while the transmitting and receiving functions are enabled. Return the E-MAC and E-DMAC to their initial states by means of the SWRT and SWRR bits in EDMR before making settings again.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[47:32]
Initial value: 0 R/W: R/W Bit: 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
MA[31:16]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 0
Bit Name
Initial Value
R/W R/W
Description MAC Address Bits 47 to 16 These bits are used to set the upper 32 bits of the MAC address. If the MAC address is 01-23-45-67-89-AB (hexadecimal), set H'01234567 in this register.
MA[47:16] All 0
Rev. 1.00 Oct. 01, 2007 Page 818 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.7
MAC Address Low Register (MALR)
MALR is a 32-bit readable/writable register that specifies the lower 16 bits of the 48-bit MAC address. The settings in this register are normally made in the initialization process after a reset. The MAC address setting must not be changed while the transmitting and receiving functions are enabled. Return the E-MAC and E-DMAC to their initial states by means of the SWRT and SWRR bits in EDMR before making settings again.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MA[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
MA[15:0]
All 0
R/W
MAC Address Bits 15 to 0 These bits are used to set the lower 16 bits of the MAC address. If the MAC address is 01-23-45-67-89-AB (hexadecimal), set H'000089AB in this register.
Rev. 1.00 Oct. 01, 2007 Page 819 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.8
Receive Frame Length Register (RFLR)
RFLR is a 32-bit readable/writable register that specifies the maximum frame length (in bytes) that can be received by this LSI. The settings in this register must not be changed while the receiving function is enabled.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RFL[17:16]
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RFL[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Initial Bit Name Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0.
31 to 18
17 to 0
RFL[17:0] All 0
R/W Receive Frame Length The frame data described here refers to all fields from the destination address up to the CRC data. Frame contents from the destination address up to the data are actually transferred to memory. CRC data is not included in the transfer. When data that exceeds the specified value is received, the part of data that exceeds the specified value is discarded. H'00000 to H'005EE: 1,518 bytes H'005EF: 1,519 bytes H'005F0: 1,520 bytes : : H'007FF: 2,047 bytes H'00800: 2,048 bytes : : : : : : H'01000: 4,096 bytes H'10000: 65,536 bytes H'20000 to H'3FFFF: 131,072 bytes
Rev. 1.00 Oct. 01, 2007 Page 820 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.9
PHY Status Register (PSR)
PSR is a read-only register that can read interface signals from the PHY-LSI.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LMON
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
LMON
0
R
ET_LNKSTA Pin Status The Link status can be read by connecting the Link signal output from the PHY-LSI to the ET_LNKSTA pin. For the polarity, refer to the specifications of the PHYLSI to be connected.
Rev. 1.00 Oct. 01, 2007 Page 821 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.10 PHY_INT Polarity Register (PIPR) PIPR is used to set the polarity of the ET_PHY-INT pin.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PHYIP
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
Bit 31 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
PHYIP
0
R/W
ET_PHY-INT Input Pin Polarity 0: ET_PHY-INT pin is low-active (enters the interrupt state at low) 1: ET_PHY-INT pin is high-active (enters the interrupt state at high) For the polarity, refer to the specifications of the PHYLSI to be connected.
Rev. 1.00 Oct. 01, 2007 Page 822 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.11 Transmit Retry Over Counter Register (TROCR) TROCR is a 16-bit counter that indicates the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer. When 16 transmission attempts have failed, this register is incremented by 1. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TROC[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
TROC[15:0] All 0
R/W
Transmit Retry Over Count These bits indicate the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer.
Rev. 1.00 Oct. 01, 2007 Page 823 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.12 Delayed Collision Detect Counter Register (CDCR) CDCR is a 16-bit counter that indicates the number of all delayed collisions that occurred on the line after the start of data transmission. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
COSDC[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
COSDC[15:0] All 0
R/W
Delayed Collision Detect Count These bits indicate the number of all delayed collisions after the start of data transmission.
Rev. 1.00 Oct. 01, 2007 Page 824 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.13 Lost Carrier Counter Register (LCCR) LCCR is a 16-bit counter that indicates the number of times the carrier was lost during data transmission. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LCC[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
LCC[15:0]
All 0
R/W
Lost Carrier Count These bits indicate the number of times the carrier was lost during data transmission.
Rev. 1.00 Oct. 01, 2007 Page 825 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.14 CRC Error Frame Receive Counter Register (CEFCR) CEFCR is a 16-bit counter that indicates the number of times a frame with a CRC error was received. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CEFC[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
CEFC[15:0] All 0
R/W
CRC Error Frame Count These bits indicate the number of CRC error frames received.
Rev. 1.00 Oct. 01, 2007 Page 826 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.15 Frame Receive Error Counter Register (FRECR) FRECR is a 16-bit counter that indicates the number of frames for which a receive error was generated by the ET_RX-ER pin input from the PHY-LSI. FRECR is incremented each time the ET_RX-ER pin becomes active. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FREC[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
FREC[15:0] All 0
R/W
Frame Receive Error Count These bits indicate the number of errors during frame reception.
Rev. 1.00 Oct. 01, 2007 Page 827 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.16 Too-Short Frame Receive Counter Register (TSFRCR) TSFRCR is a 16-bit counter that indicates the number of frames received with a length fewer than 64 bytes. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TSFC[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
TSFC[15:0] All 0
R/W
Too-Short Frame Receive Count These bits indicate the number of frames received with a length of less than 64 bytes.
Rev. 1.00 Oct. 01, 2007 Page 828 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.17 Too-Long Frame Receive Counter Register (TLFRCR) TLFRCR is a 16-bit counter that indicates the number of frames received with a length exceeding the value specified by the receive frame length register (RFLR). When the value in this register reaches H'0000FFFF, count-up is halted. This register is not incremented when a frame containing residual bits is received. In this case, the reception of the frame is indicated in the residual-bit frame receive counter register (RFCR). This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TLFC[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
TLFC[15:0] All 0
R/W
Too-Long Frame Receive Count These bits indicate the number of frames received with a length exceeding the value in RFLR.
Rev. 1.00 Oct. 01, 2007 Page 829 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.18 Residual-Bit Frame Receive Counter Register (RFCR) RFCR is a 16-bit counter that indicates the number of frames received containing residual bits (less than an 8-bit unit). When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RFC[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
RFC[15:0]
All 0
R/W
Residual-Bit Frame Receive Count These bits indicate the number of frames received containing residual bits.
Rev. 1.00 Oct. 01, 2007 Page 830 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.19 Carrier Extension Loss Counter Register (CERCR) CERCR is a 16-bit counter that indicates the number of frames received with the carrier extension lost. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CERC[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
CERC[15:0] All 0
R/W
Carrier Extension Loss Frame Receive Count These bits indicate the number of frames received with the carrier extension lost.
Rev. 1.00 Oct. 01, 2007 Page 831 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.20 Carrier Extension Error Counter Register (CEECR) CEECR is a 16-bit counter that indicates the number of frames received with an illegal carrier extension. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CEEC[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
CEEC[15:0] All 0
R/W
Carrier Extension Error Count These bits indicate the number of frames received with an illegal carrier extension.
Rev. 1.00 Oct. 01, 2007 Page 832 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.21 Multicast Address Frame Receive Counter Register (MAFCR) MAFCR is a 16-bit counter that indicates the number of frames received with a specified multicast address. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MAFC[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
MAFC[15:0] All 0
R/W
Multicast Address Frame Count These bits indicate the number of multicast frames received.
Rev. 1.00 Oct. 01, 2007 Page 833 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.22 Automatic PAUSE Frame Register (APR) APR is used to set the TIME parameter value of an automatic PAUSE frame. When an automatic PAUSE frame is transmitted, the value set in this register is used as the TIME parameter of the PAUSE frame.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AP[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
AP[15:0]
All 0
R/W
Automatic PAUSE These bits set the TIME parameter value of an automatic PAUSE frame. One bit is equivalent to 512 bit-time. When flow control is enabled in transmission (PAUSE frame transmission) (TXF bit in ECMR = 1), set a value other than H'0000 in these bits. H'0000: H'0001: 512 x 1 bit-time H'0002: 512 x 2 bit-time : Note: : The bit-time becomes as follows according to the transfer speed. 1000 Mbps: 1 bit-time = 1 ns 100 Mbps: 1 bit-time = 10 ns 10 Mbps: 1 bit-time = 100 ns H'FFFF: 512 x 65,535 bit-time
Rev. 1.00 Oct. 01, 2007 Page 834 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.23 Manual PAUSE Frame Register (MPR) MPR is used to set the TIME parameter value of a manual PAUSE frame. When a manual PAUSE frame is transmitted, the value set in this register is used as the TIME parameter of the PAUSE frame.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MP[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
MP[15:0]
All 0
R/W
Manual PAUSE These bits set the TIME parameter value of a manual PAUSE frame. One bit is equivalent to 512 bit-time. H'0000: H'0001: 512 x 1 bit-time H'0002: 512 x 2 bit-time : Note: : The bit-time becomes as follows according to the transfer speed. 1000 Mbps: 1 bit-time = 1 ns 100 Mbps: 1 bit-time = 10 ns 10 Mbps: 1 bit-time = 100 ns H'FFFF: 512 x 65,535 bit-time
Rev. 1.00 Oct. 01, 2007 Page 835 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.24 Automatic PAUSE Frame Retransmit Count Register (TPAUSER) TPAUSER is used to set the upper limit for the number of times to retransmit an automatic PAUSE frame. The settings in this register must not be changed while the transmitting function is enabled.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TPAUSE[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W Description R Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
TPAUSE[15:0] All 0
R/W Upper Limit for Automatic PAUSE Frame Retransmission H'0000: Retransmit count is unlimited H'0001: Retransmit count is 1 : : H'FFFF: Retransmit count is 65,535
Rev. 1.00 Oct. 01, 2007 Page 836 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.25 PAUSE Frame Transmit Counter Register (PFTCR) PFTCR is a 16-bit counter that indicates the number of times a PAUSE frame is transmitted. This register is cleared to 0 when it is read.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PFTXC[15:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 16
Bit Name
Initial Value All 0
R/W Description R Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
PFTXC[15:0]
All 0
R
PAUSE Frame Transmit Count These bits indicate the total number of automatic PAUSE frames and manual PAUSE frames transmitted.
Rev. 1.00 Oct. 01, 2007 Page 837 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.26 PAUSE Frame Receive Counter Register (PFRCR) PFRCR is a 16-bit counter that indicates the number of times a PAUSE frame is received. This register is cleared to 0 when it is read.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PFRXC[15:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 16
Bit Name
Initial Value All 0
R/W Description R Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
PFRXC[15:0]
All 0
R
PAUSE Frame Receive Count These bits indicate the number of PAUSE frames received when flow control is enabled in reception (RXF bit in ECMR = 1).
Rev. 1.00 Oct. 01, 2007 Page 838 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.27 GETHER Mode Register (GECMR) GECMR is used to set the operating mode of the GETHER.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
SPEED [1]
1
0
BSE SPEED [0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
Bit 31 to 3
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2
SPEED[1]
0
R/W
Transfer Speed Sets the transfer speed in combination with the SPEED[0] bit. Refer to the SPEED[0] bit.
1
BSE
0
R/W
Burst Transfer Enable 0: Burst transfer is not performed 1: Burst transfer is performed when the transfer speed is 1 Gpbs in half-duplex transfer (DM bit in ECMR = 0).
0
SPEED[0]
0
R/W
Transfer Speed The transfer speed is specified by a combination of the SPEED[1] and SPEED[0] bits. SPEED[1:0] 00: 10-Mbps transfer 01: 1-Gbps transfer 10: 100-Mbps transfer 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 839 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.28 Burst Cycle Count Upper-Limit Register (BCULR) BCULR sets the upper limit for the number of burst cycles.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BSTLMT[11:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 12
Bit Name
Initial Value All 0
R/W Description R Reserved These bits are always read as 0. The write value should always be 0.
11 to 0
BSTLMT[11:0] All 0
R/W Burst Cycle Upper-Limit These bits set the upper limit for burst cycles. Burst transfer is finished when the burst timer exceeds the value set in this register. If the burst timer exceeds the value set in this register while a frame is being transferred, burst transfer is continued until transfer of the corresponding frame is completed. H'000 to H'100: Burst cycle count is 256 cycles H'101: Burst cycle count is 257 cycles : : H'FFE: Burst cycle count is 4,094 cycles H'FFF: Burst cycle count is 4,095 cycles Note: 1 cycle = 32 ns
Rev. 1.00 Oct. 01, 2007 Page 840 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.29 TSU Counter Reset Register (TSU_CTRST) TSU_CTRST clears the transmit, receive, and relay frame counters to 0.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
CTRST
7
6
5
4
3
2
1
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 9
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
8
CTRST
0
R/W
TSU Counter Reset When 1 is written to this bit, the values of registers TXNLCR0/TXNLCR1, TXALCR0/TXALCR1, RXNLCR0/RXNLCR1, RXALCR0/RXALCR1, FWNLCR0/FWNLCR1, and FWALCR0/FWALCR1 are cleared to 0. Writing 0 does not affect this bit. This bit is always read as 0.
7 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 841 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.30 Relay Enable Register (Port 0 to 1) (TSU_FWEN0) TSU_FWEN0 enables or disables relay operations from the E-MAC-0 to E-MAC-1 (writing to the relay FIFO).
Bit: 31
FWEN0
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: 0 R/W: R/W Bit: 15
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31
Bit Name FWEN0
Initial Value 0
R/W R/W
Description Port 0 to 1 Relay Operation Enable 0: Port 0 to 1 relay is disabled 1: Port 0 to 1 relay is enabled When the value of bits FCM[2:0] in the relay FIFO size select register (TSU_FCM) is set to H'4, setting this bit to 1 is prohibited.
30 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 842 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.31 Relay Enable Register (Port 1 to 0) (TSU_FWEN1) TSU_FWEN1 enables or disables relay operations from the E-MAC-1 to E-MAC-0 (writing to the relay FIFO).
Bit: 31
FWEN1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: 0 R/W: R/W Bit: 15
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31
Bit Name FWEN1
Initial Value 0
R/W R/W
Description Port 1 to 0 Relay Operation Enable 0: Port 1 to 0 relay is disabled 1: Port 1 to 0 relay is enabled When the value of bits FCM[2:0] in the relay FIFO size select register (TSU_FCM) is set to H'3, setting this bit to 1 is prohibited.
30 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 843 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.32 Relay FIFO Size Select Register (TSU_FCM) TSU_FCM selects the size of the relay FIFO in the TSU, used for relay operations between the EMAC-0 and E-MAC-1.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FCM[2:0]
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
Bit 31 to 3
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
FCM[2:0]
All 0
R/W
Relay FIFO Size H'0: Port 0 to 1: 3 Kbytes H'1: Port 0 to 1: 4 Kbytes H'2: Port 0 to 1: 5 Kbytes H'3: Port 0 to 1: 6 Kbytes H'4: Port 0 to 1: Not used H'5: Port 0 to 1: 1 Kbyte H'6: Port 0 to 1: 2 Kbytes H'7: Setting prohibited This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1). When data equal to or greater than the specified size of 64 bytes is stored in the relay FIFO, an overflow is detected and the frame being transferred is discarded. Port 1 to 0: 3 Kbytes Port 1 to 0: 2 Kbytes Port 1 to 0: 1 Kbyte Port 1 to 0: Not used Port 1 to 0: 6 Kbytes Port 1 to 0: 5 Kbytes Port 1 to 0: 4 Kbytes
Rev. 1.00 Oct. 01, 2007 Page 844 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.33 Relay FIFO Overflow Alert Set Register (Port 0) (TSU_BSYSL0) The TSU has an alert function, which informs the E-MAC-0 and E-MAC-1 that writing to the relay FIFO will be disabled when the data volume written in the relay FIFO during relay operations exceeds a certain threshold. TSU_BSYSL0 sets the threshold of the relay FIFO when the TSU alerts the E-MAC-0 that writing in the relay FIFO will be disabled during relay operations.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BSYSL0[5:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 31 to 6
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 845 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 5 to 0
Bit Name
Initial Value
R/W R/W
Description These bits set the threshold of the port 0-to-1 relay FIFO size in 256-byte units when the TSU alerts the EMAC-0 that writing in the relay FIFO will be disabled during relay operations. H'00: 0 byte H'01: 256 bytes H'02: 512 bytes : : H'29: 12,032 bytes H'30: 12,288 bytes Settings are disabled for H'31 to H'3F. (Alert is not always carried out.) When the data volume written in the relay FIFO exceeds the threshold set in these bits, the TSU alerts the E-MAC-0 that writing in the relay FIFO will be disabled. Thereafter, alerting will be stopped when the data volume written in the relay FIFO becomes 16 bytes smaller than this threshold. When H'00 is set, the TSU always alerts the E-MAC-0 that writing to the relay FIFO will be disabled. When the value set is equal to or higher than the port 0-to-1 relay FIFO size set by bits FCM[2:0] in TSU_FCM, the TSU does not alert the E-MAC-0 that writing in the relay FIFO will be disabled. This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1). When the enable bit of relay operations (FWEN0 bit in TSU_FWEN0 or FWEN1 bit in TSU_FWEN1) is cleared to 0, the TSU stops alerting the E-MAC-0 that writing in the relay FIFO will be disabled.
BSYSL0[5:0] 111111
Rev. 1.00 Oct. 01, 2007 Page 846 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.34 Relay FIFO Overflow Alert Set Register (Port 1) (TSU_BSYSL1) The TSU has an alert function, which informs the E-MAC-0 and E-MAC-1 that writing to the relay FIFO will be disabled when the data volume written in the relay FIFO during relay operations exceeds a certain threshold. TSU_BSYSL1 sets the threshold of the relay FIFO when the TSU alerts the E-MAC-1 that writing in the relay FIFO will be disabled during relay operations.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BSYSL1[5:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 31 to 6
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 847 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 5 to 0
Bit Name
Initial Value
R/W R/W
Description These bits set the threshold of the port 1-to-0 relay FIFO size in 256-byte units when the TSU alerts the EMAC-1 that writing in the relay FIFO will be disabled during relay operations. H'00: 0 byte H'01: 256 bytes H'02: 512 bytes : : H'16: 5632 bytes H'17: 5888 bytes Settings are disabled for H'18 to H'3F. (Alert is not always carried out.) When the data volume written in the relay FIFO exceeds the threshold set in these bits, the TSU alerts the E-MAC-1 that writing in the relay FIFO will be disabled. Thereafter, alerting will be stopped when the data volume written in the relay FIFO becomes 16 bytes smaller than this threshold. When H'00 is set, the TSU always alerts the E-MAC-1 that writing to the relay FIFO will be disabled. When the value set is equal to or higher than the port 1-to-0 relay FIFO size set by bits FCM[2:0] in TSU_FCM, the TSU does not alert the E-MAC-1 that writing in the relay FIFO will be disabled. This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1). When the enable bit of relay operations (FWEN0 bit in TSU_FWEN0 or FWEN1 bit in TSU_FWEN1) is cleared to 0, the TSU stops alerting the E-MAC-1 that writing in the relay FIFO will be disabled.
BSYSL1[5:0] All 1
Rev. 1.00 Oct. 01, 2007 Page 848 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.35 Transmit/Relay Priority Control Mode Register (Port 0) (TSU_PRISL0) TSU_PRISL0 sets the priority control mode when the transmission request from the E-DMAC to E-MAC-0 comes into collision with port 1 to 0 relay operations. This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
PRIMD0[2:0]
12
11
10
9
8
7
6
5
4
3
2
1
0
PRISL0[7:0]
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 15
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
14 to 12
PRIMD0[2:0] All 0
R/W
These bits set the priority control mode of E-MAC-0 transmission and port 1 to 0 relay operations. H'0: Round robin H'1: Transmission priority H'2: Relay priority H'4: Round robin, however switched to relay priority when relay FIFO use amount exceeds the PRISL0[7:0] setting H'5: Transmission priority, however switched to relay priority when relay FIFO use amount exceeds the PRISL0[7:0] setting Others: Setting prohibited
11 to 8
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 849 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 7 to 0
Bit Name
Initial Value
R/W R/W
Description These bits set the threshold of the port 1-to-0 relay FIFO size in 64-byte units in the event of switching to relay priority when bits PRIMD0[2:0] are set to H'4 or H'5. H'00: 0 byte H'01: 64 bytes H'02: 128 bytes : : H'5E: 6,016 bytes H'5F: 6,080 bytes Settings are disabled for H'60 to H'FF. When H'00 is set in these bits, relay always takes priority. When the value set is equal to or above the port 1-to-0 relay FIFO size set by bits FCM[2:0] in TSU_FCM, if bits PRIMD0[2:0] are H'4, round robin will always be set. If bits PRIMD0[2:0] are H'5, transmission always takes priority.
PRISL0[7:0] All 0
Rev. 1.00 Oct. 01, 2007 Page 850 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.36 Transmit/Relay Priority Control Mode Register (Port 1) (TSU_PRISL1) TSU_PRISL1 sets the priority control mode when the transmission request from the E-DMAC to E-MAC-1 comes into collision with port 0 to 1 relay operations. This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
PRIMD1[2:0]
12
11
10
9
8
7
6
5
4
3
2
1
0
PRISL1[7:0]
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 15
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
14 to 12
PRIMD1[2:0] All 0
R/W
These bits set the priority control mode of E-MAC-1 transmission and port 0 to 1 relay operations. H'0: Round robin H'1: Transmission priority H'2: Relay priority H'4: Round robin, however switched to relay priority when relay FIFO use amount exceeds the PRISL1[7:0] setting H'5: Transmission priority, however switched to relay priority when relay FIFO use amount exceeds the PRISL1[7:0] setting Others: Setting prohibited
11 to 8
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 851 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 7 to 0
Bit Name
Initial Value
R/W R/W
Description These bits set the threshold of the port 0-to-1 relay FIFO size in 64-byte units in the event of switching to relay priority when bits PRIMD1[2:0] are set to H'4 or H'5. H'00: 0 byte H'01: 64 bytes H'02: 128 bytes : : H'5E: 6,016 bytes H'5F: 6,080 bytes Settings are disabled for H'60 to H'FF. When H'00 is set in these bits, relay always takes priority. When the value set is equal to or above the port 0-to-1 relay FIFO size set by bits FCM[2:0] in TSU_FCM, if bits PRIMD1[2:0] are H'4, round robin will always be set. If bits PRIMD1[2:0] are H'5, transmission always takes priority.
PRISL1[7:0] All 0
Rev. 1.00 Oct. 01, 2007 Page 852 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.37 Receive/Relay Function Set Register (Port 0 to 1) (TSU_FWSL0) TSU_FWSL0 sets the processing method (enable or disable relay operation) of each frame in port 0 reception and port 0 to 1 relay operations. For multicast frames and frames whose destinations are other than this LSI, the processing method in relay operations can be determined by referring to the CAM evaluation results. (For details, refer to section 23.4.5, CAM Function.) This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
RMSA0
3
2
1
0
FW50 FW40 FW30 FW20 FW10
Initial value: R/W:
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R
0 R
0 R/W
0 R
0 R
0 R
0 R
Bit 31 to 13
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
12
FW50
0
R/W
Sets the processing method when frames from port 0 are MAC control frames. 0: Frames are not relayed 1: Frames are relayed to port 1
11
FW40
0
R/W
Sets the processing method when frames from port 0 are addressed to this LSI. 0: Frames are not relayed 1: Frames are relayed to port 1
10
FW30
0
R/W
Sets the processing method when frames from port 0 are Broadcast frames. 0: Frames are not relayed 1: Frames are relayed to port 1
Rev. 1.00 Oct. 01, 2007 Page 853 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 9
Bit Name FW20
Initial Value 0
R/W R/W
Description Sets the processing method when frames from port 0 are multicast frames. 0: CAM hit: Frames are relayed to port 1 CAM mishit: Frames are not relayed 1: CAM hit: Frames are not relayed CAM mishit: Frames are relayed to port 1
8
FW10
0
R/W
Sets the processing method when frames from port 0 are addressed to other than this LSI. 0: CAM hit: Frames are relayed to port 1 CAM mishit: Frames are not relayed 1: CAM hit: Frames are not relayed CAM mishit: Frames are relayed to port 1
7 to 5
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
RMSA0
0
R/W
Sets the processing method when the SA (source address) of a frame received from port 0 is not registered in the entry table. 0: Frame is not received 1: Frame is received However, a frame discarded because of the VLANtag evaluation result is not received. If a frame whose source address is not registered in the entry table has been received, a carrier extension error is issued regardless of whether the frame is received or not.
3 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 854 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.38 Receive/Relay Function Set Register (Port 1 to 0) (TSU_FWSL1) TSU_FWSL1 sets the processing method (enable or disable relay operation) of each frame in port 1 reception and port 1 to 0 relay operations. For multicast frames and frames whose destinations are other than this LSI, the processing method in relay operations can be determined by referring to the CAM evaluation results. (For details, refer to section 23.4.5, CAM Function.) This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
RMSA1
3
2
1
0
FW51 FW41 FW31 FW21 FW11
Initial value: R/W:
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R
0 R
0 R/W
0 R
0 R
0 R
0 R
Bit 31 to 13
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
12
FW51
0
R/W
Sets the processing method when frames from port 1 are MAC control frames. 0: Frames are not relayed 1: Frames are relayed to port 0
11
FW41
0
R/W
Sets the processing method when frames from port 1 are addressed to this LSI. 0: Frames are not relayed 1: Frames are relayed to port 0
10
FW31
0
R/W
Sets the processing method when frames from port 1 are Broadcast frames. 0: Frames are not relayed 1: Frames are relayed to port 0
Rev. 1.00 Oct. 01, 2007 Page 855 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 9
Bit Name FW21
Initial Value 0
R/W R/W
Description Sets the processing method when frames from port 1 are multicast frames. 0: CAM hit: Frames are relayed to port 0 CAM mishit: Frames are not relayed 1: CAM hit: Frames are not relayed CAM mishit: Frames are relayed to port 0
8
FW11
0
R/W
Sets the processing method when frames from port 1 are addressed to other than this LSI. 0: CAM hit: Frames are relayed to port 0 CAM mishit: Frames are not relayed 1: CAM hit: Frames are not relayed CAM mishit: Frames are relayed to port 0
7 to 5
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
RMSA1
0
R/W
Sets the processing method when the SA (source address) of a frame received from port 1 is not registered in the entry table. 0: Frame is not received 1: Frame is received However, a frame discarded because of the VLANtag evaluation result is not received. If a frame whose source address is not registered in the entry table has been received, a carrier extension error is issued regardless of whether the frame is received or not.
3 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 856 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.39 Relay Function Set Register (Common) (TSU_FWSLC) When the CAM is used, the referred area in the CAM entry table (partially or wholly) can be specified by the TSU_POST1 to TSU_POST4 registers. TSU_FWSLC enables settings by the TSU_POST1 to TSU_POST4 registers. This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POST POST ENU ENL
Initial value: R/W:
0 R
0 R
0 R/W
0 R/W
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 14
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13
POSTENU
0
R/W
Enables the settings of the POST field of CAM entry tables 0 to 15 (settings by the TSU_POST1 and TSU_POST2 registers). 0: Disables the settings of the POST field. (The CAM entry table is referred to only in port 0 reception.) 1: Enables the settings of the POST field. (The CAM entry table reference conditions follow the POST field settings.)
12
POSTENL
0
R/W
Enables the settings of the POST field of CAM entry tables 16 to 31 (settings by the TSU_POST3 and TSU_POST4 registers). 0: Disables the settings of the POST field. (The CAM entry table is referred to only in port 1 reception.) 1: Enables the settings of the POST field. (The CAM entry table reference conditions follow the POST field settings.)
Rev. 1.00 Oct. 01, 2007 Page 857 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 11 to 0
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 858 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.40 Qtag Addition/Deletion Set Register (Port 0 to 1) (TSU_QTAG0) TSU_QTAG0 sets the functions adding Qtag to the normal Ethernet frames (no Qtag) to convert them into IEEE802.1Q frames (with Qtag) and deleting Qtag from IEEE802.1Q frames (with Qtag) to convert them into normal Ethernet frames (no Qtag) during port 0 to 1 relay operations. This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
QTAG0[2:0]
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
Bit 31 to 3
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
QTAG0[2:0]
All 0
R/W
These bits set Qtag adding and deleting functions during port 0 to 1 relay operations. H'0: Disables Qtag adding and deleting functions H'1: Disables Qtag adding and deleting functions H'2: Deletes Qtag from frames with Qtag H'3: Adds Qtag to frames with no Qtag (Does not add Qtag to MAC control frames) H'4: Disables Qtag adding and deleting functions H'5: Setting prohibited H'6: Setting prohibited H'7: Adds Qtag to frames with no Qtag (Adds Qtag to MAC control frames) This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Rev. 1.00 Oct. 01, 2007 Page 859 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.41 Qtag Addition/Deletion Set Register (Port 1 to 0) (TSU_QTAG1) TSU_QTAG1 sets the functions adding Qtag to the normal Ethernet frames (no Qtag) to convert them into IEEE802.1Q frames (with Qtag) and deleting Qtag from IEEE802.1Q frames (with Qtag) to convert them into normal Ethernet frames (no Qtag) during port 1 to 0 relay operations. This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
QTAG1[2:0]
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
Bit 31 to 3
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
QTAG1[2:0]
All 0
R/W
These bits set Qtag adding and deleting functions during port 1 to 0 relay operations. H'0: Disables Qtag adding and deleting functions H'1: Disables Qtag adding and deleting functions H'2: Deletes Qtag from frames with Qtag H'3: Adds Qtag to frames with no Qtag (Does not add Qtag to MAC control frames) H'4: Disables Qtag adding and deleting functions H'5: Setting prohibited H'6: Setting prohibited H'7: Adds Qtag to frames with no Qtag (Adds Qtag to MAC control frames) This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Rev. 1.00 Oct. 01, 2007 Page 860 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.42 Relay Status Register (TSU_FWSR) TSU_FWSR is a 32-bit readable/writable register that indicates the status during relay operations. By setting the relay status interrupt mask register (TSU_FWINMK), this status can be notified to the CPU as an interrupt source. The status bit set to 1 will be cleared to 0 by writing 1 to the corresponding bit. (The status bit retains the value until it is cleared to 0.) Interrupts generated due to this status register are identified as EINT2. For details on the priority order of interrupts, see section 9.4.6, Interrupt Exception Handling and Priority in section 9, Interrupt Controller (INTC). If an error other than RBSY1 or RBSY0 occurs during relay operations, the corresponding relay frame is discarded.
Bit: 31
30
29
28
27
26
25
24
23
OVF0
22
RBSY 0
21
RINT 60
20
RINT 50
19
RINT 40
18
RINT 30
17
RINT 20
16
RINT 10
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
15
14
13
12
11
10
9
8
7
OVF1
6
RBSY 1
5
RINT 61
4
RINT 51
3
RINT 41
2
RINT 31
1
RINT 21
0
RINT 11
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 24
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
23 22
OVF0 RBSY0
0 0
R/W R/W
Port 0-to-1 Relay FIFO Overflow Detect Set to 1 when the port 0-to-1 relay FIFO overflows. E-MAC-0 Overflow Alert Signal Output Set to 1 when the threshold of TSU_BSYSL0 is valid and exceeded.
21
RINT60
0
R/W
E-MAC-0 Carrier Extension Loss Error Detect Set to 1 when a frame with the carrier extension lost is received in the E-MAC-0.
Rev. 1.00 Oct. 01, 2007 Page 861 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 20
Bit Name RINT50
Initial Value 0
R/W R/W
Description E-MAC-0 Residual-Bit Frame Receive Set to 1 when a frame containing residual bits (less than an 8-bit unit) is received in the E-MAC-0.
19
RINT40
0
R/W
E-MAC-0 Too-Long Frame Receive Set to 1 when a frame exceeding the value set by RFLR0 is received in the E-MAC-0.
18
RINT30
0
R/W
E-MAC-0 Too-Short Frame Receive Set to 1 when a frame with a length of less than 64 bytes is received in the E-MAC-0.
17
RINT20
0
R/W
E-MAC-0 Frame Receive Error Set to 1 when a receive error is detected on the ET0_RX-ER pin input from the PHY-LSI in the E-MAC0.
16
RINT10
0
R/W
E-MAC-0 CRC Error Frame Receive Set to 1 when a receive frame results in a CRC error in the E-MAC-0.
15 to 8
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
7 6
OVF1 RBSY1
0 0
R/W R/W
Port 1-to-0 Relay FIFO Overflow Detect Set to 1 when the port 1-to-0 relay FIFO overflows. E-MAC-1 Overflow Alert Signal Output Set to 1 when the threshold of TSU_BSYSL1 is valid and exceeded.
5
RINT61
0
R/W
E-MAC-1 Carrier Extension Loss Error Detect Set to 1 when a frame with the carrier extension lost is received in the E-MAC-1.
4
RINT51
0
R/W
E-MAC-1 Residual-Bit Frame Receive Set to 1 when a frame containing residual bits (less than an 8-bit unit) is received in the E-MAC-1.
3
RINT41
0
R/W
E-MAC-1 Too-Long Frame Receive Set to 1 when a frame exceeding the value set by RFLR1 is received in the E-MAC-1.
Rev. 1.00 Oct. 01, 2007 Page 862 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 2
Bit Name RINT31
Initial Value 0
R/W R/W
Description E-MAC-1 Too-Short Frame Receive Set to 1 when a frame with a length of less than 64 bytes is received in the E-MAC-1.
1
RINT21
0
R/W
E-MAC-1 Frame Receive Error Set to 1 when a receive error is detected on the ET1_RX-ER pin input from the PHY-LSI in the E-MAC1.
0
RINT11
0
R/W
E-MAC-1 CRC Error Frame Receive Set to 1 when a receive frame results in a CRC error in the E-MAC-1.
Rev. 1.00 Oct. 01, 2007 Page 863 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.43 Relay Status Interrupt Mask Register (TSU_FWINMK) TSU_FWINMK is a 32-bit readable/writable register that sets the interrupt mask for status bits in TSU_FWSR.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OVFM RBSYM RINTM RINTM RINTM RINTM RINTM RINTM 0 0 60 50 40 30 20 10
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OVFM RBSYM RINTM RINTM RINTM RINTM RINTM RINTM 1 1 61 51 41 31 21 11
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 24
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
23
OVFM0
0
R/W
Port 0-to-1 Relay FIFO Overflow Detect Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
22
RBSYM0
0
R/W
E-MAC-0 Overflow Alert Signal Output Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
21
RINTM60
0
R/W
E-MAC-0 Carrier Extension Loss Error Detect Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
20
RINTM50
0
R/W
E-MAC-0 Residual-Bit Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
19
RINTM40
0
R/W
E-MAC-0 Too-Long Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
Rev. 1.00 Oct. 01, 2007 Page 864 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 18
Bit Name RINTM30
Initial Value 0
R/W R/W
Description E-MAC-0 Too-Short Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
17
RINTM20
0
R/W
E-MAC-0 Frame Receive Error Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
16
RINTM10
0
R/W
E-MAC-0 CRC Error Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
15 to 8
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
7
OVFM1
0
R/W
Port 1-to-0 Relay FIFO Overflow Detect Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
6
RBSYM1
0
R/W
E-MAC-1 Overflow Alert Signal Output Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
5
RINTM61
0
R/W
E-MAC-1 Carrier Extension Loss Error Detect Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
4
RINTM51
0
R/W
E-MAC-1 Residual-Bit Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
3
RINTM41
0
R/W
E-MAC-1 Too-Long Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
2
RINTM31
0
R/W
E-MAC-1 Too-Short Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
Rev. 1.00 Oct. 01, 2007 Page 865 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 1
Bit Name RINTM21
Initial Value 0
R/W R/W
Description E-MAC-1 Frame Receive Error Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
0
RINTM11
0
R/W
E-MAC-1 CRC Error Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled
Rev. 1.00 Oct. 01, 2007 Page 866 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.44 Added Qtag Value Set Register (Port 0 to 1) (TSU_ADQT0) TSU_ADQT0 sets the Qtag data to be added in the conversion of normal Ethernet frames (no Qtag) to IEEE802.1Q frames (with Qtag) in port 0 to 1 relay operations (if bits QTAG0[2:0] in TSU_QTAG0 are set to H'3 or H'7 when using the Qtag adding function). This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
QTAG0[31:16]
Initial value: 1 R/W: R/W Bit: 15
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
QTAG0[15:13]
QTAG0[11:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value
R/W Description
QTAG0[31:16] H'8100 R/W Be sure to set the value of the upper 16 bits (QTAG0[31:16]) as H'8100 (indicates the Qtag extension frame format is used). The value read is H'8100. QTAG0[15:13] H'0 R/W Priority Setting (PRT) These bits set the processing priority of frames with Qtag. For details on the settings, refer to the specifications on Qtag control specified in IEEE802.1Q.
15 to 13
12
0
R
Reserved This bit is always read as 0. The write value should always be 0.
11 to 0
QTAG0[11:0]
H'000
R/W V-LAN ID Setting (VID) These bits should be set when frames with Qtag are to be used in systems supporting V-LAN. For details on settings, refer to the specifications on Qtag control specified in IEEE802.1Q.
Rev. 1.00 Oct. 01, 2007 Page 867 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.45 Added Qtag Value Set Register (Port 1 to 0) (TSU_ADQT1) TSU_ADQT1 sets the Qtag data to be added in the conversion of normal Ethernet frames (no Qtag) to IEEE802.1Q frames (with Qtag) in port 1 to 0 relay operations (if bits QTAG1[2:0] in TSU_QTAG1 are set to H'3 or H'7 when using the Qtag adding function). This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
QTAG1[31:16]
Initial value: 1 R/W: R/W Bit: 15
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
QTAG1[15:13]
QTAG1[11:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value
R/W Description
QTAG1[31:16] H'8100 R/W Be sure to set the value of the upper 16 bits (QTAG1[31:16]) as H'8100 (indicates the Qtag extension frame format is used). The value read is H'8100. QTAG1[15:13] H'0 R/W Priority Setting (PRT) These bits set the processing priority of frames with Qtag. For details on the settings, refer to the specifications on Qtag control specified in IEEE802.1Q.
15 to 13
12
0
R
Reserved This bit is always read as 0. The write value should always be 0.
11 to 0
QTAG1[11:0]
H'000
R/W V-LAN ID Setting (VID) These bits should be set when frames with Qtag are to be used in systems supporting V-LAN. For details on settings, refer to the specifications on Qtag control specified in IEEE802.1Q.
Rev. 1.00 Oct. 01, 2007 Page 868 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.46 VLANtag Set Register (Port 0) (TSU_VTAG0) TSU_VTAG0 enables or disables the frame receive/discard evaluation function based on the VLAN number in port 0 relay operations, and also sets the VLAN number.
Bit: 31
VTAG 0
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: 0 R/W: R/W Bit: 15
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VID0[11:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31
Bit Name VTAG0
Initial Value 0
R/W Description R/W Port 0 VLANtag Evaluation Function 0: Disables receive/discard evaluation for frames based on the VLAN number 1: Enables receive/discard evaluation for frames based on the VLAN number
30 to 12
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
11 to 0
VID0[11:0]
All 0
R/W V-LAN ID Setting (VID) These bits set the VLAN number received by port 0 receive frames.
Rev. 1.00 Oct. 01, 2007 Page 869 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.47 VLANtag Set Register (Port 1) (TSU_VTAG1) TSU_VTAG1 enables or disables the frame receive/discard evaluation function based on the VLAN number in port 1 relay operations, and also sets the VLAN number.
Bit: 31
VTAG 1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: 0 R/W: R/W Bit: 15
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VID1[11:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31
Bit Name VTAG1
Initial Value 0
R/W Description R/W Port 1 VLANtag Evaluation Function 0: Disables receive/discard evaluation for frames based on the VLAN number 1: Enables receive/discard evaluation for frames based on the VLAN number
30 to 12
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
11 to 0
VID1[11:0]
All 0
R/W V-LAN ID Setting (VID) These bits set the VLAN number received by port 1 receive frames.
Rev. 1.00 Oct. 01, 2007 Page 870 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.48 CAM Entry Table Busy Register (TSU_ADSBSY) When CAM entry table registers (TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31) are set by register writing, the ADSBSY bit in this register is set to 1 (when the process of reflecting the contents of the CAM entry table registers in the CAM controller is completed inside the TSU, the ADSBSY bit is automatically restored to 0). Access to TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31 is prohibited, while the ADSBSY bit in this register is set to 1. This register is a read-only status register, which must not be written to.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADS BSY
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 1
Bit Name
Initial Value All 0
R/W Description R Reserved These bits are always read as 0. The write value should always be 0.
0
ADSBSY
0
R
CAM Entry Table Setting Busy When TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31 are set by register writing, this bit is set to 1. When the process of reflecting the contents of the CAM entry table registers in the CAM controller is completed inside the TSU, this bit is automatically restored to 0. Access to TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31 is prohibited, while this bit is set to 1. Writing to this register is also prohibited.
Rev. 1.00 Oct. 01, 2007 Page 871 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.49 CAM Entry Table Enable Register (TSU_TEN) TSU_TEN enables or disables the settings of TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31.
Bit: 31
TEN0
30
TEN1
29
TEN2
28
TEN3
27
TEN4
26
TEN5
25
TEN6
24
TEN7
23
TEN8
22
21
20
19
18
17
16
TEN9 TEN10 TEN11 TEN12 TEN13 TEN14 TEN15
Initial value: 0 R/W: R/W Bit: 15
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TEN16 TEN17 TEN18 TEN19 TEN20 TEN21 TEN22 TEN23 TEN24 TEN25 TEN26 TEN27 TEN28 TEN29 TEN30 TEN31
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31
Bit Name TEN0
Initial Value 0
R/W R/W
Description CAM Entry Table 0 (TSU_ADRH0 and TSU_ADRL0) Setting 0: Disabled 1: Enabled
30
TEN1
0
R/W
CAM Entry Table 1 (TSU_ADRH1 and TSU_ADRL1) Setting 0: Disabled 1: Enabled
29
TEN2
0
R/W
CAM Entry Table 2 (TSU_ADRH2 and TSU_ADRL2) Setting 0: Disabled 1: Enabled
28
TEN3
0
R/W
CAM Entry Table 3 (TSU_ADRH3 and TSU_ADRL3) Setting 0: Disabled 1: Enabled
27
TEN4
0
R/W
CAM Entry Table 4 (TSU_ADRH4 and TSU_ADRL4) Setting 0: Disabled 1: Enabled
Rev. 1.00 Oct. 01, 2007 Page 872 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 26
Bit Name TEN5
Initial Value 0
R/W R/W
Description CAM Entry Table 5 (TSU_ADRH5 and TSU_ADRL5) Setting 0: Disabled 1: Enabled
25
TEN6
0
R/W
CAM Entry Table 6 (TSU_ADRH6 and TSU_ADRL6) Setting 0: Disabled 1: Enabled
24
TEN7
0
R/W
CAM Entry Table 7 (TSU_ADRH7 and TSU_ADRL7) Setting 0: Disabled 1: Enabled
23
TEN8
0
R/W
CAM Entry Table 8 (TSU_ADRH8 and TSU_ADRL8) Setting 0: Disabled 1: Enabled
22
TEN9
0
R/W
CAM Entry Table 9 (TSU_ADRH9 and TSU_ADRL9) Setting 0: Disabled 1: Enabled
21
TEN10
0
R/W
CAM Entry Table 10 (TSU_ADRH10 and TSU_ADRL10) Setting 0: Disabled 1: Enabled
20
TEN11
0
R/W
CAM Entry Table 11 (TSU_ADRH11 and TSU_ADRL11) Setting 0: Disabled 1: Enabled
19
TEN12
0
R/W
CAM Entry Table 12 (TSU_ADRH12 and TSU_ADRL12) Setting 0: Disabled 1: Enabled
Rev. 1.00 Oct. 01, 2007 Page 873 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 18
Bit Name TEN13
Initial Value 0
R/W R/W
Description CAM Entry Table 13 (TSU_ADRH13 and TSU_ADRL13) Setting 0: Disabled 1: Enabled
17
TEN14
0
R/W
CAM Entry Table 14 (TSU_ADRH14 and TSU_ADRL14) Setting 0: Disabled 1: Enabled
16
TEN15
0
R/W
CAM Entry Table 15 (TSU_ADRH15 and TSU_ADRL15) Setting 0: Disabled 1: Enabled
15
TEN16
0
R/W
CAM Entry Table 16 (TSU_ADRH16 and TSU_ADRL16) Setting 0: Disabled 1: Enabled
14
TEN17
0
R/W
CAM Entry Table 17 (TSU_ADRH17 and TSU_ADRL17) Setting 0: Disabled 1: Enabled
13
TEN18
0
R/W
CAM Entry Table 18 (TSU_ADRH18 and TSU_ADRL18) Setting 0: Disabled 1: Enabled
12
TEN19
0
R/W
CAM Entry Table 19 (TSU_ADRH19 and TSU_ADRL19) Setting 0: Disabled 1: Enabled
11
TEN20
0
R/W
CAM Entry Table 20 (TSU_ADRH20 and TSU_ADRL20) Setting 0: Disabled 1: Enabled
Rev. 1.00 Oct. 01, 2007 Page 874 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 10
Bit Name TEN21
Initial Value 0
R/W R/W
Description CAM Entry Table 21 (TSU_ADRH21 and TSU_ADRL21) Setting 0: Disabled 1: Enabled
9
TEN22
0
R/W
CAM Entry Table 22 (TSU_ADRH22 and TSU_ADRL22) Setting 0: Disabled 1: Enabled
8
TEN23
0
R/W
CAM Entry Table 23 (TSU_ADRH23 and TSU_ADRL23) Setting 0: Disabled 1: Enabled
7
TEN24
0
R/W
CAM Entry Table 24 (TSU_ADRH24 and TSU_ADRL24) Setting 0: Disabled 1: Enabled
6
TEN25
0
R/W
CAM Entry Table 25 (TSU_ADRH25 and TSU_ADRL25) Setting 0: Disabled 1: Enabled
5
TEN26
0
R/W
CAM Entry Table 26 (TSU_ADRH26 and TSU_ADRL26) Setting 0: Disabled 1: Enabled
4
TEN27
0
R/W
CAM Entry Table 27 (TSU_ADRH27 and TSU_ADRL27) Setting 0: Disabled 1: Enabled
3
TEN28
0
R/W
CAM Entry Table 28 (TSU_ADRH28 and TSU_ADRL28) Setting 0: Disabled 1: Enabled
Rev. 1.00 Oct. 01, 2007 Page 875 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 2
Bit Name TEN29
Initial Value 0
R/W R/W
Description CAM Entry Table 29 (TSU_ADRH29 and TSU_ADRL29) Setting 0: Disabled 1: Enabled
1
TEN30
0
R/W
CAM Entry Table 30 (TSU_ADRH30 and TSU_ADRL30) Setting 0: Disabled 1: Enabled
0
TEN31
0
R/W
CAM Entry Table 31 (TSU_ADRH31 and TSU_ADRL31) Setting 0: Disabled 1: Enabled
Rev. 1.00 Oct. 01, 2007 Page 876 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.50 CAM Entry Table POST1 Register (TSU_POST1) When using the CAM, the conditions for referring to each CAM entry table can be specified by using the TSU_POST1 to TSU_POST4 registers. TSU_POST1 specifies the conditions for referring to TSU_ADRH0 to TSU_ADRH7 and TSU_ADRL0 to TSU_ADRL7. The settings of this register are valid when the POSTENU bit in TSU_FWSLC is set to 1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POST0[3:0]
POST1[3:0]
POST2[3:0]
POST3[3:0]
Initial value: 0 R/W: R/W Bit: 15
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POST4[3:0]
POST5[3:0]
POST6[3:0]
POST7[3:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 28
Bit Name POST0[3:0]
Initial Value All 0
R/W Description R/W These bits set the conditions for referring to CAM entry table 0. By setting multiple bits to 1, multiple conditions can be selected. POST0[3]: CAM entry table 0 is referred to in port 0 reception. POST0[2]: CAM entry table 0 is referred to in port 0 to 1 relay. POST0[1]: CAM entry table 0 is referred to in port 1 reception. POST0[0]: CAM entry table 0 is referred to in port 1 to 0 relay.
27 to 24
POST1[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 1. By setting multiple bits to 1, multiple conditions can be selected. POST1[3]: CAM entry table 1 is referred to in port 0 reception. POST1[2]: CAM entry table 1 is referred to in port 0 to 1 relay. POST1[1]: CAM entry table 1 is referred to in port 1 reception. POST1[0]: CAM entry table 1 is referred to in port 1 to 0 relay.
Rev. 1.00 Oct. 01, 2007 Page 877 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 23 to 20
Bit Name POST2[3:0]
Initial Value All 0
R/W Description R/W These bits set the conditions for referring to CAM entry table 2. By setting multiple bits to 1, multiple conditions can be selected. POST2[3]: CAM entry table 2 is referred to in port 0 reception. POST2[2]: CAM entry table 2 is referred to in port 0 to 1 relay. POST2[1]: CAM entry table 2 is referred to in port 1 reception. POST2[0]: CAM entry table 2 is referred to in port 1 to 0 relay.
19 to 16
POST3[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 3. By setting multiple bits to 1, multiple conditions can be selected. POST3[3]: CAM entry table 3 is referred to in port 0 reception. POST3[2]: CAM entry table 3 is referred to in port 0 to 1 relay. POST3[1]: CAM entry table 3 is referred to in port 1 reception. POST3[0]: CAM entry table 3 is referred to in port 1 to 0 relay.
15 to 12
POST4[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 4. By setting multiple bits to 1, multiple conditions can be selected. POST4[3]: CAM entry table 4 is referred to in port 0 reception. POST4[2]: CAM entry table 4 is referred to in port 0 to 1 relay. POST4[1]: CAM entry table 4 is referred to in port 1 reception. POST4[0]: CAM entry table 4 is referred to in port 1 to 0 relay.
Rev. 1.00 Oct. 01, 2007 Page 878 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 11 to 8
Bit Name POST5[3:0]
Initial Value All 0
R/W Description R/W These bits set the conditions for referring to CAM entry table 5. By setting multiple bits to 1, multiple conditions can be selected. POST5[3]: CAM entry table 5 is referred to in port 0 reception. POST5[2]: CAM entry table 5 is referred to in port 0 to 1 relay. POST5[1]: CAM entry table 5 is referred to in port 1 reception. POST5[0]: CAM entry table 5 is referred to in port 1 to 0 relay.
7 to 4
POST6[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 6. By setting multiple bits to 1, multiple conditions can be selected. POST6[3]: CAM entry table 6 is referred to in port 0 reception. POST6[2]: CAM entry table 6 is referred to in port 0 to 1 relay. POST6[1]: CAM entry table 6 is referred to in port 1 reception. POST6[0]: CAM entry table 6 is referred to in port 1 to 0 relay.
3 to 0
POST7[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 7. By setting multiple bits to 1, multiple conditions can be selected. POST7[3]: CAM entry table 7 is referred to in port 0 reception. POST7[2]: CAM entry table 7 is referred to in port 0 to 1 relay. POST7[1]: CAM entry table 7 is referred to in port 1 reception. POST7[0]: CAM entry table 7 is referred to in port 1 to 0 relay.
Rev. 1.00 Oct. 01, 2007 Page 879 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.51 CAM Entry Table POST2 Register (TSU_POST2) When using the CAM, the conditions for referring to each CAM entry table can be specified by using the TSU_POST1 to TSU_POST4 registers. TSU_POST2 specifies the conditions for referring to TSU_ADRH8 to TSU_ADRH15 and TSU_ADRL8 to TSU_ADRL15. The settings of this register are valid when the POSTENU bit in TSU_FWSLC is set to 1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POST8[3:0]
POST9[3:0]
POST10[3:0]
POST11[3:0]
Initial value: 0 R/W: R/W Bit: 15
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POST12[3:0]
POST13[3:0]
POST14[3:0]
POST15[3:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 28
Bit Name POST8[3:0]
Initial Value All 0
R/W Description R/W These bits set the conditions for referring to CAM entry table 8. By setting multiple bits to 1, multiple conditions can be selected. POST8[3]: CAM entry table 8 is referred to in port 0 reception. POST8[2]: CAM entry table 8 is referred to in port 0 to 1 relay. POST8[1]: CAM entry table 8 is referred to in port 1 reception. POST8[0]: CAM entry table 8 is referred to in port 1 to 0 relay.
27 to 24
POST9[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 9. By setting multiple bits to 1, multiple conditions can be selected. POST9[3]: CAM entry table 9 is referred to in port 0 reception. POST9[2]: CAM entry table 9 is referred to in port 0 to 1 relay. POST9[1]: CAM entry table 9 is referred to in port 1 reception. POST9[0]: CAM entry table 9 is referred to in port 1 to 0 relay.
Rev. 1.00 Oct. 01, 2007 Page 880 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 23 to 20
Bit Name POST10[3:0]
Initial Value All 0
R/W Description R/W These bits set the conditions for referring to CAM entry table 10. By setting multiple bits to 1, multiple conditions can be selected. POST10[3]: CAM entry table 10 is referred to in port 0 reception. POST10[2]: CAM entry table 10 is referred to in port 0 to 1 relay. POST10[1]: CAM entry table 10 is referred to in port 1 reception. POST10[0]: CAM entry table 10 is referred to in port 1 to 0 relay.
19 to 16
POST11[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 11. By setting multiple bits to 1, multiple conditions can be selected. POST11[3]: CAM entry table 11 is referred to in port 0 reception. POST11[2]: CAM entry table 11 is referred to in port 0 to 1 relay. POST11[1]: CAM entry table 11 is referred to in port 1 reception. POST11[0]: CAM entry table 11 is referred to in port 1 to 0 relay.
15 to 12
POST12[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 12. By setting multiple bits to 1, multiple conditions can be selected. POST12[3]: CAM entry table 12 is referred to in port 0 reception. POST12[2]: CAM entry table 12 is referred to in port 0 to 1 relay. POST12[1]: CAM entry table 12 is referred to in port 1 reception. POST12[0]: CAM entry table 12 is referred to in port 1 to 0 relay.
Rev. 1.00 Oct. 01, 2007 Page 881 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 11 to 8
Bit Name POST13[3:0]
Initial Value All 0
R/W Description R/W These bits set the conditions for referring to CAM entry table 13. By setting multiple bits to 1, multiple conditions can be selected. POST13[3]: CAM entry table 13 is referred to in port 0 reception. POST13[2]: CAM entry table 13 is referred to in port 0 to 1 relay. POST13[1]: CAM entry table 13 is referred to in port 1 reception. POST13[0]: CAM entry table 13 is referred to in port 1 to 0 relay.
7 to 4
POST14[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 14. By setting multiple bits to 1, multiple conditions can be selected. POST14[3]: CAM entry table 14 is referred to in port 0 reception. POST14[2]: CAM entry table 14 is referred to in port 0 to 1 relay. POST14[1]: CAM entry table 14 is referred to in port 1 reception. POST14[0]: CAM entry table 14 is referred to in port 1 to 0 relay.
3 to 0
POST15[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 15. By setting multiple bits to 1, multiple conditions can be selected. POST15[3]: CAM entry table 15 is referred to in port 0 reception. POST15[2]: CAM entry table 15 is referred to in port 0 to 1 relay. POST15[1]: CAM entry table 15 is referred to in port 1 reception. POST15[0]: CAM entry table 15 is referred to in port 1 to 0 relay.
Rev. 1.00 Oct. 01, 2007 Page 882 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.52 CAM Entry Table POST3 Register (TSU_POST3) When using the CAM, the conditions for referring to each CAM entry table can be specified by using the TSU_POST1 to TSU_POST4 registers. TSU_POST3 specifies the conditions for referring to TSU_ADRH16 to TSU_ADRH23 and TSU_ADRL16 to TSU_ADRL23. The settings of this register are valid when the POSTENL bit in TSU_FWSLC is set to 1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POST16[3:0]
POST17[3:0]
POST18[3:0]
POST19[3:0]
Initial value: 0 R/W: R/W Bit: 15
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POST20[3:0]
POST21[3:0]
POST22[3:0]
POST23[3:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 28
Bit Name POST16[3:0]
Initial Value All 0
R/W Description R/W These bits set the conditions for referring to CAM entry table 16. By setting multiple bits to 1, multiple conditions can be selected. POST16[3]: CAM entry table 16 is referred to in port 0 reception. POST16[2]: CAM entry table 16 is referred to in port 0 to 1 relay. POST16[1]: CAM entry table 16 is referred to in port 1 reception. POST16[0]: CAM entry table 16 is referred to in port 1 to 0 relay.
27 to 24
POST17[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 17. By setting multiple bits to 1, multiple conditions can be selected. POST17[3]: CAM entry table 17 is referred to in port 0 reception. POST17[2]: CAM entry table 17 is referred to in port 0 to 1 relay. POST17[1]: CAM entry table 17 is referred to in port 1 reception. POST17[0]: CAM entry table 17 is referred to in port 1 to 0 relay.
Rev. 1.00 Oct. 01, 2007 Page 883 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 23 to 20
Bit Name POST18[3:0]
Initial Value All 0
R/W Description R/W These bits set the conditions for referring to CAM entry table 18. By setting multiple bits to 1, multiple conditions can be selected. POST18[3]: CAM entry table 18 is referred to in port 0 reception. POST18[2]: CAM entry table 18 is referred to in port 0 to 1 relay. POST18[1]: CAM entry table 18 is referred to in port 1 reception. POST18[0]: CAM entry table 18 is referred to in port 1 to 0 relay.
19 to 16
POST19[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 19. By setting multiple bits to 1, multiple conditions can be selected. POST19[3]: CAM entry table 19 is referred to in port 0 reception. POST19[2]: CAM entry table 19 is referred to in port 0 to 1 relay. POST19[1]: CAM entry table 19 is referred to in port 1 reception. POST19[0]: CAM entry table 19 is referred to in port 1 to 0 relay.
15 to 12
POST20[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 20. By setting multiple bits to 1, multiple conditions can be selected. POST20[3]: CAM entry table 20 is referred to in port 0 reception. POST20[2]: CAM entry table 20 is referred to in port 0 to 1 relay. POST20[1]: CAM entry table 20 is referred to in port 1 reception. POST20[0]: CAM entry table 20 is referred to in port 1 to 0 relay.
Rev. 1.00 Oct. 01, 2007 Page 884 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 11 to 8
Bit Name POST21[3:0]
Initial Value All 0
R/W Description R/W These bits set the conditions for referring to CAM entry table 21. By setting multiple bits to 1, multiple conditions can be selected. POST21[3]: CAM entry table 21 is referred to in port 0 reception. POST21[2]: CAM entry table 21 is referred to in port 0 to 1 relay. POST21[1]: CAM entry table 21 is referred to in port 1 reception. POST21[0]: CAM entry table 21 is referred to in port 1 to 0 relay.
7 to 4
POST22[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 22. By setting multiple bits to 1, multiple conditions can be selected. POST22[3]: CAM entry table 22 is referred to in port 0 reception. POST22[2]: CAM entry table 22 is referred to in port 0 to 1 relay. POST22[1]: CAM entry table 22 is referred to in port 1 reception. POST22[0]: CAM entry table 22 is referred to in port 1 to 0 relay.
3 to 0
POST23[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 23. By setting multiple bits to 1, multiple conditions can be selected. POST23[3]: CAM entry table 23 is referred to in port 0 reception. POST23[2]: CAM entry table 23 is referred to in port 0 to 1 relay. POST23[1]: CAM entry table 23 is referred to in port 1 reception. POST23[0]: CAM entry table 23 is referred to in port 1 to 0 relay.
Rev. 1.00 Oct. 01, 2007 Page 885 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.53 CAM Entry Table POST4 Register (TSU_POST4) When using the CAM, the conditions for referring to each CAM entry table can be specified by using the TSU_POST1 to TSU_POST4 registers. TSU_POST4 specifies the conditions for referring to TSU_ADRH24 to TSU_ADRH31 and TSU_ADRL24 to TSU_ADRL31. The settings of this register are valid when the POSTENL bit in TSU_FWSLC is set to 1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POST24[3:0]
POST25[3:0]
POST26[3:0]
POST27[3:0]
Initial value: 0 R/W: R/W Bit: 15
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POST28[3:0]
POST29[3:0]
POST30[3:0]
POST31[3:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 28
Bit Name POST24[3:0]
Initial Value All 0
R/W Description R/W These bits set the conditions for referring to CAM entry table 24. By setting multiple bits to 1, multiple conditions can be selected. POST24[3]: CAM entry table 24 is referred to in port 0 reception. POST24[2]: CAM entry table 24 is referred to in port 0 to 1 relay. POST24[1]: CAM entry table 24 is referred to in port 1 reception. POST24[0]: CAM entry table 24 is referred to in port 1 to 0 relay.
27 to 24
POST25[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 25. By setting multiple bits to 1, multiple conditions can be selected. POST25[3]: CAM entry table 25 is referred to in port 0 reception. POST25[2]: CAM entry table 25 is referred to in port 0 to 1 relay. POST25[1]: CAM entry table 25 is referred to in port 1 reception. POST25[0]: CAM entry table 25 is referred to in port 1 to 0 relay.
Rev. 1.00 Oct. 01, 2007 Page 886 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 23 to 20
Bit Name POST26[3:0]
Initial Value All 0
R/W Description R/W These bits set the conditions for referring to CAM entry table 26. By setting multiple bits to 1, multiple conditions can be selected. POST26[3]: CAM entry table 26 is referred to in port 0 reception. POST26[2]: CAM entry table 26 is referred to in port 0 to 1 relay. POST26[1]: CAM entry table 26 is referred to in port 1 reception. POST26[0]: CAM entry table 26 is referred to in port 1 to 0 relay.
19 to 16
POST27[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 27. By setting multiple bits to 1, multiple conditions can be selected. POST27[3]: CAM entry table 27 is referred to in port 0 reception. POST27[2]: CAM entry table 27 is referred to in port 0 to 1 relay. POST27[1]: CAM entry table 27 is referred to in port 1 reception. POST27[0]: CAM entry table 27 is referred to in port 1 to 0 relay.
15 to 12
POST28[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 28. By setting multiple bits to 1, multiple conditions can be selected. POST28[3]: CAM entry table 28 is referred to in port 0 reception. POST28[2]: CAM entry table 28 is referred to in port 0 to 1 relay. POST28[1]: CAM entry table 28 is referred to in port 1 reception. POST28[0]: CAM entry table 28 is referred to in port 1 to 0 relay.
Rev. 1.00 Oct. 01, 2007 Page 887 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 11 to 8
Bit Name POST29[3:0]
Initial Value All 0
R/W Description R/W These bits set the conditions for referring to CAM entry table 29. By setting multiple bits to 1, multiple conditions can be selected. POST29[3]: CAM entry table 29 is referred to in port 0 reception. POST29[2]: CAM entry table 29 is referred to in port 0 to 1 relay. POST29[1]: CAM entry table 29 is referred to in port 1 reception. POST29[0]: CAM entry table 29 is referred to in port 1 to 0 relay.
7 to 4
POST30[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 30. By setting multiple bits to 1, multiple conditions can be selected. POST30[3]: CAM entry table 30 is referred to in port 0 reception. POST30[2]: CAM entry table 30 is referred to in port 0 to 1 relay. POST30 [1]: CAM entry table 30 is referred to in port 1 reception. POST30[0]: CAM entry table 30 is referred to in port 1 to 0 relay.
3 to 0
POST31[3:0]
All 0
R/W These bits set the conditions for referring to CAM entry table 31. By setting multiple bits to 1, multiple conditions can be selected. POST31[3]: CAM entry table 31 is referred to in port 0 reception. POST31[2]: CAM entry table 31 is referred to in port 0 to 1 relay. POST31[1]: CAM entry table 31 is referred to in port 1 reception. POST31[0]: CAM entry table 31 is referred to in port 1 to 0 relay.
Rev. 1.00 Oct. 01, 2007 Page 888 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.54 CAM Entry Table 0H to 31H Registers (TSU_ADRH0 to TSU_ADRH31) TSU_ADRH0 to TSU_ADRH31 are entry tables referred to by the CAM in reception and relay. Each of these registers sets the upper 32 bits of the 48-bit MAC address. Maximum 32 entries of MAC addresses can be registered.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADRHn[31:16] (n = 0 to 31)
Initial value: 0 R/W: R/W Bit: 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
ADRHn[15:0] (n = 0 to 31)
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 0
Bit Name ADRHn[31:0] (n: 0 to 31)
Initial Value All 0
R/W Description R/W MAC Address Bits These bits set the upper 32 bits of the MAC address. When the MAC address is 01-23-45-67-89-AB (displayed in hexadecimal), set H'01234567 in this register.
Note:
Set the CAM entry tables following the procedure below. 1. Check that the ADSBSY bit in TSU_ADSBSY is cleared to 0. 2. Set the upper 32 bits of the MAC addresses by TSU_ADRH0 to TSU_ADRH31. 3. Set the lower 16 bits of the MAC addresses by TSU_ADRL0 to TSU_ADRL31.
Rev. 1.00 Oct. 01, 2007 Page 889 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.55 CAM Entry Table 0L to 31L Registers (TSU_ADRL0 to TSU_ADRL31) TSU_ADRL0 to TSU_ADRL31 are entry tables referred to by the CAM in reception and relay. Each of these registers sets the lower 16 bits of the 48-bit MAC address. Maximum 32 entries of MAC addresses can be registered.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADRLn[15:0] (n = 0 to 31)
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W Description R Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
ADRLn[15:0] (n: 0 to 31)
All 0
R/W MAC Address Bits These bits set the lower 16 bits of the MAC address. When the MAC address is 01-23-45-67-89-AB (displayed in hexadecimal), set H'000089AB in this register.
Note:
Set the CAM entry tables following the procedure below. 1. Check that the ADSBSY bit in TSU_ADSBSY is cleared to 0. 2. Set the upper 32 bits of the MAC addresses by TSU_ADRH0 to TSU_ADRH31. 3. Set the lower 16 bits of the MAC addresses by TSU_ADRL0 to TSU_ADRL31.
Rev. 1.00 Oct. 01, 2007 Page 890 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.56 Transmit Frame Counter Register (Port 0) (Normal Transmission Only) (TXNLCR0) TXNLCR0 is a 32-bit counter indicating the number of frames successfully transmitted in the EMAC-0. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register. This register cannot be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NTC0[31:16] Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0
NTC0[15:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 31 to 0
Bit Name NTC0[31:0]
Initial Value All 0
R/W Description R Port 0 Transmit Frame Counter Bits These bits indicate the number of frames successfully transmitted.
Rev. 1.00 Oct. 01, 2007 Page 891 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.57 Transmit Frame Counter Register (Port 0) (Normal and Erroneous Transmission) (TXALCR0) TXALCR0 is a 32-bit counter indicating the number of frames transmitted in the E-MAC-0, including the number of frames erroneously transmitted. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register. This register cannot be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TC0[31:16] Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0
TC0[15:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 31 to 0
Bit Name TC0[31:0]
Initial Value All 0
R/W Description R Port 0 Transmit Frame Counter Bits These bits indicate the number of frames successfully transmitted and erroneously transmitted.
Rev. 1.00 Oct. 01, 2007 Page 892 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.58 Receive Frame Counter Register (Port 0) (Normal Reception Only) (RXNLCR0) RXNLCR0 is a 32-bit counter indicating the number of frames successfully received in the EMAC-0. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register. This register cannot be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NRC0[31:16] Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0
NRC0[15:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 31 to 0
Bit Name NRC0[31:0]
Initial Value All 0
R/W Description R Port 0 Receive Frame Counter Bits These bits indicate the number of frames successfully received.
Rev. 1.00 Oct. 01, 2007 Page 893 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.59 Receive Frame Counter Register (Port 0) (Normal and Erroneous Reception) (RXALCR0) RXALCR0 is a 32-bit counter indicating the number of frames received in the E-MAC-0, including the number of frames erroneously received. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register. This register cannot be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RC0[31:16]
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
RC0[15:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 0
Bit Name RC0[31:0]
Initial Value All 0
R/W Description R Port 0 Receive Frame Counter Bits These bits indicate the number of frames successfully received and erroneously received.
Rev. 1.00 Oct. 01, 2007 Page 894 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.60 Relay Frame Counter Register (Port 1 to 0) (Normal Relay Only) (FWNLCR0) FWNLCR0 is a 32-bit counter indicating the number of frames successfully relayed in port 1 to 0 relay operations. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register. This register cannot be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NFC0[31:16]
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
NFC0[15:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 0
Bit Name NFC0[31:0]
Initial Value All 0
R/W Description R Port 1 to 0 Relay Frame Counter Bits These bits indicate the number of frames successfully relayed.
Rev. 1.00 Oct. 01, 2007 Page 895 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.61 Relay Frame Counter Register (Port 1 to 0) (Normal and Erroneous Transmission) (FWALCR0) FWALCR0 is a 32-bit counter indicating the number of frames relayed in port 1 to 0 relay operations, including the number of frames erroneously relayed. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register. This register cannot be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FC0[31:16]
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
FC0[15:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 0
Bit Name FC0[31:0]
Initial Value All 0
R/W Description R Port 1 to 0 Relay Frame Counter Bits These bits indicate the number of frames successfully relayed and erroneously relayed.
Rev. 1.00 Oct. 01, 2007 Page 896 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.62 Transmit Frame Counter Register (Port 1) (Normal Transmission Only) (TXNLCR1) TXNLCR1 is a 32-bit counter indicating the number of frames successfully transmitted in the EMAC-1. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register. This register cannot be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NTC1[31:16]
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
NTC1[15:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 0
Bit Name NTC1[31:0]
Initial Value All 0
R/W Description R Port 1 Transmit Frame Counter Bits These bits indicate the number of frames successfully transmitted.
Rev. 1.00 Oct. 01, 2007 Page 897 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.63 Transmit Frame Counter Register (Port 1) (Normal and Erroneous Transmission) (TXALCR1) TXALCR1 is a 32-bit counter indicating the number of frames transmitted in the E-MAC-1, including the number of frames erroneously transmitted. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register. This register cannot be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TC1[31:16]
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
TC1[15:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 0
Bit Name TC1[31:0]
Initial Value All 0
R/W Description R Port 1 Transmit Frame Counter Bits These bits indicate the number of frames successfully transmitted and erroneously transmitted.
Rev. 1.00 Oct. 01, 2007 Page 898 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.64 Receive Frame Counter Register (Port 1) (Normal Reception Only) (RXNLCR1) RXNLCR1 is a 32-bit counter indicating the number of frames successfully received in the EMAC-1. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register. This register cannot be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NRC1[31:16]
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
NRC1[15:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 0
Bit Name NRC1[31:0]
Initial Value All 0
R/W Description R Port 1 Receive Frame Counter Bits These bits indicate the number of frames successfully received.
Rev. 1.00 Oct. 01, 2007 Page 899 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.65 Receive Frame Counter Register (Port 1) (Normal and Erroneous Reception) (RXALCR1) RXALCR1 is a 32-bit counter indicating the number of frames received in the E-MAC-1, including the number of frames erroneously received. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register. This register cannot be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RC1[31:16]
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
RC1[15:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 0
Bit Name RC1[31:0]
Initial Value All 0
R/W Description R Port 1 Receive Frame Counter Bits These bits indicate the number of frames successfully received and erroneously received.
Rev. 1.00 Oct. 01, 2007 Page 900 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.66 Relay Frame Counter Register (Port 0 to 1) (Normal Relay Only) (FWNLCR1) FWNLCR1 is a 32-bit counter indicating the number of frames successfully relayed in port 0 to 1 relay operations. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register. This register cannot be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NFC1[31:16]
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
NFC1[15:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 0
Bit Name NFC1[31:0]
Initial Value All 0
R/W Description R Port 0 to 1 Relay Frame Counter Bits These bits indicate the number of frames successfully relayed.
Rev. 1.00 Oct. 01, 2007 Page 901 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.67 Relay Frame Counter Register (Port 0 to 1) (Normal and Erroneous Transmission) (FWALCR1) FWALCR1 is a 32-bit counter indicating the number of frames relayed in port 0 to 1 relay operations, including the number of frames erroneously relayed. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register. This register cannot be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FC1[31:16]
Initial value: R/W: Bit:
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
FC1[15:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 0
Bit Name FC1[31:0]
Initial Value All 0
R/W Description R Port 0 to 1 Relay Frame Counter Bits These bits indicate the number of frames successfully relayed and erroneously relayed.
Rev. 1.00 Oct. 01, 2007 Page 902 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.68 E-DMAC Start Register (EDSR) EDSR specifies activation of the transmitting unit and receiving unit of the E-DMAC. This register can only be written to, and the read values are invalid.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ENT
0
ENR
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 W
0 W
Bit 31 to 2
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1
ENT
0
W
E-DMAC Transmitting Unit Start 0: Stops the E-DMAC transmitting unit 1: Starts the E-DMAC transmitting unit
0
ENR
0
W
E-DMAC Receiving Unit Start 0: Stops the E-DMAC receiving unit 1: Starts the E-DMAC receiving unit
Rev. 1.00 Oct. 01, 2007 Page 903 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.69 E-DMAC Mode Register (EDMR) EDMR is a 32-bit readable/writable register that specifies E-DMAC resetting and the transmit/receive descriptor length. This register is to be set before the transmitting or receiving function is enabled (before the TR bit in EDTRR or the RR bit in EDRRR is set to 1). However, the SWRR and SWRT bits can be written to even after the transmitting or receiving function is enabled. If a software reset is executed with this register during data transmission, abnormal data may be transmitted on the line. Execute a software reset with this register before specifying the transmit/receive descriptor length or modifying the settings of TDLAR, RDLAR, and so forth, the setting of ECMR (E-MAC mode register), and the settings of registers related to the E-DMAC and E-MAC operation. To execute a software reset with this register, 1 must be written to both the SWRT and SWRR bits simultaneously. Writing 1 to the SWRT and SWRR bits initializes the E-MAC registers and EDMAC registers, except for TDLAR, RDLAR, and RMFCR of the E-DMAC. The TSU registers (registers whose names are prefixed with TSU_) are not initialized. Writing 1 to the SWRT and SWRR bits in EDMR0 initializes the registers related to the E-DMAC0 and E-MAC-0, whereas, writing 1 to the SWRT and SWRR bits in EDMR1 initializes the registers related to the EDMAC1 and E-MAC-1. When relay operations are enabled in the TSU by specifying the relay enable register (port 0 to 1) (TSU_FWEN0) and relay enable register (port 1 to 0) (TSU_FWEN1), a software reset should not be performed using this register. Note that during the period a software reset is issued (for 64 cycles of the internal bus clock Bck), accesses to all Ethernet-related registers are prohibited.
Bit: 31
-
0 R
30
-
0 R
29
-
0 R
28
-
0 R
27
-
0 R
26
-
0 R
25
24
23
22
21
20
19
18
17
16
-
0 R 9
-
0 R 8
-
0 R 7
-
0 R 6
DE
-
0 R 5
-
0 R 4
-
0 R 3
-
0 R 2
-
0 R 1
-
0 R 0
Initial value: R/W: Bit:
15
14
13
12
11
10
-
Initial value: R/W: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
DL[1:0]
-
0 R
-
0 R
SWRT SWRR
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Rev. 1.00 Oct. 01, 2007 Page 904 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 31 to 7
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
6
DE
0
R/W
Transmit/Receive Frame Endian Sets the endian mode for DMA transfer of frame data between the transmit/receive FIFO and transmit/receive buffer. 0: Big endian (longword access) 1: Little endian (longword access)
5, 4
DL[1:0]
00
R/W
Transmit/Receive Descriptor Length These bits specify the descriptor length. (See section 23.4.1, Descriptors and Descriptor List.) 00: 16 bytes 01: 32 bytes 10: 64 bytes 11: Setting prohibited
3, 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1
SWRT
0
R/W
Software Reset of Transmit FIFO Controller [Writing] 0: Disabled 1: Software reset started [Reading] 0: Software reset not executed (or completed) 1: Software reset being executed
0
SWRR
0
R/W
Software Reset of Receive FIFO Controller [Writing] 0: Disabled 1: Software reset started [Reading] 0: Software reset not executed (or completed) 1: Software reset being executed
Rev. 1.00 Oct. 01, 2007 Page 905 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.70 E-DMAC Transmit Request Register (EDTRR) EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC. After writing 11 to bits TR[1:0] in this register, the E-DMAC reads the transmit descriptor at the address specified by TDLAR. If the TACT bit of this transmit descriptor is set to 1 (valid), transmit DMA transfer by the E-DMAC starts. When DMA transfer based on the first transmit descriptor is completed, the E-DMAC reads the next transmit descriptor. If the TACT bit of that transmit descriptor is set to 1 (valid), the E-DMAC continues transmit DMA operation. If the TACT bit of a transmit descriptor is cleared to 0 (invalid), the E-DMAC clears bits TR[1:0] and stops transmit DMA operation.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TR[1:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
Bit 31 to 2
Initial Bit Name Value All 0
R/W Description R Reserved These bits are always read as 0. The write value should always be 0.
1, 0
TR[1:0]
00
R/W Transmit Request 00, 01, 10: Transmission-halted state If 00, 01, or 10 is written to these bits, the EDMAC stops DMA transfer of the currently processed transmit descriptor, reads the next transmit descriptor, and then clears these bits. (Write-back is completed for the valid transmit descriptors that have been detected up till then.) The E-DMAC clears these bits when transmit descriptor empty occurs, or transmission of a transmit descriptor has completed. (Write-back is completed for the valid transmit descriptors that have been detected up till then.) 11: Transmit DMA operation by E-DMAC After writing 11 to these bits, the E-DMAC starts reading a transmit descriptor.
Rev. 1.00 Oct. 01, 2007 Page 906 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.71 E-DMAC Receive Request Register (EDRRR) EDRRR is a 32-bit readable/writable register that issues receive directives to the E-DMAC. After writing 1 to the RR bit in this register, the E-DMAC reads the receive descriptor at the address specified by RDLAR. If the RACT bit of this receive descriptor is set to 1 (valid), and the receive FIFO holds a receive frame, the E-DMAC starts receive DMA transfer. When DMA transfer based on the first receive descriptor is completed, the E-DMAC reads the next receive descriptor. If the RACT bit of that receive descriptor is set to 1 (valid), the E-DMAC continues receive DMA operation. However, if the receive FIFO holds no receive data, the E-DMAC places receive DMA operation in the standby state. If the RACT bit of the receive descriptor is cleared to 0 (invalid), the E-DMAC clears the RR bit and stops receive DMAC operation.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RR
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
Bit 31 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
RR
0
R/W
Receive Request 0: Receiving function is disabled* If 0 is written to this bit, the E-DMAC stops receive operation after DMA transfer of one frame has completed and then clears this bit. The E-DMAC clears this bit when receive descriptor empty occurs. 1: Receive descriptor is read, and the E-DMAC is ready to receive
Rev. 1.00 Oct. 01, 2007 Page 907 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Note:
*
If the receiving function is disabled during frame reception, write-back is not performed successfully to the receive descriptor. Following pointers to read a receive descriptor become abnormal and the E-DMAC cannot operate successfully. In this case, to make E-DMAC reception enabled again, execute a software reset by the SWRT and SWRR bits in EDMR0 (EDMR1). To disable the E-DMAC receiving function without executing a software reset, specify the RE bit in ECMR0 (ECMR1). Next, after the E-DMAC has completed the reception and write-back to the receive descriptor has been confirmed, disable the receiving function using this register.
23.3.72 Transmit Descriptor List Start Address Register (TDLAR) TDLAR is a 32-bit readable/writable register that specifies the start address of the transmit descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bits in EDMR. This register must not be modified during transmission. Modifications to this register should only be made in the transmission-halted state specified by bits TR[1:0] (= 00) in the E-DMAC transmit request register (EDTRR).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDLA[31:15]
Initial value: 0 R/W: R/W Bit: 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
TDLA[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 0
Bit Name TDLA[31:0]
Initial Value All 0
R/W Description R/W Transmit Descriptor Start Address The lower bits are set according to the specified descriptor length. 16-byte boundary: TDLA[3:0] = 0000 32-byte boundary: TDLA[4:0] = 00000 64-byte boundary: TDLA[5:0] = 000000
Rev. 1.00 Oct. 01, 2007 Page 908 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.73 Receive Descriptor List Start Address Register (RDLAR) RDLAR is a 32-bit readable/writable register that specifies the start address of the receive descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bits in EDMR. This register must not be modified during reception. Modifications to this register should only be made while reception is disabled by the RR bit (= 0) in the E-DMAC receive request register (EDRRR).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDLA[31:15]
Initial value: 0 R/W: R/W Bit: 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
RDLA[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 0
Bit Name RDLA[31:0]
Initial Value All 0
R/W Description R/W Receive Descriptor Start Address The lower bits are set according to the specified descriptor length. 16-byte boundary: RDLA[3:0] = 0000 32-byte boundary: RDLA[4:0] = 00000 64-byte boundary: RDLA[5:0] = 000000
Rev. 1.00 Oct. 01, 2007 Page 909 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.74 E-MAC/E-DMAC Status Register (EESR) EESR is a 32-bit readable/writable register that shows communications status information on the E-DMAC in combination with the E-MAC. The information in this register is reported in the form of interrupt sources. Individual bits are cleared by writing 1 (however, bit 22 (ECI) is a read-only bit that is not cleared by writing 1) and are not affected by writing 0. Each interrupt source can also be masked by means of the corresponding bit in the E-MAC/E-DMAC status interrupt permission register (EESIPR). The interrupts generated by this status register are GEINT0 for port 0 and GEINT1 for port 1. For interrupt priorities, see section 9.4.6, Interrupt Exception Handling and Priority in section 9, Interrupt Controller (INTC). GEINT2 is an interrupt generated by TSU_FWSR in the TSU.
Bit: 31 30 29
TC[1]
28
TUC
27
ROC
26
TABT
25
24
23
22
ECI
21
TC[0]
20
TDE
19
TFUF
18
FR
17
RDE
16
RFE
TWB[1:0]
RABT RFCOF
Initial value: 0 R/W: R/W Bit: 15
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
14
13
12
11
10
DLC
9
CD
8
TRO
7
6
5
CELF
4
RRF
3
RTLF
2
RTSF
1
PRE
0
CERF
RMAF CEEF
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31, 30
Bit Name TWB[1:0]
Initial Value 00
R/W R/W
Description Write-Back Complete Indicates that write-back from the E-DMAC to the corresponding descriptor after frame transmission has completed. This operation is enabled only when the TWBI bit in the transmit descriptor that includes the end of the transmit frame is set to 1. 00: Write-back has not completed, or no transmission directive 11: Write-back has completed Others: Setting disabled
Rev. 1.00 Oct. 01, 2007 Page 910 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 29
Bit Name TC[1]
Initial Value 0
R/W R/W
Description Frame Transmission Complete Indicates, in combination with the TC[0] bit, that all the data specified by the transmit descriptor has been transmitted from the E-MAC. This bit is set to 1 on assuming the completion of transmission. This is when transmission of one frame is completed and the transmit descriptor valid bit (TACT) of the next transmit descriptor not being set in single-frame/singledescriptor operation or when the last data of a frame has been transmitted and the transmit descriptor valid bit (TACT) of the next descriptor not being set in multibuffer frame processing based on single-frame/multidescriptor operation. After frame transmission has completed, the E-DMAC writes the transmission status back to the relevant descriptor. TC[1:0] 00: Transmission has not completed, or no transmission directive 11: Transmission has completed Others: Setting disabled
28
TUC
0
R/W
Transmit Underflow Frame Write-Back Complete 0: Write-back has not completed for the frame causing transmit underflow 1: Write-back has completed for the frame causing transmit underflow
27
ROC
0
R/W
Receive Overflow Frame Write-Back Complete 0: Write-back has not completed for the frame causing receive overflow 1: Write-back has completed for the frame causing receive overflow
26
TABT
0
R/W
Transmit Abort Detect Indicates that the E-MAC aborts transmitting a frame because of failures during frame transmission. 0: Frame transmission has not been aborted or no transmission directive 1: Frame transmission has been aborted
Rev. 1.00 Oct. 01, 2007 Page 911 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 25
Bit Name RABT
Initial Value 0
R/W R/W
Description Receive Abort Detect Indicates that the E-MAC aborts receiving a frame because of failures during frame reception. 0: Frame reception has not been aborted or no reception directive 1: Frame reception has been aborted
24
RFCOF
0
R/W
Receive Frame Counter Overflow Indicates that the frame counter in the receive FIFO has overflowed. 0: Receive frame counter has not overflowed 1: Receive frame counter has overflowed
23
0
R
Reserved This bit is always read as 0. The write value should always be 0.
22
ECI
0
R
E-MAC Status Register Source This bit is a read-only bit. When the source of an ECSR interrupt is cleared, this bit is also cleared. 0: E-MAC status interrupt source has not been detected 1: E-MAC status interrupt source has been detected
21
TC[0]
0
R/W
Frame Transmission Complete Indicates, in combination with the TC[1] bit, that all the data specified by the transmit descriptor has been transmitted from the E-MAC. For details, see the description of the TC[1] bit.
Rev. 1.00 Oct. 01, 2007 Page 912 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 20
Bit Name TDE
Initial Value 0
R/W R/W
Description Transmit Descriptor Empty Indicates that the transmit descriptor valid bit (TACT) of a transmit descriptor read by the E-DMAC is not set if the previous descriptor does not represent the end of a frame in multi-buffer frame processing based on singleframe/multi-descriptor operation. As a result, an incomplete frame may be sent. 0: Transmit descriptor active bit TACT = 1 detected 1: Transmit descriptor active bit TACT = 0 detected When transmit descriptor empty (TDE = 1) occurs, execute a software reset and initiate transmission. In this case, transmission starts from the address that is stored in the transmit descriptor list start address register (TDLAR).
19
TFUF
0
R/W
Transmit FIFO Underflow Indicates that an underflow has occurred in the transmit FIFO during frame transmission. Incomplete data is sent onto the line. 0: Underflow has not occurred 1: Underflow has occurred
18
FR
0
R/W
Frame Reception Indicates that a frame has been received and the receive descriptor has been updated. This bit is set to 1 each time a frame is received. 0: Frame has not been received 1: Frame has been received
17
RDE
0
R/W
Receive Descriptor Empty Indicates that the RACT bit of a receive descriptor read by the E-DMAC for receive DMA operation is cleared to 0 (invalid). When receive descriptor empty (RDE = 1) occurs, reception can be resumed by setting the RACT bit (cleared to 0) of the receive descriptor to 1 and then writing 1 to the RR bit in EDRRR. 0: Receive descriptor active bit RACT = 1 detected 1: Receive descriptor active bit RACT = 0 detected
Rev. 1.00 Oct. 01, 2007 Page 913 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 16
Bit Name RFOF
Initial Value 0
R/W R/W
Description Receive FIFO Overflow Indicates that the receive FIFO has overflowed during frame reception. 0: Overflow has not occurred 1: Overflow has occurred
15 to 11
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
10
DLC
0
R/W
Detect Loss of Carrier Indicates that loss of the carrier has been detected during frame transmission. 0: Loss of carrier has not been detected 1: Loss of carrier has been detected
9
CD
0
R/W
Delayed Collision Detect Indicates that a delayed collision has been detected during frame transmission. 0: Delayed collision has not been detected 1: Delayed collision has been detected
8
TRO
0
R/W
Transmit Retry Over Indicates that a retry-over condition has occurred during frame transmission. Total 16 transmission retries including 15 retries based on the back-off algorithm have failed after the E-MAC transmission starts. 0: Transmit retry-over condition not detected 1: Transmit retry-over condition detected
7
RMAF
0
R/W
Receive Multicast Address Frame 0: Multicast address frame has not been received 1: Multicast address frame has been received
6
CEEF
0
R/W
Carrier Extension Error Indicates that a carrier extension error has occurred during frame reception in 1-Gigabit/half-duplex transfer. 0: Carrier extension error has not occurred 1: Carrier extension error has occurred
Rev. 1.00 Oct. 01, 2007 Page 914 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 5
Bit Name CELF
Initial Value 0
R/W R/W
Description Carrier Extension Loss Indicates that the carrier extension has been lost in 1Gigabit/half-duplex transfer. This means that the sum of a frame and carrier extension is smaller than SLOT_TIME (4096 bits). 0: Carrier extension loss has not occurred 1: Carrier extension loss has occurred
4
RRF
0
R/W
Receive Residual-Bit Frame 0: Residual-bit frame has not been received 1: Residual-bit frame has been received
3
RTLF
0
R/W
Receive Too-Long Frame Indicates that a frame whose byte size exceeds the upper limit for the receive frame length set by RFLR has been received. 0: Too-long frame has not been received 1: Too-long frame has been received
2
RTSF
0
R/W
Receive Too-Short Frame Indicates that a frame of fewer than 64 bytes has been received. 0: Too-short frame has not been received 1: Too-short frame has been received
1
PRE
0
R/W
PHY-LSI Receive Error 0: PHY-LSI receive error has not been detected 1: PHY-LSI receive error has been detected
0
CERF
0
R/W
CRC Error on Received Frame 0: CRC error has not been detected 1: CRC error has been detected
Rev. 1.00 Oct. 01, 2007 Page 915 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.75 E-MAC/E-DMAC Status Interrupt Permission Register (EESIPR) EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual bits in the E-MAC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the corresponding bit.
Bit: 31 30 29
TC1 IP
28
TUC IP
27
ROC IP
26
TABT IP
25
24
23
22
ECI IP
21
TC0 IP
20
TDE IP
19
TFUF IP
18
FR IP
17
RDE IP
16
RFE IP
TWB1 TWB0 IP IP
RABT RFCOF IP IP
Initial value: 0 R/W: R/W Bit: 15
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
14
13
12
11
10
DLC IP
9
CD IP
8
TRO IP
7
6
5
CELF IP
4
RRF IP
3
RTLF IP
2
RTSF IP
1
PRE IP
0
CERF IP
RMAF CEEF IP IP
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31
Bit Name TWB1IP
Initial Value 0
R/W R/W
Description Write-Back Complete Interrupt Enable 0: Write-back complete interrupt is disabled 1: Write-back complete interrupt is enabled
30
TWB0IP
0
R/W
Write-Back Complete Interrupt Enable 0: Write-back complete interrupt is disabled 1: Write-back complete interrupt is enabled
29
TC1IP
0
R/W
Frame Transmission Complete Interrupt Enable 0: Frame transmission complete interrupt is disabled 1: Frame transmission complete interrupt is enabled
28
TUCIP
0
R/W
Transmit Underflow Frame Write-Back Complete Interrupt Enable 0: Transmit underflow frame write-back complete interrupt is disabled 1: Transmit underflow frame write-back complete interrupt is enabled
Rev. 1.00 Oct. 01, 2007 Page 916 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 27
Bit Name ROCIP
Initial Value 0
R/W R/W
Description Receive Overflow Frame Write-Back Complete Interrupt Enable 0: Receive overflow frame write-back complete interrupt is disabled 1: Receive overflow frame write-back complete interrupt is enabled
26
TABTIP
0
R/W
Transmit Abort Detect Interrupt Enable 0: Transmit abort detect interrupt is disabled 1: Transmit abort detect interrupt is enabled
25
RABTIP
0
R/W
Receive Abort Detect Interrupt Enable 0: Receive abort detect interrupt is disabled 1: Receive abort detect interrupt is enabled
24
RFCOFIP
0
R/W
Receive Frame Counter Overflow Interrupt Enable 0: Receive frame counter overflow interrupt is disabled 1: Receive frame counter overflow interrupt is enabled
23
0
R
Reserved This bit is always read as 0. The write value should always be 0.
22
ECIIP
0
R/W
E-MAC Status Register Source Interrupt Enable 0: E-MAC status interrupt is disabled 1: E-MAC status interrupt is enabled
21
TC0IP
0
R/W
Frame Transmission Complete Interrupt Enable 0: Frame transmission complete interrupt is disabled 1: Frame transmission complete interrupt is enabled
20
TDEIP
0
R/W
Transmit Descriptor Empty Interrupt Enable 0: Transmit descriptor empty interrupt is disabled 1: Transmit descriptor empty interrupt is enabled
19
TFUFIP
0
R/W
Transmit FIFO Underflow Interrupt Enable 0: Underflow interrupt is disabled 1: Underflow interrupt is enabled
18
FRIP
0
R/W
Frame Reception Interrupt Enable 0: Frame reception interrupt is disabled 1: Frame reception interrupt is enabled
Rev. 1.00 Oct. 01, 2007 Page 917 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 17
Bit Name RDEIP
Initial Value 0
R/W R/W
Description Receive Descriptor Empty Interrupt Enable 0: Receive descriptor empty interrupt is disabled 1: Receive descriptor empty interrupt is enabled
16
RFOFIP
0
R/W
Receive FIFO Overflow Interrupt Enable 0: Overflow interrupt is disabled 1: Overflow interrupt is enabled
15 to 11
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
10
DLCIP
0
R/W
Detect Loss of Carrier Interrupt Enable 0: Detect loss of carrier interrupt is disabled 1: Detect loss of carrier interrupt is enabled
9
CDIP
0
R/W
Delayed Collision Detect Interrupt Enable 0: Delayed collision detect interrupt is disabled 1: Delayed collision detect interrupt is enabled
8
TROIP
0
R/W
Transmit Retry Over Interrupt Enable 0: Transmit retry over interrupt is disabled 1: Transmit retry over interrupt is enabled
7
RMAFIP
0
R/W
Receive Multicast Address Frame Interrupt Enable 0: Receive multicast address frame interrupt is disabled 1: Receive multicast address frame interrupt is enabled
6
CEEFIP
0
R/W
Carrier Extension Error Interrupt Enable 0: Carrier extension error interrupt is disabled 1: Carrier extension error interrupt is enabled
5
CELFIP
0
R/W
Carrier Extension Loss Interrupt Enable 0: Carrier extension loss interrupt is disabled 1: Carrier extension loss interrupt is enabled
4
RRFIP
0
R/W
Receive Residual-Bit Frame Interrupt Enable 0: Receive residual-bit frame interrupt is disabled 1: Receive residual-bit frame interrupt is enabled
Rev. 1.00 Oct. 01, 2007 Page 918 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 3
Bit Name RTLFIP
Initial Value 0
R/W R/W
Description Receive Too-Long Frame Interrupt Enable 0: Receive too-long frame interrupt is disabled 1: Receive too-long frame interrupt is enabled
2
RTSFIP
0
R/W
Receive Too-Short Frame Interrupt Enable 0: Receive too-short frame interrupt is disabled 1: Receive too-short frame interrupt is enabled
1
PREIP
0
R/W
PHY-LSI Receive Error Interrupt Enable 0: PHY-LSI receive error interrupt is disabled 1: PHY-LSI receive error interrupt is enabled
0
CERFIP
0
R/W
CRC Error on Received Frame Interrupt Enable 0: CRC error interrupt is disabled 1: CRC error interrupt is enabled
Rev. 1.00 Oct. 01, 2007 Page 919 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.76 Transmit/Receive Status Copy Enable Register (TRSCER) TRSCER specifies whether the information for the transmit and receive state reported by bits 17, 16, and 10 to 0 in the E-MAC/E-DMAC status register (EESR) is to be reflected in the TFE or RFE bit of the corresponding descriptor. The bits in this register correspond to bits 17, 16, and 10 to 0 in EESR. When a bit is cleared to 0, the transmit status (bits 17 and 10 to 8 in EESR) is reflected in the TFE bit of the transmit descriptor, and the receive status (bits 16 and 7 to 0 in EESR) is reflected in the RFE bit of the receive descriptor. In this case, the state of a status bit set to 1 is reflected as the TFE or RFE bit set to 1. When a bit is set to 1, the occurrence of the corresponding source is not reflected in the descriptor. After this LSI is reset, all bits are cleared to 0.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TABT CE
16
RABT CE
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
15
14
13
12
11
10
DLC CE
9
CD CE
8
TRO CE
7
6
5
4
RRF CE
3
RTLF CE
2
RTSF CE
1
PRE CE
0
CERF CE
RMAF CEEF CELF CE CE CE
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 18
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
17
TABTCE
0
R/W
TABT Bit Copy Directive 0: Reflects the TABT bit status in the TFE bit of the transmit descriptor 1: Occurrence of the corresponding source is not reflected in the TFE bit of the transmit descriptor
16
RABTCE
0
R/W
RABT Bit Copy Directive 0: Reflects the RABT bit status in the RFE bit of the receive descriptor 1: Occurrence of the corresponding source is not reflected in the RFE bit of the receive descriptor
Rev. 1.00 Oct. 01, 2007 Page 920 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 15 to 11
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
10
DLCCE
0
R/W
DLC Bit Copy Directive 0: Reflects the DLC bit status in the TFE bit of the transmit descriptor 1: Occurrence of the corresponding source is not reflected in the TFE bit of the transmit descriptor
9
CDCE
0
R/W
CD Bit Copy Directive 0: Reflects the CD bit status in the TFE bit of the transmit descriptor 1: Occurrence of the corresponding source is not reflected in the TFE bit of the transmit descriptor
8
TROCE
0
R/W
TRO Bit Copy Directive 0: Reflects the TRO bit status in the TFE bit of the transmit descriptor 1: Occurrence of the corresponding source is not reflected in the TFE bit of the transmit descriptor
7
RMAFCE
0
R/W
RMAF Bit Copy Directive 0: Reflects the RMAF bit status in the RFE bit of the receive descriptor 1: Occurrence of the corresponding source is not reflected in the RFE bit of the receive descriptor
6
CEEFCE
0
R/W
CEEF Bit Copy Directive 0: Reflects the CEEF bit status in the RFE bit of the receive descriptor 1: Occurrence of the corresponding source is not reflected in the RFE bit of the receive descriptor
5
CELFCE
0
R/W
CELF Bit Copy Directive 0: Reflects the CELF bit status in the RFE bit of the receive descriptor 1: Occurrence of the corresponding source is not reflected in the RFE bit of the receive descriptor
Rev. 1.00 Oct. 01, 2007 Page 921 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 4
Bit Name RRFCE
Initial Value 0
R/W R/W
Description RRF Bit Copy Directive 0: Reflects the RRF bit status in the RFE bit of the receive descriptor 1: Occurrence of the corresponding source is not reflected in the RFE bit of the receive descriptor
3
RTLFCE
0
R/W
RTLF Bit Copy Directive 0: Reflects the RTLF bit status in the RFE bit of the receive descriptor 1: Occurrence of the corresponding source is not reflected in the RFE bit of the receive descriptor
2
RTSFCE
0
R/W
RTSF Bit Copy Directive 0: Reflects the RTSF bit status in the RFE bit of the receive descriptor 1: Occurrence of the corresponding source is not reflected in the RFE bit of the receive descriptor
1
PRECE
0
R/W
PRE Bit Copy Directive 0: Reflects the PRE bit status in the RFE bit of the receive descriptor 1: Occurrence of the corresponding source is not reflected in the RFE bit of the receive descriptor
0
CERFCE
0
R/W
CERF Bit Copy Directive 0: Reflects the CERF bit status in the RFE bit of the receive descriptor 1: Occurrence of the corresponding source is not reflected in the RFE bit of the receive descriptor
Rev. 1.00 Oct. 01, 2007 Page 922 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.77 Receive Missed-Frame Counter Register (RMFCR) RMFCR is a 16-bit counter that indicates the number of frames that could not be saved in the receive buffer and so were discarded during reception. When the receive FIFO overflows, the receive frames in the FIFO are discarded. The number of frames discarded at this time is counted. When the value in this register reaches H'FFFF, count-up is halted. Clear the counter by writing H'0000 in this register.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MCF[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 0
MFC[15:0]
All 0
R/W
Missed-Frame Counter These bits indicate the number of frames that are discarded and not transferred to the receive buffer during reception.
Rev. 1.00 Oct. 01, 2007 Page 923 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.78 Transmit FIFO Threshold Register (TFTR) TFTR is a 32-bit readable/writable register that specifies the transmit FIFO threshold at which the first transmission is started. The actual threshold is 4 times the set value. The E-MAC starts transmission when the amount of data in the transmit FIFO exceeds the number of bytes specified by this register, when the transmit FIFO is full, or when one frame of data write is performed. This register must not be written to during transmission (bits TR[1:0] in EDTRR = 11).
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
TFT[10:0]
4
3
2
1
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 11
Initial Bit Name Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0.
10 to 0
TFT[10:0] All 0
R/W Transmit FIFO Threshold A value in 32-byte units and smaller than the FIFO size specified by FDR must be set as the transmit FIFO threshold. H'000: Store and forward modes H'008: 32 bytes H'010: 64 bytes H'018: 128 bytes : : H'07F: 508 bytes H'080: 512 bytes : : H'0FF: 1,020 bytes H'100: 1,024 bytes : : H'1FF: 2,044 bytes H'200: 2,048 bytes
Rev. 1.00 Oct. 01, 2007 Page 924 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Note: When starting transmission before one frame of data write has completed, take care no underflow occurs.
23.3.79 FIFO Depth Register (FDR) FDR is a 32-bit readable/writable register that specifies the sizes of the transmit and receive FIFOs.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
TFD[2:0]
8
7
6
5
4
3
2
RFD[4:0]
1
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
1 R/W
1 R/W
1 R/W
0 R
0 R
0 R
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 31 to 11
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
10 to 8
TFD[2:0]
All 1
R/W
Transmit FIFO Size Specifies 256 bytes to 2 Kbytes in 256-byte units as the size of the transmit FIFO whose maximum size is 2 Kbytes. The setting must not be changed after transmission/reception has started. H'00 : 256 bytes H'01 : 512 bytes : : H'07 : 2048 bytes
7 to 5
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 925 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 4 to 0
Bit Name RFD[4:0]
Initial Value All 1
R/W R/W
Description Receive FIFO Size Specifies 256 bytes to 8 Kbytes in 256-byte units as the size of the receive FIFO whose maximum size is 8 Kbytes. The setting must not be changed after transmission/reception has started. H'00 : 256 bytes H'01 : 512 bytes : : H'1F : 8192 bytes
23.3.80 Receiving Method Control Register (RMCR) RMCR is a 32-bit readable/writable register that specifies the control method for the RE bit in ECMR while a frame is received. This register must be set during the receiving-halted state.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RNC
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
Bit 31 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 926 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 0
Bit Name RNC
Initial Value 0
R/W R/W
Description Receive Enable Control Sets whether to continue frame reception. 0: Upon completion of reception of one frame, the EDMAC writes the receive status to the descriptor and clears the RR bit in EDRRR to 0. 1: Upon completion of reception of one frame, the EDMAC writes (writes back) the receive status to the descriptor. In addition, the E-DMAC reads the next descriptor and prepares for reception of the next frame.
23.3.81 Receive Descriptor Fetch Address Register (RDFAR) RDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor information from the receive descriptor. Which receive descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually fetching a descriptor may be different from the value read from this register. In the initial setting, set the address of the receive descriptor at which receive processing is to be started.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDFA[31:16]
Initial value: 0 R/W: R/W Bit: 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
RDFA[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 0
Bit Name RDFA[31:0]
Initial Value All 0
R/W R/W
Description Receive Descriptor Fetch Address Writing to these bits during the reception is prohibited.
Rev. 1.00 Oct. 01, 2007 Page 927 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.82 Receive Descriptor Finished Address Register (RDFXR) RDFXR stores the start address of the receive descriptor for which the E-DMAC has just completed the write-back processing. Up to which receive descriptor has been processed by the EDMAC can be recognized by monitoring addresses displayed in this register. In the initial setting, set the address of the descriptor immediately before the descriptor that is pointed to by the address in RDFAR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDFX[31:16]
Initial value: 0 R/W: R/W Bit: 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
RDFX[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 0
Bit Name RDFX[31:0]
Initial Value All 0
R/W R/W
Description Receive Descriptor Finished Address Writing to these bits during the reception is prohibited.
Rev. 1.00 Oct. 01, 2007 Page 928 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.83 Receive Descriptor Final Flag Register (RDFFR) RDFFR indicates whether the receive descriptor for which the E-DMAC has just completed the write-back processing and whose start address is stored in RDFXR is at the end of the receive descriptor queue (descriptor list).
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDLF
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
Bit 31 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
RDLF
0
R/W
Receive Descriptor Queue Last Flag Indicates whether the receive descriptor for which the EDMAC has just completed the write-back processing and whose start address is stored in RDFXR is at the end of the receive descriptor queue (descriptor list). 0: Not the last descriptor in the receive descriptor queue 1: Last descriptor in the receive descriptor queue
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Section 23 Gigabit Ethernet Controller (GETHER)
23.3.84 Transmit Descriptor Fetch Address Register (TDFAR) TDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor information from the transmit descriptor. Which transmit descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually fetching a descriptor may be different from the value read from this register. In the initial setting, set the address of the transmit descriptor at which transmit processing is to be started.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDFA[31:16]
Initial value: 0 R/W: R/W Bit: 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
TDFA[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 0
Bit Name TDFA[31:0]
Initial Value All 0
R/W R/W
Description Transmit Descriptor Fetch Address Writing to these bits during transmission is prohibited.
Rev. 1.00 Oct. 01, 2007 Page 930 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.85 Transmit Descriptor Finished Address Register (TDFXR) TDFXR stores the start address of the transmit descriptor for which the E-DMAC has just completed the write-back processing. Up to which transmit descriptor has been processed by the E-DMAC can be recognized by monitoring addresses displayed in this register. In the initial setting, set the address of the transmit descriptor immediately before the descriptor that is pointed to by the address in TDFAR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDFX[31:16]
Initial value: 0 R/W: R/W Bit: 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
TDFX[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 0
Bit Name TDFX[31:0]
Initial Value All 0
R/W R/W
Description Transmit Descriptor Finished Address Writing to these bits during transmission is prohibited.
Rev. 1.00 Oct. 01, 2007 Page 931 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.86 Transmit Descriptor Final Flag Register (TDFFR) TDFFR indicates whether the transmit descriptor for which the E-DMAC has just completed the write-back processing and whose start address is stored in TDFXR is at the end of the transmit descriptor queue (descriptor list).
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TDLF
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
Bit 31 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
TDLF
0
R/W
Transmit Descriptor Queue Last Flag Indicates whether the transmit descriptor for which the E-DMAC has just completed the write-back processing and whose start address is stored in TDFXR is at the end of the transmit descriptor queue (descriptor list). 0: Not the last descriptor in the transmit descriptor queue 1: Last descriptor in the transmit descriptor queue
Rev. 1.00 Oct. 01, 2007 Page 932 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.87 Overflow Alert FIFO Threshold Register (FCFTR) FCFTR is a 32-bit readable/writable register that sets the flow control of the E-MAC. The threshold can be set by the size of the receive FIFO data (bits RFD[7:0]) and the number of receive frames (bits RFF[4:0]). If the same receive FIFO size as set by the FIFO depth register (FDR) is set when flow control is turned on according to the RFD setting condition, flow control is turned on with (FIFO data size * 64) bytes. For instance, when the RFD bits in FDR = 7 and the RFD bits in this register = 7, flow control is turned on when (2,048 * 64) bytes of data is stored in the receive FIFO. The value set in the RFD bits in this register should be equal to or less than that set in the RFD bits in FDR. Flow control is turned on when either of the setting conditions of bits RFF[4:0] and bits RFD[7:0] is satisfied. Flow control is turned off when neither of the conditions is satisfied (release).
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
RFF[4:0]
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RFD[7:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 31 to 21
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
20 to 16
RFF[4:0]
H'1F
R/W
Receive FIFO Overflow Alert Signal Output Threshold H'00: When one receive frame has been stored in the receive FIFO H'01: When two receive frames have been stored in the receive FIFO : : H'16: When 23 receive frames have been stored in the receive FIFO H'17: When 24 receive frames have been stored in the receive FIFO
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Section 23 Gigabit Ethernet Controller (GETHER)
Bit 15 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7 to 0
RFD[7:0]
H'FF
R/W
Receive FIFO Overflow Alert Signal Output Threshold H'00: When (256 - 32) bytes of data is stored in the receive FIFO H'01: When (512 - 32) bytes of data is stored in the receive FIFO : : H'06: When (1,792 - 32) bytes of data is stored in the receive FIFO H'07: When (2,048 - 64) bytes of data is stored in the receive FIFO
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Section 23 Gigabit Ethernet Controller (GETHER)
23.3.88 Receive Data Padding Insert Register (RPADIR) RPADIR is a 32-bit readable/writable register that inserts padding in receive data. When changing the settings of this register, execute a software reset by means of the SWRT and SWRR bits in the E-DMAC mode register (EDMR) before making settings again.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
PADS[4:0]
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PADR[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 21
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
20 to 16
PADS[4:0]
H'00
R/W
Padding Size H'00: No padding insertion H'01: 1-byte insertion : : H'1F: 31-byte insertion
15 to 0
PADR[15:0] H'0000
R/W
Padding Slot H'0000: Inserts specified size of padding at the first byte H'0001: Inserts specified size of padding at the second byte : : H'FFFF: Inserts specified size of padding at the 64K byte
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Section 23 Gigabit Ethernet Controller (GETHER)
23.4
Operation
The GETHER consists of the following three function units: * DMA transfer controller (E-DMAC): DMA transfer between the transmit/receive buffer in the memory and the transmit/receive FIFO * MAC controller (E-MAC): Transmission/reception processing between the transmit/receive FIFO and the GMII/MII/RMII * Transfer Switching Unit (TSU): Transfer processing between port 0 and port 1, and CAM processing Using its direct memory access (DMA) function, the E-DMAC performs DMA transfer of frame data between a user-specified Ethernet frame transmission/reception data storage destination (accessible memory space: transmit buffer/receive buffer) and the transmit/receive FIFO in the EDMAC. The user cannot read and write data from and to the transmit/receive FIFO directly via the CPU. To enable the E-DMAC to perform DMA transfer, information (data) including a transmit/receive data storage address and so forth, referred to as a descriptor, is required. The E-DMAC reads transmit data from the transmit buffer or writes receive data to the receive buffer according to the descriptor information. By arranging multiple descriptors as a descriptor row (list) (to be placed in a readable/writable memory space), multiple Ethernet frames can be transmitted or received continuously. The E-DMAC consists of two systems: one for port 0 and the other for port 1, and both operate independently for transmission and reception. The E-MAC constructs an Ethernet frame using the data written to the transmit FIFO and transmits the frame to the GMII/MII/RMII. It also performs a CRC check of an Ethernet frame received from the GMII/MII/RMII and deconstructs the frame to write to the receive FIFO. The EMAC supports three formats MII, GMII and RMII for interface to the PHI-LSI connected externally to this LSI. The E-MAC consists of two controllers: E-MAC0 for port 0 and E-MAC1 for port 1, which correspond to E-DMAC0 and E-DMAC1 respectively. The TSU performs Ethernet frame data transfer between the E-MAC0 and E-MAC1. The TSU, which is placed between the E-DMAC and E-MAC, references the CAM entry table to select one of the following tasks according to the Ethernet frame destination address (DA) input to the EMAC.
Rev. 1.00 Oct. 01, 2007 Page 936 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
* * * *
Receives data and writes to the receive FIFO. Transfers data and writes to the transfer FIFO. Receives data and writes to the receive FIFO and transfer FIFO. Discards data.
The TSU performs transfers from port 0 to port 1 and from port 1 to port 0 independently.
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Section 23 Gigabit Ethernet Controller (GETHER)
Figure 23.2 shows the frame data path and an overview of each setting.
Port 0 Transmit data buffer Receive data buffer
In memory
Port 1
Transmit/receive descriptor
Transmit/receive descriptor
Transmit data buffer
Receive data buffer
SuperHyway (SHwy) bridge bus
Transmit request EDTRR0.TR=11 E-DMAC-0
Receive request EDRRR0.RR=1
GETHER
Transmit request EDTRR1.TR=11
Receive request EDRRR1.RR=1 E-DMAC-1
DMA transfer
Descriptor access
Descriptor access
DMA transfer
Transmitter startup EDSR0.ENT=1
Receiver startup EDSR0.ENR=1
Transmitter startup EDSR1.ENT=1
Receiver startup EDSR1.ENR=1
Transmit FIFO Receive FIFO
Transmit FIFO Receive FIFO
TSU CAM reference
CAM control CAM entry table
(32 entries x 48 bits)
CAM reference
(Reference setting: TSU_TEN, TSU_FWSLC) Relay enable TSU_FWEN0.FWEN1=1 Determination of priority TSU_PRISL0
Relay FIFO (1 to 0)
CAM reference
CAM reference
Relay FIFO (1 to 0)
Determination of priority TSU_PRISL1
Relay enable TSU_FWEN0.FWEN0=1 Transmission enabled ECMR0.TE=1 E-MAC-0 Reception enabled ECMR0.RE=1 Reception enabled ECMR1.RE=1 E-MAC-1 Transmission enabled ECMR1.TE=1
PHY-0 GMII/MII/RMII
PHY-1 GMII/MII/RMII
Figure 23.2 GETHER Data Path and Various Settings
Rev. 1.00 Oct. 01, 2007 Page 938 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.4.1
Descriptors and Descriptor List
The E-DMAC performs DMA transfer according to the information (data), referred to as a descriptor, written in memory space. There are two types of descriptors: transmit descriptors and receive descriptors. Before a DMA transfer, DMA transfer information including a transmit/receive frame data storage address must be set by software. The E-DMAC automatically starts reading a transmit/receive descriptor when the TR bits in EDTRR are set to 11 or the RR bit in EDRRR is set to 1, and performs DMA transfer of frame data between the transmit/receive buffer and transmit/receive FIFO according to the information stored in the descriptor. After completion of Ethernet frame transmission/reception, the E-DMAC disables the descriptor valid/invalid bit and reflects the result of transmission/reception in the status bits. Descriptors are placed in a readable/writable memory space. The address of the start descriptor (descriptor to be read first by the E-DMAC) is set in TDLAR/RDLAR. When multiple descriptors are prepared as a descriptor row (descriptor list), the descriptors are placed in continuous addresses (memory) according to the descriptor length set in the DL0 and DL1 bits in EDMR. The E-DMAC consists of two systems: one for port 0 and the other for port 1. The DMAC for transmission and the DMAC for reception operate independently, and the DMAC for port 0 and the DMAC for port 1 operate independently. Place descriptors for transmission and reception and descriptors for port 0 and port 1 in those address spaces that do not overlap. If addresses are overlapped, E-DMAC does not successfully operate. (1) Transmit Descriptor
Figure 23.3 shows the configuration of a transmit descriptor and the relationship with a transmit buffer. The data of a transmit descriptor consists of TD0, TD1, TD2, and padding data in groups of 32 bits from top to end. The length of padding data is determined according to the descriptor length specified by the DL0 and DL1 bits in EDMR. TD0 indicates whether the transmit descriptor is valid or invalid, and information about the descriptor configuration and status. TD1 indicates the length of data in a transmit buffer to be transferred (TDL) as specified by the descriptor. TD2 indicates the start address of a transmit buffer that holds data to be transferred (TBA). Depending on the descriptor specification, one transmit descriptor can specify all transmit data of one frame (single-frame/single-buffer) or multiple descriptors can specify the transmit data of one
Rev. 1.00 Oct. 01, 2007 Page 939 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
frame (single-frame/multi-buffer). As an example of single-frame/multi-buffer operation, the data portion that is used in a fixed manner in each Ethernet frame transmission can be referenced by multiple descriptors. For example, multiple descriptors can share the destination address and transmit source address in an Ethernet frame, and the remaining data can be stored in each separate buffer.
Transmit deschriptor 31 30 29 28 27 26 25 T TT TT F FF AD P EE CL TE I 12 Reserved 11 TFS[26:0] 0 Transmit buffer
TD0
Valid transmit data TD1 TD2 31 31 TDL 16 0
TBA Padding (4/20/52 bytes)*
Note: *According to the descripotr lenght set by the DL0 and DL 1 bits in EDMR, the padding size is detemined as follows: For 16 bytes Padding = 4 bytes For 32 bytes padding = 20bytes For 64 bytes Padding = 52bytes
Figure 23.3 Relationship between Transmit Descriptor and Transmit Buffer (a) Transmit Descriptor 0 (TD0)
Before the TR bits in EDTRR are set to 11, the user sets whether the bits of the descriptor are valid or invalid bit and sets other descriptor configuration. After Ethernet frame transmission, the E-DMAC disables the valid/invalid bits of the descriptor and writes status information. This operation is referred to as write-back. When using TD0, the user should write desired values to bits 31 to 28 and 26 according to the descriptor configuration. Bits 27 and 25 to 0 should be cleared to 0.
Rev. 1.00 Oct. 01, 2007 Page 940 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 31
Bit Name TACT
Initial Value 0
R/W R/W
Description Transmit Descriptor Valid/Invalid Indicates whether the corresponding descriptor is valid or invalid. To make this bit valid, store transmit data in a transmit buffer (user-specified transmit data storage destination) beforehand, then write 1 to this bit. The EDMAC clears this bit to 0 after data transfer. 0: Indicates that this transmit descriptor is invalid Indicates the initial setting state, the state after 0 is written, or (in case the user writes 1 to this bit) that this bit is cleared to 0 because the E-DMAC data transfer processing is completed. If this state is recognized when the E-DMAC reads a descriptor, the E-DMAC clears the TR bit in EDTRR to 0, and halts transfer operation related to transmission by the E-DMAC. 1: Indicates that this transmit descriptor is valid After the user writes 1 to this bit, this bit indicates that data is not transferred yet or data is being transferred. When there is a descriptor row (descriptor list) consisting of multiple continuous descriptors, the E-DMAC can continue operation when this bit of the next descriptor is valid.
30
TDLE
0
R/W
Transmit Descriptor List End Indicates whether the corresponding descriptor is the last descriptor of the descriptor row (descriptor list). 0: Not last descriptor After transfer of the corresponding descriptor, the EDMAC reads the next one in the list of continuous descriptors. 1: Last descriptor After transfer of the corresponding descriptor, the EDMAC reads the descriptor placed at the address indicated by TDLAR.
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Section 23 Gigabit Ethernet Controller (GETHER)
Bit 29, 28
Bit Name
Initial Value
R/W R/W
Description Transmit Frame Position These bits indicate whether information of this descriptor represents information about the start, middle, or end of the transmit frame. 00: The information of the descriptor represents information about the middle of the frame. 01: The information of the descriptor represents information about the end of the frame. 10: The information of the descriptor represents information about the start of the frame. 11: The information of the descriptor represents all information about the frame (single-frame/singledescriptor (single-buffer)). Reference When one frame is divided for use, the method of specifying this bit for a descriptor row according to the number of divisions is described below. * * For single-frame/single-descriptor operation First descriptor: TFP[1:0] = 11 For single-frame/two-descriptor operation First descriptor: TFP[1:0] = 10 Second descriptor: TFP[1:0] = 01 * For single-frame/three-descriptor operation First descriptor: TFP[1:0] = 10 Second descriptor: TFP[1:0] = 00 Third descriptor: TFP[1:0] = 01 When the number of divisions is large, a descriptor row is configured by adding intermediate descriptors with TFP[1:0] = 00.
TFP[1:0] 00
Rev. 1.00 Oct. 01, 2007 Page 942 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Bit 27
Initial Bit Name Value TFE 0
R/W R/W
Description Transmit Frame Error Occurrence Indicates that an error occurred in the transmit frame. 0: The TFS11 to TFS0 bits are all 0 1: One of the TFS11 to TFS0 bits is 1 The TFS8 to TFS0 bits can be masked for each factor by using TRSCER. TheTFS11 to TFS9 bits cannot be masked. This bit is set by the E-DMAC write-back operation.
26
TWBI
0
R/W
Write-Back Completion Interrupt Notification 0: Does not notify of a write-back completion interrupt 1: After a write-back operation to this descriptor is complete, this bit sets the TWB1 and TWB0 bits in EESR to 11 and notifies the CPU of a write-back completion interrupt. This bit is valid only for the descriptor including the end of transmit frame (TFP = 01 or 11). This bit is cleared to 0 by the E-DMAC write-back operation.
25 to 12
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
11 to 0
TFS[11:0] All 0
R/W
Transmit Frame Status These bits indicate the status of the corresponding frame. A bit below, which is set by the E-DMAC write-back operation, indicates the occurrence of the corresponding event when set to 1. * * * * TFS[11:10]: Reserved (The write value should always be 0.) TFS[9]: Transmit FIFO underflow (Corresponding to the TUC bit in EESR) TFS[8]: Detection of transmission abort (Corresponding to the TABT bit in EESR) TFS[7:0]: Reserved (The write value should always be 0.)
Rev. 1.00 Oct. 01, 2007 Page 943 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
(b)
Transmit Descriptor 1 (TD1)
TD1 indicates the data length of the transmit buffer used by the corresponding descriptor. The user should set TD1 before the start of a read by the E-DMAC.
Bit 31 to 16 Bit Name TDL Initial Value All 0 R/W R/W Description Transmit Buffer Data Length (in bytes) These bits indicate the data length of the corresponding transmit buffer in bytes. The maximum length is between 64 kbytes and 32 bytes (H'FFE0). 15 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
(c)
Transmit Descriptor 2 (TD2)
TD2 indicates the start address of the corresponding 32-bit width transmit buffer. An address value should be specified in a longword boundary.
Bit 31 to 0 Bit Name TBA Initial Value All 0 R/W R/W Description Transmit Buffer Start Address These bits set the start address of the corresponding transmit buffer in a 16-bit boundary.
If descriptors are set below, the E-DMAC does not return to normal operation until a system reset is performed. * TFP (transmit frame position) is not logically correct Example: The TFP bits are set to 11 in a descriptor (descriptor A) and the TFP bits are set to 01 in the next descriptor (descriptor B). This specification means that there is no descriptor indicating the start of the transmit frame specified by descriptor B. * TBL (transmit buffer length) is set to 0
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Section 23 Gigabit Ethernet Controller (GETHER)
When one transmit frame is divided into three parts or more with transmit descriptors, the EDMAC performs the following write-back operation: * A write-back operation is performed for a transmit descriptor including information for the start of the transmit frame (TFP = 10 or 11) and for a transmit descriptor including information for the end of the frame (TFP = 01 or 11). * A write-back operation is not performed for a transmit descriptor for the middle of the frame (TFP = 00). However, TFE (transmit frame error occurrence) or TFS (transmit frame status) is written only to a transmit descriptor including information for the end of the frame (TFP = 01 or 11) by a writeback operation. Before changing a transmit descriptor with the software, make sure that a write-back operation has been performed (TACT = 0) for the transmit descriptor including information for the end of the frame (TFP = 01 or 11) to avoid overwriting (re-setting) an unprocessed transmit descriptor. (2) Receive Descriptor
Figure 23.4 shows the relationship between a receive descriptor and receive buffer. The data of a receive descriptor consists of RD0, RD1, RD2, and padding data in groups of 32 bits from top to end. The length of padding data is determined according to the descriptor length specified by the DL0 and DL1 bits in EDMR. RD0 indicates whether the receive descriptor is valid or invalid, and information about descriptor configuration and status. RD1 indicates the length of data that can be received in the receive buffer specified by the descriptor (RBL) and the length of the received frame data (RDL). RD2 indicates the start address of the receive buffer for storing receive data (RBA). Depending on the descriptor specification, one receive descriptor can specify the storing of all receive data of one frame in a receive buffer (single-frame/single-buffer) or multiple descriptors can specify the storing of the receive data of one frame in receive buffers (single-frame/multibuffer). As an example of single-frame/multi-buffer operation, suppose that a row of multiple descriptors (descriptor list) is prepared, RBL of each descriptor is 500 bytes, and a 1514-byte Ethernet frame is received. In such a case, the received Ethernet frame is transferred sequentially to buffers, 500 bytes for each buffer, starting with the first descriptor. Only the last 14 bytes are transferred to the fourth buffer. When a frame longer than RBL of a descriptor is received, the EDMAC transfers the remaining data to the receive buffer by using the subsequent descriptors. As an example of efficient single-frame/multi-buffer operation, information items on different processing layers in an Ethernet frame can be separated from each other by using different buffers. For example, the destination address, transmit source address, and type field data in an Ethernet
Rev. 1.00 Oct. 01, 2007 Page 945 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
frame can be stored in buffer 1 (set RBL to 14 bytes) and the remaining data can be stored in buffer 2 (set RBL to 1500 bytes). All receive frames, of course, can be stored in a single buffer if multiple descriptors are prepared and RBL of each descriptor is set to more than 1514 bytes (maximum Ethernet frame length).
Receive deschriptor 31 30 29 28 27 26 25 RR R R P AD F FV CL PE TE 12 Reserved 11 TFS[26:0] 0 Transmit buffer
RD0
Valid transmit data RD1 RD2 31 31 RBL 16 0 RBA Padding (4/20/52 bytes)* 15 0
Note: *According to the descripotr lenght set by the DL0 and DL 1 bits in EDMR, the padding size is detemined as follows: For 16 bytes Padding = 4 bytes For 32 bytes padding = 20bytes For 64 bytes Padding = 52bytes
Figure 23.4 Relationship between Receive Descriptor and Receive Buffer (a) Receive Descriptor 0 (RD0)
The user sets whether the bits of the descriptor are valid or invalid and whether the descriptor represents the end of the descriptor list in RD0 before the RR bit in EDRRR is set to 1 and the start of a read by the E-DMAC. After receive DMA transfer of an Ethernet frame by the EDMAC, the E-DMAC disables the valid/invalid bits of the descriptor and writes status information. This operation is referred to as write-back. When using RD0, the user should write desired values to bits 31 and 30 according to the descriptor configuration. Bits 29 to 0 should be cleared to 0.
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Section 23 Gigabit Ethernet Controller (GETHER)
Bit 31
Bit Name RACT
Initial Value 0
R/W R/W
Description Receive Descriptor Valid/Invalid Indicates whether this descriptor is valid or invalid. To make this bit valid, prepare a receive buffer (user-specified receive data storage destination) beforehand, then write 1 to this bit. The E-DMAC clears this bit to 0 after data transfer. 0: Indicates that this receive descriptor is invalid Indicates the initial setting state, the state after 0 is written to, or (in case the user writes 1 to this bit) that this bit is cleared to 0 because the E-DMAC data transfer processing is completed If this state is recognized when the E-DMAC reads a descriptor, the E-DMAC clears the RR bit in EDRRR to 0, and halts transfer operation related to reception by the E-DMAC 1: Indicates that this receive descriptor is valid Indicates that data is not transferred yet after the user writes 1 to this bit, or that data is being transferred When there is a descriptor row (descriptor list) consisting of multiple continuous descriptors, the E-DMAC can continue operation when this bit of the next descriptor is valid
30
RDLE
0
R/W
Receive Descriptor List End Indicates whether this descriptor is the last descriptor of the descriptor row (descriptor list). 0: Not last descriptor After transfer of this descriptor, the E-DMAC reads the next one in the list of continuous descriptors 1: Last descriptor After transfer of this descriptor, the E-DMAC reads the descriptor placed at the address indicated by RDLAR
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Section 23 Gigabit Ethernet Controller (GETHER)
Bit 29, 28
Bit Name
Initial Value
R/W R/W
Description Receive Frame Position 1, 0 The E-DMAC indicates by write-back operation whether information of the corresponding descriptor represents information about the start, middle, or end of the receive frame. 00: The information of the descriptor represents information about the middle of the frame 01: The information of the descriptor represents information about the end of the frame 10: The information of the descriptor represents information about the start of the frame 11: The information of the descriptor represents all information about the frame (single-frame/singledescriptor (single-buffer)) Reference The relationship between a frame after reception of one frame and a descriptor is described below. * * For single-frame/single-descriptor operation First descriptor: RFP[1:0] = 11 For single-frame/two-descriptor operation First descriptor: RFP[1:0] = 10 Second descriptor: RFP[1:0] = 01 * For single-frame/three-descriptor operation First descriptor: RFP[1:0] = 10 Second descriptor: RFP[1:0] = 00 Third descriptor: RFP[1:0] = 01 When the number of divisions is large, a descriptor row is configured by adding intermediate descriptors with RFP[1:0] = 00.
RFP[1:0] 00
27
RFE
0
R/W
Receive Frame Error Occurrence Indicates that an error occurred in the receive frame. 0: RFS11 to RFS0 are all 0 1: One of RFS11 to RFS0 is 0 Each of RFS8 to RFS0 can be masked by using TRSCER. RFS11 to RFS9 cannot be masked. This bit is set by the E-DMAC write-back operation.
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Section 23 Gigabit Ethernet Controller (GETHER)
Bit 26
Bit Name PV
Initial Value R/W 0 R/W
Description Padding Insertion Indicates whether the padding specified by RPADIR was inserted in the receive frame processed with this descriptor or not. 0: No padding inserted 1: Padding inserted This bit can be changed by the E-DMAC write-back processing.
25 to 12
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
11 to 0
RFS[11:0] All 0
R/W
Receive Frame Status Indicate the status of the corresponding frame. A bit below, when set to 1, indicates the occurrence of the corresponding event. If an event indicated by any of RFS9 to RFS0 occurs, the frame is not received completely. RFS[11:10]: Reserved RFS[9]: Receive FIFO overflow (corresponding to the RFOF bit in EESR) RFS[8]: Detection of reception abort (Corresponding to the RABT bit in EESR) RFS[7]: Multicast address frame received (corresponding to the RMAF bit in EESR) RFS[6]: Carrier extension error (corresponding to the CEEF bit in EESR) RFS[5]: Carrier extension loss (corresponding to the CELF bit in EESR) RFS[4]: Residual-bit frame receive error (corresponding to the RRF bit in EESR) RFS[3]: Long frame receive error (corresponding to the RTLF bit in EESR) RFS[2]: Short frame receive error (corresponding to the RTSF bit in EESR) RFS[1]: PHY-LSI receive error (corresponding to the PRE bit in EESR) RFS[0]: CRC error on receive frame (corresponding to the CERF bit in EESR)
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Section 23 Gigabit Ethernet Controller (GETHER)
(b)
Receive Descriptor 1 (RD1)
In RD1, the user specifies the data length of a receive buffer usable by the corresponding descriptor. After reception of a frame, RD1 indicates the length of a frame received by the EDMAC. The user should set RD1 before the start of a read by the E-DMAC.
Bit 31 to 16 Bit Name RBL Initial Value All 0 R/W R/W Description Receive Buffer Data Length (in bytes, to be specified with a 32-byte boundary) These bits set the length of data that can be received by the corresponding receive buffer with an integral multiple of 32 bytes. The maximum receive buffer data length is between 64 kbytes and 32 bytes (H'FFE0). 15 to 0 RDL All 0 R Receive Data Length These bits indicate the data length of a receive frame stored in the receive buffer. Receive data transferred to the receive buffer does not include CRC data (4 bytes) placed at the end of a frame. As a receive frame length, the number of bytes (valid data bytes) not including CRC data are reported. In single-frame/multi-buffer (descriptor) operation, only the receive data length of the last descriptor is valid. The receive data length of an intermediate descriptor has no meaning. The maximum frame length that can be received is: When padding function is invalid: 64 kbytes between 1 byte (H'FFFF) When padding function is valid: 64 kbytes between 32 bytes (H'FFE0)
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Section 23 Gigabit Ethernet Controller (GETHER)
(c)
Receive Descriptor 2 (RD2)
RD2 indicates the start address of the corresponding receive buffer. Set the start address of a receive buffer with a 32-byte boundary.
Bit 31 to 0 Bit Name RBA Initial Value All 0 R/W R/W Description Receive Buffer Start Address These bits set the start address of the corresponding receive buffer with a 32-byte boundary.
The E-DMAC performs DMAtransfer for a receive frame from the address specified by RBA (receive buffer address) to the receive buffer in 32-byte units. RBL (receive buffer length) must be set to be an integral multiple of 32 bytes. If data to be transferred is less than 32 bytes, invalid data will be written to. [Example] When the receive frame length is 170 bytes and the required receive buffer capacity is 192 bytes (32 bytes x 6), the sixth DMA-transfer causes invalid data to be written to the receive buffer (In the 32-byte DMA data, the former 10 bytes are valid and the latter 22 bytes are invalid). Padding of the value 0 can be inserted into only one position in the receive frame by setting RPADIR. The padding size can be selected from 1 byte to 31 bytes in byte units. When padding is inserted into a receive frame, a receive buffer area equal to the total of "receive frame length and padding size" is required. RPADIR setting is valid for all receive frames. RFE (receive frame error occurrence), PV (padding insertion), RFS (receive frame status) and RFS (receive frame status) are only set in the receive descriptor including information for the end of the frame (TFP = 01 or 11) by a write-back operation. Before re-setting a receive descriptor with the software, completion of a write-back operation for the receive descriptor (RACT = 0) must be confirmed to avoid rewriting to (and re-setting) an unprocessed receive descriptor.
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Section 23 Gigabit Ethernet Controller (GETHER)
(3) (a)
Descriptor and Transmit/Receive Buffer Transmission
Each transmit descriptor specifies one transmit buffer. The E-DMAC transfers a transmit frame stored in a transmit buffer specified by a transmit descriptor to the transmit FIFO. Multiple transmit frames stored in transmit buffers specified by multiple descriptors can be connected into one transmit frame and transferred to the transmit FIFO. Figure 23.5 shows the relationship between the transmit descriptors and transmit buffers.
Tfansmit descriptor ring (in memory) Tfansmit buffer (in memory)
Transmit frame data (Transmit data transferred by DMA transfer from memory to transmit FIFO is configured as a frame in the MAC and output to the GMII/MII/RMII.)
TACT TDL TFP[1:0]
1011
Transmit descriptor 1 (Transmit frame A)
4 bytes
Transmit frame A Transmit buffer 1 Transmit buffer 1
1010
Transmit descriptor 2 (Transmit frame B) Transimit buffer 2
Transmit frame B Transmit buffer 4 Transmit buffer 3
Transimit buffer 2
1000
Transmit descriptor 3 (Transmit frame B)
Transmit buffer 3
Transmit buffer 2 to 4 are connected to be one frame (transmit frame B) and output to the GMII/MII/RMII.
1001
Transmit descriptor 4 (Transmit frame B)
Transmit buffer 4
1010
Transmit descriptor 5 (Transmit frame C) Transmit buffer 5
Transmit frame C Transmit buffer 6
Transmit buffer 5
1001
Transmit descriptor 6 (Transmit frame C) Transmit buffer 6
Transmit buffer 5 and 6 are connented to be one frame. (transmit frame C) arnd output to the GMII/MII/RMII.
1011
Transmit descriptor 7 (Transmit frame D)
Transimit buffer 7
Transmit frame D Transmit buffer 7 Transmit frame E Transmit buffer 8
1111
Transmit descriptor 8 (Transmit frame E) Transmit buffer 8
Figure 23.5 Relationship between Transmit Descriptor and Transmit Buffer (b) Reception
Each receive descriptor specifies one receive buffer. The E-DMAC receives a receive frame from the receive FIFO and stores it in a receive buffer specified by a receive descriptor. If the receive frame size exceeds the receive buffer size, the remaining data of the receive frame can be stored in
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Section 23 Gigabit Ethernet Controller (GETHER)
a different receive buffer specified by a different receive descriptor. Thus, one receive frame can be stored in multiple receive buffers. Figure 23.6 shows the relationship between the receive descriptors and receive buffers.
Receive descriptor ring (in memory) Receive buffer (in memory) Receive frame data (A frame input from the GMII/MII/RMIi is written to the receive FIFO. Then the frame is transferred by DMA transfer from the receive FIFO to the receive buffer in memory.)
Receive frame A Receive frame A (29 bytes) (Underfined value) 32 bytes of unused area 29 bytes When the receive frame ;ength is not a multiple of 32 bytes, an undefined value is written.
RACT RDL RFP[1:0] 0011
Transmit descriptor 1 (Transmit frame A)
4 bytes
32-bytes boundary 32-bytes boundary
0010
Transmit descriptor 2 (Transmit frame B)
32-bytes boundary 32-bytes boundary
0001
Transmit descriptor 3 (Transmit frame B)
Receive frame B Receive frame B (Former 32 bytes) 63 bytes This frame is divided into two descriptor and stored Receive frame B (Former 32 bytes)
0011
Transmit descriptor 4 (Transmit frame C)
32-bytes boundary 32-bytes boundary
0011
Transmit descriptor 5 (Transmit frame D)
10 - Transmit descriptor 6
(Waiting for a receive frame)
32-bytes boundary 32-bytes boundary
10 - Transmit descriptor 7
(Waiting for a receive frame)
Padding data Receive frame C (53 bytes) Receive frame C 53 bytes When padding data is inserted at the top of the receive frame. the receive frame can be written to arbitrary byte boundary in memory.
32-bytes boundary
11 - Transmit descriptor 8
(Waiting for a receive frame)
32-bytes boundary
32-bytes boundary 32-bytes boundary
Receive frame D (Former 29 bytes) Padding data Receive frame D (Latter 35 bytes)
Receive frame D 64 bytes When padding data is inserted in the middle of the receive frame, PRADIR should be set so that the latter half of data is written from to the 4-bytes boundary in the receive buffer.
32-bytes boundary
32-bytes boundary
32-bytes boundary
Figure 23.6 Relationship between Receive Descriptor and Receive Buffer
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Section 23 Gigabit Ethernet Controller (GETHER)
(4)
Descriptor Pointer
The E-DMAC controls the transmit and receive descriptor addresses in memory and the processing priority by using the following registers. 1. * * * * 2. * * * * Registers related to a transmit descriptor TDLAR: Address of the start descriptor in a list of transmit descriptors. TDFAR: Address of the transmit descriptor to be processed TDFXR: Address of the transmit descriptor that finished processing (set by a write-back operation) last TDFFR (DL bit): Indicates whether the TDLE value of the transmit descriptor specified by TDFXR is 1 or not. Registers related to receive descriptor: RDLAR: Address of the start descriptor in a list of receive descriptors. RDFAR: Address of the receive descriptor to be processed RDFXR: Address of the receive descriptor that finished processing (set by a write-back operation) last RDFFR (DL bit): Indicates whether the RDLE value of the receive descriptor specified by RDFXR is 1 or not.
Transmit descriptors and receive descriptors have a ring structure. When the TDLE (RDLE) value of the processed transmit (receive) descriptor is 0, the next descriptor will be processed. The next descriptor is the transmit (receive) descriptor at the address obtained by adding the processed transmit (receive) descriptor address to the descriptor length specified by the DL bit in EDMR. When the TDLE (RDLE) value of the processed transmit (receive) descriptor is 1, the transmit descriptor indicated by TDLAR (RDLAR) will be processed next. Figure 23.7 shows the relationship between the transmit/receive descriptor ring and read pointer. The transmit descriptor list must be large enough to point to five or more transmit frames. If four or less transmit frames are pointed to in a list, E-DMAC operation is not guaranteed. Accordingly, do not set that all the transmit descriptors in a ring are used by four or less descriptors. The receive descriptor list does not have this restriction. For example, one receive frame can use all receive descriptors in a list. In the initial setting, the start address of a descriptor list must be set to TDLAR (RDLAR) and TDFAR (RDFAR), and the end descriptor address of the descriptor list to TDFXR (RDFXR) by the software. The E-DMAC updates TDFAR (RDFAR), TDFXR (RDFXR) and the DL bit in TDFFR (DL bit in RDFFR) each time a descriptor is processed.
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Section 23 Gigabit Ethernet Controller (GETHER)
Transmit descriptor ring (in memory) TACT TDLE Transmit descriptor list start address register (TDLAR) H'0000 H'0010 H'0020 Transmit descriptor processed address register (TDFXR) Transmit descriptor fetch address register (TDFAR) H'0030 H'0040 H'0050 The transmit descriptor final flag register (TDFFR) is set to H'00000000. H'0060 H'0070 10
Transmit descriptor 1
10
Transmit descriptor 2
00
Transmit descriptor 3
00
Transmit descriptor 4
10
Transmit descriptor 5
in processing
10
Transmit descriptor 6
10
Transmit descriptor 7
11
Transmit descriptor 8
Receive descriptor ring (in memory) RACT RDLE Receive descriptor list start address register (RDLAR) Receive descriptor fetch address register (RDFAR) H'0000 H'0010 H'0020 H'0030 H'0040 H'0050 H'0060 Receive descriptor processed address register (RDFXR) The receive descriptor final flag register (RDFFR) is set to H'00000001. H'0070 10 Receive descriptor 1 10 Receive descriptor 2 10 Receive descriptor 3 10 Receive descriptor 4 10 Receive descriptor 5 00 Receive descriptor 6 00 Receive descriptor 7 01 Receive descriptor 8
in processing
Note: Addresses in the descriptor list are shown as an example when the descriptor length is 16 bytes
Figure 23.7 Relationship between Transmit/Receive Descriptor and Descriptor Pointing Registers
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Section 23 Gigabit Ethernet Controller (GETHER)
23.4.2 (1)
Transmission
Transmission Procedure and Processing Flow
When 11 is written to the TR bits in EDTRR with the TE bit in ECMR set to 1 and there is empty space of 32 bytes or more in the transmit FIFO, the E-DMAC reads the descriptor following the previously used descriptor from the transmit descriptor list (or the descriptor indicated by TDLAR at the initial startup). If the TACT bit of the read descriptor is set to 1 (valid), the E-DMAC sequentially reads transmit frame data from the transmit buffer start address specified by TD2 and transfers the data to the transmit FIFO. The E-DMAC configures a transmit frame and starts transmission to the GMII/MII/RMII. After DMA transfer of data equivalent to the buffer length specified in the descriptor, the following processing is carried out according to the TFP value. * TFP = 10 (start of a frame) Descriptor write-back (writing 0 to the TACT bit) is performed after completion of DMA transfer. * TFP = 01 or 11 (end of a frame) Descriptor write-back (writing 0 to the TACT bit and writing status) is performed after completion of frame transmission. * TFP = 00 (frame continued) Descriptor write-back is not performed. The TACT bit retains the value 1. As long as the TACT bit of a read descriptor is set to 1 (valid), the reading of E-DMAC descriptors and the transmission of frames continue. When a descriptor with the TACT bit cleared to 0 (invalid) is read, the E-DMAC performs the following processing and completes transmit processing. * Clears the TR bits in EDTRR to 00. * Writes the TC bits in EESR to 11 and generates an interrupt to the CPU. The E-DMAC can store up to four frames of data in the transmit FIFO.
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Section 23 Gigabit Ethernet Controller (GETHER)
When the following conditions are satisfied, the E-MAC transmit processing section reads transmit data from the transmit FIFO to configure a frame and transmits the frame to the GMII/MII/RMII * The amount of data in the transmit FIFO exceeds the number of bytes specified by TFTR. * One or more frame of data is stored in the transmit FIFO. * The transmit FIFO has no space (full of transmit wait data for the GMII/MII/RMII).
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Section 23 Gigabit Ethernet Controller (GETHER)
Figure 23.8 shows an example of transmission flow.
Transmission flowchart
This LSI + memory
E-DMAC
Transmit FIFO
E-MAC
Ethernet GMII/MII/RMIi
GETHER initalization
Transmit descriptor and transmit buffer setting Start of transmission Transmit descriptor read
Transmit data transfer
Transmit descriptor write-back Transmit descriptor read
Frame transmission Transmit data transfer
Transmit descriptor write-back Transmission completed
[Legend] GETHER initialization: Executes a software reset with the SWR bit in EDMR set to 1. Transmit descriptor and transmit setting: Setes transmit descriptors and transmit buffer, and sets E-MAC and E-DMAC registeers, then writes 11 to the TE bit in ECMR and the TR bit in EDTRR. Start of transmission: Occurs when 1 is written to the TE bit in ECMR and 11 is written to the TR bit in EDTRR. Transmit descriptor read: The E-DMAC reads a transmit descriptor. Transmit data transfer : Writes transmit dara to the transmit FIFO by using DMA transfer by the E-DMAC Transmit descriptor write-back: The E-DMAC writes 0 to the TACT bit and writes the transmit status to the transmit descriptor.
Figure 23.8 Sample Transmission Flowchart (Single-Frame/Two-Description)
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Section 23 Gigabit Ethernet Controller (GETHER)
Figure 23.9 shows the status change of the E-MAC transmitter. This operation is common among port 0 and port 1. 1. When the TE bit in ECMR is set, the transmitter enters the transmit idle state. 2. When a transmit request is issued by the transmit E-DMAC, the E-MAC sends the preamble to GMII/MII/RMII after a transmission delay caused by the carrier detection and frame interval time. If full-duplex transfer is selected, which does not require carrier detection, the preamble is sent as soon as a transmit request is issued by the E-DMAC. 3. The transmitter sends the SFD, data, and CRC sequentially. At the end of transmission, the transmit E-DMAC generates a transmission complete interrupt (TC). If a collision or the carrier-not-detected state occurs during data transmission, these are reported as interrupt sources. 4. After waiting for the frame interval time, the transmitter enters the idle state, and if there is more transmit data, continues transmitting.
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Section 23 Gigabit Ethernet Controller (GETHER)
Transmission flowchart
TE set
ldle
FDPX Carrier detection
Start of transmission (preamble transmission)
Transmission halted
TE reset Carrier detection
HDPX
FDPX
Reset Carrier non-detection Collision
Carrier detection Carrier detection
Retransfer processing*1
Failure of 15 retransfer attempts or collision after 512-bit time
SFD tansmission Error Collision*2 Error Data transmission Collision*2 Error
Error notification
Error detection
Normal transmission
CRC transmission
Legend FDPX: Full-duplex HDPX: Half-duplex Notes: 1. Transmission retry processing includes both jam transmission that depends on collision detection and the adjustment of transmission intervals based on the back-off algorithm. 2. Transmission is retried only when data of 512 bits or less (including the premble and SFD) is transmitted. When a xollision is detected during the transmission of data oreater than 512 bits, only jam is transmitted and transmission based on the back-off algorithm is not retried.
Figure 23.9 E-MAC Transmitter State Transitions
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Section 23 Gigabit Ethernet Controller (GETHER)
(2) (a)
Transmission Error Processing Transmission Abort
If a transmission error is detected during frame transmission from the transmit FIFO to the GMII/MII/RMII, transmission of the frame data is aborted. At this time, if DMA transfer of the appropriate frame from the transmit buffer to the transmit FIFO has not been completed, the DMA transfer is also aborted. Following a write-back operation to the transmit descriptor related to the transmit frame aborted by a transmission error, 1 is written to the TABT bit in EESR and an interrupt is issued to the CPU. The subsequent transmit descriptors will be processed normally. (b) Transmit FIFO Underflow
If the transmit FIFO is empty (transmit FIFO underflow) during frame transmission from the transmit FIFO to the GMII/MII/RMII, the E-MAC forcibly aborts transmission of the frame to the GMII/MII/RMII. At this time, the frame that the E-MAC receives from the E-DMAC is cut off halfway. Then, the E-MAC performs the following operation: * Writes the TFUF bit in EESR to 1 and generates an interrupt to the CPU. * Performs a write-back operation to the transmit descriptor corresponding to the transmit frame. * Following the write-back operation, writes the TUC bit in EESR and generates an interrupt to the CPU. The subsequent transmit descriptors operate normally. The E-MAC waits to start frame transmission from the transmit FIFO to the GMII/MII/RMII until the data that was stored in the transmit FIFO exceeds the number of the bytes specified by TFTR. Through the effective use of TFTR, the transmit FIFO underflow counts can be controlled. (c) Transmit Descriptor Empty
When the TFP bits of the descriptor previously processed are set to 00 or 10 and the TACT bit of the read transmit descriptor is set to 0 (invalid), a transmit descriptor empty state is determined and 1 is written to the TDE bit in EESR, and then an interrupt is issued to the CPU. When a transmit descriptor state is empty, start transmission processing after a software reset.
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Section 23 Gigabit Ethernet Controller (GETHER)
23.4.3 (1)
Reception
Reception Procedure and Processing Flow
The E-MAC receiver separates the frame from the GMII/MII/RMII into preamble, SFD, data and CRC, and transfers the fields from DA (destination address) to the data to the receive FIFO. Up to 24 frames can be written in the receive FIFO. Figure 23.10 shows the status change of the E-MAC receiver. This operation is common among port 0 and port 1. 1. When the RE bit in ECMR is set to 1, the receiver enters the receive idle state. 2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver starts receive processing. A frame with an invalid pattern is discarded. 3. In normal mode, if the destination of the frame address is this LSI, the receiver starts data reception when broadcast or multicast transmission is specified. In promiscuous mode, data reception starts regardless of the frame type. 4. Following data reception from the GMII/MII/RMII, the receiver carries out a CRC check. The result is indicated as a status bit in the descriptor after the frame data has been written to the receive FIFO. Reports an error status in the case of an abnormality. After one frame has been received, if the RE bit in ECMR is set to 1, the receiver prepares to receive the next frame.
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Section 23 Gigabit Ethernet Controller (GETHER)
lllegal carrrier detection
RX-DV negation
ldle RE set Reception halted Premble detection RE reset
Start of frame reception
Wait for SFD reception SFD reception
Reset
Promiscuous and other station destination address
Destination address reception Own destination address or broadcast or broadcast or promiscuous Data reception
Receive error detection Error notification* Error detection
Recevice error decection CRC reception Legend SFD: Start frame delimiter Note: The error frame also transmits data to the buffer.
Figure 23.10 E-MAC Receiver State Transitions CAM evaluation can be referenced during frame processing in reception (for details on the CAM function, refer to section 23.4.5, CAM Function). When 1 is written to the RR bit in EDRRR while the RE bit in ECMR is set to 1, the E-DMAC reads the descriptor following the previously used descriptor from the receive descriptor list (or the descriptor indicated by RDLAR at the initial startup) then enters the receive wait state. If 32 bytes or more of data or the last byte of the receive frame is stored in the receive FIFO, the EDMAC transfers receive FIFO data to the receive buffer specified by RD2 according to the receive descriptor with the RACT bit set to 1 (valid). If the data length of a received frame is longer than the buffer length specified by RD1, the EDMAC performs a write-back operation to the descriptor (set RFP to 10 or 00) when the buffer is full, then reads the next descriptor. The E-DMAC then continues to transfer data to the receive buffer specified by the new RD2. When the following conditions are satisfied, a write-back operation is performed for the descriptor (RFP = 11 or 01), 11 is written to the FR bits in EESR, and an interrupt is issued to the CPU. * The receive buffer has been full during DMA transfer. * DMA transfer to the receive buffer of the last byte of the receive frame has been completed.
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Section 23 Gigabit Ethernet Controller (GETHER)
After the reception processing of the frame, the next descriptor reading standby state begins. At this time, if 32 bytes or more of data or the last byte of the receive frame is stored in the receive FIFO, the next receive descriptor process is performed continuously. When the TACT bit of the read receive descriptor is 0 (invalid), the receive descriptor empty state is determined and the RDE bit in EESR is written to 1, and then an interrupt is issued to the CPU. To receive frames continuously, set the RNC bit in RMCR to 1. The initial value is 0.
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Section 23 Gigabit Ethernet Controller (GETHER)
Figure 23.11 shows an example of reception flow.
Reception flowchart This LSI + memory E-DMAC
Receive FIFO E-MAC Ethernet GMII/MII/RMII
GETHER initialization
Receive descriptor and receive buffer setting Start of reception Receive descriptor read
Frame reception
Receive data transfer
Receive descriptor write-back Receive descriptor read
Receive data transfer
Receive descriptor write-back Receive descriptor read (preparation for receiving the next frame)
Reception completed
[Legend] GETHER initialization: Executes a software reset with the SWR bit in EDMR set to 1.
Receive descriptor and receive buffer setting: Sets receive descriptors and receive buffers, and sets E-MAC and E-DMAC registers, then writes 1 to the RE bit in ECMR and the RR bit in EDRRR. Start of Reception: Receive descriptor read: Receive data transfer: Occurs when 1 is written to the RE bit in ECMR and the RR bit in EDRRR. The E-DMAC reads a receive descriptor. Writes receive data from the receive FIFO to the receive buffer by using DMA transfer by the E-DMAC.
Receive descriptor write-back: The E-DMAC writes 0 to the RACT bit and writes the receive status to the receive descriptor
Figure 23.11 Sample Reception Flowchart (Single-Frame/Two-Descriptor)
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Section 23 Gigabit Ethernet Controller (GETHER)
(2) (a)
Reception Error Processing Reception Error
When a reception error occurs, the FR and RABT bits in EESR are set to 1 and an interrupt is issued to the CPU after a write-back operation for the receive descriptor related to the reception error frame. If a reception error occurs when the length of the frame received from the GMII/MII/RMII is less than 32 bytes, DMA transfer to the receive buffer for the frame is not performed. At this time, the receive frame is discarded in the E-DMAC (flush function). However, if padding is inserted in the receive frame by RPADIR, the flush function is performed when the frame length including the padding bytes is less than 32 bytes. (b) Receive FIFO Overflow
In any of the following cases, the E-MAC cannot receive frames from the GMII/MII/RMII because it has no space to store receive frames, and all the receive frames that have been transferred to the E-MAC will be discarded in the E-MAC (receive FIFO overflow). * Receive FIFO is full of data waiting for DMA transfer (the receive FIFO has no space). * The number of receive frames waiting for DMA transfer is 24 in total (the receive frame information managing area has no empty space; up to 24 frames can be managed). If an overflow occurs due to the former case, the RFE bit in EESR is set to 1 and an interrupt is generated to the CPU. If an overflow occurs due to the latter case, the RFCOF bit in EESR is set to 1 and an interrupt is generated to the CPU. Each time a receive frame is discarded due to an overflow, RMFCR is incremented. However, RMFCR is not incremented for a receive frame that is cut off due to insufficient receive FIFO space. If a receive frame is cut off due to insufficient receive FIFO space (the frame is partially stored in the receive FIFO), the E-DMAC performs the following operation: * Performs DMA transfers for the cut-off frame stored in the receive FIFO to the receive buffer. * After the DMA transfer, performs a write-back operation on the receive descriptor. * After the write-back operation, sets the ROC bit in EESR to 1 and generates an interrupt to the CPU. When the receive FIFO is full of data waiting for DMA transfer, frame reception from the GMII/MII/RMII can be resumed if DMA transfer is performed from the receive FIFO to the receive buffer and 32 bytes or more of empty space is generated in the receive FIFO. When the number of receive frames waiting for DMA transfer is 24 in total, frame reception from the GMII/MII/RMII can be resumed if one or more frame has been DMA transferred from the receive
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Section 23 Gigabit Ethernet Controller (GETHER)
FIFO to the receive buffer. For restarting frame reception from the GMII/MII/RMII, when the EDMAC resumes frame reception from the GMII/MII/RMII, it only accepts from the start of the frame. (c) Flow Control
When the amount of receive data or the number of receive frames in the receive FIFO leads to one of the following conditions, the E-DMAC notifies the E-MAC to control E-MAC writing to the receive FIFO. * When the space used in the receive FIFO exceeds the data amount specified by FCFTR * When the number of receive frames in the receive FIFO exceeds the value specified by FCFTR The threshold of the receive data amount can be set in a range from 256 to 65536 bytes in 256byte units. The threshold of receive frames can be set in a range from 1 to 24 frames (by the frame) in frame units. (d) Receive Descriptor Empty
When the RACT bit of the read descriptor is 0 (invalid), the receive descriptor empty state is determined and DMA transfer is stopped. Then the following operation is performed. * Writes the RR bit in EDRRR to 0 * Sets the RDE bit in EESR to 1 and generates an interrupt to the CPU. To resume the DMA transfer to the receive buffer, the interrupt source needs to be cleared by software, the receive descriptor needs to be re-set and the RR bit in EDRRR should be set to 1. Even if receive descriptor is empty, frame reception from the GMII/MII/RMII to the receive FIFO is continued if there is empty space left in the receive FIFO and receive frame information management area. Therefore, even if a receive descriptor empty state is determined, the DMA transfer can be performed without discarding the frames received from the GMII/MII/RMII if DMA transfer to the receive buffer can be resumed before an overflow occurs.
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Section 23 Gigabit Ethernet Controller (GETHER)
23.4.4 (1)
Relay
Relay Procedure and Processing Flow
The GETHER has a function to relay frames received by either E-MAC0 or E-MAC1 to the other E-MAC. When relay is enabled, frames input from the E-MAC are sent to both relay FIFO and receive FIFO in the TSU, and determined independently whether to receive or not by the receive system and whether to relay or not by the relay system. To perform relay, both E-MAC controllers should be set as promiscuous mode, and the MAC address in both E-MAC controllers should be the same one (hereafter this MAC address is referred to as MAC address of this LSI). The relay frame processing (relay/discard) is set by the TSU_FWSL0 and TSU_FWSL1. Frames passing the relay FIFO during relaying are sent to the GMII/MII/RMII from E-MAC-1 in a relay from E-MAC0 to E-MAC1, from E-MAC0 in a relay from E-MAC1 to E-MAC0. At this time, collision with the relay frames from the E-DMAC may occur. The priority of the process when collision occurs can be set by TSU_PRISL0/1. When the relay FIFO use exceeds the TSU_PRISL0/1 setting, frame transmission from the relay FIFO takes priority. By using this function, lost frames due to relay FIFO overflow can be prevented. For multicast frames and frames their destinations are other than this LSI, the CAM evaluation in frame relay processing can be referenced (for details on the CAM function, refer to section 23.4.5, CAM Function). Table 23.4 shows the settings of the relay frame processing (without CAM). Table 23.4 Relay Frame Process (Without CAM)
Frame Type Frame for this LSI Relay Function Setting Frame Processing Register Bit FW40/1 = 0 FW40/1 = 1 Broadcast frame FW30/1 = 0 FW30/1 = 1 Multicast frame FW20/1 = 0 FW20/1 = 1 Frames having destinations other than this LSI FW10/1 = 0 FW10/1 = 1 Discarded Relayed Discarded Relayed Discarded Relayed Discarded Relayed
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Section 23 Gigabit Ethernet Controller (GETHER)
23.4.5
CAM Function
Frames input to the E-MAC are grouped into the following four types; unicast for this LSI, broadcast, multicast, and unicast to other destinations. The MAC addresses of unicast for this LSI and broadcast are fixed, and determined only by register settings. Consequently, only multicast and unicast to other destinations determine whether to receive or not and whether to transfer or not by using the CAM (unicast frames whose destination MAC addresses match this LSI are called unicast frames to this LSI, and those that do not are called unicast frames to other destinations). Furthermore, the evaluation of receive and relay of unicast to other destinations and multicast frames by using CAM are performed by referencing the registered MAC addresses of the CAM entry table in the TSU. By using this function, receive FIFO overflow can be prevented caused by accumulation of frame data not required for reception, and CPU processing for determining receive can be reduced. The POST table is composed of 4 bits, and each bit corresponds to port 0 reception, port 1 reception, port 0 to port 1 relay, and port 1 to port 0 relay. When the corresponding bit is set to 1, the CAM evaluation results are used for determining receive and relay. In other words, when the corresponding bit of the POST table is cleared to 0, receive and relay evaluation will be the same as when CAM is not used shown in table 23.4. The on-chip CAM has entry tables which can register the MAC address of 32 entries, the details of which can be set by TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31. The setting to enable/disable referencing of the on-chip CAM entry table is performed by the CAM entry table enable setting register which sets whether to perform CAM evaluation or not, and the CAM entry table POST setting register for setting whether to use the CAM determination results for determining receive or relay. When on-chip CAM entry table referencing during receive is enabled, the destination address in the frame and MAC address registered in the CAM entry table are compared, and it is determined whether to transfer the frames input to the E-MAC to E-DMAC (have E-DMAC receive the frames) or discard the frames. When relaying and CAM entry table referencing during relay are both enabled, whether to transfer or discard multicast frames and frames for destinations other than this LSI can be determined by comparing the destination address in the frame and MAC address registered in the CAM entry table. Table 23.5 shows the processing method of frames (receive or discard) in reception from E-MAC0 to E-DMAC0 or that from E-MAC1 to E-DMAC1, while table 23.6 shows the processing for frames in relay from EMAC0 to E-MAC1 or that from E-MAC1 to E-MAC0 (relay or discard).
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Section 23 Gigabit Ethernet Controller (GETHER)
Table 23.5 Receive Frame Processing
CAM Entry Table Referencing Results Types of Frame CAM hit (when addresses match) Frame to this LSI Broadcast frame Multicast frame Normal Mode MCT = 0 Discarded Discarded Discarded Received MCT = 1 Promiscuous Mode MCT = 0 Discarded Discarded Discarded Discarded Received MCT = 1
Frames having Received destinations other than this LSI CAM mishit (when addresses do not match) Frames to this LSI Received Broadcast frame Multicast frame Received Received Discarded
Received Received Received Received Discarded
Frames having Discarded destinations other than this LSI
[Legend] MCT (Bit 13 in ECMR): Multicast receive mode (0: Receive when CAM mishit/1: Receive when CAM hit)
Table 23.6 Relay Frame Process (With CAM)
Frame Multicast frame Relay Function Setting Register Bit FW40/1 = 0 FW40/1 = 1 Frames having destinations other than this LSI FW40/1 = 0 FW40/1 = 1 CAM Hit Relayed Discarded Relayed Discarded CAM Mishit Discarded Relayed Discarded Relayed
Note: CAM can only be referenced by multicast frames and frames with destinations other than this LSI. The frames with destinations set to this LSI and broadcast frames are processed based on the relay function setting register values, regardless of CAM reference.
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Section 23 Gigabit Ethernet Controller (GETHER)
23.4.6
Transmit/Receive Processing of Multi-Buffer Frame (Single-Frame/MultiDescriptor)
(1)
Multi-Buffer Frame Transmit Processing
If an error occurs during multi-buffer frame transmission, the processing shown in figure 23.12 is carried out by the E-DMAC. In the figure where the transmit descriptor is shown as inactive (TACT bit = 0), buffer data has already been transmitted successfully, and where the transmit descriptor is shown as active (TACT bit = 1), buffer data has not been transmitted. If a frame transmit error occurs in the first descriptor part where the transmit descriptor is active (TACT bit = 1), transmission is halted, and the TACT bit is cleared to 0, immediately. The next descriptor is then read, and the position within the transmit frame is determined on the basis of bits TFP1 and TFP0 (continuing [B00] or end [B01]). In the case of a continuing descriptor, the TACT bit is cleared to 0, and the next descriptor is read immediately. If the descriptor is the final descriptor, not only is the TACT bit cleared to 0, but write-back is also performed to the TFE and TFS bits at the same time. Data in the buffer is not transmitted between the occurrence of an error and write-back to the final descriptor. If error interrupts are enabled in EESIPR, an interrupt is generated immediately after the final descriptor write-back.
Descriptors TT AD CL TE 00 00 00 E-DMAC Inacrivates TACT (change 1 to 0) Descriptor read Inactivates TACT Descriptor read Inactivates TACT Descriptor read Inactivates TACT Descriptor read Inactivates TACT 10 10 10 10 10 11 TT FF PP 10 10 00 00 00 00 00 00 01 10 Frame Type
Start Continune Continune Continune Continune Continune Continune End Start Utransmitted data is not transmitted after error occurrence. Descriptor is only processed Transmit error occurrence
One frame
Buffer length set by descriptor
Transmitted data Untransmitted dara
Figure 23.12 E-DMAC Operation after Transmit Error
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Section 23 Gigabit Ethernet Controller (GETHER)
(2)
Receive Processing in the Case of Multi-Buffer Frame
If an error occurs during reception in the case of a multi-buffer frame where a receive frame is divided for storage in multiple buffers, the E-DMAC performs the processing shown in figure 23.13. In the figure, the invalid receive descriptors (with the RACT bit cleared to 0) represent the successful reception of data to be stored in buffers, and the valid receive descriptors (with the RACT bit set to 1) represent unreceived buffers. If a frame receive error occurs with a descriptor shown in the figure, the status is written back to the corresponding descriptor. If error interrupts are enabled in EESIPR, an interrupt is generated immediately after the writeback. If there is a new frame receive request, reception is continued from the buffer after that in which the error occurred.
Descriptors
TT AD CL TE 00 00 00 TT FF PP 10 10 00 00 00 00 00 00 00 10
Frame Type Start of frame
Start Continune Continune
E-DMAC Inactivates RATC and writes RFE, RFS Descriptor read
10 10 10 10 10 11
Receive error occurence
New frame reception continues from this buffer
Buffer length set by descriptor
Transmitted data
Untransmitted dara
Figure 23.13 E-DMAC Operation after Receive Error
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Section 23 Gigabit Ethernet Controller (GETHER)
23.4.7
Padding Insertion in Receive Data
In the E-DMAC, one to three bytes of padding can be inserted in any byte position of receive data to improve software handling capability. By using this function, for instance, inserting 2-byte padding after the MAC header (14 bytes) of Ethernet frame enables data following the MAC header to set in 4-byte boundary.
[No padding]
Receive buffer area 16-byte boundary MAC header (14 bytes)
16-byte boundary
Padding for separation at 16 byte boundary MAC header (14 bytes)
16-byte boundary
MAC header (14 bytes)
[No padding]
4 bytes
Insert 2-byte padding after 14th byte Receive buffer area 16-byte boundary MAC header (14 bytes) 2 bytes padding inserted after MAC header
16-byte boundary
MAC header (14 bytes)
16-byte boundary
MAC header (14 bytes)
Padding for separation at 16-bytes boundary
4 bytes
Figure 23.14 Padding Insertion in Receive Data
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Section 23 Gigabit Ethernet Controller (GETHER)
23.4.8 (1)
Interrupt Processing
Interrupt Sources
The GETHER issues three types of interrupts to the CPU: receive/transmit interrupts for port 0 (GEINT0), receive/transmit interrupts for port 1 (GEINT1) and transfer interrupts between port 0 and port 1 (GEINT2). Table 23.7 shows these three interrupts, the interrupt sources, interrupt status registers/bits set at interrupt occurrence, and interrupt generation timing. GEINT0 or GEINT1 interrupts are generated in correspondence with the port 0 or port 1 transmit/receive operation. When an interrupt source is generated, it is set in EESR0 or EESR1 and an interrupt is issued to the CPU. For some interrupt sources, the EESR0/EESR1 setting and an interrupt to the CPU are performed after a write-back operation to a descriptor is completed, not immediately after the interrupt source is detected. Interrupt sources other than the E-MAC status register source (ECI bit) are cleared by writing a 1 to the corresponding source bit. The EMAC status register source (ECI bit) is cleared by writing a 1 to the corresponding source bit in ECSR. Interrupt source bits retain the values until they are cleared. GEINT0 or GEINT1 interrupt source is allowed to issue interrupts by setting the corresponding bit in EESIPR0 or EESIPR1. Each E-MAC state register source (ECI bit) is allowed to issue an interrupt by setting the corresponding bit in ECSIPR. In the initial value, interrupts are disabled. GEINT2 interrupt is issued in correspondence with relay operation between port 1 and port 0. When an interrupt source is generated, it is set to the corresponding bit in TSU_FWSR and an interrupt is issued to the CPU. Each GEINT2 interrupt source is cleared by writing a 1 to the corresponding bit. The interrupt source bit retains the value until it is cleared. Each GEINT2 interrupt source is allowed to issue an interrupt by setting the corresponding bit in TSU_FWSR. In the initial state, interrupts are disabled. Table 23.7 shows these three interrupts, interrupt sources, interrupt status registers and bits set at interrupt occurrence and interrupt generation timing.
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Section 23 Gigabit Ethernet Controller (GETHER)
Table 23.7 List of GETHER Interrupts
Interrupt Interrupt Source Register and Bit EESR0.TWB EESR0.TUC EESR0.ROC EESR0.TABT EESR0.RABT EESR0.RFCOF EESR0.ECI EESR0.TUC EESR0.TDE EESR0.TFUF EESR0.FR EESR0.RDE EESR0.RFOF EESR0.DLC EESR0.CD EESR0.TRO Interrupt Generation Timing After write-back After write-back After write-back After write-back After write-back When the interrupt source is detected When the interrupt source is detected After write-back When the interrupt source is detected When the interrupt source is detected After write-back When the interrupt source is detected When the interrupt source is detected When the interrupt source is detected When the interrupt source is detected When the interrupt source is detected
Write-back completed Transmit/ receive Transmit underflow frame write-back interrupt for completed port 0 Receive underflow frame write-back (GEINT0) completed Transmission abort detection Reception abort detection Receive frame counter overflow E-MAC status register source Frame transmission completed Transmit descriptor empty Transmit FIFO underflow Frame reception Receive descriptor empty Receive FIFO overflow Detect Loss of Carrier Delayed Collision Detect Transmit Retry Over
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Section 23 Gigabit Ethernet Controller (GETHER)
Interrupt
Interrupt Source
Register and Bit EESR0.RMAF EESR0.CEEF EESR0.CELF EESR0.RRF EESR0.RTLF EESR0.RTSF EESR0.PRE EESR0.CERF EESR1.TWB EESR1.TUC EESR1.ROC EESR1.TABT EESR1.RABT EESR1.RFCOF EESR1.ECI EESR1.TUC EESR1.TDE EESR1.TFUF EESR1.FR EESR1.RDE EESR1.RFOF EESR1.DLC EESR1.CD
Interrupt Generated Timing After write-back After write-back After write-back After write-back After write-back After write-back After write-back After write-back After write-back After write-back After write-back After write-back After write-back When the interrupt source is detected When the interrupt source is detected After write-back When the interrupt source is detected When the interrupt source is detected After write-back When the interrupt source is detected When the interrupt source is detected When the interrupt source is detected When the interrupt source is detected
Transmit/ Receive Multicast Address Frame receive Carrier Extension Error interrupt for Carrier Extension Loss port 0 (GEINT0) Receive Residual-Bit Frame Receive Too-Long Frame Receive Too-Short Frame PHY-LSI Receive Error CRC Error on Received Frame Transmit/ Write-Back Completed receive Transmit Underflow Frame Write-Back interrupt for Completed port 1 Receive Overflow Frame Write-Back (GEINT1) Completed Transmit Abort Detect Receive Abort Detect Receive Frame Counter Overflow E-MAC Status Register Source Frame Transmission Completed Transmit Descriptor Empty Transmit FIFO Underflow Frame Reception Receive Descriptor Empty Receive FIFO Overflow Carrier Loss Detection Delayed Collision Detect
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Section 23 Gigabit Ethernet Controller (GETHER)
Interrupt Transmit/ receive interrupt for port 1 (GEINT1)
Interrupt Source Transmit Retry Over Receive Multicast Address Frame Carrier Extension Error Carrier Extension Loss Receive Residual-Bit Frame Receive Too-Long Frame Receive Too-Short Frame PHY-LSI Receive Error CRC Error on Received Frame
Register and Bit EESR1.TRO EESR1.RMAF EESR1.CEEF EESR1.CELF EESR1.RRF EESR1.RTLF EESR1.RTSF EESR1.PRE EESR1.CERF TSU_FWSR.OVF0
Interrupt Generated Timing When the interrupt source is detected After write-back After write-back After write-back After write-back After write-back After write-back After write-back After write-back When the interrupt source is detected
Interrupt with Port 0-to-1 Transfer FIFO Overflow transfer Detect between port E-MAC-0 Overflow Alert Signal Output 0 and port 1 (GEINT2) E-MAC-0 Carrier Extension Loss Error Detect E-MAC-0 Residual-Bit Frame Receive E-MAC-0 Too-Long Frame Receive E-MAC-0 Too-Short Frame Receive E-MAC-0 Frame Receive Error E-MAC-0 CRC Error Frame Receive Port 1-to-0 Transfer FIFO Overflow Detect E-MAC-1 Overflow Alert Signal Output E-MAC-1 Carrier Extension Loss Error Detect E-MAC-1 Residual-Bit Frame Receive
TSU_FWSR.RBSY0 When the interrupt source is detected TSU_FWSR.RINT60 When the interrupt source is detected TSU_FWSR.RINT50 When the interrupt source is detected TSU_FWSR.RINT40 When the interrupt source is detected TSU_FWSR.RINT30 When the interrupt source is detected TSU_FWSR.RINT20 When the interrupt source is detected TSU_FWSR.RINT10 When the interrupt source is detected TSU_FWSR.OVF1 When the interrupt source is detected
TSU_FWSR.RBSY1 When the interrupt source is detected TSU_FWSR.RINT61 When the interrupt source is detected TSU_FWSR.RINT51 When the interrupt source is detected
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Section 23 Gigabit Ethernet Controller (GETHER)
Interrupt
Interrupt Source
Register and Bit
Interrupt Generated Timing
Interrupt with E-MAC-1 Too-Long Frame Receive transfer between port E-MAC-1 Too-Short Frame Receive 0 and port 1 (GEINT2) E-MAC-1 Frame Receive Error E-MAC-1 CRC Error Frame Receive
TSU_FWSR.RINT41 When the interrupt source is detected TSU_FWSR.RINT31 When the interrupt source is detected TSU_FWSR.RINT21 When the interrupt source is detected TSU_FWSR.RINT11 When the interrupt source is detected
23.4.9
Activation Procedure
The GETHER should be activated by the following procedure: (1) 1. 2. * 3. * 4. 5. * (2) Reset Perform a power-on reset. Start the E-DMAC transmitter and receiver (activation of descriptor engine). Set ENT to 1 and ENR to 1 in EDSR. Perform a software reset. Set SWRR to 1 and SWRT to 1 in EDMR simultaneously. Initialize the descriptor entry table. Confirm cancellation of the software reset. Check that the SWRR and SWRT bits in EDMR are cleared to 0. Registration of Descriptor Ring
The address of a descriptor ring configured in memory is registered in the descriptor entry table. 1. * * * * Transmit Descriptor Setting Set TDLAR. Set TDFAR. Set TDFXR. Set TDFFR. When the descriptor indicated by TDFXR is the last descriptor in the descriptor list, set H'00000001.
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Section 23 Gigabit Ethernet Controller (GETHER)
2. * * * *
Receive Descriptor Setting Set RDLAR. Set RDFAR. Set RDFXR. Set RDFFR. When the descriptor indicated by RDFXR is the last descriptor in the descriptor list, set H'00000001. Register Settings
(3)
The following registers should be set as necessary. 1. * * * * * * * * 2. * * * * * * * * * * * E-DMAC-related registers Set EDMR: Operating mode, etc. Set EESIPR: Interrupt masks Set TRSCER: Error masks Set TFTR: Transmit FIFO threshold Set FDR: External FIFO size Set RMCR: Reset method for reception activation Set RPADIR: Padding insertion into receive data Set FCFTR: Receive BSY output threshold E-MAC-related registers Set ECMR setting: Transmission/reception specifications Set ECSIPR setting: Interrupt masks Set MAHR: MAC address Set MALR: MAC address Set RFLR: Maximum receive frame length Set PIPR: ET_PHY_INT pin polarity Set APR: TIME parameter value of an automatic pause frame Set MPR: TIME parameter value of a manual PAUSE frame Set TPAUSER: Upper limit of automatic PAUSE frame retransmission Set GECMR: Transfer speed Set BCULR: Upper limit of burst cycles
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Section 23 Gigabit Ethernet Controller (GETHER)
(4)
Activation
1. Start the E-DMAC transmission/reception function * Set the TR bits in EDTRR to 11. * Set the RR bit in EDRRR to 1. 2. Start the E-MAC transmission/reception function * Set the TE and RE bits in ECMR to 1. 23.4.10 Flow Control The GETHER supports flow control functions conforming to IEEE802.3x for full-duplex operation. The flow control can be applied to both receive and transmit operations. When transmitting PAUSE frames, flow control can be performed by the following two procedures : (1) Automatic PAUSE Frame Transmission
For receive frames, PAUSE frames are automatically transmitted when the number of data written to the receive FIFO reaches the value set in FCFTR. The TIME parameter included in the PAUSE frame is set by APR. The automatic PAUSE frame transmission is repeated until the number of data in the receive FIFO becomes less than the value set in FCFTR as the receive data is read from the FIFO. Using TPAUSER, the upper limit of retransmission counts of the PAUSE frames can also be set in the range from 1 to 65535. In this case, PAUSE frame transmission is repeated until the number of receive FIFO data becomes less than the FCFTR value, or the number of transmits reaches the value set by TPAUSER. The transmission counter is cleared to 0 when the next PAUSE frame is transmitted after the number of data in the receive FIFO becomes less than the FCFTR value. The automatic PAUSE frame transmission is enabled when the TXF bit in ECMR is 1. (2) Manual PAUSE Frame Transmission
PAUSE frames are transmitted by directives from the software. When writing the Timer value to MPR, manual PAUSE frame transmission is started. With this method, PAUSE frame transmission is carried out only once.
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Section 23 Gigabit Ethernet Controller (GETHER)
(3)
PAUSE Frame Reception
The next frame is not transmitted until the time indicated by the Timer value elapses after receiving a PAUSE frame. However, the transmission of the current frame is continued. A received PAUSE frame is valid only when the RXF bit in ECMR is set to 1. The number of times of PAUSE frame receptions is counted. (4) 0-Time PAUSE Frame Control
Flow control is performed using a PAUSE frame with the TIME parameter value set to 0. The PAUSE frame with the TIME parameter set to 0 can be enabled or disabled by the ZPF bit in ECMR. * When PAUSE frame control with the TIME parameter value set to 0 is enabled A PAUSE frame with the TIME parameter value set to 0 is transmitted when the number of data in the receive FIFO is less than the FCFTR value before the time indicated by the TIME parameter value has not elapsed. When a PAUSE frame with the time indicated by the TIME parameter value set to 0 is received, the transmit standby state is canceled. * When PAUSE frame control with the TIME parameter value set to 0 is disabled A PAUSE frame with the TIME parameter value set to 0 is not transmitted. When a PAUSE frame with the TIME parameter value set to 0 is received, the PAUSE frame is discarded. 23.4.11 Magic Packet Detection The GETHER has a Magic Packet detection function. This function provides a Wake-On-LAN (WOL) facility that starts each peripheral device connected to a LAN from the host device or other source. This enables to construct a system in which a peripheral device receives a Magic Packet sent from the host device or other source, and starts itself. When the Magic Packet is detected, data is stored in the FIFO by the broadcast packet that has received data previously and the EMAC is notified of the receiving status. To return to normal operation from the interrupt processing, the E-MAC, TSU and E-DMAC must be initialized by using ARST bit in ARSTR. With a Magic Packet, reception is performed regardless of the destination address. As a result, this function is valid, and the ET_WOL pin enabled, only in the case of a match with the destination address specified by the format in the Magic Packet. Further information on Magic Packets can be found in the technical documentation published by AMD Corporation.
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Section 23 Gigabit Ethernet Controller (GETHER)
The procedure for using the WOL function with this LSI is as follows. 1. 2. 3. 4. Disable interrupt source output by means of the various interrupt enable/mask registers. Set the MPDE bit in ECMR. Set the MPDIP bit in ECSIPR to the enable setting. If necessary, set the CPU operating mode to sleep mode or set peripheral modules to module standby mode. 5. When a Magic Packet is detected, an interrupt is sent to the CPU. The ET_WOL pin notifies peripheral LSIs that the Magic Packet has been detected. 23.4.12 Direction for IEEE802.1Q Qtag The GETHER supports IEEE802.1Q frame processing. It can add or delete Qtags to or from frames processed in relay. This function can also transmit and receive QoS frames. During relay, if the Ethernet device connected to one E-MAC controller cannot transmit or receive QoS frames, the frames can converted to the normal IEEE802.3 frames and relayed in this LSI. Whether to add or delete Qtags depends on TSU_QTAGM0/1. When the Qtag is added, the Qtag to be added can be set by TSU_ADQT0/1. Figure 23.15 shows the outlines of the Qtag add function. Figure 23.16 shows the comparison between the normal Ethernet frames and IEEE802.1Q frames (with Qtag). For details on Qtag setting, see the specifications on Qtag control specified in IEEE802.1Q
Figure 23.15 Outlines of Qtag Additional Functions
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Section 23 Gigabit Ethernet Controller (GETHER)
Normal Ethernet frame 7 oct PR 1 oct SFD 6 oct DA 6 oct SA
(Without Qtag) 2 oct L/T 46 to 1500 oct Data 4 oct FCS
802.1Q conforming frame 7 oct PR 1 oct SFD 6 oct DA 6 oct SA
(With Qtag) 4 oct Qtag 2 oct L/T 42 to 1500 oct Data
4 oct
FCS
8 bit H'81
8 bit H'00
3 bit PRT
1 bit CFI
12 bit VID
Extension code (Fixed) Legend: PR: SFD: DA: SA: L/T: FCS: PReamble Start Frame Delimiter Destination Address Source Address Length or Type Frame Check Sequence Qtag setting (TSU_ADQT0/1) PRT: CFI: Proprity Fixed at 0
VID: V-LAN ID setting
Figure 23.16 Comparison of Normal Ethernet Frame and IEEE802.1Q Frame (with Qtag)
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Section 23 Gigabit Ethernet Controller (GETHER)
23.5
23.5.1
Connection to PHY-LSI
MII Frame Transmission/Reception Timing
Each MII frame transmission/reception timing is shown in figures 23.17 to 23.22.
ET_TX-CLK ET_TX-EN ET_TXD3 to 0 ET_TX-ER ET_CRS ET_COL
Preamble
SFD
Data
CRC
Figure 23.17 MII Frame Transmit Timing (Normal Transmission)
ET_TX-CLK ET_TX-EN ET_TXD3 to 0 ET_TX-ER ET_CRS ET_COL Preamble JAM
Figure 23.18 MII Frame Transmit Timing (Collision)
Rev. 1.00 Oct. 01, 2007 Page 984 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
ET_TX-CLK ET_TX-EN ET_TXD3 to 0 ET_TX-ER ET_CRS ET_COL Preamble SFD Data
Figure 23.19 MII Frame Transmit Timing (Transmit Error)
ET_RX-CLK ET_RX-DV ET_RXD3 to 0 ET_RX-ER
Preamble
SFD
Data
CRC
Figure 23.20 MII Frame Receive Timing (Normal Reception)
ET_RX-CLK ET_RX-DV ET_RXD3 to 0 ET_RX-ER
Preamble SFD Data XXXX
Figure 23.21 MII Frame Receive Timing (Reception Error (1))
ET_RX-CLK ET_RX-DV ET_RXD3 to 0 ET_RX-ER
XXXX
1110
XXXX
Figure 23.22 MII Fame Receive Timing (Reception Error (2))
Rev. 1.00 Oct. 01, 2007 Page 985 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.5.2
GMII/MII Frame Reception Timing
Each GMII/MII frame reception timing is shown in figures 23.23 to 23.28.
ET_RX-CLK ET_RX-DV
GET_ERXD7 to 4 ET_ERXD3 to 0 Preamble SFD Data CRC
ET_RX-ER
ET_RX-CRS
Figure 23.23 GMII/MII Fame Receive Timing (Normal Reception)
ET_RX-CLK ET_RX-DV GET_ERXD7 to 4 ET_ERXD3 to 0 ET_RX-ER ET_RX-CRS CRC 0F
Figure 23.24 GMII/MII Fame Receive Timing (with Carrier Extension)
ET_RX-CLK ET_RX-DV GET_ERXD7 to 4 ET_ERXD3 to 0 ET_RX-ER ET_RX-CRS CRC 0F Preamble
Figure 23.25 GMII/MII Fame Receive Timing (Burst Reception)
Rev. 1.00 Oct. 01, 2007 Page 986 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
ET_RX-CLK ET_RX-DV
GET_ERXD7 to 4 ET_ERXD3 to 0 Preamble SFD
X
ET_RX-ER
ET_RX-CRS
Figure 23.26 GMII/MII Fame Receive Timing (Reception Error)
ET_RX-CLK ET_RX-DV GET_ERXD7 to 4 ET_ERXD3 to 0 ET_RX-ER ET_RX-CRS CRC 1F
Figure 23.27 GMII/MII Fame Receive Timing (Error with Carrier Extension)
ET_RX-CLK ET_RX-DV
GET_ERXD7 to 4 ET_ERXD3 to 0
ET_RX-ER
X
Figure 23.28 GMII/MII Fame Receive Timing (False Carrier Indication)
Rev. 1.00 Oct. 01, 2007 Page 987 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.5.3
RMII Frame Transmission/Reception Timing
Each RMII frame transmission/reception timing is shown in figures 23.29 to 23.31.
REF50CK RMII_CRS_DV RMII_RXD1
RMII_RXD0 0
0
nibble boundary
0
0
0
0
0
0
/J/
0
0
0
0
/K/
0
1
0
1
0
1
0
1
0
1
0
1
1
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
I
I
J
J
0
0
Preamble
SFD
Data
Figure 23.29 RMII Fame Receive Timing (Normal 100-Mbps Reception)
REF50CK RMII_CRS_DV RMII_RXD1
RMII_RXD0 0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
False Carrier detected
Figure 23.30 RMII Fame Receive Timing (100-Mbps Reception with Illegal Carrier Detected)
REF50CK RMII_TX_EN RMII_TXD1
0
0
0
0
0
0
0
0
0
0
0
0
1
A
B
C
D
E
F
G
H
I
J
0
RMII_TXD0
1
1
1
1
1
1
1
1
1
1
1
1
1
A
B
C
D
E
F
G
H
I
J
0
Preamble
SFD
Data
Figure 23.31 RMII Fame Transmit Timing (Normal 100-Mbps Transmission)
Rev. 1.00 Oct. 01, 2007 Page 988 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.5.4
Accessing MII Registers
MII registers in the PHY-LSI are accessed via PIR in this LSI. PIR is used as a serial interface conforming to the MII frame format specified in IEEE802.3u. (1) MII Management Frame Format
Figure 23.32 shows the format of an MII management frame. To access an MII register, a management frame is implemented by the program in accordance with the procedures shown in MII Register Access Procedure.
Access Type Item Number of bits Read Write PRE 32 1..1 1..1 ST 2 01 01 OP 2 10 01 MII Management Frame PHYAD 5 00001 00001 REGAD 5 RRRRR RRRRR TA 2 Z0 10 DATA 16 D..D D..D X IDLE
[Legend] PRE: ST: OP: PHYAD:
32 consecutive 1s Write of 01 indicating start of frame Write of code indicating access type Write of 0001 if the PHY-LSI address is 1 (sequential write starting with the MSB). This bit changes depending on the PHY-LSI address. REGAD: Write of 000q if the register address is 1 (sequential write starting with the MSB). This bit changes depending on the PHY-LSI register address. TA: Time for switching data transmission source on MII interface (a) Write: 10 written (b) Read: Bus release (notation: Z0) perdormed DATA: 16-bit data. Sequential write or read from MSB (a) Write: 16-bit data write (b) Read: 16-bit data read IDLE: Wait time until next MII management format input (a) Write: Independent bus release (notation: X) performad (d) Read: Bus already released in TA: control unnecessary
Figure 23.32 MII Management Frame Format
Rev. 1.00 Oct. 01, 2007 Page 989 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
(2)
MII Register Access Procedure
The program accesses MII registers via PIR. Access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data read, bus release, and independent bus release. Figure 23.33 shows the MII register access timing. The timing will differ depending on the PHY-LSI type.
(1) Write to PHY interface register
ET_MDC
ET_MMD = 1 ET_MDO = write data ET_MDC = 0
ET_MDO
(2) Write to PHY interface register ET_MMD = 1 ET_MDO = write data ET_MDC = 1
(1) (2)
(3)
1-bit data write timing relationship
(3) Write to PHY interface register ET_MMD = 1 ET_MDO = write data ET_MDC = 0
Figure 23.33 1-Bit Data Write Flowchart
(1)
Write to PHY interface register ET_MMD = 0 ET_MDC = 0 ET_MDC ET_MDO
(2)
Write to PHY interface register ET_MMD = 0 ET_MDC = 1 (1) (2) (3)
Bus release timing relationship
(3)
Write to PHY interface register ET_MMD = 0 ET_MDC = 1
Figure 23.34 Bus Release Flowchart (TA in Read in Figure 23.33)
Rev. 1.00 Oct. 01, 2007 Page 990 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
(1)
Write to PHY interface register ET_MMD = 0 ET_MDC = 1
ET_MDC ET_MDI
(2)
Read from PHY interface register ET_MMD = 0 ET_MDC = 1 ET_MDI is read data
(1)
(2)
(3)
1-bit data read timing relatinship
(2)
Write to PHY interface register ET_MMD = 0 ET_MDC = 0
Figure 23.35 1-Bit Data Read Flowchart
(1)
Write to PHY interface register ET_MDC ET_MMD = 0 ET_MDC = 0 ET_MDO
(1) Independent bus release timing relationship
Figure 23.36 Independent Bus Release Flowchart (IDLE in Write in Figure 23.33) 23.5.5 Mll-RMII Interface Conversion
This LSI supports an RMII interface. The RMII signals are generated by converting the MII signals in the MII-RMII conversion circuit. (1) Clock
REF50CK (50 MHz) from the RMII interface is divided and ET_TX-CLK/ET_RX-CLK (25 MHz or 2.5 MHz) is output.
Rev. 1.00 Oct. 01, 2007 Page 991 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
(2)
Reception
Waveforms received from the RMII interface are converted to MII waveforms and output (10 Mbps or 100 Mbps). Illegal carrier detection signal received from the RMII interface is converted to MII signal and output. RMII_RX-ER signal received from the RMII interface is converted to MII interface signal and output. Note: Illegal carrier detection is not generated from preamble detection to reception completion (ET_RX_DV negation). (3) Transmission
Transmit waveforms from the MII interface is converted to the RMII interface waveforms and output (10 Mbps or 100 Mbps). The collision signal, ET_COL, is generated by AND operation of the ET_CRS and ET_TX-EN signals. (4) Full-Duplex/Half-Duplex Selection
In full-duplex transfer mode, the assertion of the COL is suppressed. Figure 23.37 shows a schematic of the conversion cicuit.
MII-RMII conversion ET_TX-EN ET_ETXD3 to ET_ETXD0 ET_COL
D
RMII_TX-EN
4 bit-to-2 bit conversion
RMII_TXD1 RMII_TXD0
Half-duplex/full-duplex
ET_CRS ET_RX-DV
CRS and RX_DV generation 2 bit-to-4 bit conversion
RMII_CRS-DV
ET_ERXD3 to ET_ERXD0 ET_TX-ER
RMII_RXD1 RMII_RXD0
D
RMII_RX-ER
False carrier detection
ET_TX-CLK ET_RX-CLK
Clock generation
REF50CK
Figure 23.37 MII-RMll Conversion Circuit
Rev. 1.00 Oct. 01, 2007 Page 992 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
23.6
23.6.1
Usage Notes
Checksum Calculation of Ethernet Frames
This LSI is capable of calculating the checksum data of the received frames. Only the data fields of the Ethernet frames are subject to calculation. Specifically, a data field follows the length/type field and is followed by the CRC field. Calculation involves 16-bit addition only; it does not involve bit reversal. Note: Also for the frames with VLANTag inserted, the 15th byte from the top and the following bytes before the CRC field are subject to calculation.
Destination address (6 bytes) Source address (6 bytes) Type (2 bytes)
Destination address (6 bytes)
Source address (6 bytes) VLANtag (4 bytes) Type (2 bytes) Data subject to checksum calculation Data subject to checksum calculation
Data (46 to 1500 bytes)
Data (60 bytes)
CRC (4 bytes) Schematic of an Ethernet frame (without VLANtag)
CRC (4 bytes) Schematic of an Ethernet frame (with VLANtag)
Figure 23.38 Data Subject to Checksum Calculation 23.6.2 Notes on TSU Use
The TSU of this LSI supports up to 100BASE-T data transfers. Therefore, even when The TSU of this LSI is used with 1000BASE-T, the transfer performance is equal to that with 100BASE-T.
Rev. 1.00 Oct. 01, 2007 Page 993 of 1956 REJ09B0256-0100
Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 1.00 Oct. 01, 2007 Page 994 of 1956 REJ09B0256-0100
Section 24 IP Security Accelerator (SECURITY)
Section 24 IP Security Accelerator (SECURITY)
This section will be made available on conclusion of a nondisclosure agreement. For details, contact your Renesas Technology sales agency.
Rev. 1.00 Oct. 01, 2007 Page 995 of 1956 REJ09B0256-0100
Section 24 IP Security Accelerator (SECURITY)
Rev. 1.00 Oct. 01, 2007 Page 996 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
Section 25 Stream Interface (STIF)
The stream interface (STIF) transfers stream data between an 8-bit parallel bus and external memory using general DMAC peripheral module requests (transfer size is fixed at 16 bytes).
25.1
Features
* Number of parallel stream data transfer channels: 2 channels * Stream data transfer interface Clock valid reception Strobe reception Clock valid transmission Strobe transmission * Input/output packet length: 188 or 192 bytes is selectable The external pin input or peripheral clock 0 (Pck0) can be selected as the stream data transfer clock source. * Transmit/receive FIFO size: 768 bytes * Time stamp adding function Includes a free-running timer for time stamp. (The free-running timer input clock can be selected from among 1/2, 1/4, and 1/8 of peripheral clock 0.) At reception: The free-running timer value is added to the receive packet as the time stamp value and stored in memory. At transmission: A packet is transmitted with the free-running timer value added as the time stamp value. * DMA transfer Data transfer with external memory by means of DMA transfer is supported.
Rev. 1.00 Oct. 01, 2007 Page 997 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
Figure 25.1 shows a block diagram of the STIF.
Perioheral clock 0 (Pck 0)
Channel 0
ST0_CLK/ST0_STRB
Peripheral bus interface
Stream interface control unit
FIFO register
ST0_REQ
ST0_START
ST0_VALID
ST0_D7 to ST0_D0
ST0M_CLKIO/ST0M_STRBI
ST0M_REQO
Peripheral bus 0
Stream interface (STIF)
ST0M_STARTI
ST0M_VALIDI
Channel 1
ST0M_D7I to ST0M_D0I
ST1_CLK/ST1_STRB
Peripheral bus interface
Stream interface control unit
ST1_REQ
ST1_START
ST1_VALID
ST1_D7 to ST1_D0
FIFO register
Figure 25.1 Block Diagram of STIF
Rev. 1.00 Oct. 01, 2007 Page 998 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
25.2
Input/Output Pins
Table 25.1 shows the pin configuration of this module. Channel 0 has two pin groups: normal I/O pins and mirror input pins. Note that the mirror input pin group can only be used for input. The pin select register of the PFC is used to select normal I/O pins or mirror input pins. The normal I/O pins and mirror input pins cannot be used simultaneously or mixed together. Table 25.1 Pin Configuration
Channel 0 Pin Name I/O I/O I/O I/O I/O I/O I/O Output Input Input Input I/O I/O I/O I/O I/O Function Stream data clock/strobe Stream data receive ready request Stream data synchronization Stream data valid Stream data input/output Stream data clock/strobe Stream data receive ready request Stream data synchronization input Stream data valid input Stream data input Stream data clock/strobe Stream data receive ready request Stream data synchronization Stream data valid Stream data input Description
Normal I/O ST0_CLK/ST0_STRB pins ST0_REQ ST0_START ST0_VALID ST0_D7 to ST0_D0 Mirror input ST0M_CLKIO/ ST0M_STRBI pins* ST0M_REQO ST0M_STARTI ST0M_VALIDI ST0M_D7I to ST0M_D0I
1
ST1_CLK/ST1_STRB ST1_REQ ST1_START ST1_VALID ST1_D7 to ST1_D0
Note:
*
Mirror pins are only for input.
Rev. 1.00 Oct. 01, 2007 Page 999 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
25.3
Register Descriptions
Table 25.2 shows the STIF register configuration. Table 25.3 shows the register states in each operating mode. Table 25.2 Register Configuration
Register Name Mode register 0 Control register 0 Interrupt status register 0 Interrupt enable register 0 Time stamp counter register 0 Transmit/receive packet count register 0 Transmit/receive packet counter register 0 Abbreviation R/W STIMDR0 STICR0 STIISR0 STIIER0 STITSC0 STIPNR0 STIPCR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Area P4 Address H'FFEE 0000 H'FFEE 0004 H'FFEE 0008 H'FFEE 000C H'FFEE 0010 H'FFEE 0018 H'FFEE 0014 H'FFEE 0400 H'FFEE 8000 H'FFEE 8004 H'FFEE 8008 H'FFEE 800C H'FFEE 8010 H'FFEE 8018 H'FFEE 8014 H'FFEE 8400 Area 7 Address Access Size
H'1FEE 0000 32 H'1FEE 0004 32 H'1FEE 0008 32 H'1FEE 000C 32 H'1FEE 0010 32 H'1FEE 0018 32 H'1FEE 0014 32 H'1FEE 0400 32 H'1FEE 8000 32 H'1FEE 8004 32 H'1FEE 8008 32 H'1FEE 800C 32 H'1FEE 8010 32 H'1FEE 8018 32 H'1FEE 8014 32 H'1FEE 8400 32
Transmit/receive FIFO data register 0 STIFIFO0 Mode register 1 Control register 1 Interrupt status register 1 Interrupt enable register 1 Time stamp counter register 1 Transmit/receive packet count register 1 Transmit/receive packet counter register 1 STIMDR1 STICR1 STIISR1 STIIER1 STITSC1 STIPNR1 STIPCR1
Transmit/receive FIFO data register 1 STIFIFO1
Rev. 1.00 Oct. 01, 2007 Page 1000 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
Table 25.3 Register States in Each Operating Mode
Register Name Mode register 0 Control register 0 Interrupt status register 0 Interrupt enable register 0 Time stamp counter register 0 Transmit/receive packet count register 0 Transmit/receive packet counter register 0 Abbrevia- Power-On tion Reset STIMDR0 STICR0 STIISR0 STIIER0 STITSC0 STIPNR0 STIPCR0 Manual Reset Sleep Standby
H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained H'00000000 H'00000000 Retained Retained
Transmit/receive FIFO data register 0 STIFIFO0 Mode register 1 Control register 1 Interrupt status register 1 Interrupt enable register 1 Time stamp counter register 1 Transmit/receive packet count register 1 Transmit/receive packet counter register 1 STIMDR1 STICR1 STIISR1 STIIER1 STITSC1 STIPNR1 STIPCR1
Transmit/receive FIFO data register 1 STIFIFO1
Rev. 1.00 Oct. 01, 2007 Page 1001 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
25.3.1
Mode Registers 0, 1 (STIMDR0, STIMDR1)
STIMDR sets the STIF operating mode and clock definition for stream data transmission/reception.
Bit: 31 30 29
MD[2:0] 0 R/W 0 R/W 0 R/W
28
27
26
25
24
PLEN 0 R/W
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit:
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
STMP[1:0] 0 R/W 0 R/W
-
0 R
-
0 R
WORK[1:0] 0 R/W 0 R/W
15
CKSL
14
13
12
11
10
9
8
REQ EN
7
6
5
4
3
2
1
0
-
0 R
CKDV[1:0] 0 R/W 0 R/W
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
FRC[1:0] 0 R/W 0 R/W
STRB REQ 0 R/W 0 R/W
VLD STAT 0 R/W 0 R/W
Initial value: R/W:
0 R/W
0 R/W
Bit 31
Initial Bit Name Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
30 to 28 MD[2:0]
000
R/W
Stream Data Transfer Interface 000: Clock valid reception 010: Strobe reception 100: Clock valid transmission 101: Strobe transmission Other than above: Setting prohibited
27 to 25
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
24
PLEN
0
R/W
Transmit/Receive Packet Length Sets the packet length of the stream data to be transmitted or received. 0: Packet length is 188 bytes 1: Packet length is 192 bytes
23, 22
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1002 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
Bit 21, 20
Bit Name STMP[1:0]
Initial Value 00
R/W R/W
Description Time Stamp At reception: These bits select whether to add a fixed value, add the time stamp, or do not add any value when transferring the receive packet to external memory. 00: Adds a fixed value to the receive packet and transfers it to external memory 01: Adds the time stamp to the receive packet and transfers it to external memory 10: Transfers the receive packet to external memory without any changes (only when the packet size is 192 bytes) 11: Setting prohibited At transmission: These bits select the packet interval for transmitting the transmit packet. 00: Packet interval is in accordance with the ICYC bits in STICR 01: Packet interval is in accordance with the time stamp 10, 11: Setting prohibited
19, 18
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
17, 16
WORK[1:0] 00
R/W
Work Area Size These bits specify the work area size allocated at the front of the packet in external memory. 00: Work area is 0 bytes 01: Work area is 16 bytes 10: Work area is 32 bytes 11: Work area is 48 bytes
Rev. 1.00 Oct. 01, 2007 Page 1003 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
Bit 15
Bit Name CKSL
Initial Value 0
R/W R/W
Description Operating Clock Selects the source clock for the stream data transfer clock 0: Peripheral clock 0 is used as the stream data transfer clock (stream data transfer clock is output from the ST_CLK pin) 1: External input clock is used as the stream data transfer clock (stream data transfer clock is input from the ST_CLK pin)
14
0
R
Reserved This bit is always read as 0. The write value should always be 0.
13, 12
CKDV[1:0] 00
R/W
Operating Clock Division Ratio These bits specify the division ratio when peripheral clock 0 is selected as the stream data transfer clock. 00: Stream data transfer clock is 1/2 of peripheral clock 0 01: Stream data transfer clock is 1/4 of peripheral clock 0 10: Stream data transfer clock is 1/8 of peripheral clock 0 11: Setting prohibited
11 to 9
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
REQEN
0
R/W
ST_REQ Pin Enable Selects whether or not to use the ST_REQ pin. 0: ST_REQ pin is not used 1: ST_REQ pin is used (1) At reception: ST_REQ is output when the free space in FIFO is 8 bytes or less (2) At transmission: Transmission is stopped when ST_REQ is input
Rev. 1.00 Oct. 01, 2007 Page 1004 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
Bit 7, 6
Initial Bit Name Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
5, 4
FRC[1:0]
00
R/W
Input Clock of Free-Running Timer 00: Timer input clock is 1/2 of peripheral clock 0 01: Timer input clock is 1/4 of peripheral clock 0 10: Timer input clock is 1/8 of peripheral clock 0 11: Setting prohibited
3
STRB
0
R/W
ST_STRB Pin Polarity 0: Data is transferred/received on the rising edge of ST_STRB 1: Data is transferred/ received on the falling edge of ST_STRB
2
REQ
0
R/W
ST_REQ Pin Polarity 0: ST_REQ is active-high 1: ST_REQ is active-low
1
VLD
0
R/W
ST_VALID Pin Polarity 0: ST_VALID is active- high 1: ST_VALID is active- low
0
STAT
0
R/W
ST_START Pin Polarity 0: ST_START is active- high 1: ST_START is active- low
Rev. 1.00 Oct. 01, 2007 Page 1005 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
25.3.2
Control Registers 0, 1 (STICR0, STICR1)
STICR enables or disables the STIF module and sets the packet interval for stream data transmission.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit: 0 R
-
0 R
-
0 R
-
0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
ICYC[11:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 EN 0 R/W
15
RTS
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
Initial value: R/W:
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 28
27 to 16 ICYC[11:0] All 0
R/W
Number of Cycles between Transmit Packets These bits set the fixed value when a fixed value is used as the number of cycles between packets during transmission. 1 to 4096 cycles of peripheral clock 0 can be inserted as idle cycles between packets.
15
RST
0
R/W
STIF Module Reset Writing 1 to this bit resets the STIF module. This bit is always read as 0.
14 to 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
EN
0
R/W
STIF Module Enable 0: STIF module is disabled 1: STIF module is enabled
Rev. 1.00 Oct. 01, 2007 Page 1006 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
25.3.3
Interrupt Status Registers 0, 1 (STIISR0, STIISR1)
STIISR shows the states of STIF interrupts.
Bit:
31
30
29
28
TPN 0 R/W
27
26
25
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R 0 TSTO 0 R/W
15
14
13
12
RPN 0 R/W
11
10
9
8
7
6
5
4
ROVF 0 R/W
3
2
1
-
Initial value: R/W: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
LONG SHORT 0 R/W 0 R/W
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
Bit
Initial Bit Name Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 29
28
TPN
0
R/W* Transmit Packet Count Interrupt 0: Transmit packet count register value > Transmit packet counter value 1: Transmit packet count register value = Transmit packet counter value After an interrupt is issued, the transmit packet counter is cleared to 0 and continues counting.
27 to 13
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
12
RPN
0
R/W* Receive Packet Count Interrupt 0: Receive packet count register value > Receive packet counter value 1: Receive packet count register value = Receive packet counter value After an interrupt is issued, the receive packet counter is cleared to 0 and continues counting.
Rev. 1.00 Oct. 01, 2007 Page 1007 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
Bit 11, 10
Initial Bit Name Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
9
LONG
0
R/W* Long Packet Reception Interrupt 0: Packet exceeding 188 or 192 bytes has not been received 1: Packet exceeding 188 or 192 bytes has been received When a packet exceeding 188 or 192 bytes is received, the long packet counter and packet counter are both incremented by one. Data of 188 or 192 bytes is transferred to memory and the excess data is discarded.
8
SHORT
0
R/W* Short Packet Reception Interrupt 0: Packet less than 188 or 192 bytes has not been not received 1: Packet less than 188 or 192 bytes has been received When a packet less than 188 or 192 bytes is received, the short packet counter is incremented by one and the packet is discarded.
7 to 5
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
ROVF
0
R/W* Receive FIFO Overflow Interrupt 0: Receive FIFO has not overflowed 1: Receive FIFO has overflowed The packets already received are retained, but the packet that caused overflow is discarded.
3 to 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
TSTO
0
R/W* Time Stamp Counter Overflow Interrupt 0: Time stamp counter has not cycled once after receiving the last packet. 1: Time stamp counter has cycled once after receiving the last packet.
Note:
*
Write 1 to clear the bit.
Rev. 1.00 Oct. 01, 2007 Page 1008 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
25.3.4
Interrupt Enable Registers 0, 1 (STIIER0, STIIER1)
STIIER enables or disables the STIF interrupts.
Bit:
31
30
29
28
TPNE 0 R/W
27
26
25
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R 0
TSTOE
15
14
13
12
RPNE 0 R/W
11
10
9
8
7
6
5
4
ROVFE
3
2
1
-
Initial value: R/W: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
SHO LONGE RTE
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Initial Bit Name Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 29
28
TPNE
0
R/W
Transmit Packet Count Interrupt Enable 0: Transmit packet count interrupt is disabled 1: Transmit packet count interrupt is enabled
27 to 13
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
12
RPNE
0
R/W
Receive Packet Count Interrupt Enable 0: Receive packet count interrupt is disabled 1: Receive packet count interrupt is enabled
11, 10
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9
LONGE
0
R/W
Long Packet Reception Interrupt Enable 0: Long packet reception interrupt is disabled 1: Long packet reception interrupt is enabled
8
SHORTE 0
R/W
Short Packet Reception Interrupt Enable 0: Short packet reception interrupt is disabled 1: Short packet reception interrupt is enabled
Rev. 1.00 Oct. 01, 2007 Page 1009 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
Bit 7 to 5
Initial Bit Name Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
4
ROVFE
0
R/W
Receive FIFO Overflow Interrupt Enable 0: Receive FIFO overflow interrupt is disabled 1: Receive FIFO overflow interrupt is enabled
3 to 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
TSTOE
0
R/W
Time Stamp Counter Overflow Interrupt Enable 0: Time stamp counter overflow interrupt is disabled 1: Time stamp counter overflow interrupt is enabled
Rev. 1.00 Oct. 01, 2007 Page 1010 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
25.3.5
Time Stamp Counter Registers 0, 1 (STITSC0, STITSC1)
STITSC is used to count the time stamp.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS[31:16] Initial value: R/W: Bit: 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0
TS[15:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit
Bit Name
Initial Value All 0
R/W R/W
Description Time Stamp Counter * When time stamp is used At reception: Starts counting from reception of the first packet. Counting can be started from any desired value by setting the value before reception. However, this register cannot be written to during reception of a packet. At transmission: Starts counting from transmission of the first packet. Counting can be started from any desired value by setting the value before transmission. However, this register cannot be written to during transmission of a packet. * When fixed value is used At reception: This register value is added to the front of a packet as a fixed value.
31 to 0 TS[31:0]
Rev. 1.00 Oct. 01, 2007 Page 1011 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
25.3.6
Transmit/Receive Packet Count Registers 0, 1 (STIPNR0, STIPNR1)
STIPNR sets the number of packets of the stream data to be transmitted or received.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
PN[20:16]
17
16
-
Initial value: R/W: Bit: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R 0 R/W 0 R/W
0 R/W
0 R/W
0 R/W 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PN[15:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit
Initial Bit Name Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 21
20 to 0
PN[20:0]
All 0
R/W
Number of Transmit/Receive Packets These bits set the number of packets for transmission or reception. An interrupt occurs when the number of packets actually transmitted or received has reached the value set in these bits. An interrupt does not occur when 0 is set in these bits.
Rev. 1.00 Oct. 01, 2007 Page 1012 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
25.3.7
Transmit/Receive Packet Counter Registers 0, 1 (STIPCR0, STIPCR1)
The number of packets of stream data that have been transmitted or received is set in STIPCR. At reception, the number of packets in this register is incremented after the last byte in the packet has been transferred to memory. At transmission, the number of packets is incremented after the last data in the packet has been sent from the ST_D7 to ST_D0 pins. In addition, the numbers of short packets and long packets that have been received are also set in this register.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
PC[20:16]
17
16
SC[3:0] Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R
LC[3:0] 0 R 0 R 0 R
-
0 R
-
0 R
-
0 R 0 R 0 R
0 R
0 R
0 R 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PC[15:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit
Initial Bit Name Value All 0 All 0 All 0
R/W R R R
Description Number of Received Short Packets Cleared to 0 at a reset. Number of Received Long Packets Cleared to 0 at a reset. Reserved These bits are always read as 0. The write value should always be 0.
31 to 28 SC[3:0] 27 to 24 LC[3:0] 23 to 21
20 to 0
PC[20:0]
All 0
R
Number of Transmitted/Received Packets Cleared to 0 when a transmit packet count interrupt or receive packet count interrupt occurs, or at a reset.
Rev. 1.00 Oct. 01, 2007 Page 1013 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
25.3.8
Transmit/Receive FIFO Data Registers 0, 1 (STIFIFO0, STIFIFO1)
STIFIFO is an FIFO register that relays the stream data to be transmitted or received.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STD[31:16] Initial value: R/W: Bit: 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0
STD[15:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit
Bit Name
Initial Value All 0
R/W R/W
Description Transmit/Receive Stream Data At transmission, transmit data should be written to this register. At reception, received data is read from this register.
31 to 0 STD[31:0]
Rev. 1.00 Oct. 01, 2007 Page 1014 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
25.3.9
Operation
25.3.10 External Memory Configuration for Stream Data Transmission/Reception Figure 25.2 shows the external memory data configuration when transmitting or receiving stream data (in the case of a 16-byte work area). The work area size can be selected from among 0, 16, 32, and 48 bytes by the WORK bits in STIMDR. If addition of time stamp or fixed value is selected and the data length is 192 bytes, the first four bytes of the received data will be overwritten.
0 16 20 0 16 20 0 16
Work area TS or fixed value
Work area TS or fixed value
Work area
Data 188 bytes
Data 188 bytes
Data 192 bytes
208 Work area 2
208
Work area 2
208
Work area 2
(1) Data length = 188 bytes Time stamp (TS) or fixed value added
(2) Data length = 192 bytes Time stamp (TS) or fixed value added
(3) Data length = 192 bytes Time stamp (TS) or fixed value added
Figure 25.2 Transmit/Receive Data Structure in External Memory (with 16-Byte Work Area)
Rev. 1.00 Oct. 01, 2007 Page 1015 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
25.3.11 Stream Data Receive Operation (1) DMAC Register Setting
When starting the stream data receive processing, set the following DMAC registers. * Set the P4 area address for the data register of the transmit/receive FIFO of the STIF in SAR. * Set the external memory address in DAR. * Set the DMA transfer count in TCR according to the following equation. Only the value calculated below should be set.
Transfer count = (192 bytes + work area byte count)/16 bytes x transmit/receive packet count
* Set H'0001 0001 in TCRB. The upper bits indicate the transfer count until reloading is performed, and the lower bits indicate the transfer counter value. * Set H'0E20 5819 in CHCR.* * Set the module ID and register ID (H'D3 when STIF channel 0 is used and H'D7 when STIF channel 1 is used) of the transfer request source in the DMARS bits corresponding to the DMAC channel used. Note: * When STIF is not used, do not set CHCR.DVMD bit to 1.
Rev. 1.00 Oct. 01, 2007 Page 1016 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
(2) (a)
Clock Valid Reception (Input Data Rate: Max. 30 Mbps) Clock Valid Reception Interface
* Timing chart Figure 25.3 shows the timing of the clock valid reception interface.
ST_CLK (input/output) ST_START (input) ST_VALID (input) ST_REQ (input) ST_D7 to ST_D0 (input/output)
Up to 8 bytes be received
Figure 25.3 Clock Valid Reception Timing * I/O selection for ST_CLK pin For the ST_CLK pin, input of an external clock or output of an internally generated clock can be selected by the CKSL bit in STIMDR (maximum frequency is 33 MHz). * Active level setting for ST_START, ST_VALID, and ST_REQ pins The active levels of the ST_START, ST_VALID, and ST_REQ pins can be set by the STAT, VLD, and REQ bits in STIMDR, respectively. * Selection of ST_REQ pin usage Whether or not to use the ST_REQ pin can be selected by the REQEN bit in STIMDR. When usage of the ST_REQ pin is enabled, the ST_REQ pin is asserted when the free space in the transmit/receive FIFO for stream data becomes eight bytes or less. After assertion, up to eight bytes of data can be received. The ST_REQ pin is negated when the free space in the FIFO has become 192 bytes or more. When usage of the ST_REQ pin is disabled, the ST_REQ pin output is fixed at low or high depending on the REQ bit value.
Rev. 1.00 Oct. 01, 2007 Page 1017 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
(b)
Receive Packet Length
The receive packet length can be selected from 188 and 192 bytes. (c) Work Area
The size of the work area in external memory can be selected from among 0, 16, 32, and 48 bytes. (d) Time Stamp Setting at Reception
The time stamp setting at reception can be selected from among reception with a fixed value added, reception with a time stamp added, or reception without changes, according to the STMP[1:0] bits in STIMDR. * Reception with a fixed value added The value set in the time stamp counter is used as the fixed value (counting is not performed). When the packet length is 188 bytes, a 4-byte fixed value is added to the front of the packet. When the packet length is 192 bytes, the first four bytes of the packet are overwritten with the fixed value. * Reception with a time stamp added When the packet length is 188 bytes, the time stamp counter value is added to the front of the packet. When the packet length is 192 bytes, data at the beginning of the packet is overwritten with the time stamp counter value. The time stamp counter starts counting from reception of the first packet. Counting can be started from any desired value by setting the value before reception. Writing to the counter during reception of a packet is prohibited. * Reception without changes This selection is possible only when the packet length is 192 bytes. In this case, the received packet is transferred to memory without any changes. (e) Interrupt Sources during Reception
During clock valid reception, the following interrupt sources are available. * * * * * Receive packet count interrupt Short packet reception interrupt Long packet reception interrupt Receive FIFO overflow interrupt Time stamp counter overflow interrupt (only at reception with a time stamp added)
Rev. 1.00 Oct. 01, 2007 Page 1018 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
(3) (a)
Strobe Reception Strobe Reception Interface
* Timing chart Figure 25.4 shows the timing of the strobe reception interface.
ST_STRB (input) ST_START (input) ST_VALID (input) ST_REQ (output)
ST_D7 to ST_D0 (input) Up to 8 bytes can be received
don't care don't care
Figure 25.4 Strobe Reception Timing * Active level setting for ST_STRB, ST_START, ST_VALID, and ST_REQ pins The active levels of the ST_STRB, ST_START, ST_VALID, and ST_REQ pins can be set by the STRB, STAT, VLD, and REQ bits in STIMDR, respectively. * Selection of ST_REQ pin usage Whether or not to use the ST_REQ pin can be selected by the REQEN bit in STIMDR. When usage of the ST_REQ pin is enabled, the ST_REQ pin is asserted when the free space in the transmit/receive FIFO for stream data becomes eight bytes or less. After assertion, up to eight bytes of data can be received. The ST_REQ pin is negated when the free space in the FIFO has become 192 bytes or more. When usage of the ST_REQ pin is disabled, the ST_REQ pin output is fixed at low or high depending on the REQ bit value. (b) Receive Packet Length
The receive packet length can be selected from 188 and 192 bytes. (c) Work Area
The size of the work area in external memory can be selected from among 0, 16, 32, and 48 bytes.
Rev. 1.00 Oct. 01, 2007 Page 1019 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
(d)
Time Stamp Setting at Reception
For the time stamp setting at strobe reception, only reception with a fixed value added can be selected. Set the STMP[1:0] bits in STIMDR to 00. * Reception with a fixed value added The value set in the time stamp counter is used as the fixed value. Counting is not performed. When the packet length is 188 bytes, a 4-byte fixed value is added to the front of the packet. When the packet length is 192 bytes, the first four bytes of the packet are overwritten with the fixed value. (e) Interrupt Sources during Reception
During strobe reception, the following interrupt sources are available. * Receive packet count interrupt * Receive FIFO overflow interrupt 25.3.12 Stream Data Transmit Operation (1) DMAC Register Setting
When starting the stream data transmit processing, set the following DMAC registers. * Set the external memory address in SAR. * Set the P4 area address for the data register of the transmit/receive FIFO of the STIF in DAR. * Set the DMA transfer count in TCR according to the following equation. Only the value calculated below should be set.
Transfer count = (192 bytes + work area byte count)/16 bytes x transmit/receive packet count
* Set H'0001 0001 in TCRB. The upper bits indicate the transfer count until reloading is performed, and the lower bits indicate the transfer counter value. * Set H'0E20 5819 in CHCR.* * Set the module ID and register ID (H'D3 when STIF channel 0 is used and H'D7 when STIF channel 1 is used) of the transfer request source in the DMARS bits corresponding to the used DMAC channel. Note: * Besides a purpose to use STIF, do not set CHCR.DVMD bit to 1.
Rev. 1.00 Oct. 01, 2007 Page 1020 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
(2) (a)
Clock Valid Transmission Clock Valid Transmission Interface
* Timing chart Figure 25.5 shows the timing of the clock valid transmission interface.
ST_CLK (input/output) ST_START (output) ST_VALID (output) ST_REQ (input) ST_D7 to ST_D0 (output)
Figure 25.5 Clock Valid Transmission Timing * I/O selection for ST_CLK pin For the ST_CLK pin, input of an external clock or output of an internally generated clock can be selected by the CKSL bit in STIMDR (maximum frequency is 33 MHz). * Active level setting for ST_START, ST_VALID, and ST_REQ pins The active levels of the ST_START, ST_VALID, and ST_REQ pins can be set by the STAT, VLD, and REQ bits in STIMDR, respectively. * Selection of ST_REQ pin usage Whether or not to use the ST_REQ pin can be selected by the REQEN bit in STIMDR. When usage of the ST_REQ pin is enabled, the ST_VALID pin is negated within four bytes after assertion of the ST_REQ pin. When usage of the ST_REQ pin is disabled, the ST_VALID pin is not negated until 188 or 192 bytes have been transferred. (b) Transmit Packet Length
The transmit packet length can be selected from 188 and 192 bytes. Since the packet length is handled as 192 bytes in external memory, the first four bytes of a packet are removed before transmission when the transmit packet length is set to 188 bytes. When the transmit packet length is set to 192 bytes, external memory data is transmitted without changes.
Rev. 1.00 Oct. 01, 2007 Page 1021 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
(c)
Work Area
The size of the work area in external memory can be selected from among 0, 16, 32, and 48 bytes. (d) Transmit Packet Interval Setting at Transmission
The transmit packet interval setting at transmission can be selected from fixed-interval transmission or time-stamp transmission, according to the STMP[1:0] bits in STIMDR. * Fixed-interval transmission Transmission is performed using the value set in the ICYC[11:0] bits in STICR as the packet interval. 1 to 4096 cycles of peripheral clock 0 can be set. * Time-stamp transmission Transmission is performed with time stamp-based packet intervals. The time stamp counter starts counting from transmission of the first packet. Counting can be started from any desired value by setting the value before transmission. Note that writing to the counter during transmission of a packet is prohibited. (e) Interrupt Source during Transmission
During clock valid transmission, the following interrupt source is available. * Transmit packet count interrupt
Rev. 1.00 Oct. 01, 2007 Page 1022 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
(3) (a)
Strobe Transmission Strobe Transmission Interface
* Timing chart Figure 25.6 shows the timing of the strobe transmission interface. Data is updated simultaneously with the falling edge of the ST_STRB pin.
ST_STRB (output) ST_START (output) ST_VALID (output) ST_REQ (input) ST_D7 to ST_D0 (output)
Figure 25.6 Strobe Transmission Timing * Active level setting for ST_STRB, ST_START, ST_VALID, and ST_REQ pins The active levels of the ST_STRB, ST_START, ST_VALID, and ST_REQ pins can be set by the STRB, STAT, VLD, and REQ bits in STIMDR, respectively. * Selection of ST_REQ pin usage When strobe transmission is selected, the ST_REQ pin always functions as an input pin regardless of the REQEN bit setting in STIMDR. (b) Transmit Packet Length
The transmit packet length can be selected from 188 and 192 bytes. Since the packet length is handled as 192 bytes in external memory, the first four bytes of a packet are removed before transmission when the transmit packet length is set to 188 bytes. When the transmit packet length is set to 192 bytes, external memory data is transmitted without changes. (c) Work Area
The size of the work area in external memory can be selected from among 0, 16, 32, and 48 bytes.
Rev. 1.00 Oct. 01, 2007 Page 1023 of 1956 REJ09B0256-0100
Section 25 Stream Interface (STIF)
(d)
Transmit Packet Interval Setting at Transmission
For the transmit packet interval setting at strobe transmission, only fixed-interval transmission can be selected. Set the STMP[1:0] bits in STIMDR to 00. * Fixed-interval transmission Transmission is performed using the value set in the ICYC[11:0] bits in STICR as the packet interval. Cycles of half the frequency of peripheral clock 0 are counted, and 1 to 4096 cycles can be set. (e) Interrupt Source during Transmission
During strobe transmission, the following interrupt source is available. * Transmit packet count interrupt
Rev. 1.00 Oct. 01, 2007 Page 1024 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
Section 26 I2C Bus Interface (IIC)
26.1 Features
The I2C bus interface has the following features: * * * * * * Supports the Philips I2C bus interface Multi-master compatible Seven- or ten-bit address compatible master Seven-bit slave address Fast mode compatible Variable clock frequencies
Figure 26.1 shows a block diagram for the I2C bus interface.
IIC_SCL Clock Generator
IIC_SCL Clock Filter Master
IIC_SDA IIC_SDA Data Filter Slave
Tx Data
IO Bus
Control/Status Register Rx Data
Figure 26.1 Block Diagram for I2C Bus Interface
Rev. 1.00 Oct. 01, 2007 Page 1025 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
26.2
Input/Output Pins
Table 26.1 lists the pins used in the I2C bus interface. Table 26.1 Pin Configuration
Channel 0 Pin Name IIC0_SCL IIC0_SDA 1 Note: * IIC1_SCL IIC1_SDA I/O I/O I/O I/O I/O Description I2C serial clock input/output pin* I2C serial data input/output pin* I2C serial clock input/output pin* I2C serial data input/output pin*
The SCL and SDA pins are open drain pins (3.3 V).
26.3
Register Descriptions
Table 26.2 shows the IIC register configuration. Table 26.3 shows the register state in each operating mode. Table 26.2 Register Configuration
Channel Register Name 0 Slave control register 0 Master control register 0 Slave status register 0 Master status register 0 Slave interrupt enable register 0 Master interrupt enable register 0 Clock control register 0 Slave address register 0
Abbreviation R/W
Area P4 Address*1
Area 7 Address*1
Access Size
ICSCR0 ICMCR0 ICSSR0 ICMSR0 ICSIER0 ICMIER0 ICCCR0 ICSAR0
R/W R/W
2
H'FFE7 0000 H'1FF7 0000 8 H'FFE7 0004 H'1FF7 0004 8
R/(W)* H'FFE7 0008 H'1FF7 0008 8 R/(W)*3 H'FFE7 000C H'1FF7 000C 8 R/W R/W R/W R/W R/W R/W R/W H'FFE7 0010 H'1FF7 0010 8 H'FFE7 0014 H'1FF7 0014 8 H'FFE7 0018 H'1FF7 0018 8 H'FFE7 001C H'1FF7 001C 8 H'FFE7 0020 H'1FF7 0020 8 H'FFE7 0024 H'1FF7 0024 8 H'FFE7 0024 H'1FF7 0024 8
Master address register 0 ICMAR0 Receive data register 0 Transmit data register 0 ICRXD0 ICTXD0
Rev. 1.00 Oct. 01, 2007 Page 1026 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
Channel Register Name 1 Slave control register 1 Master control register 1 Slave status register 1 Master status register 1 Slave interrupt enable register 1 Master interrupt enable register 1 Clock control register 1 Slave address register 1
Abbreviation R/W
Area P4 Address*1
Area 7 Address*1
Access Size
ICSCR1 ICMCR1 ICSSR1 ICMSR1 ICSIER1 ICMIER1 ICCCR1 ICSAR1
R/W R/W
2
H'FFE7 8000 H'1FF7 8000 8 H'FFE7 8004 H'1FF7 8004 8
R/(W)* H'FFE7 8008 H'1FF7 8008 8 R/(W)*3 H'FFE7 800C H'1FF7 800C 8 R/W R/W R/W R/W R/W R/W R/W H'FFE7 8010 H'1FF7 8010 8 H'FFE7 8014 H'1FF7 8014 8 H'FFE7 8018 H'1FF7 8018 8 H'FFE7 801C H'1FF7 801C 8 H'FFE7 8020 H'1FF7 8020 8 H'FFE7 8024 H'1FF7 8024 8 H'FFE7 8024 H'1FF7 8024 8
Master address register 1 ICMAR1 Receive data register 1 Transmit data register 1 ICRXD1 ICTXD1
Notes: 1. P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB. 2. Only 0 can be written to bits 4 to 0 to clear the flags. 3. Only 0 can be written to bits 6 to 0 to clear the flags.
Rev. 1.00 Oct. 01, 2007 Page 1027 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
Table 26.3 Register State in Each Operating Mode
Channel Register Name 0 Slave control register 0 Master control register 0 Slave status register 0 Master status register 0
Slave interrupt enable register 0 Power-On Manual Abbreviation Reset Reset Sleep
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
ICSCR0 ICMCR0 ICSSR0 ICMSR0 ICSIER0 ICMIER0 ICCCR0 ICSAR0 ICMAR0 ICRXD0 ICTXD0 ICSCR1 ICMCR1 ICSSR1 ICMSR1 ICSIER1 ICMIER1 ICCCR1 ICSAR1 ICMAR1 ICRXD1 ICTXD1
H'00 H'x0 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'x0 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00
H'00 H'x0 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'x0 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Master interrupt enable register 0 Clock control register 0 Slave address register 0 Master address register 0 Receive data register 0 Transmit data register 0 1 Slave control register 1 Master control register 1 Slave status register 1 Master status register 1
Slave interrupt enable register 1
Master interrupt enable register 1 Clock control register 1 Slave address register 1 Master address register 1 Receive data register 1 Transmit data register 1
Rev. 1.00 Oct. 01, 2007 Page 1028 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
26.3.1
Slave Control Register (ICSCR)
Bit:
-
0 R
7
-
0 R
6
-
0 R
5
-
0 R
4
3
SDBS
2
SIE
1
GCAE
0
FNA
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 to 4 3
Bit Name -- SDBS
Initial Value All 0 0
R/W R R/W
Description Reserved The write value should always be 0. Slave Data Buffer Select This bit is used to select the data buffer. The double-buffer mode and single-buffer mode are available. When this bit is set to 0, the double-buffer mode is selected. During a reception, as long as both buffers are full and the SDR flag has not been cleared, SCL is held low. When the SDR flag is cleared, the low level state of SCL is released. When this bit is set to 1, the single-buffer mode is selected. SCL will be held low from the timing when the receive data register acquires the data packet until the SDR flag is cleared. 0: Double-buffer mode 1: Single-buffer mode
2
SIE
0
R/W
Slave Interface Enable This bit must be set for the slave operation. If this bit is low, the slave interface is reset. This bit is cleared by setting the MIE bit to 1.
1
GCAE
0
R/W
General Call Acknowledgement Enable When a master requires a slave to issue an acknowledgement, this bit must be set to 1
Rev. 1.00 Oct. 01, 2007 Page 1029 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
Bit 0
Bit Name FNA
Initial Value 0
R/W R/W
Description Forced Non Acknowledgement In the slave receive mode, the level of this bit is sent to the transmitting device as the acknowledge signal. This bit is set to 0 during the period that the data packet is being received, and set to 1 on completion of data reception. Forced non acknowledgement is returned to the master during slave reception. When the slave has received the last byte of data in a data packet, the slave communicates with the master by sending a nack, meaning that the acknowledgement is not driven. The master issues a stop on the bus after receiving a nack. The setting of this bit does not affect the acknowledgement of the slave address.
Rev. 1.00 Oct. 01, 2007 Page 1030 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
26.3.2
Slave Status Register (ICSSR)
The status bits (bits 0 to 4) in the slave status register are cleared by writing 0 to the respective status bit positions. The individual bits are held 1 until 0 is written to (other than the GCAR and STM bits).
Bit: 7 6
GCAR
5
STM
4
SSR
3
SDE
2
SDT
1
SDR
0
SAR
-
Initial value: R/W:
0 R
0 R
0 R
0 0 0 0 0 R/W* R/W* R/W* R/W* R/W*
Bit 7 6
Bit Name -- GCAR
Initial Value 0 0
R/W R R
Description Reserved The write value should always be 0. General Call Address Received Indicates that the address received from the bus is a general call address (00H). This status bit does not cause an interrupt. This bit is automatically cleared by hardware when the SIE bit (bit 2 in the slave control register) is set to 0 or when the SSR bit (bit 4 in this register) is set to 1.
5
STM
0
R
Slave Transmit Mode Indicates whether the current slave transmit mode is read or write. When this bit is set to 1, the mode is read. When this bit is set to 0, the mode is write. This status bit does not cause an interrupt. This bit is automatically cleared by hardware when the SIE bit (bit 2 in the slave control register) is set to 0 or when the SSR bit (bit 4 in the slave status register) is set to 1.
Rev. 1.00 Oct. 01, 2007 Page 1031 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
Bit 4
Bit Name SSR
Initial Value 0
R/W R/W*
Description Slave Stop Received A stop condition has been output on the bus. This status bit becomes active after the rising edge of SDA during the stop bit.
3
SDE
0
R/W*
Slave Data Empty Indicates that data to be transmitted has been loaded into the shift register. At the start of byte data transmission, the contents of the ICTXD register are loaded into a shift register ready for outputting data on the bus. This status bit indicates that data has been loaded and the ICTXD register is again ready for further data. This status bit becomes active on the falling edge of SCL before the first data bit. During the single-buffer mode, this bit must be reset every time new data has been written to the ICTXD register. This is because the slave holds SCL low to stop the bus while this bit is set to 1 even if a slave transmission cycle is started.
2
SDT
0
R/W*
Slave Data Transmitted A byte of data has been transmitted to the bus. This bit becomes active after the falling edge of SCL during the last data bit.
1
SDR
0
R/W*
Slave Data Received A byte of data has been received from the bus and is ready for read in the receive data register. This bit becomes active after the falling edge of SCL during the last data bit. During the single-buffer mode, this bit must be reset after data has been read from the ICRXD register. When SDBS is set to 1, SCL will be held low from the timing when the receive data register acquires the data packet until the SDR flag is cleared.
Rev. 1.00 Oct. 01, 2007 Page 1032 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
Bit 0
Bit Name SAR
Initial Value 0
R/W R/W*
Description Slave Address Received Indicates that the slave has recognized its own address on the bus (defined by the contents of the slave address register). If the general call acknowledgement enable bit is enabled in the slave control register, then this status bit is also set to 1 even if the address on the bus is a general call address. In this case, the GCAR bit in this register is used to determine whether or not the address is a general call address. The STM bit indicates whether the access is read (high) or write (low). This status becomes active after the falling edge of SCL during the last address bit. The slave holds SCL low during the start of the ACK phase until the software resets this status bit.
Note:
*
This bit can be read from or written to. Writing 0 clears this bit to 0 and writing 1 is ignored.
Rev. 1.00 Oct. 01, 2007 Page 1033 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
26.3.3
Slave Interrupt Enable Register (ICSIER)
BIt: 7
-
6
- 0 R
5
- 0 R
4
SSRE
3
SDEE
2
SDTE
1
SDRE
0
SARE
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 to 5 4
Bit Name -- SSRE
Initial Value All 0 0
R/W R R/W
Description Reserved The write value should always be 0. Slave Stop Received Interrupt Enable 0: Disables the SSR interrupt. 1: Enables the SSR interrupt.
3
SDEE
0
R/W
Slave Data Empty Interrupt Enable 0: Disables the SDE interrupt. 1: Enables the SDE interrupt.
2
SDTE
0
R/W
Slave Data Transmitted Interrupt Enable 0: Disables the SDT interrupt. 1: Enables the SDT interrupt.
1
SDRE
0
R/W
Slave Data Received Interrupt Enable 0: Disables the SDR interrupt. 1: Enables the SDR interrupt.
0
SARE
0
R/W
Slave Address Received Interrupt Enable 0: Disables the SAR interrupt. 1: Enables the SAR interrupt.
Rev. 1.00 Oct. 01, 2007 Page 1034 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
26.3.4
Slave Address Register (ICSAR)
BIt:
7 6 5 4 3
SADDO[6:0]
2
1
0
- Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 to 0
Bit Name -- SADD0[6:0]
Initial Value 0 All 0
R/W R R/W
Description Reserved The write value should always be 0. Slave Address This is the unique 7-bit address allocated to the 2 slave on the I C bus. The slave interface compares this address with the first seven bits transmitted as the slave address, at the beginning of a data packet transmission.
Rev. 1.00 Oct. 01, 2007 Page 1035 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
26.3.5
Master Control Register (ICMCR)
BIt:
7
MDBS
6
FSCL
5
FSDA
4
OBPC
3
MIE
2
TSBE
1
FSB
0
ESG
Initial value: R/W:
0 R
- R/W
- R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name MDBS
Initial Value 0
R/W R/W
Description Master Data Buffer Select This bit is used to select the data buffer. The double-buffer mode and singe-buffer mode are available. When this bit is set to 0, the double-buffer mode is selected. During a reception, as long as both buffers are full and the MDR flag has not been cleared, SCL is held low. When the MDR flag is cleared, the low level state of SCL is released. When this bit is set to 1, the single-buffer mode is selected. SCL will be held low from the timing when the receive data register acquires the data packet until the MDR flag is cleared. 0: Double-buffer mode 1: Single-buffer mode
6
FSCL
--
R/W
Forced SCL This bit controls the status of the I2C_SCL pin (reading reflects the current level on the I2C bus). When the OBPC bit is set, this bit directly controls the SCL line on the bus. During a read cycle, the level on this bit (which includes the reset level) will change depending on the level on I2C_SCL since it reflects the level on the I2C_SCL.
5
FSDA
--
R/W
Forced SDA This bit controls the status of the I2C_SDA pin (reading reflects the busy status level on the I2C_SDA). When the OBPC bit is set then this bit directly controls the SDA line on the bus. During a read cycle, the level of this bit (which includes the reset level) will show the busy 2 status of the I C bus (1 for busy; 0 for not busy).
Rev. 1.00 Oct. 01, 2007 Page 1036 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
Bit 4
Bit Name OBPC
Initial Value 0
R/W R/W
Description Override Bus Pin Control When this bit is set to 1, the FSDA and FSCL bits in this register control SDA and SCL directly. This mode is used for testing purposes only.
3
MIE
0
R/W
Master Interface Enable When this bit is set to 1, the master interface is enabled.
2
TSBE
0
R/W
Start Byte Transmission Enable When this bit is set to 1, the master transmit is issuing a start byte (01H) on the bus after. The start byte is used for interfacing to slower 2 microcontroller compatible with I C bus interfaces.
1
FSB
0
R/W
Forced Stop onto the Bus When this bit is set to 1, the master transmits a STOP condition on the bus at the end of the current transfer. If ESG is also set, the master immediately transmits a START condition and begins transmitting a new data packet. If ESG is not set, state the master enters the idle state.
0
ESG
0
R/W
Enable Start Generation When this bit is set to 1, the master starts transmission of a data packet. If the bus is idle when ESG is set, the master transmits a START condition on the bus and then transmits the slave address. If the master is transferring data when ESG is set, at the end of that data byte transfer, the master transmits a repeated START condition before transmitting the slave address. When transmitting a data packet, the software must reset this bit when the slave address has been transmitted, otherwise a repeated START condition is transmitted after every transmission is completed.
Rev. 1.00 Oct. 01, 2007 Page 1037 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
26.3.6
Master Status Register (ICMSR)
The status bits (bits 0 to 6) in the master status register are cleared by writing 0 to the respective status bit positions. The individual status bits are held 1 until a reset by writing 0 to the appropriate bit position.
BIt:
7
-
6
MNR
5
MAL
4
MST
3
MDE
2
MDT
1
MDR
0
MAT
Initial value: R/W:
0 R
0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit 7 6
Bit Name -- MNR
Initial Value 0 0
R/W R R/W*
Description Reserved The write value should always be 0. Master Nack Received When this bit is set to 1, this bit indicates that the master has received a nack response (the SDA line is high during the acknowledge cycle on the bus) to either an address or data transmission.
5
MAL
0
R/W*
Master Arbitration Lost In a multi-master system, when this bit is set to 1, it indicates that the master has lost arbitration to one of other masters on the bus. At this point, MIE is reset and the master interface is disabled.
4
MST
0
R/W*
Master Stop Transmitted When this bit is set to 1, it indicates that the master has sent a STOP condition on the bus. A STOP condition can be sent either as a result of the setting of the forced stop bit in the control register, or from a nack being received from a slave during a slave receive data packet.
Rev. 1.00 Oct. 01, 2007 Page 1038 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
Bit 3
Bit Name MDE
Initial Value 0
R/W R/W*
Description Master Data Empty At the start of a byte data byte transmission, the contents of the transmit data register are loaded into a shift register ready for transmitting on the bus. When this bit is set to 1, it indicates that the transmit data register is available for further data by setting this register. During master transmit mode, the MDE bit is set at the same timing as the MAT bit is also set after transmission of the slave address. In this case, you need to set the MDT and MAT bits after the ICMCR's ESG bit is cleared. The clearing will restart the data transmission.
2
MDT
0
R/W*
Master Data Transmitted Byte data has been sent to the slave on the bus. This status bit becomes active after the falling edge of SCL during the last data bit.
1
MDR
0
R/W*
Master Data Received Byte data has been received from the bus and is in the receive data register. This status bit becomes active after the falling edge of SCL during the last data bit. During single-buffer mode, this status bit must be reset after data has been read from the receive data register. When MDBS is set to 1, SCL will be held low from the timing when the receive data register acquires the data packet until the MDR flag is cleared. During master reception mode, the MDR bit is set at the same timing as the MAT bit set after transmission of the salve address. In this case, you must clear the MDR and MAT bits after the ICMCR's ESG bit is cleared. Clearing will start the data reception
0
MAT
0
R/W*
Master Address Transmitted The master has been transmitted the slave address byte of a data packet. This bit becomes active after the falling edge of SCL during the ack bit of after the address.
Note:
*
This bit can be read from or written to. Writing 0 clears this bit to 0 and writing 1 is ignored.
Rev. 1.00 Oct. 01, 2007 Page 1039 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
26.3.7
Master Interrupt Enable Register (ICMIER)
BIt: 7
-
6
MNRE
5
MALE
4
MSTE
3
2
1
0
MATE
MDEE MDTE MDRE
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6
Bit Name -- MNRE
Initial Value 0 0
R/W R R/W
Description Reserved The write value should always be 0. Master Nack Received Interrupt Enable 0: Disables the MNR interrupt. 1: Enables the MNR interrupt.
5
MALE
0
R/W
Master Arbitration Lost Interrupt Enable 0: Disables the MAL interrupt. 1: Enables the MAL interrupt.
4
MSTE
0
R/W
Master Stop Transmitted Interrupt Enable 0: Disables the MST interrupt. 1: Enables the MST interrupt.
3
MDEE
0
R/W
Master Data Empty Interrupt Enable 0: Disables the MDE interrupt. 1: Enables the MDE interrupt.
2
MDTE
0
R/W
Master Data Transmitted Interrupt Enable 0: Disables the MDT interrupt. 1: Enables the MDT interrupt.
1
MDRE
0
R/W
Master Data Received Interrupt Enable 0: Disables the MDR interrupt. 1: Enables the MDR interrupt.
0
MATE
0
R/W
Master Address Transmitted Interrupt Enable 0: Disables the MAT interrupt. 1: Enables the MAT interrupt.
Rev. 1.00 Oct. 01, 2007 Page 1040 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
26.3.8
Master Address Register (ICMAR)
BIt: 7 6 5 4
SADD1[6:0]
3
2
1
0
STM1
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 to 1
Bit Name
Initial Value
R/W R/W
Description Slave Address These bits are the address of the slave which the master communicates with.
SADD1[6:0] All 0
0
STM1
0
R/W
Slave Transfer Mode This bit specifies the mode in which the slave operates. Bit STM1 sets the operating mode (transmit or receive mode) of the slave, which is an external slave device whose address matches the slave address (SADD1) sent from the master. The slave device is automatically set to transmit/receive mode by hardware on reception of the STM1 signal. When this bit is set to 1, it indicates a read operation, when this bit is cleared to 0, it indicates a write operation.
26.3.9
Clock Control Register (ICCCR)
Bit: 7 6 5 4 3 2 1 0
SCGD[5:0]
CDF[1:0]
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Rev. 1.00 Oct. 01, 2007 Page 1041 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
Bit 7 to 2
Bit Name SCGD
Initial Value All 0
R/W R/W
Description SCL Clock Generation Divider When operating in master mode, the SCL clock is generated from the internal clock using SCGD as the ratio. The slave will also operate on the clock generated from the internal clock when SCL is held low to hold the bus up when an overflow occurs. SCGD must be specified in both master and slave modes. The formula expressing the relationship is: Equation 2 SCL rate calculation SCLfreq = IICck / (20 + (SCGD * 8)) IICck: I C internal clock frequency Suggested settings for CDF and SCGD for 2 various CPU speeds and the two I C bus speeds are given in table 26.4.
2
1, 0
CDF
All 0
R/W
Clock Division Factor The internal clock used in most blocks in the 2 I C module is a divided peripheral clock. The internal I2C clock is generated from the peripheral clock using the CDF as the division ratio: Equation 1 I C internal clock frequency calculation IICck = Pck0 / (1 + CDF) Pck0: Peripheral clock The minimum time to ensure adequate setup and hold times on the SDA line relative to the SCL line on the bus. The clock frequency is to ensure that the glitch filtering will operate with glitches of up to 50 ns 2 as described in the fast mode I C specification.
2
Note: CDF must be set so that the clock frequency (IICck) is lower than 20 MHz.
Rev. 1.00 Oct. 01, 2007 Page 1042 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
Table 26.4 Suggested Settings for CDF and SCGD*
Peripheral Clock Frequency 66.7 MHz Error Note: * 100 kHz CDF 3 - 3.05 % These are suggested values for the SCL rate. SCGD 19 CDF 3 - 5.26 % 400 kHz SCGD 3
26.3.10 Receive and Transmit Data Registers (ICRXD and ICTXD) Reading from or writing to these registers access different physical internal registers. When data is to be transmitted, the contents of the shift register are loaded via TXD. After data has been received into the shift register from the I2C bus, it is then loaded into RXD. * Receive Data Register (ICRXD)
BIt: 7 6 5 4 3 2 1 0
RXD[7:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 7 to 0
Bit Name RXD[7:0]
Initial Value All 0
R/W R
Description Read--Receive Data Data received by master or slave.
* Transmit Data Register (ICTXD)
BIt: 7 6 5 4 3 2 1 0
TXD[7:0]
Initial value: R/W:
0 W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
Bit 7 to 0
Bit Name TXD[7:0]
Initial Value All 0
R/W W
Description Write--Transmit Data Data transmitted by master or slave.
Rev. 1.00 Oct. 01, 2007 Page 1043 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
26.4
26.4.1
Operations
Data and Clock Filters
These blocks filter out glitches on signals coming from the I2C bus. Glitches up to one internal clock period in width are rejected (For details on the internal clock frequency see section 26.3.9, Clock Control Register (ICCCR)). This is for the faster I2C bit rate (400 KHz) but does not violate the slower I2C bus rate specification. These blocks also resynchronizes bus signals with the internal clock. 26.4.2 Clock Generator
The clock generator has two functions. Firstly, it generates the SCL I2C bus clock according to commands from of the master or slave interface. Secondly, it controls the internal clock rate, used by filtering blocks and the master and slave interfaces. This clock functions as a clock enable signal of the registers in these blocks. 26.4.3 Master/Slave Interfaces
These two interfaces run independently and in parallel. The master interface controls the transmission of address and data on the I2C bus. The slave interface monitors the I2C bus and takes part in transmissions if its programmed address is seen on the bus. The interfaces communicate with the control/status registers independently. There is only one interrupt line output from the I2C module. The interrupt source is either the master or the slave. 26.4.4 Software Status Interlocking
In order that the software interface to the I2C module be as robust as possible, various status interlocks are built into the operation of the master and slave interfaces. The status bits involved are: (1) MDR and SDR
MDR and SDR are set to 1 when data is received. Clear the status after reading the receive data register. If data is received while MDR and SDR are set, hardware recognizes that unread data remains in the receive data register and automatically holds SCL at low level and suspends data transmission. In this case, transmission can be resumed by clearing the status after reading the receive data.
Rev. 1.00 Oct. 01, 2007 Page 1044 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
Consequently, when receiving data continuously, be sure to clear the status of MDR and SDR after reading the receive data register. (2) MDE and SDE
If the MDE or SDE status bits are still set data in the transmit data register is to be transmitted on the I2C bus by the slave or master, the SCL line must be held low until the MDE and SDE status bits are reset. The MDE or SDE status bit being set indicates that the data currently held in the Transmit Data Register has already been transmitted on the I2C bus. The software must clear this status bit when it writes to the transmit data register which is ready to transmit subsequent data bytes. This is not required for the first byte of data to be transmitted on the bus. (3) MAL
When the master loses arbitration, the MAL bit (of the master status register) is set and the MIE bit (of the master control register) is reset. At this point, master mode is invalid and the I2C bus interface enters the slave mode. When master operation is restarted, data transfer from the master begins after the MAL bit has been cleared. (4) SAR
The SAR status bit is set when the slave identifies its address on the I2C bus. At this point the slave interface forces the SCL line low until the SAR status bit is reset. This is particularly important when a slave transmit is about to take place on the bus, and the slave will transmit the data from the transmit data register. The software responds to the SAR status by writing the required data into the transmit data register and then resetting the SAR status bit. This allows the slave interface to continue the access. When the slave is about to receive data, the software may be reading data loaded in a previous access from the receive data register. In this case the valid data still held in the receive data register is overwritten. However, this is avoided using the SAR status bit. After the software has read data in the receive data register, reset the SAR bit (if it is set). Then overwriting the receive data register is avoided.
Rev. 1.00 Oct. 01, 2007 Page 1045 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
26.4.5
I2C Bus Data Format
Figure 26.2 shows a timing chart for the I2C bus interface. Table 26.5 describes the meaning of each symbol in figure 26.2.
IIC_SDA
IIC_SCL S
1-7
8
9
ACK
1-7
DATA
8
9
ACK
1-7
DATA
8
9
P
ADDRESS R/W
ACK
Stop condition
Start condition
Figure 26.2 I2C Bus Timing Table 26.5 Description on Symbols of I2C Bus Data Format
Symbol S SLA R/W Description Indicates a start condition. A master device changes SDA from high to low while SCL is high level. Indicates a slave address. A slave address is used when a master device selects a slave device. Indicates the direction of data transmission. If the R/W bit is 1, the data flows from the slave to the master device. If the bit is 0, the data flows from the master to the slave device. Indicates data acknowledge. Data receiving device makes SDA low level (the slave device returns a data acknowledge signal in master transmission mode, and vice versa). Indicates transmit or receive data. The data length is eight bits, which are transferred in the MSB first. Indicates a stop condition. A master device changes SDA from low to high while SCL is high.
A
DATA P
Rev. 1.00 Oct. 01, 2007 Page 1046 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
26.4.6
7-Bit Address Format
Figure 26.3 shows the format of data transfer from a master to a slave device (master data transmit format). Figure 26.4 shows the data transfer format (master data receive format) when a master device reads the second and the following byte data from a slave device.
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A/A
P
Data transferres (n Bytes + ACKNOWLEDGE) 0(Write) : From MASTER to SLAVE : From SLAVE to MASTER A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) S = Strat condition P = Stop condition
Figure 26.3 Master Data Transmit Format
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A/A
P
Data transferred (n Bytes + ACKNOWLEDGE) 1(Read)
Figure 26.4 Master Data Receive Format Figure 26.5 shows the combined format when the data transfer direction changes during one transfer. When changing the direction after the first transfer, the repeated START condition (Sr), slave address and R/W bits are transmitted. In this case, the R/W bit is set to the direction opposite to the first transfer direction. The repeated START condition is issued by the master at the end of a transmit or receive cycle if the enable start generation bit in the master control register has been set.
Rev. 1.00 Oct. 01, 2007 Page 1047 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
S
SLAVE ADDRESS
R/W
A
DATA
A/A
Sr
SLAVE ADDRESS
R/W
A
DATA
A/A
P
Read or Write
(n BYTES + ACK)*
Read or Write Sr = Repeated start condition
(n BYTES + ACK)*
Direction pf transfer may change at this point
Notes: 1. Tramsfer dorection of data and acknowledge bits depends on R/W bits. 2. Repeated START condition: Tramsfer is started whrn the I2C_SDL signal is driven high and the I2C_SDA signal is driven low.
Figure 26.5 Combination Transfer Format of Master Transfer 26.4.7 10-Bit Address Format
Description is given below on the 10-bit address transfer format supported in master mode. This format has three transfer methods as the 7-bit address transfer format. Figure 26.6 shows the data transmit format. The set value in the master address register is output in one byte following the first START condition (S). The value set in the transmit data register (TXD) is transmitted as a slave address in the second byte. Data on and after the third byte is transferred in the same way as the 7-bit address data.
11110XX S SLAVE ADDRESS 1st Byte, 7 Bits
0(Write) R/W
A1
SLAVE ADDRESS
A2
DATA
A
DATA
A/A
P
2nd Byte
Data transferred (n Bytes + ACKNOWLEDGE)
Figure 26.6 10-Bit Address Data Transmit Format Figure 26.7 shows the data receive format. Two bytes of an address is transmitted a repeated START in the same way as in the data transmit format. Then, repeated START condition (Sr) is transmitted and the value set in the address register is output. At this time, STM1 must be set to 1 (receive mode). Data is transferred in the same way as in the 7-bit address data receive format.
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Section 26 I C Bus Interface (IIC)
2
11110XX S SLAVE ADDRESS 1st Byte, 7 Bits 0 (Write) R/W A1 SLAVE ADDRESS 2nd Byte
A2
11110XX
Sr
SLAVE ADDRESS
R/W
A3
DATA
A
DATA
A
P
1st Byte, 7 Bits
1 (read)
Data transferred (n Bytes + ACKNOWLEDGE)
Figure 26.7 10-Bit Address Data Receive Format Figure 26.8 shows the data transmit/receive combined format. In the data transmit/receive combined format, data is transmitted after an address is transmitted with the first two bytes. Then, the repeated START condition (Sr) is transmitted instead of STOP condition (P). After Sr is transmitted, the procedure is the same as that in the data receive format.
11110XX S SLAVE ADDRESS 1st Byte, 7 Bits 0(Write) R/W A1 SLAVE ADDRESS 2nd Byte Data transferred A2 DATA A DATA A/A
11110XX Sr SLAVE ADDRESS 1st Byte, 7 Bits 1(Read) Data transferred R/W A3 DATA A DATA A P
Figure 26.8 10-Bit Address Transmit/Receive Combined Format
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Section 26 I C Bus Interface (IIC)
2
26.4.8
Master Transmit Operation
The transmit procedure and operation in master transmit mode are described below. Figure 26.9 shows the timing chart in master transmit mode. Setting the MDBS bit in the master control register allows the IIC to operate in single-buffer mode. 1. For initial setting, set the clock control register and the master interrupt enable register according to the slave address, transmit data, and the transmit speed. Since slave mode is also required even when master mode is used, set the device address in the slave address register. 2. Monitor the FSDA bit in the master control register. Confirm that this bit is low, meaning that other I2C devices are not using the bus. After confirmation, set the MIE (bit 3) and ESG (bit 0) bits in the master control register to 1 to start master transmission. 3. After the transmit START condition, slave address, and data transfer direction bits are transmitted, an interrupt due to the MAT and MDE bits in the master status register is generated at the timing of (1) in figure 26.9. At this time, clear the ESG bit to 0. To suspend the data transmission, the master device will hold SCL low until the MDE bit is cleared. 4. An interrupt due to the SAR bit is generated at the timing of (3) shown in figure 26.9. If the IRQ handling in the slave device is delayed, the slave device extends the IIC_SCL period to suspend data transmission (at the timing of (7) in figure 26.9). The slave device drives IIC_SDA low at the ninth clock and returns ACK. 5. Data is transmitted in units of nine bits: 8-bit data and 1-bit ACK. An interrupt of MDE (bit 3) is generated at the ninth clock before data transfer (at the timing of (2) in figure 26.9). An interrupt of MDT (bit 2) is generated at the eighth clock after 1-byte data transfer (at the timing of (4) in figure 26.9). Clear MDE to 0 after setting transmit data. An interrupt of SDR (slave data receive) of the slave device is generated at the eighth clock (at the timing of (6) in figure 26.9). Clear SDR after the slave device reads the receive data. If this processing is delayed, the slave device extends the SCL period to suspend data transmit (at the timing of (8) in figure 26.9). 6. To end data transfer, an interrupt of MNR (bit 6) in the master status register is generated at the ninth clock (at the timing of (5) in figure 26.9) when ACK from the slave device is 1 (Nack). The master device receives this Nack and outputs data transfer end condition. When data transmission ends on the master device side, set FSB (bit 1) in the master control register to 1 to output the suspend condition. After the IIC module fetches FSB on completion of transmission or reception of the last of byte data, it enters the stop state. Therefore in order to stop the communication after the predetermined number of byte data is transferred, the FSB bit needs to be set before the last byte data transfer is started. 7. The FSB bit needs to be set before the last byte data is transferred. In master transmit mode, after the last byte data is set, the MST (master stop transmitted) bit is checked by either
Rev. 1.00 Oct. 01, 2007 Page 1050 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
interrupt or polling. At the same time MNR (master NACK received) bit must be checked. If NACK is returned, an error routine is executed to retransmit the last byte data. Signal level changes of (1) to (6) in figure 26.9 are generated after the falling edge of the clock.
IIC_SDA IIC_SCL
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7
1
2
3
4
5
6
7
8
9
1
S
IIC_SDA (MASTER output) IIC_SDA (SLAVE output)
ACK
MASTER IRQ (1) SLAVE IRQ (3) (7)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7
IIC_SDA
IIC_SCL IIC_SDA (Master output) IIC_SDA (Slave output) MASTER IRQ
9
1
2
3
4
5
6
7
8
9
1
ACK
(4) (2) (5) (6) (8)
(2)
SLAVE IRQ
Figure 26.9 Data Transmit Mode Operation Timing
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Section 26 I C Bus Interface (IIC)
2
26.4.9
Master Receive Operation
The data receive procedure and operation in master receive mode are described below. Figure 26.10 shows the timing chart in master receive mode. Setting the MDBS bit in the master control register allows the IIC to operate in single-buffer mode. 1. In master receive mode, as to transmit of a slave address and a 1-bit signal indicating the data transfer direction, operation is the same as that in master transmit mode. At this time, set the data transfer direction to 1 (reception). 2. The slave device automatically enters the data transmit mode according to the signal that indicates the data transfer direction, and transmits 1-byte data in synchronization with the SCL clock output from the master device. The master device generates an interrupt of MDR (bit 1) at the eighth clock (at the timing of (2) in figure 11). Clear the MDR bit after the master device reads receive data. If this processing is delayed, the slave device extends the SCL period to suspend data transmission, as shown at the timing of (3) in figure 26.10. 3. The slave device generates an interrupt of the status SDT (bit 2) indicating 1-byte data transfer end at the eighth clock (at the timing of (2) in figure 26.10) and an interrupt of the status SDE (bit 3) indicating data empty at the ninth clock (at the timing of (1) in figure 26.10). Clear SDE after writing slave transmit data to TXD. 4. To end data transfer, set FSB (bit 1) in the master control register of the master device and output suspend condition. After the IIC module fetches FSB on completion of transmission or reception of the last of byte data, it enters the stop state. . Therefore in order to stop the communication after predetermined number of byte data is transferred, FSB bit needs to be set before the last byte data transfer is started. After confirmation of the last byte data reception, though the master receiver finishes the receive transaction, the protocol layer will inform the slave transmitter or retransmission if the last byte is incorrect. Signal level changes of (1) to (3) in figure 26.10 are generated after the falling edge of the clock.
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Section 26 I C Bus Interface (IIC)
2
IIC_SDA
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
IIC_SCL IIC_SDA (Master output) IIC_SDA (Slave output) Master IRQ
9
1
2
3
4
5
6
7
8
9
1
ACK
Slave IRQ
(1)
(2)
(1)
(3)
Figure 26.10 Data Receive Mode Operation Timing
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Section 26 I C Bus Interface (IIC)
2
26.5
26.5.1
Programming Examples
Master Transmitter
In order to set up the master interface to transmit a data packet on the I2C bus, follow the following procedure: (1) Load Clock Control Register
1. SCL clock generation divider (SCGD) = H'03 (SCL frequency of 400 kHz) 2. Clock division ratio (CDF) = H'3 (The peripheral clock is 66.7 MHz and the IIC's internal clock IICck is 16.7 MHz.) (2) Load Master Control Register (First Data Byte and Address)
1. Master address register = address of slave being accessed and STM1 bit (write mode: 0) 2. Transmit data register = first data byte to be transmitted 3. Master control register = H'89 (MDBS = 1, MIE = 1, ESG = 1) (3) Wait for Outputting Address
1. Wait for master event (an interrupt of the MAT and MDE bits in the master status register). 2. Set the master control register to H'88 (To suspend the data transmission, the master device will hold the SCL low until the MDE bit is cleared.) If only one byte of data is transmitted, set the master control register to H'8A, meaning that the stop generation is enabled. This generates a stop on the bus as soon as one byte has been transmitted. 3. Reset the MAT bit. (4) Monitor Transmission of Data
1. Wait for master event, MDE in the master status register. 2. Transmit data register = subsequent data.
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Section 26 I C Bus Interface (IIC)
2
3. Reset the MDE bit. Clear MDE after setting the last byte to be transmitted. After the last byte data is transmitted, MDE is generated. To clear the MDE, you must set the master control register to H'8A. (Set the force stop control bit). (5) Wait for End of Transmission
1. Wait for the master event, MST in the master status register. 2. Reset the MST bit after confirming MNR (Master NACK Received). 26.5.2 Master Receiver
To set up the master interface to receive a data packet on the I2C bus, follow the following procedure: (1) Load Clock Control Register
1. SCL clock generation divider (SCGD) = H'03 (SCL frequency of 400 kHz). 2. Clock division ratio (CDF) = H'3 (The peripheral clock is 66.7 MHz and the IIC's internal clock IICck is 16.7 MHz.) (2) Load Master Control Register and Address
1. Set master address register to address of slave being accessed and STM1 bit (read mode: 1). 2. Set master control register to H'89 (MDBS = 1, MIE = 1, ESG = 1). (3) Wait for Outputting Address
1. Wait for master event (an interrupt of the MAT and MDR bits in the master status register). 2. Set the master control register to H'88 (To suspend the data transmission, the master device will hold the SCL low until the MDR bit is cleared). If only one byte of data is received, set the master control register to H'8A, meaning that the stop generation is enabled. This generates a stop on the bus as soon as one byte has been received. 3. Reset the MAT bit.
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Section 26 I C Bus Interface (IIC)
2
(4)
Monitor Reception of Data
1. Wait for master event, bit MDR in the master status register. 2. Read data from the received data register. If the next byte of data is the second to last byte to be transmitted by the slave device, the following applies to the receive interrupt (that is, MDR interrupt) in the second to last byte. 3. Set the master control register to H'8A (Set the force stop control bit). 4. Reset the MDR bit. (5) Wait for End of Reception
1. Handle the receive interrupt (MDR) in the last byte: that is, read the data and clear the MDR. 2. Wait for master event, MST in the master status register. 3. Reset the MST bit. 26.5.3 Master Transmitter--Restart--Master Receiver
In order to set up the master interface to transmit a data packet on the I2C bus, issue a restart, then read byte data back from the slave, follow the following procedure: (1) Load Clock Control Register
1. Set the SCL clock generation divider (SCGD) to H'03 (SCL frequency of 400 kHz). 2. Set the clock division (CDF) to H'2 (The peripheral clock is 66.7 MHz and the IIC's internal clock IICck is 16.7 MHz.) (2) Load Master Control Register and Address
1. Set the master address register to address of slave being accessed and STM1 bit (writes mode: 0). 2. Set the master control register to H'89 (MDBS = 1, MIE = 1, ESG = 1). (3) Wait for Outputting Address
1. Wait for master event (an interrupt of the MAT and MDE bits in the master status register).
Rev. 1.00 Oct. 01, 2007 Page 1056 of 1956 REJ09B0256-0100
Section 26 I C Bus Interface (IIC)
2
2. Set the master address register to address of slave being accessed and STM1 bit (read mode: 1). When the enable start generation bit in the master control register is still set, at the end of the byte transmission the master will issue a restart. Since the new address has been loaded above the bus direction will be changed. 3. Reset the MAT bit. (4) Wait for Outputting Address
1. Wait for master event (an interrupt of the MAT and MDR bits in the master status register). 2. Set the master control register to H'88 (To suspend stop the data transmission, the master device will hold the IIC_SCL low until the MDR bit is cleared.) 3. Reset the MAT bit. (5) Monitor of Data
1. Wait for master event, the MDR bit in the master status register. Read data from the received data register. If the next byte of data is the second to last byte but one to be transmitted by the slave device, the following applies to a receive interrupt (that is, MDR interrupt) in the second to last byte 2. Set the master control register to H'8A (set the force stop control bit). 3. Reset the MDR bit. (6) Wait for End of Reception
1. Handle the receive interrupt (MDR) in the last byte: that is, read the data and clear the MDR. 2. Wait for the master event MST in the master status register. 3. Reset the MST bit.
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Section 26 I C Bus Interface (IIC)
2
Rev. 1.00 Oct. 01, 2007 Page 1058 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Section 27 Serial Communication Interface with FIFO (SCIF)
This LSI is equipped with a 2-channel serial communication interface with built-in FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform both asynchronous and clocked synchronous serial communications. 64-stage FIFO buffers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. Channels 0 and 1 of the SCIF have modem control functions (RTS, CTS).
27.1
Features
The SCIF has the following features. * Asynchronous serial communication mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). There is a choice of 8 serial data transfer formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even/odd/none Receive error detection: Parity, framing, and overrun errors Break detection: A break is detected when a framing error lasts for more than 1 frame length at Space 0 (low level). When a framing error occurs, a break can also be detected by reading the SCIFn_RXD (n = 0, 1) pin level directly from the serial port register (SCSPTR). * Clocked synchronous serial communication mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other LSIs that have a synchronous communication function. There is a single serial data communication format. Data length: 8 bits Receive error detection: Overrun errors
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Section 27 Serial Communication Interface with FIFO (SCIF)
* Full-duplex communication capability The transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling continuous serial data transmission and reception. * On-chip baud rate generator allows any bit rate to be selected. * Choice of serial clock source: internal clock from baud rate generator or external clock from SCIF_SCK0 or SCIF_SCK1 pin * Four interrupt sources There are four interrupt sources--transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error--that can issue requests independently. * The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt. * When not in use, the SCIF can be stopped by halting its clock supply to reduce power consumption. * In asynchronous mode, modem control functions (SCIF0_RTS, SCIF1_RTS, SCIF0_CTS, and SCIF1_CTS) are provided. * The amount of data in the transmit/receive FIFO registers, and the number of receive errors in the receive data in the receive FIFO register, can be ascertained. * In asynchronous mode, a timeout error (DR) can be detected during reception. Figure 27.1 shows a block diagram of the SCIF. Figures 27.2 to 27.6 show block diagrams of the I/O ports in SCIF. There are two channels in this LSI. In figures 27.1 to 27.6, the channels are omitted and explained.
Rev. 1.00 Oct. 01, 2007 Page 1060 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Module data bus
SCFRDRn 64-stage
SCFTDRn 64-stage
SCSMRn SCLSRn SCTFDRn
SCBRRn
SCIFn_RXD SCRSRn SCTSRn
SCRFDRn SCFCRn SCFSRn SCSCRn SCSPTRn SCRERn Baud rate generator
Bus interface
SCIFn_TXD Parity generation SCIFn_CLK SCIFn_CTS SCIFn_RTS Parity check
Transmit/receive control
Clock External clock TXIn RXIn ERIn BRIn SCIFn
Note: n = 0, 1 [Legend] SCRSRn: SCFRDRn: SCTSRn: SCFTDRn: SCSMRn: SCSCRn: SCFSRn: Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register Serial status register SCBRRn: SCSPTRn: SCFCRn: SCTFDRn: SCRFDRn: SCLSRn: SCRERn: Bit rate register Serial port register FIFO control register Transmit FIFO data count register Receive FIFO data count register Line status register Serial error register
Figure 27.1 Block Diagram of SCIF
Rev. 1.00 Oct. 01, 2007 Page 1061 of 1956 REJ09B0256-0100
Peripheral bus
Pck0 Pck0/4 Pck0/16 Pck0/64
Section 27 Serial Communication Interface with FIFO (SCIF)
Figures 27.2 to 27.6 show block diagrams of the I/O ports in SCIF.
Reset R D7 Q D RTSIO C SPTRW
SCIFn_RTS Reset R D6 Q D RTSDT C SPTRW
Modem control enable signal*
Peripheral bus
SCIF_RTS signal
SPTRR SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Notes: n = 0, 1 * The SCIFn_RTS pin function is designated as modem control by the MCE bit in SCFCR.
Figure 27.2 SCIFn_RTS Pin (n = 0, 1)
Rev. 1.00 Oct. 01, 2007 Page 1062 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Reset
R D5 Q D CTSIO C
Peripheral bus
SPTRW
SCIFn_CTS
Reset
R D4 Q D CTSDT C
SPTRW
SCIF_CTS signal
Modem control enable signal*
SPTRR
SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Notes: n = 0, 1 * The SCIFn_CTS pin function is designated as modem control by the MCE bit in SCFCR.
Figure 27.3 SCIFn_CTS Pin (n = 0, 1)
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Section 27 Serial Communication Interface with FIFO (SCIF)
Reset R Q D SCKIO C SPTRW SCIFn_CLK Reset D SCKDT C SPTRW Clock output enable signal * Serial clock output signal * Serial clock input signal * Serial input enable signal * Q R D2 D3 Peripheral bus
SPTRR SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Note: * The SCIFn_CLK pin function is designated as internal clock output or external clock input by the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR.
Figure 27.4 SCIFn_SCK Pin (n = 0, 1)
Reset R Q D SPB2IO C SPTRW
SCIFn_TXD Reset R Q D SPB2DT C SPTRW
D1 Peripheral bus
D0
Transmit enable signal
Serial transmit data
SPTRW: Write to SCSPTR
Figure 27.5 SCIFn_TXD Pin (n = 0, 1)
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Section 27 Serial Communication Interface with FIFO (SCIF)
SCIFn_RXD Serial receive data
Peripheral bus SPTRR SPTRR: Read from SCSPTR
Figure 27.6 SCIFn_RXD Pin (n = 0, 1)
27.2
Input/Output Pins
Table 27.1 shows the SCIF pin configuration. Since the pin functions are the same in each channel, the channel number is omitted in the description below. Table 27.1 Pin Configuration
Pin Name SCIFn_SCK (n = 0, 1) SCIFn_RXD (n = 0, 1) SCIFn_TXD (n = 0, 1) SCIFn_CTS (n = 0, 1) SCIFn_RTS (n = 0, 1) Function Serial clock pin Receive data pin Transmit data pin Modem control pin Modem control pin I/O I/O Input Output I/O I/O Description Clock input/output Receive data input Transmit data output Transmission enabled Transmission request
Note: These pins are made to function as serial pins by performing SCIF operation settings with the C/A bit in SCSMR, the TE, RE, CKE1, and CKE0 bits in SCSCR, and the MCE bit in SCFCR. Break state transmission and detection can be set in SCSPTR of the SCIF.
Rev. 1.00 Oct. 01, 2007 Page 1065 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
27.3
Register Descriptions
The SCIF has the following registers. Since the register functions are the same in each channel, the channel number is omitted in the description below. Table 27.2 Register Configuration (1)
Ch. Register Name Abbrev. R/W P4 Address Area 7 Address Size
0
Serial mode register 0 Bit rate register 0 Serial control register 0
Transmit FIFO data register 0
SCSMR0 SCBRR0 SCSCR0
R/W R/W R/W
1
H'FFE0 0000 H'FFE0 0004 H'FFE0 0008 H'FFE0 000C H'FFE0 0010 H'FFE0 0014 H'FFE0 0018 H'FFE0 001C H'FFE0 0020 H'FFE0 0024
2
H'1FE0 0000 H'1FE0 0004 H'1FE0 0008 H'1FE0 000C H'1FE0 0010 H'1FE0 0014 H'1FE0 0018 H'1FE0 001C H'1FE0 0020 H'1FE0 0024 H'1FE0 0028 H'1FE0 002C H'1FE0 8000 H'1FE0 8004 H'1FE0 8008 H'1FE0 800C H'1FE0 8010 H'1FE0 8014 H'1FE0 8018 H'1FE0 801C H'1FE0 8020 H'1FE0 8024 H'1FE0 8028 H'1FE0 802C
16 8 16 8 16 8 16 16 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 16
SCFTDR0 W SCFSR0 R/W*
Serial status register 0
Receive FIFO data register 0 SCFRDR0 R FIFO control register 0
Transmit FIFO data count register 0 Receive FIFO data count register 0
SCFCR0
R/W
SCTFDR0 R SCRFDR0 R SCSPTR0 R/W SCLSR0 SCRER0 SCSMR1 SCBRR1 SCSCR1 R/W* R R/W R/W R/W
1
Serial port register 0 Line status register 0 Serial error register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1
Transmit FIFO data register 1
H'FFE0 0028 H'FFE0 002C H'FFE0 8000 H'FFE0 8004 H'FFE0 8008 H'FFE0 800C H'FFE0 8010 H'FFE0 8014 H'FFE0 8018 H'FFE0 801C H'FFE0 8020 H'FFE0 8024
SCFTDR1 W SCFSR1 R/W*
Serial status register 1
Receive FIFO data register 1 SCFRDR1 R FIFO control register 1
Transmit FIFO data count register 1 Receive FIFO data count register 1
SCFCR1
R/W
SCTFDR1 R SCRFDR1 R SCSPTR1 R/W SCLSR1 SCRER1 R/W* R
2
Serial port register 1 Line status register 1 Serial error register 1
H'FFE0 8028 H'FFE0 802C
Notes: 1. To clear the flags, 0s can only be written to bits 7 to 4, 1, and 0. 2. To clear the flag, 0 can only be written to bit 0.
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Section 27 Serial Communication Interface with FIFO (SCIF)
Table 27.3 Register State in Each Operating Mode
Ch. Register Name 0 Serial mode register 0 Bit rate register 0 Serial control register 0
Transmit FIFO data register 0
Abbrev. SCSMR0 SCBRR0 SCSCR0 SCFTDR0 SCFSR0 SCFRDR0 SCFCR0 SCTFDR0
Power-on Reset H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000 H'0000*1 H'0000 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000 H'0000*2 H'0000 H'0000
Manual Reset H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000 H'0000*1 H'0000 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000 H'0000*2 H'0000 H'0000
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Serial status register 0 Receive FIFO data register 0 FIFO control register 0 Transmit FIFO data count register 0
Receive FIFO data count SCRFDR0 register 0 Serial port register 0 Line status register 0 Serial error register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1
Transmit FIFO data register 1
SCSPTR0 SCLSR0 SCRER0 SCSMR1 SCBRR1 SCSCR1 SCFTDR1 SCFSR1 SCFRDR1 SCFCR1 SCTFDR1
Serial status register 1
Receive FIFO data register 1
FIFO control register 1 Transmit FIFO data count register 1
Receive FIFO data count SCRFDR1 register 1 Serial port register 1 Line status register 1 Serial error register 1 SCSPTR1 SCLSR1 SCRER1
Notes: 1. Bits 2 and 0 are undefined. 2. Bits 6, 4, 2,and 0 are undefined.
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Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.1
Receive Shift Register (SCRSR)
SCRSR is the register used to receive serial data. The SCIF sets serial data input from the SCIF_RXD pin in SCRSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to SCFRDR, automatically. SCRSR cannot be directly read from and written to by the CPU.
BIt: 7 6 5 4 3 2 1 0
Initial value: R/W:
27.3.2
Receive FIFO Data Register (SCFRDR)
SCFRDR is an 8-bit FIFO register of 64 stages that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for reception, and consecutive receive operations can be performed until SCFRDR is full (64 data bytes). SCFRDR is a read-only register, and cannot be written to by the CPU. If a read is performed when there is no receive data in SCFRDR, an undefined value will be returned. When SCFRDR is full of receive data, subsequent serial data is lost.
BIt: 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 R
Initial value: R/W:
Rev. 1.00 Oct. 01, 2007 Page 1068 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.3
Transmit Shift Register (SCTSR)
SCTSR is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to SCTSR, then sends the data to the SCIF_TXD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR to SCTSR, and transmission started, automatically. SCTSR cannot be directly read from and written to by the CPU.
BIt: 7 6 5 4 3 2 1 0
Initial value: R/W:

27.3.4
Transmit FIFO Data Register (SCFTDR)
SCFTDR is an 8-bit FIFO register of 64 stages that stores data for serial transmission. If SCTSR is empty when transmit data has been written to SCFTDR, the SCIF transfers the transmit data written in SCFTDR to SCTSR and starts serial transmission. SCFTDR is a write-only register, and cannot be read by the CPU. The next data cannot be written when SCFTDR is filled with 64 bytes of transmit data. Data written in this case is ignored.
BIt: 7 6 5 4 3 2 1 0
Initial value: R/W:
-- W
-- W
-- W
-- W
-- W
-- W
-- W
-- W
Rev. 1.00 Oct. 01, 2007 Page 1069 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.5
Serial Mode Register (SCSMR)
SCSMR is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate generator clock source. SCSMR can always be read from and written to by the CPU.
BIt: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 3 2 0 R 1 0
O/E STOP 0 R/W 0 R/W
CKS1 CKS0 0 R/W 0 R/W
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7
C/A
0
R/W
Communication Mode Selects asynchronous mode or clocked synchronous mode as the SCIF operating mode. 0: Asynchronous mode 1: Clocked synchronous mode
6
CHR
0
R/W
Character Length Selects 7 or 8 bits as the asynchronous mode data length. In clocked synchronous mode, the data length is fixed at 8 bits regardless of the CHR bit setting. When 7-bit data is selected, the MSB (bit 7) of SCFTDR is not transmitted. 0: 8-bit data 1: 7-bit data
Rev. 1.00 Oct. 01, 2007 Page 1070 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 5
Bit Name PE
Initial Value 0
R/W R/W
Description Parity Enable In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking is performed in reception. In clocked synchronous mode, parity bit addition and checking is disabled regardless of the PE bit setting. 0: Parity bit addition and checking disabled 1: Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit.
4
O/E
0
R/W
Parity Mode Selects either even or odd parity for use in parity addition and checking. In asynchronous mode, the O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking. In clocked synchronous mode or when parity addition and checking is disabled in asynchronous mode, the O/E bit setting is invalid. 0: Even parity 1: Odd parity When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd.
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Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 3
Bit Name STOP
Initial Value 0
R/W R/W
Description Stop Bit Length In asynchronous mode, selects 1 or 2 bits as the stop bit length. The stop bit setting is valid only in asynchronous mode. Since the stop bit is not added in clocked synchronous mode, the STOP bit setting is invalid. 0: 1 stop bit*
1 2
1: 2 stop bits*
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Note: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. 2 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator. The clock source can be selected from Pck0, Pck0/4, Pck0/16, and Pck0/64, according to the setting of bits CKS1 and CKS0. For details of the relationship between clock sources, bit rate register settings, and baud rate, see section 27.3.8, Bit Rate Register (SCBRR). 00: Pck0 clock 01: Pck0/4 clock 10: Pck0/16 clock 11: Pck0/64 clock Note: Pck0 = Peripheral Clock0
Rev. 1.00 Oct. 01, 2007 Page 1072 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.6
Serial Control Register (SCSCR)
SCSCR is a register used to enable/disable transmission/reception by SCIF, serial clock output, interrupt requests, and to select transmission/reception clock source for the SCIF. SCSCR can always be read from and written to by the CPU.
BIt: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 REIE 0 R/W 2 0 R 1 0
CKE1 CKE0 0 R/W 0 R/W
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7
TIE
0
R/W
Transmit Interrupt Enable Enables or disables transmit-FIFO-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCFTDR to SCTSR, the number of data bytes in SCFTDR falls to or below the transmit trigger set number, and the TDFE flag in SCFSR is set to 1. TXI interrupt requests can be cleared using the following methods: Either by reading 1 from the TDFE flag, writing transmit data exceeding the transmit trigger set number to SCFTDR and then clearing the TDFE flag to 0, or by clearing the TIE bit to 0. 0: Transmit-FIFO-data-empty interrupt (TXI) request disabled 1: Transmit-FIFO-data-empty interrupt (TXI) request enabled
Rev. 1.00 Oct. 01, 2007 Page 1073 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 6
Bit Name RIE
Initial Value 0
R/W R/W
Description Receive Interrupt Enable Enables or disables generation of a receive-data-full interrupt (RXI) request when the RDF flag or DR flag in SCFSR is set to 1, a receive-error interrupt (ERI) request when the ER flag in SCFSR is set to 1, and a break interrupt (BRI) request when the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1. 0: Receive-data-full interrupt (RXI) request, receiveerror interrupt (ERI) request, and break interrupt (BRI) request disabled 1: Receive-data-full interrupt (RXI) request, receiveerror interrupt (ERI) request, and break interrupt (BRI) request enabled Note: An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag, then clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0.
5
TE
0
R/W
Transmit Enable Enables or disables the start of serial transmission by the SCIF. Serial transmission is started when transmit data is written to SCFTDR while the TE bit is set to 1. 0: Transmission disabled 1: Transmission enabled* Note: SCSMR and SCFCR settings must be made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set to 1.
Rev. 1.00 Oct. 01, 2007 Page 1074 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 4
Bit Name RE
Initial Value 0
R/W R/W
Description Receive Enable Enables or disables the start of serial reception by the SCIF. Serial reception is started when a start bit is detected in this state in asynchronous mode or a synchronization clock is input while the RE bit is set to 1. It should be noted that clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER flags, which retain their states. Serial reception begins once the start bit is detected in these states. 0: Reception disabled 1: Reception enabled* Note: * SCSMR and SCFCR settings must be made, the reception format decided, and the receive FIFO reset, before the RE bit is set to 1.
3
REIE
0
R/W
Receive Error Interrupt Enable Enables or disables generation of receive-error interrupt (ERI) and break interrupt (BRI) requests. The REIE bit setting is valid only when the RIE bit is 0. Receive-error interrupt (ERI) and break interrupt (BRI) requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. When REIE is set to 1, ERI and BRI interrupt requests will be generated even if RIE is cleared to 0. In DMAC transfer, this setting is made if the interrupt controller is to be notified of ERI and BRI interrupt requests. 0: Receive-error interrupt (ERI) and break interrupt (BRI) requests disabled 1: Receive-error interrupt (ERI) and break interrupt (BRI) requests enabled
2
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1075 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 1 0
Bit Name CKE1 CKE0
Initial Value 0 0
R/W R/W R/W
Description Clock Enable 1, 0 These bits select the SCIF clock source and whether to enable or disable the clock output from the SCIF_SCK pin. The CKE1 and CKE0 bits are used together to specify whether the SCIF_SCK pin functions as a serial clock output pin or a serial clock input pin. Note however that the CKE0 bit setting is valid only when an internal clock is selected as the SCIF clock source (CKE1 = 0). When an external clock is selected (CKE1 = 1), the CKE0 bit setting is invalid. The CKE1 and CKE0 bits must be set before determining the SCIF's operating mode with SCSMR. * Asynchronous mode 00: Internal clock/SCIF_SCK pin functions as port 01: Internal clock/SCIF_SCK pin functions as clock output* clock input*2 * Clocked synchronous mode 0x: Internal clock/SCIF_SCK pin functions as synchronization clock output 1x: External clock/SCIF_SCK pin functions as synchronization clock input
1
1x: External clock/SCIF_SCK pin functions as
Notes: x: Don't care 1. Outputs a clock with a frequency 16 times the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate.
Rev. 1.00 Oct. 01, 2007 Page 1076 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.7
Serial Status Register (SCFSR)
SCFSR is a 16-bit register that consists of status flags that indicate the operating status of the SCIF. SCFSR can be read from or written to by the CPU at all times. However, 1 cannot be written to flags ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they must be read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be modified.
BIt: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 ER 6 5 4 3 FER 0 R 2 PER 0 R 1 RDF 0 DR
TEND TDFE BRK
0 1 1 0 R/W* R/W* R/W* R/W*
0 0 R/W* R/W*
Note: * Only 0 can be written, to clear the flag.
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1077 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 7
Bit Name ER
Initial Value 0
R/W
1
Description
R/W* Receive Error Indicates that a framing error or parity error occurred during reception. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR, and reception continues. The FER and PER bits in SCFSR can be used to determine whether there is a receive error in the readout data from SCFRDR. 0: No framing error or parity error occurred during reception [Clearing conditions] * Power-on reset or manual reset * When 0 is written to ER after reading ER = 1 1: A framing error or parity error occurred during reception [Setting conditions] * When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0*2 * When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SCSMR R/W*1 Transmit End Indicates that transmission has been ended without valid data in SCFTDR after transmission of the last bit of the transmit character. 0: Transmission is in progress [Clearing conditions] * * When transmit data is written to SCFTDR, and 0 is written to TEND after reading TEND = 1 When data is written to SCFTDR by the DMAC
6
TEND
1
1: Transmission has been ended [Setting conditions] * * * Power-on reset or manual reset When the TE bit in SCSCR is 0 When there is no transmit data in SCFTDR after transmission of the last bit of a 1-byte serial transmit character
Rev. 1.00 Oct. 01, 2007 Page 1078 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 5
Bit Name TDFE
Initial Value 1
R/W
1
Description Indicates that data has been transferred from SCFTDR to SCTSR, the number of data bytes in SCFTDR has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in SCFCR, and new transmit data can be written to SCFTDR. 0: A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR [Clearing conditions] * When transmit data exceeding the transmit trigger set number is written to SCFTDR after reading TDFE = 1, and 0 is written to TDFE When transmit data exceeding the transmit trigger set number is written to SCFTDR by the DMAC
R/W* Transmit FIFO Data Empty
*
1: The number of transmit data bytes in SCFTDR does not exceed the transmit trigger set number (Initial value) [Setting conditions] * * Power-on reset or manual reset When the number of SCFTDR transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation*3
4
BRK
0
R/W*1 Break Detect Indicates that a receive data break signal has been detected. 0: A break signal has not been received [Clearing conditions] * * Power-on reset or manual reset When 0 is written to BRK after reading BRK = 1
4
1: A break signal has been received* [Setting condition] *
When data with a framing error is received, followed by the space "0" level (low level ) for at least one frame length
Rev. 1.00 Oct. 01, 2007 Page 1079 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 3
Bit Name FER
Initial Value 0
R/W R
Description Framing Error In asynchronous mode, indicates whether or not a framing error has been found in the data that is to be read next from SCFRDR. 0: There is no framing error that is to be read from SCFRDR [Clearing conditions] * * Power-on reset or manual reset When there is no framing error in the data that is to be read next from SCFRDR
1: There is a framing error that is to be read from SCFRDR [Setting condition] * 2 PER 0 R When there is a framing error in the data that is to be read next from SCFRDR
Parity Error In asynchronous mode, indicates whether or not a parity error has been found in the data that is to be read next from SCFRDR. 0: There is no parity error that is to be read from SCFRDR [Clearing conditions] * * Power-on reset or manual reset When there is no parity error in the data that is to be read next from SCFRDR
1: There is a parity error in the receive data that is to be read from SCFRDR [Setting condition] * When there is a parity error in the data that is to be read next from SCFRDR
Rev. 1.00 Oct. 01, 2007 Page 1080 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 1
Bit Name RDF
Initial Value 0
R/W
1
Description
R/W* Receive FIFO Data Full Indicates that the received data has been transferred from SCRSR to SCFRDR, and the number of receive data bytes in SCFRDR is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR. 0: The number of receive data bytes in SCFRDR is less than the receive trigger set number [Clearing conditions] * * Power-on reset or manual reset When SCFRDR is read until the number of receive data bytes in SCFRDR falls below the receive trigger set number after reading RDF = 1, and 0 is written to RDF When SCFRDR is read by the DMAC until the number of receive data bytes in SCFRDR falls below the receive trigger set number
*
1: The number of receive data bytes in SCFRDR is equal to or greater than the receive trigger set number [Setting condition] * When SCFRDR contains at least the receive trigger 5 set number of receive data bytes*
Rev. 1.00 Oct. 01, 2007 Page 1081 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 0
Bit Name DR
Initial Value 0
R/W
1
Description In asynchronous mode, indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR, and no further data has arrived for at least 15 etu after the stop bit of the last data received. This is not set when using clocked synchronous mode. 0: Reception is in progress or has ended normally and there is no receive data left in SCFRDR [Clearing conditions] * * * Power-on reset or manual reset When all the receive data in SCFRDR has been read after reading DR = 1, and 0 is written to DR When all the receive data in SCFRDR has been read by the DMAC
R/W* Receive Data Ready
1: No further receive data has arrived [Setting condition] * When SCFRDR contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received*6
[Legend] etu: Elementary time unit (time for transfer of 1 bit) Notes: 1. Only 0 can be written, to clear the flag. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. 3. As SCFTDR is a 64-byte FIFO register, the maximum number of bytes that can be written when TDFE = 1 is 64 - (transmit trigger set number). Data written in excess of this will be ignored. SCTFDR indicates the number of data bytes transmitted to SCFTDR. 4. When a break is detected, the receive data (H'00) following detection is not transferred to SCFRDR. When the break ends and the receive signal returns to mark "1", receive data transfer is resumed. 5. SCFRDR is a 64-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If all the data in SCFRDR is read and another read is performed, the data value will be undefined. The number of receive data bytes in SCFRDR is indicated by SCRFDR. 6. Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format.
Rev. 1.00 Oct. 01, 2007 Page 1082 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.8
Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that set the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR. SCBRR can always be read from and written to by the CPU. The SCBRR setting is found from the following equation. Asynchronous mode:
N=
Pck0 64 x 22n - 1 x B x 106 - 1
Clocked synchronous mode:
N=
Pck0 8 x 22n - 1 x B x 106 - 1
Where B: Bit rate (bits/s) N: SCBRR setting for baud rate generator (0 N 255) Pck0: Peripheral module operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See table 27.4 for the relation between n and the clock.) Table 27.4 SCSMR Settings
SCSMR Setting n 0 1 2 3 Clock Pck0 Pck0/4 Pck0/16 Pck0/64 CKS1 0 0 1 1 CKS0 0 1 0 1
The bit rate error in asynchronous mode is found from the following equation:
Error (%) =
Pck0 x 106 -1 (N + 1) x B x 64 x 22n - 1
x 100
Rev. 1.00 Oct. 01, 2007 Page 1083 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.9
FIFO Control Register (SCFCR)
SCFCR performs data count resetting and trigger data number setting for transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR can always be read from and written to by the CPU.
BIt: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10
RST RG2
9
RST RG1
8
7
6
5
4
3
2
TFCL
1
0
RST RTRG1 RTRG0 TTRG1 TTRG0 MCE RG0
RFCL LOOP
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15 to 11
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
10 9 8
RSTRG2 RSTRG1 RSTRG0
0 0 0
R/W R/W R/W
SCIF_RTS Output Active Trigger The SCIF_RTS signal becomes high when the number of receive data stored in SCFRDR exceeds the trigger number shown below. 000:63 001:1 010:8 011:16 100:32 101:48 110:54 111:60
7 6
RTRG1 RTRG0
0 0
R/W R/W
Receive FIFO Data Number Trigger These bits are used to set the number of receive data bytes that sets the RDF flag in SCFSR. The RDF flag is set when the number of receive data bytes in SCFRDR is equal to or greater than the trigger set number shown below. 00:1 01:16 10:32 11:48
Rev. 1.00 Oct. 01, 2007 Page 1084 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 5 4
Bit Name TTRG1 TTRG0
Initial Value 0 0
R/W R/W R/W
Description Transmit FIFO Data Number Trigger These bits are used to set the number of remaining transmit data bytes that sets the TDFE flag in SCFSR. The TDFE flag is set when the number of transmit data bytes in SCFTDR is equal to or less than the trigger set number shown below. 00: 32 (32)*1 01:16 (48) 10: 2 (62) 11: 0 (64)
3
MCE
0
R/W
Modem Control Enable Enables the SCIF_CTS and SCIF_RTS modem control signals. Always set the MCE bit to 0 in clocked synchronous mode. 0: Modem signals disabled*2 1: Modem signals enabled
2
TFCL
0
R/W
Transmit FIFO Data Register Reset Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state. 0: Reset operation disabled*3 1: Reset operation enabled
1
RFCL
0
R/W
Receive FIFO Data Register Reset Invalidates the receive data in the receive FIFO data register and resets it to the empty state. 0: Reset operation disabled*3 1: Reset operation enabled
0
LOOP
0
R/W
Loopback Test Internally connects the transmit output pin (SCIF_TXD) and receive input pin (SCIF_RXD), and the SCIF_RTS pin and SCIF_CTS pin, enabling loopback testing. 0: Loopback test disabled 1: Loopback test enabled
Notes: 1. Figures in parentheses are the number of empty bytes in SCFTDR when the flag is set. 2. SCIF_CTS is fixed at active-0 regardless of the input value, and SCIF_RTS output is also fixed at 0. 3. A reset operation is performed in the event of a power-on reset or manual reset.
Rev. 1.00 Oct. 01, 2007 Page 1085 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.10 Transmit FIFO Data Count Register (SCTFDR) SCTFDR is a 16-bit register that indicates the number of transmit data bytes stored in SCFTDR. SCTFDR can always be read from the CPU.
BIt: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 T6 0 R 5 T5 0 R 4 T4 0 R 3 T3 0 R 2 T2 0 R 1 T1 0 R 0 T0 0 R
Bit 15 to 7
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
6 to 0
T6 to T0
All 0
R
These bits show the number of untransmitted data bytes in SCFTDR. A value of H'0000 indicates that there is no transmit data, and a value of H'0040 indicates that SCFTDR is full of transmit data.
27.3.11 Receive FIFO Data Count Register (SCRFDR) SCRFDR is a 16-bit register that indicates the number of receive data bytes stored in SCFRDR. SCRFDR can always be read from the CPU.
BIt: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 R6 0 R 5 R5 0 R 4 R4 0 R 3 R3 0 R 2 R2 0 R 1 R1 0 R 0 R0 0 R
Bit 15 to 7
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
6 to 0
R6 to R0
All 0
R
These bits show the number of receive data bytes in SCFRDR. A value of H'0000 indicates that there is no receive data, and a value of H'0040 indicates that SCFRDR is full of receive data.
Rev. 1.00 Oct. 01, 2007 Page 1086 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.12 Serial Port Register (SCSPTR) SCSPTR is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins at all times. Input data can be read from the SCIF_RXD pin, output data written to the SCIF_TXD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. All SCSPTR bits except bits 6, 4, 2, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, 2, and 0 is undefined. SCSPTR is not initialized in the module standby state. Note that when reading data via a serial port pin in the SCIF, the peripheral clock value from 2 cycles before is read.
BIt: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7
RTS IO
6
RTS DT
5
CTS IO
4
CTS DT
3
SCK IO
2
SCK DT
1
SPB2 IO
0
SPB2 DT
0 R/W
R/W
0 R/W
R/W
0 R/W
R/W
0 R/W
R/W
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7
RTSIO
0
R/W
Serial Port SCIF_RTS Port Input/Output Specifies the serial port SCIF_RTS pin input/output condition. When actually setting the SCIF_RTS pin as a port output pin to output the value set by the RTSDT bit, the MCE bit in SCFCR should be cleared to 0. 0: RTSDT bit value is not output to SCIF_RTS pin 1: RTSDT bit value is output to SCIF_RTS pin
6
RTSDT
--
R/W
Serial Port SCIF_RTS Port Data Specifies the serial port SCIF_RTS pin input/output data. Input or output is specified by the RTSIO bit. In output mode, the RTSDT bit value is output to the SCIF_RTS pin. The SCIF_RTS pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. 0: Input/output data is low-level 1: Input/output data is high-level
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Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 5
Bit Name CTSIO
Initial Value 0
R/W R/W
Description Serial Port SCIF_CTS Port Input/Output Specifies the serial port SCIF_CTS pin input/output condition. When actually setting the SCIF_CTS pin as a port output pin to output the value set by the CTSDT bit, the MCE bit in SCFCR should be cleared to 0. 0: CTSDT bit value is not output to SCIF_CTS pin 1: CTSDT bit value is output to SCIF_CTS pin
4
CTSDT
--
R/W
Serial Port SCIF_CTS Port Data Specifies the serial port SCIF_CTS pin input/output data. Input or output is specified by the CTSIO bit. In output mode, the CTSDT bit value is output to the SCIF_CTS pin. The SCIF_CTS pin value is read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. 0: Input/output data is low-level 1: Input/output data is high-level
3
SCKIO
0
R/W
Serial Port Clock Port Input/Output Specifies the serial port SCIF_SCK pin input/output condition. When actually setting the SCIF_SCK pin as a port output pin to output the value set by the SCKDT bit, the CKE1 and CKE0 bits in SCSCR should be cleared to 0. 0: SCKDT bit value is not output to SCIF_SCK pin 1: SCKDT bit value is output to SCIF_SCK pin
2
SCKDT
--
R/W
Serial Port Clock Port Data Specifies the serial port SCIF_SCK pin input/output data. Input or output is specified by the SCKIO bit. In output mode, the SCKDT bit value is output to the SCIF_SCK pin. The SCIF_SCK pin value is read from the SCKDT bit regardless of the value of the SCKIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. 0: Input/output data is low-level 1: Input/output data is high-level
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Section 27 Serial Communication Interface with FIFO (SCIF)
Bit 1
Bit Name SPB2IO
Initial Value 0
R/W R/W
Description Serial Port Break Input/Output Specifies the serial port SCIF_TXD pin output condition. When actually setting the SCIF_TXD pin as a port output pin to output the value set by the SPB2DT bit, the TE bit in SCSCR should be cleared to 0. 0: SPB2DT bit value is not output to the SCIF_TXD pin 1: SPB2DT bit value is output to the SCIF_TXD pin
0
SPB2DT
--
R/W
Serial Port Break Data Specifies the serial port SCIF_RXD pin input data and SCIF_TXD pin output data. The SCIF_TXD pin output condition is specified by the SPB2IO bit. When the SCIF_TXD pin is designated as an output, the value of the SPB2DT bit is output to the SCIF_TXD pin. The SCIF_RXD pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. 0: Input/output data is low-level 1: Input/output data is high-level
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Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.13 Line Status Register (SCLSR)
BIt: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 ORER 0 R/W*
Note: * Only 0 can be written, to clear the flag.
Bit 15 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
ORER
0
R/W* Overrun Error Indicates that an overrun error occurred during reception, causing abnormal termination. 0: Reception in progress, or reception has ended 2 normally* [Clearing conditions] * * Power-on reset or manual reset When 0 is written to ORER after reading ORER = 1
1
1: An overrun error occurred during reception*3 [Setting condition] * When the next serial reception is completed while SCFRDR receives 64-byte data (SCFRDR is full)
Notes: 1. Only 0 can be written, to clear the flag. 2. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. 3. The receive data prior to the overrun error is retained in SCFRDR, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1.
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Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.14 Serial Error Register (SCRER) SCRER is a 16-bit register that indicates the number of receive errors in the data in SCFRDR. SCRER can always be read from the CPU.
BIt: 15 Initial value: R/W: 0 R 14 0 R 13 12 11 10 9 8 7 0 R 6 0 R 5 4 3 2 1 0
PER5 PER4 PER3 PER2 PER1 PER0 0 R 0 R 0 R 0 R 0 R 0 R
FER5 FER4 FER3 FER2 FER1 FER0 0 R 0 R 0 R 0 R 0 R 0 R
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13 12 11 10 9 8
PER5 PER4 PER3 PER2 PER1 PER0
0 0 0 0 0 0
R R R R R R
Number of Parity Errors These bits indicate the number of data bytes in which a parity error occurred in the receive data stored in SCFRDR. After the ER bit in SCFSR is set, the value indicated by bits PER5 to PER0 is the number of data bytes in which a parity error occurred. If all 64 bytes of receive data in SCFRDR have parity errors, the value indicated by bits PER5 to PER0 will be 0.
7, 6
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
5 4 3 2 1 0
FER5 FER4 FER3 FER2 FER1 FER0
0 0 0 0 0 0
R R R R R R
Number of Framing Errors These bits indicate the number of data bytes in which a framing error occurred in the receive data stored in SCFRDR. After the ER bit in SCFSR is set, the value indicated by bits FER5 to FER0 is the number of data bytes in which a framing error occurred. If all 64 bytes of receive data in SCFRDR have framing errors, the value indicated by bits FER5 to FER0 will be 0.
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Section 27 Serial Communication Interface with FIFO (SCIF)
27.4
27.4.1
Operation
Overview
The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character and in synchronous mode, in which synchronization is achieved with clock pulses. For details on asynchronous mode, see section 27.4.2, Operation in Asynchronous Mode. 64-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead, and enabling fast and continuous communication to be performed. SCIF_RTS and SCIF_CTS signals are also provided as modem control signals (channel 0 only). The serial transfer format is selected using SCSMR, as shown in table 27.5. The SCIF clock source is determined by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR, as shown in table 27.6. Asynchronous Mode: * Data length: Choice of 7 or 8 bits * Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receivedata-ready state, and breaks, during reception * Indication of the number of data bytes stored in the transmit and receive FIFO registers * Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on the baud rate generator clock and can output a clock with frequency of 16 times the bit rate. When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). Clocked Synchronous Mode: * Data length: Fixed at 8 bits * Detection of overrun errors during reception * Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on the baud rate generator clock and a serial clock is output to external devices.
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Section 27 Serial Communication Interface with FIFO (SCIF)
When external clock is selected: The on-chip baud rate generator is not used and the SCIF operates on the input serial clock. Table 27.5 SCSMR Settings for Serial Transfer Format Selection
SCSMR Settings Bit 7: C/A 0 Bit 6: CHR 0 Bit 5: PE 0 Bit 3: STOP 0 1 1 0 1 1 0 0 1 1 0 1 1 x x x Clocked synchronous mode 8-bit data No Yes 7-bit data No Yes Mode Asynchronous mode SCIF Transfer Format Data Length 8-bit data Parity Bit No Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits No
Note: x: Don't care
Table 27.6 SCSMR and SCSCR Settings for SCIF Clock Source Selection
SCSMR Bit 7: C/A 0 SCSCR Settings Bit 1: CKE1 0 Bit 0: CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Clocked synchronous mode Internal Mode Asynchronous mode Clock Source Internal SCK Pin Function SCIF does not use SCIF_SCK pin Outputs clock with frequency of 16 times the bit rate External Inputs clock with frequency of 16 times the bit rate Outputs synchronization clock
External
Inputs synchronization clock
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Section 27 Serial Communication Interface with FIFO (SCIF)
27.4.2
Operation in Asynchronous Mode
In asynchronous mode, a character that consists of data with a start bit indicating the start of communication and a stop bit indicating the end of communication is transmitted or received. In this mode, serial communication is performed with synchronization achieved character by character. Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and receiver have a 64-stage FIFO buffer structure, so that data can be read or written during transmission or reception, enabling continuous data transmission and reception. Figure 27.7 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCIF monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One character in serial communication consists of a start bit (low level), followed by transmit/receive data (LSB-first; from the lowest bit), a parity bit (high or low level), and finally stop bits (high level). In reception in asynchronous mode, the SCIF synchronizes with the fall of the start bit. Receive data can be latched at the middle of each bit because the SCIF samples data at the eighth clock which has a frequency of 16 times the bit rate.
Idle state (mark state) 1
0/1
Parity bit 1 bit or none
1
Serial data
LSB 0 Start bit
1 bit
MSB
D1 D2 D3 D4 D5 D6 D7 1 1
D0
Stop bit
Transmit/receive data
7 or 8 bits
1 or 2 bits
One unit of transfer data (character or frame)
Figure 27.7 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, and Two Stop Bits)
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Section 27 Serial Communication Interface with FIFO (SCIF)
(1)
Data Transfer Format
Table 27.7 shows the data transfer formats that can be used. Any of 8 transfer formats can be selected according to the SCSMR settings. Table 27.7 Serial Transfer Formats (Asynchronous Mode)
SCSMR Settings
CHR PE 0 0 STOP 0 1 S 2
Serial Transfer Format and Frame Length
3 4 5 8-bit data 6 7 8 9 10
STOP
11
12
0
0
1
S
8-bit data
STOP STOP
0
1
0
S
8-bit data
P
STOP
0
1
1
S
8-bit data
P
STOP STOP
1
0
0
S
7-bit data
STOP
1
0
1
S
7-bit data
STOP STOP
1
1
0
S
7-bit data
P
STOP
1
1
1
S
7-bit data
P
STOP STOP
[Legend] S : Start bit STOP : Stop bit P : Parity bit
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Section 27 Serial Communication Interface with FIFO (SCIF)
(2)
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCIF_SCK pin can be selected as the SCIF's serial clock, according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source selection, see table 27.6. When an external clock is input at the SCIF_SCK pin, the clock frequency should be 16 times the bit rate used. When the SCIF is operated on an internal clock, a clock whose frequency is 16 times the bit rate is output from the SCIF_SCK pin. (3) SCIF Initialization (Asynchronous Mode)
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0, then initialize the SCIF as described below. When the operating mode or transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. 1. 2. When the TE bit is cleared to 0, SCTSR is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR, SCFTDR, or SCFRDR. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in SCFSR has been set. TEND can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state after the clearance. Before setting TE again to start transmission, the TFCL bit in SCFCR should first be set to 1 to reset SCFTDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case.
3.
Rev. 1.00 Oct. 01, 2007 Page 1096 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Figure 27.8 shows a sample SCIF initialization flowchart.
Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFCL and RFCL bits in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR (leaving TE, RE, TIE, and RIE bits cleared to 0) Set data transfer format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Yes Set RTRG1-0, TTRG1-0 bits, and MCE in SCFCR, and clear TFCL and RFCL bits to 0 Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits No
[1] Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0. [2] Set the data transfer format in SCSMR. [3] Write a value corresponding to the bit rate into SCBRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE bit or RE bit in SCSCR to 1. Also set the RIE, REIE, and TIE bits. Setting the TE and RE bits enables the SCIF_TXD and SCIF_RXD pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit.
[1]
[2]
[3]
[4]
End of initialization
Figure 27.8 Sample SCIF Initialization Flowchart
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Section 27 Serial Communication Interface with FIFO (SCIF)
(4)
Serial Data Transmission (Asynchronous Mode):
Figure 27.9 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Start of transmission
[1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE and TEND flags to 0. The number of transmit data bytes that can be written is 64 - (transmit trigger set number). [1] [2] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0. [3] Break output at the end of serial transmission: To output a break in serial transmission, clear the SPB2DT bit to 0 and set the SPB2IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR to 0. In [1] and [2], it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR indicated by SCTFDR.
Read TDFE flag in SCFSR
No
TDFE = 1?
Yes
Write transmit data in SCFTDR, and clear TDFE flag and TEND flag in SCFSR to 0
No
All data transmitted?
Yes
[2]
Read TEND flag in SCFSR
No
TEND = 1? Yes Break output? Yes Clear SPB2DT to 0 and set SPB2IO to 1 Clear TE bit in SCSCR to 0
No
[3]
End of transmission
Figure 27.9 Sample Serial Transmission Flowchart
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Section 27 Serial Communication Interface with FIFO (SCIF)
In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmitting. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is at least 64 - (transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls to or below the transmit trigger number set in SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFOdata-empty interrupt (TXI) request is generated. The serial transmit data is sent from the SCIF_TXD pin in the following order. (a) Start bit: One 0-bit is output. (b) Transmit data: 8-bit or 7-bit data is output in LSB-first order. (c) Parity bit: One parity bit (even or odd parity) is output. A format in which a parity bit is not output can also be selected. (d) Stop bit(s): One or two 1-bits (stop bits) are output. (e) Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data after the stop bit is sent, the TEND flag in SCFSR is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output from the SCIF_TXD pin.
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Section 27 Serial Communication Interface with FIFO (SCIF)
Figure 27.10 shows an example of the operation for transmission in asynchronous mode.
Start bit Data Parity Stop Start bit bit bit Data Parity Stop bit bit D7 0/1 1
1
Serial data
1 Idle state (mark state)
0
D0
D1
D7
0/1
1
0
D0
D1
TDFE TEND TXI interrupt TXI interrupt request Data written to SCFTDR request and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame
Figure 27.10 Sample SCIF Transmission Operation (Example with 8-Bit Data, Parity, One Stop Bit) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the SCIF_CTS input value. When SCIF_CTS is set to 1 during transmission , the line goes to the mark state after transmission of one frame. When SCIF_CTS is set to 0, the next transmit data is output starting from the start bit. Figure 27.11 shows an example of the operation when modem control is used.
Start bit
Serial data SCIF_TXD SCIF_CTS
ParityStop bit bit
D0 D1 D7 0/1
Start bit
0 D0 D1 D7 0/1
0
Drive high before stop bit
Figure 27.11 Sample Operation Using Modem Control (SCIF_CTS)
Rev. 1.00 Oct. 01, 2007 Page 1100 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
(5)
Serial Data Reception (Asynchronous Mode)
Figure 27.12 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception.
[1] Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR, and the ORER flag in SCLSR, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the SCIF_RXD pin. [2] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading from SCRFDR.
Start of reception
Read ER, DR, BRK flags in SCFSR and ORER flag in SCLSR
[1]
ER, DR, BRK or ORER = 1? No Read RDF flag in SCFSR No
Yes
Error handling [2]
RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0
No
All data received? Yes Clear RE bit in SCSCR to 0 End of reception
[3]
Figure 27.12 Sample Serial Reception Flowchart (1)
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Section 27 Serial Communication Interface with FIFO (SCIF)
Error handling
No
ORER = 1? Yes Overrun error handling
[1] Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in SCFSR. [2] When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00, and the break data in which a framing error occurred is stored.
No
ER = 1?
Yes
Receive error handling
No
BRK = 1?
Yes
Break handling
No
DR = 1?
Yes
Read receive data in SCFRDR
Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR, to 0
End
Figure 27.12 Sample Serial Reception Flowchart (2)
Rev. 1.00 Oct. 01, 2007 Page 1102 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0-start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. (a) Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. (b) The SCIF checks whether receive data can be transferred from SCRSR to SCFRDR.* (c) Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun error has occurred.* (d) Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set.* If (b), (c), and (d) checks are passed, the receive data is stored in SCFRDR. Note: * Reception continues even when a parity error or framing error occurs. 4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. Figure 27.13 shows an example of the operation for reception in asynchronous mode.
Start bit Data Parity Stop Start bit bit bit Data Parity Stop bit bit
1
Serial data
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
0
0/1
RDF
FER
RXI interrupt request
One frame
Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler
ERI interrupt request generated by receive error
Figure 27.13 Sample SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit)
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Section 27 Serial Communication Interface with FIFO (SCIF)
5. When modem control is enabled, the SCIF_RTS signal is output when SCFRDR is empty. When SCIF0_RTS is 0, reception is possible. When SCIF_RTS is 1, this indicates that SCFRDR contains bytes of data equal to or more than the SCIF_RTS output active trigger number. The SCIF_RTS output active trigger value is specified by bits 10 to 8 in the FIFO control register (SCFCR). For details, see section 27.3.9, FIFO control register (SCFCR). In addition, SCIF_RTS is also 1 when the RE bit in SCSCR is cleared to 0. Figure 27.14 shows an example of the operation when modem control is used.
Start bit Serial data SCIF_RXD 0 D0 D1 D2 ParityStop bit bit D7 0/1 1 Start bit 0
SCIF_RTS
Figure 27.14 Sample Operation Using Modem Control (SCIF0_RTS) (Only in Channel 0) 27.4.3 Operation in Clocked Synchronous Mode
Clocked synchronous mode, in which data is transmitted or received in synchronization with clock pulses, is suitable for fast serial communication. Since the transmitter and receiver are independent units in the SCIF, full-duplex communication can be achieved by sharing the clock. Both the transmitter and receiver have a 64-stage FIFO buffer structure, so that data can be read or written during transmission or reception, enabling continuous data transfer and reception. Figure 27.15 shows the general format for clocked synchronous communication.
One unit of transfer data (character or frame)
*
*
Synchronization clock
LSB
MSB
Serial data
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don't care
Note: * High except in continuous transfer
Don't care
Figure 27.15 Data Format in Clocked Synchronous Communication
Rev. 1.00 Oct. 01, 2007 Page 1104 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
In clocked synchronous serial communication, data on the communication line is output from one fall of the synchronization clock to the next fall. Data is guaranteed to be accurate at the start of the synchronization clock. In serial communication, each character is output starting with the LSB and ending with the MSB. After the MSB is output, the communication line remains in the state of the last data. In clocked synchronous mode, the SCIF receives data in synchronization with the rise of the synchronization clock. (1) Data Transfer Format
A fixed 8-bit data format is used. No parity bit can be added. (2) Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCIF_SCK pin can be selected as the SCIF's serial clock, according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source selection, see table 27.6. When the SCIF is operated on an internal clock, the synchronization clock is output from the SCIF_SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When an internal clock is selected in a receive operation only, as long as the RE bit in SCSCR is set to 1, clock pulses are output until the number of receive data bytes in the receive FIFO data register reaches the receive trigger number. (3) SCIF Initialization (Clocked Synchronous Mode):
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0, then initialize the SCIF as described below. When changing the operating mode or transfer format, etc., the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, SCTSR is initialized. Note that clearing the RE bit to 0 does not initialize the RDF, PER, FER, or ORER flag state or change the contents of SCFRDR. Figure 27.16 shows a sample SCIF initialization flowchart.
Rev. 1.00 Oct. 01, 2007 Page 1105 of 1956 REJ09B0256-0100
Section 27 Serial Communication Interface with FIFO (SCIF)
Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFCL and RFCL bits in SCFCR to 1 to clear the FIFO buffer After reading BRK, DR, and ER flags in SCFSR, write 0 to clear them Set CKE1 and CKE0 bits in SCSCR (leaving TE, RE, TIE, and RIE bits cleared to 0) Set data transfer format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Yes Set RTRG1-0 and TTRG1-0 bits in SCFCR, and clear TFCL and RFCL bits to 0 Set external pins to be used (SCIF_SCK, SCIF_TXD, and SCIF_RXD) Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits No
[1]
[1] Leave the TE and RE bits cleared to 0 until the initialization almost ends. Be sure to clear the TIE, RIE, TE, and RE bits to 0. [2] Set the CKE1 and CKE0 bits. [3] Set the data transfer format in SCSMR. [4] Write a value corresponding to the bit rate into SCBRR. This is not necessary if an external clock is used. Wait at least one bit interval after this write before moving to the next step.
[2]
[3]
[5] Set the external pins to be used. Set SCIF_RXD input for reception and SCIF_TXD output for transmission. The input/output of the SCIF_SCK pin must match the setting of the CKE1 and CKE0 bits. [6] Set the TE or RE bit in SCSCR to 1. Also set the TIE, RIE, and REIE bits to enable the SCIF_TXD, SCIF_RXD, and SCIF_SCK pins to be used. When transmitting, the SCIF_TXD pin will go to the mark state. When receiving in clocked synchronous mode with the synchronization clock output (clock master) selected, a clock starts to be output from the SCIF_SCK pin at this point.
[4]
[5]
[6]
End of initialization
Figure 27.16 Sample SCIF Initialization Flowchart
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Section 27 Serial Communication Interface with FIFO (SCIF)
(4)
Serial Data Transmission (Clocked Synchronous Mode)
Figure 27.17 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Initialization Start of transmission
[1]
[1] SCIF initialization: See sample SCIF initialization flowchart in figure 27.16. [2] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE flag to 0. The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Serial transmission continuation procedeure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, them write data to SCFTDR, and then clear the TDFE flag to 0.
Read TDFE flag in SCFSR
No
[2]
TDFE = 1?
Yes
Write transmit data to SCFTDR and clear TDFE flag and TEND flag in SCFSR to 0
No
All data transmitted?
Yes Read TEND flag in SCFSR
[3]
TEND = 1? Yes Clear TE bit in SCSCR to 0
No
End of transmission
Figure 27.17 Sample Serial Transmission Flowchart In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmitting. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is at least 64 (transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls to or below the transmit trigger number set in
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Section 27 Serial Communication Interface with FIFO (SCIF)
SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFOdata-empty interrupt (TXI) request is generated. If clock output mode is selected, the SCIF outputs eight synchronization clock pulses for each data. When the external clock is selected, data is output in synchronization with the input clock. The serial transmit data is sent from the SCIF_TXD pin in the LSB-first order. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the last bit. If data is present, the data is transferred from SCFTDR to SCTSR, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1 after the last bit is sent, and the transmit data pin (SCIF_TXD pin) retains the output state of the last bit. 4. After serial transmission ends, the CLK pin is fixed high. Figure 27.18 shows an example of the operation for transmission in clocked synchronous mode.
Synchronization clock Serial data
LSB Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TDFE TEND
TXI interrupt request
Data written to SCFTDR TXI interrupt and TDFE flag cleared to 0 by TXI interrupt handler
One frame
Figure 27.18 Sample SCIF Transmission Operation in Clocked Synchronous Mode
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Section 27 Serial Communication Interface with FIFO (SCIF)
(5)
Serial Data Reception (Clocked Synchronous Mode)
Figure 27.19 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. When switching the operating mode from asynchronous mode to clocked synchronous mode without initializing the SCIF, make sure that the ORER, PER7 to PER0, and FER7 to FER0 flags are cleared to 0.
[1] SCIF initialization: See Sample SCIF Initialization Flowchart in figure 27.16. [2] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Transmission/reception cannot be resumed while the ORER flag is set to 1.
[2] No Error handling [3]
Initialization
[1]
Start of reception
Read ORER flag in SCLSR
ORER = 1?
Yes
Read RDF flag in SCFSR
No
RDF = 1?
Yes
[3] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [4] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading SCFRDR.
Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0
No
[4]
All data received?
Yes
Clear RE bit in SCSCR to 0 End of reception
Figure 27.19 Sample Serial Reception Flowchart (1)
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Section 27 Serial Communication Interface with FIFO (SCIF)
Error handling No
ORER = 1? Yes Overrun error handling
Clear ORER flag in SCLSR to 0
End
Figure 27.19 Sample Serial Reception Flowchart (2) In serial reception, the SCIF operates as described below. 1. The SCIF is initialized internally in synchronization with the input or output of the synchronization clock. 2. The received data is stored in SCRSR in LSB-to-MSB order. After receiving the data, the SCIF checks whether the receive data can be transferred from SCRSR to SCFRDR. If this check is passed, the receive data is stored in SCFRDR. If an overrun error is detected in the error check, reception cannot continue. 3. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR is set to 1 when the ORER flag changes to 1, a break interrupt (BRI) request is generated.
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Section 27 Serial Communication Interface with FIFO (SCIF)
Figure 27.20 shows an example of the operation for reception in clocked synchronous mode.
Synchronization clock Serial data
Bit 7 LSB Bit 0 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
RDF
ORER
RXI interrupt request
Data read from RXI interr pt u SCFRDR and RDF flag cleared to 0 by RXI interrupt handler
BRI interrupt request by overrun error
One frame
Figure 27.20 Sample SCIF Reception Operation in Clocked Synchronous Mode
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Section 27 Serial Communication Interface with FIFO (SCIF)
(6)
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
Figure 27.21 shows a sample flowchart for simultaneous serial data transmission and reception. Use the following procedure for simultaneous serial transmission and reception after enabling the SCIF for both transmission and reception.
Initialization Start of transmission and reception [1] [1] SCIF initialization: See Sample SCIF Initialization Flowchart in figure 27.16. [2] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE flag to 0. The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Transmission/reception cannot be resumed while the ORER flag is set to 1. [4] SCIF status check and receive data read: Yes Read SCFSR and check that RDF = 1, then read the receive data in [3] SCFRDR, and clear the RDF flag to Error handling 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission and reception continuation procedure: To continue serial transmission and reception, read 1 from the RDF flag and the receive data in SCFRDR, and clear the RDF flag to 0 before receiving the MSB in the current frame. Similarly, read 1 from the TDFE flag to confirm that writing is possible before transmitting the MSB in the current frame. Then write data to SCFTDR and clear the TDFE flag to 0. Note: When switching from a transmit operation or receive operation to simultaneous transmission and reception operations, clear the TE and RE bits to 0, and then set them simultaneously to 1.
Read TDFE flag in SCFSR No
[2]
TDFE = 1? Yes Write transmit data to SCFTDR, and clear TDFE flag in SCFSR to 0
Read ORER flag in SCLSR
ORER = 1? No Read RDF flag in SCFSR No
RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 [4]
No
All data received? Yes Clear TE and RE bits in SCSCR to 0 End of transmission and reception [5]
Figure 27.21 Sample Simultaneous Serial Transmission and Reception Flowchart
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Section 27 Serial Communication Interface with FIFO (SCIF)
27.5
SCIF Interrupt Sources and the DMAC
The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receiveerror interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt (BRI) request. Table 27.8 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. If the TDFE flag in SCFSR is set to 1 when a TXI interrupt is enabled by the TIE bit, a TXI interrupt request and a transmit-FIFO-data-empty request for DMA transfer are generated. If the TDFE flag is set to 1 when a TXI interrupt is disabled by the TIE bit, only a transmit-FIFO-dataempty request for DMA transfer is generated. A transmit-FIFO-data-empty request can activate the DMAC to perform data transfer. If the RDF or DR flag in SCFSR is set to 1 when an RXI interrupt is enabled by the RIE bit, an RXI interrupt request and a receive-FIFO-data-full request for DMA transfer are generated. If the RDF or DR flag is set to 1 when an RXI interrupt is disabled by the RIE bit, only a receive-FIFOdata-full request for DMA transfer is generated. A receive-FIFO-data-full request can activate the DMAC to perform data transfer. Note that generation of an RXI interrupt request or a receiveFIFO-data-full request by setting the DR flag to 1 occurs only in asynchronous mode. When the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1, a BRI interrupt request is generated. If transmission/reception is carried out using the DMAC, set and enable the DMAC before making the SCIF settings. Also make settings to inhibit output of RXI and TXI interrupt requests to the interrupt controller. If output of interrupt requests is enabled, these interrupt requests to the interrupt controller can be cleared by the DMAC regardless of the interrupt handler. By setting the REIE bit to 1 while the RIE bit is cleared to 0 in SCSCR, it is possible to output ERI interrupt requests, but not RXI interrupt requests.
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Section 27 Serial Communication Interface with FIFO (SCIF)
Table 27.8 SCIF Interrupt Sources
Interrupt Source ERI RXI BRI TXI Note: * DMAC Activation Not possible Possible Priority on Reset Release High
Description Interrupt initiated by receive error flag (ER) Interrupt initiated by receive FIFO data full flag (RDF) or receive data ready flag (DR)*
Interrupt initiated by break flag (BRK) or overrun Not possible error flag (ORER) Interrupt initiated by transmit FIFO data empty flag (TDFE) Possible Low
An RXI interrupt by setting of the DR flag is available only in asynchronous mode.
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Section 27 Serial Communication Interface with FIFO (SCIF)
27.6
Usage Notes
Note the following when using the SCIF. (1) SCFTDR Writing and the TDFE Flag
The TDFE flag in SCFSR is set when the number of transmit data bytes written in SCFTDR has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in SCFCR. After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again, even after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from SCTFDR. (2) SCFRDR Reading and the RDF Flag
The RDF flag in SCFSR is set when the number of receive data bytes in SCFRDR has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR. After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes read in SCFRDR is equal to or greater than the trigger number, the RDF flag will be set to 1 again even if it is cleared to 0. After the receive data is read, clear the RDF flag readout to 0 in order to reduce the number of data bytes in SCFRDR to less than the trigger number. The number of receive data bytes in SCFRDR can be found from SCRFDR. (3) Break Detection and Processing
If a framing error (FER) is detected, break signals can also be detected by reading the SCIF_RXD pin value directly. In the break state the input from the SCIF_RXD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Although the SCIF stops transferring receive data to SCFRDR after receiving a break, the receive operation continues.
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Section 27 Serial Communication Interface with FIFO (SCIF)
(4)
Sending a Break Signal
The input/output condition and level of the SCIF_TXD pin are determined by bits SPB2IO and SPB2DT in SCSPTR. This feature can be used to send a break signal. After the serial transmitter is initialized and until the TE bit is set to 1 (enabling transmission), the SCIF_TXD pin function is not selected and the value of the SPB2DT bit substitutes for the mark state. The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high level) in the beginning. To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), and then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized, regardless of the current transmission state, and 0 is output from the SCIF_TXD pin. (5) Receive Data Sampling Timing and Receive Margin in Asynchronous Mode
In asynchronous mode, the SCIF operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 27.22.
16 clocks 8 clocks
0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5
Base clock
-7.5 clocks Receive data (SCIF_RXD) Start bit
+7.5 clocks D0 D1
Synchronization sampling timing
Data sampling timing
Figure 27.22 Receive Data Sampling Timing in Asynchronous Mode
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Section 27 Serial Communication Interface with FIFO (SCIF)
Thus, the reception margin in asynchronous mode is given by formula (1).
M= (0.5 1 2N ) - (L - 0.5) F | D - 0.5 | (1 + F) x 100 % .................. (1) N
M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0) L: F: Frame length (L = 9 to 12) Absolute value of clock rate deviation
From equation (1), if F = 0 and D = 0.5, the reception margin is 46.875%, as given by formula (2). When D = 0.5 and F = 0:
M = (0.5 - 1 / (2 x 16) ) x 100% = 46.875% ............................................... (2)
However, this is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. (6) When Using the DMAC
When using an external clock as the synchronization clock, after SCFTDR is updated by the DMAC, an external clock should be input after at least five peripheral clock (Pck) cycles. A malfunction may occur when the transfer clock is input within four cycles after updating SCFTDR (see figure 27.23).
SCIF_CLK
t
TDRE
SCIF_TXD
D0
D1
D2
D3
D4
D5
D6
D7
Note: When the SCIF is operated on an external clock, set t > 4.
Figure 27.23 Example of Synchronization Clock Transfer by DMAC
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Section 27 Serial Communication Interface with FIFO (SCIF)
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
This LSI is equipped with a serial communication interface with FIFO/IrDA interface (SCIF/IrDA) that supports the infrared data communication function. The SCIF/IrDA consists of a serial communication interface with built-in FIFO buffers (SCIF) and infrared communication data modulation/demodulation units. By specifying the IrDA input/output options, infrared data communication can be performed with the infrared sensor/emitter in the same way as the synchronous serial data communication. The SCIF/IrDA uses channel 2 (SCIF2) as a serial communication channel. Note that some part of the operating specification differs from that of channel 0 and 1 (SCIF0, SCIF1) in the serial communication interface with FIFO (SCIF).
28.1
Features
The SCIF/IrDA has the following features. * Infrared data communication function Infrared data communication compliant with the IrDA standard 1.0 can be performed. This function modulates and demodulates the data format supported by serial communication to the data format supported by infrared data communication. * Asynchronous serial communication mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). There is a choice of 8 serial data transfer formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even/odd/none Receive error detection: Parity, framing, and overrun errors Break detection: A break is detected when a framing error lasts for more than 1 frame length at Space 0 (low level). When a framing error occurs, a break can also be detected by reading the SCIF2_RXD pin level directly from the serial port register (SCSPTR).
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
* Clocked synchronous serial communication mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other LSIs that have a synchronous communication function. There is a single serial data communication format. Data length: 8 bits Receive error detection: Overrun errors * Full-duplex communication capability The transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling continuous serial data transmission and reception. * The LSB is transmitted and received first (LSB first). * On-chip baud rate generator allows any bit rate to be selected. * Choice of clock source: internal clock from the baud rate generator based on the peripheral clock (Pck0) or external clock from the SCIF2_SCK pin * Four interrupt sources There are four interrupt sources--transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error--that can issue requests independently. * The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt. * The amount of data in the transmit/receive FIFO registers, and the number of receive errors in the receive data in the receive FIFO register, can be ascertained. * In asynchronous mode, a timeout error (DR) can be detected during reception.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Figure 28.1 shows a block diagram of the SCIF/IrDA. Figures 28.2 to 28.4 show block diagrams of the I/O ports in SCIF/IrDA.
Peripheral bus
Pck0 Pck0/4 Pck0/16 Pck0/64 TXI2 RXI2 ERI2 BRI2 External clock SCIF/IrDA [Legend] SCRSR2: SCFRDR2: SCTSR2: SCFTDR2: SCSMR2: SCSCR2: SCFSR2: Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register Serial status register SCBRR2: SCSPTR2: SCFCR2: SCLSR2: BRGDL2: BRGCKS2: SCSMRIR: Bit rate register Serial port register FIFO control register Line status register BRG frequency division register BRG clock select register IrDA serial mode register
Module data bus
SCSMRIR Infrared data communication interface
SCIF2_RXD
Demodulation unit
SCFRDR2 16-stage
SCFTDR2 16-stage
SCRSR2
SCTSR2
SCIF2_TXD Modulation unit
SCSMR2 SCLSR2 SCTFDR2 SCRFDR2 SCFCR2 SCFSR2 SCSCR2 SCSPTR2 SCRER2 Transmit/ receive control
SCBRR2
Baud rate generator
IrDA BRGDL2 BRGCKS2
Baud rate generator for external clock (BRG)
Parity generation Parity check
Clock
SCIF2_SCK
Figure 28.1 Block Diagram of SCIF/IrDA
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Bus interface
Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Figures 28.2 to 28.4 show block diagrams of the I/O ports in SCIF/IrDA.
Reset R D3 Q D SCKIO C Peripheral bus SPTRW SCIF2_CLK Reset R D2 Q D SCKDT C SPTRW Clock output enable signal* Serial clock output signal* Serial clock input signal* Serial clock input enable signal*
K
SPTRR SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Note: * The SCIF2_CLK pin function is designated as internal clock output or external clock input by the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR.
Figure 28.2 SCIF2_SCK Pin
Reset Q R C Peripheral bus SPTRW D D1
SPB2IO
SCIF2_TXD
Reset Q R D C SPTRW
Transmit enable signal Serial tansmit data
D0
SPB2DT
SPTRW: Write to SCSPTR
Figure 28.3 SCIF2_TXD Pin
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
SCIF2_RXD Serial receive data
Peripheral bus SPTRR SPTRR: Read from SCSPTR
Figure 28.4 SCIF2_RXD Pin
28.2
Input/Output Pins
Table 28.1 shows the SCIF/IrDA pin configuration. The channel number is omitted in the description below. Table 28.1 Pin Configuration
Pin Name SCIF2_SCK SCIF2_RXD SCIF2_TXD Function Serial clock pin Receive data pin Transmit data pin I/O I/O* Input Output Description Clock input/output Receive data input Transmit data output
Notes: These pins are made to function as serial pins by performing SCIF operation settings with the C/A bit in SCSMR, and the TE, RE, CKE1, and CKE0 bits in SCSCR. Break state transmission and detection can be set in SCSPTR of the SCIF. * When the infrared data communication function is selected, a serial clock should be input at the SCIF2_SCK pin
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3
Register Descriptions
Table 28.2 shows the SCIF/IrDA register configuration. Table 28.3 shows the register states in each operating mode. Table 28.2 Register Configuration
Ch. 2 Register Name Serial mode register 2 Bit rate register 2 Serial control register 2 Abbrev. SCSMR2 SCBRR2 SCSCR2 R/W R/W R/W R/W W R/W* R R/W R R/W R/W*2 R/W
1
P4 Address H'FFE1 0000 H'FFE1 0004 H'FFE1 0008 H'FFE1 000C H'FFE1 0010 H'FFE1 0014 H'FFE1 0018 H'FFE1 001C H'FFE1 0020 H'FFE1 0024 H'FFE1 0030 H'FFE1 0034 H'FFE1 0040
Area 7 Address H'1FE1 0000 H'1FE1 0004 H'1FE1 0008 H'1FE1 000C H'1FE1 0010 H'1FE1 0014 H'1FE10018 H'1FE1 001C H'1FE1 0020 H'1FE1 0024 H'FFE1 0030 H'FFE1 0034 H'FFE1 0040
Size 16 8 16 8 16 8 16 16 16 16 16 16 16
Transmit FIFO data register 2 SCFTDR2 Serial status register 2 Receive FIFO data register 2 FIFO control register 2 FIFO data count register 2 Serial port register 2 Line status register 2 BRG frequency division register BRG clock select register IrDA serial mode register SCFSR2 SCFRDR2 SCFCR2 SCFDR2 SCSPTR2 SCLSR2 BRGDL2
BRGCKS2 R/W SCSMRIR R/W
Notes: 1. To clear the flags, 0s can only be written to bits 7 to 4, 1, and 0. 2. To clear the flag, 0 can only be written to bit 0.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Table 28.3 Register States in each Operation Mode
Ch. Register Name 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Abbrev. SCSMR2 SCBRR2 SCSCR2 Power-on Reset Manual Reset Sleep H'0000 H'FF H'0000 H'0000 H'FF H'0000 Standby
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Transmit FIFO data register 2 SCFTDR2 Undefined Undefined Serial status register 2 Receive FIFO data register 2 FIFO control register 2 FIFO data count register 2 Serial port register 2 Line status register 2 BRG frequency division register BRG clock select register IrDA serial mode register Note: * SCFSR2 H'0060 H'0060
SCFRDR2 Undefined Undefined SCFCR2 SCFDR2 H'0000 H'0000 H'0000 H'0000 H'0000* H'0000 H'0000 H'0000 H'0000
SCSPTR2 H'0000* SCLSR2 BRGDL2 H'0000 H'0000
BRGCKS2 H'0000 SCSMRIR H'0000
Bits 2 and 0 are undefined.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.1
Receive Shift Register (SCRSR)
SCRSR is the register used to receive serial data. The SCIF sets serial data input from the SCIF_RXD pin in SCRSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to SCFRDR, automatically. SCRSR cannot be directly read from and written to by the CPU.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
28.3.2
Receive FIFO Data Register (SCFRDR)
SCFRDR is an 8-bit FIFO register of 16 stages that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for reception, and consecutive receive operations can be performed until SCFRDR is full (16 data bytes). SCFRDR is a read-only register, and cannot be written to by the CPU. If a read is performed when there is no receive data in SCFRDR, an undefined value will be returned. When SCFRDR is full of receive data, subsequent serial data is lost. SCFRDR is undefined at a power-on reset or a manual reset.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
R
R
R
R
R
R
R
R
Rev. 1.00 Oct. 01, 2007 Page 1126 of 1956 REJ09B0256-0100
Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.3
Transmit Shift Register (SCTSR)
SCTSR is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to SCTSR, then sends the data to the SCIF_TXD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR to SCTSR, and transmission started, automatically. SCTSR cannot be directly read from and written to by the CPU.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:

28.3.4
Transmit FIFO Data Register (SCFTDR)
SCFTDR is an 8-bit FIFO register of 16 stages that stores data for serial transmission. If SCTSR is empty when transmit data has been written to SCFTDR, the SCIF transfers the transmit data written in SCFTDR to SCTSR and starts serial transmission. SCFTDR is a write-only register, and cannot be read by the CPU. The next data cannot be written when SCFTDR is filled with 16 bytes of transmit data. Data written in this case is ignored. SCFTDR is undefined at a power-on reset or a manual reset.
Bit: 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 W
Initial value: R/W:
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.5
Serial Mode Register (SCSMR)
SCSMR is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate generator clock source. SCSMR can always be read from and written to by the CPU.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 3 2 0 R 1 0
O/E STOP 0 R/W 0 R/W
CKS1 CKS0 0 R/W 0 R/W
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7
C/A
0
R/W
Communication Mode Selects asynchronous mode or clocked synchronous mode as the SCIF operating mode. 0: Asynchronous mode 1: Clocked synchronous mode
6
CHR
0
R/W
Character Length Selects 7 or 8 bits as the asynchronous mode data length. In clocked synchronous mode, the data length is fixed at 8 bits regardless of the CHR bit setting. When 7-bit data is selected, the MSB (bit 7) of SCFTDR is not transmitted. 0: 8-bit data 1: 7-bit data
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Bit 5
Bit Name PE
Initial Value 0
R/W R/W
Description Parity Enable In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking is performed in reception. In clocked synchronous mode, parity bit addition and checking is disabled regardless of the PE bit setting. 0: Parity bit addition and checking disabled 1: Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit.
4
O/E
0
R/W
Parity Mode Selects either even or odd parity for use in parity addition and checking. In asynchronous mode, the O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking. In clocked synchronous mode or when parity addition and checking is disabled in asynchronous mode, the O/E bit setting is invalid. 0: Even parity 1: Odd parity When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Bit 3
Bit Name STOP
Initial Value 0
R/W R/W
Description Stop Bit Length In asynchronous mode, selects 1 or 2 bits as the stop bit length. The stop bit setting is valid only in asynchronous mode. Since the stop bit is not added in clocked synchronous mode, the STOP bit setting is invalid. 0: 1 stop bit*
1 2
1: 2 stop bits*
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Note: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. 2 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator. The clock source can be selected from Pck0, Pck0/4, Pck0/16, and Pck0/64, according to the setting of bits CKS1 and CKS0. For details of the relationship between clock sources, bit rate register settings, and baud rate, see section 28.3.8, Bit Rate Register (SCBRR). 00: Pck0 clock 01: Pck0/4 clock 10: Pck0/16 clock 11: Pck0/64 clock Note: Pck0 = Peripheral Clock 0
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.6
Serial Control Register (SCSCR)
SCSCR is a register used to enable/disable transmission/reception by SCIF, serial clock output, interrupt requests, and to select transmission/reception clock source for the SCIF. SCSCR can always be read from and written to by the CPU.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 REIE 0 R/W 2 0 R 1 0
CKE1 CKE0 0 R/W 0 R/W
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7
TIE
0
R/W
Transmit Interrupt Enable Enables or disables transmit-FIFO-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCFTDR to SCTSR, the number of data bytes in SCFTDR falls to or below the transmit trigger set number, and the TDFE flag in SCFSR is set to 1. TXI interrupt requests can be cleared using the following methods: Either by reading 1 from the TDFE flag, writing transmit data exceeding the transmit trigger set number to SCFTDR and then clearing the TDFE flag to 0, or by clearing the TIE bit to 0. 0: Transmit-FIFO-data-empty interrupt (TXI) request disabled 1: Transmit-FIFO-data-empty interrupt (TXI) request enabled
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Bit 6
Bit Name RIE
Initial Value 0
R/W R/W
Description Receive Interrupt Enable Enables or disables generation of a receive-data-full interrupt (RXI) request when the RDF flag or DR flag in SCFSR is set to 1, a receive-error interrupt (ERI) request when the ER flag in SCFSR is set to 1, and a break interrupt (BRI) request when the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1. 0: Receive-data-full interrupt (RXI) request, receiveerror interrupt (ERI) request, and break interrupt (BRI) request disabled 1: Receive-data-full interrupt (RXI) request, receiveerror interrupt (ERI) request, and break interrupt (BRI) request enabled Note: An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag, then clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0.
5
TE
0
R/W
Transmit Enable Enables or disables the start of serial transmission by the SCIF. Serial transmission is started when transmit data is written to SCFTDR while the TE bit is set to 1. 0: Transmission disabled 1: Transmission enabled* Note: SCSMR and SCFCR settings must be made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set to 1.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Bit 4
Bit Name RE
Initial Value 0
R/W R/W
Description Receive Enable Enables or disables the start of serial reception by the SCIF. Serial reception is started when a start bit is detected in this state in asynchronous mode or a synchronization clock is input while the RE bit is set to 1. It should be noted that clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER flags, which retain their states. Serial reception begins once the start bit is detected in these states. 0: Reception disabled 1: Reception enabled* Note: * SCSMR and SCFCR settings must be made, the reception format decided, and the receive FIFO reset, before the RE bit is set to 1.
3
REIE
0
R/W
Receive Error Interrupt Enable Enables or disables generation of receive-error interrupt (ERI) and break interrupt (BRI) requests. The REIE bit setting is valid only when the RIE bit is 0. Receive-error interrupt (ERI) and break interrupt (BRI) requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. When REIE is set to 1, ERI and BRI interrupt requests will be generated even if RIE is cleared to 0. In DMAC transfer, this setting is made if the interrupt controller is to be notified of ERI and BRI interrupt requests. 0: Receive-error interrupt (ERI) and break interrupt (BRI) requests disabled 1: Receive-error interrupt (ERI) and break interrupt (BRI) requests enabled
2
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Bit 1 0
Bit Name CKE1 CKE0
Initial Value 0 0
R/W R/W R/W
Description Clock Enable 1, 0 These bits select the SCIF clock source and whether to enable or disable the clock output from the SCIF_SCK pin. The CKE1 and CKE0 bits are used together to specify whether the SCIF_SCK pin functions as a serial clock output pin or a serial clock input pin. Note however that the CKE0 bit setting is valid only when an internal clock is selected as the SCIF clock source (CKE1 = 0). When an external clock is selected (CKE1 = 1), the CKE0 bit setting is invalid. In clock synchronous mode, to select synchronization clock output, set the C/A bit in SCSMR to 1, then set the CKE1 and CKE0 bits. * Asynchronous mode 00: The SCIF_SCK pin is not used. The SCIF_SCK pin functions as an input pin (Input signals are ignored) 01: The SCIF_SCK pin functions as clock output*
1
10: External clock/SCIF_SCK pin functions as clock input*2 11: Setting prohibited * Clocked synchronous mode 00,01: The SCIF_SCK pin functions as synchronization clock output 10: The SCIF_SCK pin functions as synchronization clock input 11: Setting prohibited Notes: X: Don't care 1. Outputs a clock with a frequency 16 times the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.7
Serial Status Register (SCFSR)
SCFSR is a 16-bit register. Its lower 8 bits are a status flag that indicates the operating status of the SCIF and its upper 8 bits indicate the number of errors for data received by the receive FIFO register. SCFSR can be read from or written to by the CPU at all times. However, 1 cannot be written to flags ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they must be read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be modified.
Bit: 15 14 13 12 11 10 9 8 7 ER 0 R 6 5 4 3 FER 0 R 2 PER 0 R 1 RDF 0 DR
PERN[3:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R
FERN[3:0] 0 R 0 R
TEND TDFE BRK
0 1 1 0 R/W*1 R/W*1 R/W*1 R/W*1
0 0 R/W*1 R/W*1
Bit 15 to 12
Bit Name PERN[3:0]
Initial Value All 0
R/W R
Description Number of Parity Errors These bits indicate the number of parity errors in data received and stored in SCFRDR. After the ER bit in SCFSR is set, the value indicated by bits 15 to 12 is the number of parity errors. If a parity error occurs in all 16-byte data received by SCFRDR, PERN indicates 0. Number of Framing Errors These bits indicate the number of framing errors in data received and stored in SCFRDR. After the ER bit in SCFSR is set, the value indicated by bits 11 to 8 is the number of framing errors. If a framing error occurs in all 16-byte data received by SCFRDR, FERN indicates 0.
11 to 8
FERN[3:0]
All 0
R
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Bit 7
Bit Name ER
Initial Value 0
R/W
1
Description
6
TEND
1
R/W* Receive Error Indicates that a framing error or parity error occurred during reception. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR, and reception continues. The FER and PER bits in SCFSR can be used to determine whether there is a receive error in the readout data from SCFRDR. 0: No framing error or parity error occurred during reception [Clearing conditions] * Power-on reset or manual reset * When 0 is written to ER after reading ER = 1 1: A framing error or parity error occurred during reception [Setting conditions] * When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends, 2 and the stop bit is 0* * When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SCSMR 1 R/W* Transmit End Indicates that transmission has been ended without valid data in SCFTDR after transmission of the last bit of the transmit character. 0: Transmission is in progress [Clearing conditions] * When transmit data is written to SCFTDR, and 0 is written to TEND after reading TEND = 1 * When data is written to SCFTDR by the DMAC 1: Transmission has been ended [Setting conditions] * Power-on reset or manual reset * When the TE bit in SCSCR is 0 * When there is no transmit data in SCFTDR after transmission of the last bit of a 1-byte serial transmit character
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Bit 5
Bit Name TDFE
Initial Value 1
R/W
1
Description
R/W* Transmit FIFO Data Empty Indicates that data has been transferred from SCFTDR to SCTSR, the number of data bytes in SCFTDR has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in SCFCR, and new transmit data can be written to SCFTDR. 0: A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR [Clearing conditions] * When transmit data exceeding the transmit trigger set number is written to SCFTDR after reading TDFE = 1, and 0 is written to TDFE When transmit data exceeding the transmit trigger set number is written to SCFTDR by the DMAC
*
1: The number of transmit data bytes in SCFTDR does not exceed the transmit trigger set number (Initial value) [Setting conditions] * * Power-on reset or manual reset When the number of SCFTDR transmit data bytes falls to or below the transmit trigger set number as 3 the result of a transmit operation*
4
BRK
0
R/W*1 Break Detect Indicates that a receive data break signal has been detected. 0: A break signal has not been received [Clearing conditions] * * Power-on reset or manual reset When 0 is written to BRK after reading BRK = 1
4
1: A break signal has been received* [Setting condition] *
When data with a framing error is received, followed by the space "0" level (low level ) for at least one frame length
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Bit 3
Bit Name FER
Initial Value 0
R/W R
Description Framing Error In asynchronous mode, indicates whether or not a framing error has been found in the data that is to be read next from SCFRDR. 0: There is no framing error that is to be read from SCFRDR [Clearing conditions] * * Power-on reset or manual reset When there is no framing error in the data that is to be read next from SCFRDR
1: There is a framing error that is to be read from SCFRDR [Setting condition] * 2 PER 0 R When there is a framing error in the data that is to be read next from SCFRDR
Parity Error In asynchronous mode, indicates whether or not a parity error has been found in the data that is to be read next from SCFRDR. 0: There is no parity error that is to be read from SCFRDR [Clearing conditions] * * Power-on reset or manual reset When there is no parity error in the data that is to be read next from SCFRDR
1: There is a parity error in the receive data that is to be read from SCFRDR [Setting condition] * When there is a parity error in the data that is to be read next from SCFRDR
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Bit 1
Bit Name RDF
Initial Value 0
R/W
1
Description
R/W* Receive FIFO Data Full Indicates that the received data has been transferred from SCRSR to SCFRDR, and the number of receive data bytes in SCFRDR is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR. 0: The number of receive data bytes in SCFRDR is less than the receive trigger set number [Clearing conditions] * * Power-on reset or manual reset When SCFRDR is read until the number of receive data bytes in SCFRDR falls below the receive trigger set number after reading RDF = 1, and 0 is written to RDF When SCFRDR is read by the DMAC until the number of receive data bytes in SCFRDR falls below the receive trigger set number
*
1: The number of receive data bytes in SCFRDR is equal to or greater than the receive trigger set number [Setting condition] * When SCFRDR contains at least the receive trigger 5 set number of receive data bytes*
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Bit 0
Bit Name DR
Initial Value 0
R/W
1
Description In asynchronous mode, indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR, and no further data has arrived for at least 15 etu after the stop bit of the last data received. This is not set when using clocked synchronous mode. 0: Reception is in progress or has ended normally and there is no receive data left in SCFRDR [Clearing conditions] * * * Power-on reset or manual reset When all the receive data in SCFRDR has been read after reading DR = 1, and 0 is written to DR When all the receive data in SCFRDR has been read by the DMAC
R/W* Receive Data Ready
1: No further receive data has arrived [Setting condition] * When SCFRDR contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received*6
[Legend] etu: Elementary time unit (time for transfer of 1 bit) Notes: 1. Only 0 can be written, to clear the flag. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. 3. As SCFTDR is a 16-byte FIFO register, the maximum number of bytes that can be written when TDFE = 1 is 16 - (transmit trigger set number). Data written in excess of this will be ignored. SCFDR indicates the number of data bytes transmitted to SCFTDR. 4. When a break is detected, the receive data (H'00) following detection is not transferred to SCFRDR. When the break ends and the receive signal returns to mark "1", receive data transfer is resumed. 5. SCFRDR is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If all the data in SCFRDR is read and another read is performed, the data value will be undefined. The number of receive data bytes in SCFRDR is indicated by SCFDR. 6. Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format.
Rev. 1.00 Oct. 01, 2007 Page 1140 of 1956 REJ09B0256-0100
Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.8
Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that set the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR. SCBRR can always be read from and written to by the CPU. This baud rate generator is intended for Pck0, Pck0/4, Pck0/16, and Pck0/64. For details on the baud rate generator for external clock, see section 28.6, Baud Rate Generator for External Clock (BRG). The SCBRR setting is found from the following equation. Asynchronous mode:
N=
Pck0 64 x 22n - 1 x B x 106 - 1
Clocked synchronous mode:
N=
Pck0 8 x 22n - 1 x B x 106 - 1
Where B: Bit rate (bits/s) N: SCBRR setting for baud rate generator (0 N 255) Pck0: Peripheral module operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See Table 28.4 for the relation between n and the clock.) Table 28.4 SCSMR Settings
SCSMR Setting n 0 1 2 3 Clock Pck0 Pck0/4 Pck0/16 Pck0/64 CKS1 0 0 1 1 CKS0 0 1 0 1
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
The bit rate error in asynchronous mode is found from the following equation:
Error (%) =
Pck0 x 106 -1 (N + 1) x B x 64 x 22n - 1
x 100
28.3.9
FIFO Control Register (SCFCR)
SCFCR performs data count resetting and trigger data number setting for transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR can always be read from and written to by the CPU.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 6 5 4 3 0 R 2 1 0
RTRG[1:0] 0 R/W 0 R/W
TTRG[1:0] 0 R/W 0 R/W
TFCL RFCL LOOP 0 R/W 0 R/W 0 R/W
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7, 6
RTRG[1:0]
All 0
R/W
Receive FIFO Data Number Trigger These bits are used to set the number of receive data bytes that sets the RDF flag in SCFSR. The RDF flag is set when the number of receive data bytes in SCFRDR is equal to or greater than the trigger set number shown below.
Asynchronous mode Clock Synchronous mode
00: 01: 10: 11:
1 4 8 14
1 2 8 14
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Bit 5, 4
Bit Name TTRG[1:0]
Initial Value All 0
R/W R/W
Description Transmit FIFO Data Number Trigger These bits are used to set the number of remaining transmit data bytes that sets the TDFE flag in SCFSR. The TDFE flag is set when the number of transmit data bytes in SCFTDR is equal to or less than the trigger set number shown below. 00: 8 (8)* 01:4 (12) 10: 2 (14) 11: 0 (16) Note: * Figures in parentheses are the number of empty bytes in SCFTDR when the flag is set.
3
--
0
R
Reserved These bits are always read as 0. The write value should always be 0.
2
TFRST
0
R/W
Transmit FIFO Data Register Reset Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * A reset operation is performed in the event of a power-on reset or manual reset.
1
RFRST
0
R/W
Receive FIFO Data Register Reset Invalidates the receive data in the receive FIFO data register and resets it to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * A reset operation is performed in the event of a power-on reset or manual reset.
0
LOOP
0
R/W
Loopback Test Internally connects the transmit output pin (SCIF_TXD) and receive input pin (SCIF_RXD) enabling loopback testing. 0: Loopback test disabled 1: Loopback test enabled
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.10 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit register that indicates the number of transmit data bytes stored in SCFTDR. SCFDR can always be read from the CPU.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 0 R 0 R 12 11 10 TDN[4:0] 0 R 0 R 0 R 9 8 7 0 R 6 0 R 5 0 R 0 R 0 R 4 3 2 RDN[4:0] 0 R 0 R 0 R 1 0
Bit 15 to 13
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
12 to 8
TDN[4:0]
All 0
R
These bits show the number of untransmitted data bytes in SCFTDR. A value of H'00 indicates that there is no transmit data, and a value of H'10 indicates that SCFTDR is full of transmit data (16-bytes). Reserved These bits are always read as 0. The write value should always be 0.
7 to 5
--
All 0
R
4 to 0
RDN[4:0]
All 0
R
These bits show the number of receive data bytes in SCFRDR. A value of H'00 indicates that there is no receive data, and a value of H'10 indicates that SCFRDR is full of receive data (16-bytes).
Rev. 1.00 Oct. 01, 2007 Page 1144 of 1956 REJ09B0256-0100
Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.11 Serial Port Register (SCSPTR) SCSPTR is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins at all times. Input data can be read from the SCIF_RXD pin, output data written to the SCIF_TXD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. All SCSPTR bits except bits 6, 4, 2, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, 2, and 0 is undefined. SCSPTR is not initialized in the module standby state.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3
SCK IO
2
SCK DT
1
SPB2 IO
0
SPB2 DT
0 R/W
R/W
0 R/W
R/W
Bit 15 to 4
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
3
SCKIO
0
R/W
Serial Port Clock Port Input/Output Specifies the serial port SCIF_SCK pin input/output condition. When actually setting the SCIF_SCK pin as a port output pin to output the value set by the SCKDT bit, the CKE1 and CKE0 bits in SCSCR should be cleared to 0. 0: SCKDT bit value is not output to SCIF_SCK pin 1: SCKDT bit value is output to SCIF_SCK pin
2
SCKDT
--
R/W
Serial Port Clock Port Data Specifies the serial port SCIF_SCK pin input/output data. Input or output is specified by the SCKIO bit. In output mode, the SCKDT bit value is output to the SCIF_SCK pin. The SCIF_SCK pin value is read from the SCKDT bit regardless of the value of the SCKIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. 0: Input/output data is low-level 1: Input/output data is high-level
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Bit 1
Bit Name SPB2IO
Initial Value 0
R/W R/W
Description Serial Port Break Input/Output Specifies the serial port SCIF_TXD pin output condition. When actually setting the SCIF_TXD pin as a port output pin to output the value set by the SPB2DT bit, the TE bit in SCSCR should be cleared to 0. 0: SPB2DT bit value is not output to the SCIF_TXD pin 1: SPB2DT bit value is output to the SCIF_TXD pin
0
SPB2DT
--
R/W
Serial Port Break Data Specifies the serial port SCIF_RXD pin input data and SCIF_TXD pin output data. The SCIF_TXD pin output condition is specified by the SPB2IO bit. When the SCIF_TXD pin is designated as an output, the value of the SPB2DT bit is output to the SCIF_TXD pin. The SCIF_RXD pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. 0: Input/output data is low-level 1: Input/output data is high-level
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.12 Line Status Register (SCLSR)
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 ORER 0 R/W*1
Bit 15 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
ORER
0
R/W*1 Overrun Error Indicates that an overrun error occurred during reception, causing abnormal termination. 0: Reception in progress, or reception has ended 2 normally* [Clearing conditions] * * Power-on reset or manual reset When 0 is written to ORER after reading ORER = 1
1: An overrun error occurred during reception*3 [Setting condition] * When the next serial reception is completed while SCFRDR receives 16-byte data (SCFRDR is full)
Notes: 1. Only 0 can be written, to clear the flag. 2. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. 3. The receive data prior to the overrun error is retained in SCFRDR, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. To resume data reception after clearing the ORER flag, be sure to first read (or clear) data in the receive FIFO and handle the error, then clear the ORER flag.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.13 BRG Frequency Division Register (BRGDL2) BRGDR2 specifies the division ratio of the division clocks generated by the BRG. The clock division ratio set in this register can be determined with the following equation. Clock division ratio = clock input frequency/(required baud rate x 16) Table 28.5 shows the clock division ratios when a 3.686 MHz crystal resonator is used.
BIt: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRGDL[15:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 15 to 0
Bit Name BRGDL [15:0]
Initial Value All 0
R/W R/W
Description Division Ratio of BRG Generated Clock These bits specify the division ratio of the division clocks generated by the BRG. A division ratio from 1 to 65535 can be specified.
Table 28.5 Baud Rate (3.6864 MHz Clock)
Baud Rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 Division Ratio 4608 3072 2095 1713 1536 768 384 192 128 115 96 64 Error Rate* -0.022 0.001 0.174
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Baud Rate 4800 7200 9600 14400 19200 38400 76800 115200 Note: * : Error rate = 0
Division Ratio 48 32 24 16 12 6 3 2
Error Rate*
28.3.14 BRG Clock Select Register (BRGCKS2)
BRGCKS2 switches output clock between the division clock generated by the BRG and the external clock (SCIF2_SCK).
Bit: 15
BRG CKS
14 0 R
13 0 R
12 0 R
11 0 R
10 0 R
9 0 R
8 0 R
7 0 R
6 0 R
5 0 R
4 0 R
3 0 R
2 0 R
1 0 R
0 0 R
Initial value: R/W:
0 R/W
Bit 15
Bit Name BRGCKS
Initial Value 0
R/W R/W
Description Switches output clock between the division clock and external clock (SCIF2_SCK). 0: Selects division clock 1: Selects external clock
14 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.15 IrDA Serial Mode Register (SCSMRIR) SCSMRIR is used for control when channel 2 (SCIF2) of the SCIF/IrDA is used as the IrDA infrared communication port.
Bit: 31 Initial value: R/W: BIt: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9
EDGEN
24 0 R 8
LOOP
23 0 R 7
IRMOD
22 0 R 6 0 R
21 0 R 5 0 R
20 0 R 4 0 R
19 0 R 3 0 R
18 0 R 2 0 R
17 0 R 1 0 R
16 0 R 0 0 R
0 R/W
0 R/W
0 R/W
Bit 31 to 10
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
9
EDGEN
0
R/W
SCIF2_RXD Pin Sampling Mode 0: The SCIF2_RXD pin is sample by an edge 1: The SCIF2_RXD pin is sample by both an edge and level
8
LOOP
0
R/W
IrDA Loop back Test 0: Normal operation 1: Loop back operation from the SCIF2_TXD pin to the SCIF2_RXD pin
7
IRMOD
0
R/W
IrDA Mode 0: SCIF2 of the SCIF/IrDA is used as the SCIF serial communication port 1: SCIF2 of the SCIF/IrDA is used as the IrDA infrared communication port
6 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.4
28.4.1
Operation
Overview
The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character and in synchronous mode, in which synchronization is achieved with clock pulses. For details on asynchronous mode, see section 28.4.2, Operation in Asynchronous Mode. 16-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead, and enabling fast and continuous communication to be performed. The serial transfer format is selected using SCSMR, as shown in Table 28.6. The SCIF clock source is determined by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR, as shown in Table 28.7. Asynchronous Mode: * Data length: Choice of 7 or 8 bits * Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receivedata-ready state, and breaks, during reception * Indication of the number of data bytes stored in the transmit and receive FIFO registers * Choice of peripheral clock 0 (Pck0) or external clock (SCIF_SCK) as SCIF clock source When peripheral clock 0 (Pck0) is selected: The SCIF operates on the baud rate generator clock and can output a clock with frequency of 16 times the bit rate. When external clock (SCIF_SCK) is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used).
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Clocked Synchronous Mode: * Data length: Fixed at 8 bits * Detection of overrun errors during reception * Choice of peripheral clock 0 (Pck0) or external clock (SCIF_SCK) as SCIF clock source When peripheral clock 0 (Pck0) is selected: The SCIF operates on the baud rate generator clock and a serial clock is output to external devices. When external clock (SCIF_SCK) is selected: The on-chip baud rate generator is not used and the SCIF operates on the input serial clock. Table 28.6 SCSMR Settings for Serial Transfer Format Selection
SCSMR Settings Bit 7: C/A 0 Bit 6: CHR 0 Bit 5: PE 0 Bit 3: STOP 0 1 1 0 1 1 0 0 1 1 0 1 1 x x x Clocked synchronous mode 8-bit data No Yes 7-bit data No Yes Mode Asynchronous mode SCIF Transfer Format Data Length 8-bit data Parity Bit No Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits No
Note: x: Don't care
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Table 28.7 SCSMR and SCSCR Settings for SCIF Clock Source Selection
SCSMR SCSCR Setting Bit 7 C/A 0 Bit 1 CKE1 0 Bit 0 CKE0 0 Mode Clock Source Description of SCK Pin The SCK pin is not used. The SCK pin functions as an input pin (Input signals are ignored). (Initial value) The SCK pin outputs the clock (with a frequency 16 times the bit rate). Input SC_CLK to baud rate generator for external clock (SCIF_CLK, Pck0) or SCK (switched by baud rate generator's CKS register) The SCK pin inputs the clock (with a frequency 16 times the bit rate). When SC_CLK is selected, the SCK pin inputs the clock (Input signals are ignored). Set the SCK input or SC_CLK so that the frequency of BRGCLK is 16 times the bit rate. When selecting SC_CLK, set the frequency of SC_CLK and DL, or when selecting SCK, adjust the frequency of the SCK input to make the frequency of BRGCLK 16 times the bit rate. 1 1 0 1 0 1 Prohibited Clock synchronous -- Internal clock Pck0, Pck0/4, Pck0/16, Pck0/64 -- The SCK pin outputs the synchronization clock. The SCK pin outputs the synchronization clock.
Asynchronous Internal clock Pck0, Pck0/4, Pck0/16, Pck0/64
1
1
0
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
SCSMR SCSCR Setting Bit 7 C/A 1 Bit 1 CKE1 1 Bit 0 CKE0 0 Mode Clock synchronous Clock Source SCK input (switched by baud rate generator's CKS register) Description of SCK Pin The SCK pin outputs the synchronization clock.
Input SC_CLK to SC_CLK cannot be used as an baud rate input clock for synchronous generator for communication. external clock (SCIF_CLK, Pck0) 1 1 Prohibited -- --
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.4.2
Operation in Asynchronous Mode
In asynchronous mode, a character that consists of data with a start bit indicating the start of communication and a stop bit indicating the end of communication is transmitted or received. In this mode, serial communication is performed with synchronization achieved character by character. Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and receiver have a 16-stage FIFO buffer structure, so that data can be read or written during transmission or reception, enabling continuous data transmission and reception. Figure 28.5 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCIF monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One character in serial communication consists of a start bit (low level), followed by transmit/receive data (LSB-first; from the lowest bit), a parity bit (high or low level), and finally stop bits (high level). In reception in asynchronous mode, the SCIF synchronizes with the fall of the start bit. Receive data can be latched at the middle of each bit because the SCIF samples data at the eighth clock which has a frequency of 16 times the bit rate.
Idle state (mark state) 1
0/1
Parity bit 1 bit or none
1
Serial data
LSB 0 Start bit
1 bit
MSB
D1 D2 D3 D4 D5 D6 D7 1 1
D0
Stop bit
Transmit/receive data
7 or 8 bits
1 or 2 bits
One unit of transfer data (character or frame)
Figure 28.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, and Two Stop Bits)
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(1)
Data Transfer Format
Table 28.8 shows the data transfer formats that can be used. Any of 8 transfer formats can be selected according to the SCSMR settings. Table 28.8 Serial Transfer Formats (Asynchronous Mode)
SCSMR Settings
CHR PE 0 0 STOP 0 1 S 2
Serial Transfer Format and Frame Length
3 4 5 8-bit data 6 7 8 9 10
STOP
11
12
0
0
1
S
8-bit data
STOP STOP
0
1
0
S
8-bit data
P
STOP
0
1
1
S
8-bit data
P
STOP STOP
1
0
0
S
7-bit data
STOP
1
0
1
S
7-bit data
STOP STOP
1
1
0
S
7-bit data
P
STOP
1
1
1
S
7-bit data
P
STOP STOP
[Legend] S : Start bit STOP : Stop bit P : Parity bit
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(2)
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCIF_SCK pin can be selected as the SCIF's serial clock, according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source selection, see Table 28.5. When an external clock is input at the SCIF_SCK pin, the clock frequency should be 16 times the bit rate used. When the SCIF is operated on an internal clock, a clock whose frequency is 16 times the bit rate is output from the SCIF_SCK pin. (3) SCIF Initialization (Asynchronous Mode)
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0, then initialize the SCIF as described below. When the operating mode or transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. 1. 2. When the TE bit is cleared to 0, SCTSR is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR, SCFTDR, or SCFRDR. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in SCFSR has been set. TEND can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state after the clearance. Before setting TE again to start transmission, the TFRST bit in SCFCR should first be set to 1 to reset SCFTDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case.
3.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Figure 28.6 shows a sample SCIF initialization flowchart.
Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFCL and RFCL bits in SCFCR to 1
Read flags of ER, DR, and BRK in SCFSR and ORER in SCLSR, then clear them to 0
[1] Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0. [2] Set the data transfer format in SCSMR. [3] Write a value corresponding to the bit rate into SCBRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE bit or RE bit in SCSCR to 1. Also set the RIE, REIE, and TIE bits. Setting the TE and RE bits enables the SCIF_TXD and SCIF_RXD pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit.
Set CKE1 and CKE0 bits in SCSCR (leaving TE, RE, TIE, and RIE bits cleared to 0) Set data transfer format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Yes Set RTRG1-0, TTRG1-0 bits, and MCE in SCFCR, and clear TFCL and RFCL bits to 0 Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits
[1]
[2]
[3]
No
[4]
End of initialization
Figure 28.6 Sample SCIF Initialization Flowchart
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(4)
Serial Data Transmission (Asynchronous Mode):
Figure 28.7 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Start of transmission
[1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE and TEND flags to 0. The number of transmit data bytes that can be written is 16 - (transmit trigger set number). [2] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0. [3] Break output at the end of serial transmission: To output a break in serial transmission, clear the SPB2DT bit to 0 and set the SPB2IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR to 0. No In [1] and [2], it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR indicated by SCFDR.
Read TDFE flag in SCFSR
No
TDFE = 1?
Yes
Write transmit data in SCFTDR
No
[1]
All data transmitted?
Yes
[2]
Read TEND flag in SCFSR
TEND = 1? Yes Break output? Yes Clear SPB2DT to 0 and set SPB2IO to 1 Clear TE bit in SCSCR to 0
No
[3]
End of transmission
Figure 28.7 Sample Serial Transmission Flowchart
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmitting. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is at least 16 - (transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls to or below the transmit trigger number set in SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFOdata-empty interrupt (TXI) request is generated. The serial transmit data is sent from the SCIF_TXD pin in the following order. (a) Start bit: One 0-bit is output. (b) Transmit data: 8-bit or 7-bit data is output in LSB-first order. (c) Parity bit: One parity bit (even or odd parity) is output. A format in which a parity bit is not output can also be selected. (d) Stop bit(s): One or two 1-bits (stop bits) are output. (e) Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data after the stop bit is sent, the TEND flag in SCFSR is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output from the SCIF_TXD pin.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Figure 28.8 shows an example of the operation for transmission in asynchronous mode.
Start bit Data Parity Stop Start bit bit bit Data Parity Stop bit bit D7 0/1 1
1
Serial data SCIF_TXD TDFE flag
1 Idle state (mark state)
0
D0
D1
D7
0/1
1
0
D0
D1
TEND flag TXI interrupt Data written to SCFTDR and TDFE flag read as 1 request then cleared to 0 by TXI interrupt handler One frame TXI interrupt request
Figure 28.8 Sample SCIF Transmission Operation (Example with 8-Bit Data, Parity, One Stop Bit)
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(5)
Serial Data Reception (Asynchronous Mode)
Figures 28.9 and 28.10 shows a sample flowcharts for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception.
[1] Receive error handling and break detection: Read the DR, ER, and BRKflags in SCFSR, and the ORER flag in SCLSR, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In thecase of a framing error, a break can also be detected by reading the value of the SCIF_RXD pin. [2] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading from SCFDR.
Start of reception
Read ER, DR, BRK flags in SCFSR and ORER flag in SCLSR
[1]
ER, DR, BRK or ORER = 1? No Read RDF flag in SCFSR No
Yes
Error handling [2]
RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0
No
All data received? Yes Clear RE bit in SCSCR to 0 End of reception
[3]
Figure 28.9 Sample Serial Reception Flowchart (1)
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Error handling No [1] Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in SCFSR.
ORER = 1? Yes Overrun error handling
No
ER = 1? Yes Receive error handling
No
BRK = 1? Yes Break handling
No
DR = 1? Yes Read receive data in SCFRDR
Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR, to 0
End
Figure 28.10 Sample Serial Reception Flowchart (2)
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0-start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. (a) Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. (b) The SCIF checks whether receive data can be transferred from SCRSR to SCFRDR.* (c) Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun error has occurred.* (d) Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set.* If (b), (c), and (d) checks are passed, the receive data is stored in SCFRDR. Note: * Reception continues even when a parity error or framing error occurs. 4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Figure 28.11 shows an example of the operation for reception in asynchronous mode.
Start bit Data Parity Stop Start bit bit bit Data Parity Stop bit bit
1
Serial data SCIF_RXD
RDF flag
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
0
0/1 Detect flaming error
FER flag
RXI interrupt request
One frame
Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler
ERI interrupt request generated by receive error
Figure 28.11 Sample SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 28.4.3 Operation in Clocked Synchronous Mode
Clocked synchronous mode, in which data is transmitted or received in synchronization with clock pulses, is suitable for fast serial communication. Since the transmitter and receiver are independent units in the SCIF, full-duplex communication can be achieved by sharing the clock. Both the transmitter and receiver have a 16-stage FIFO buffer structure, so that data can be read or written during transmission or reception, enabling continuous data transfer and reception. Figure 28.12 shows the general format for clocked synchronous communication.
One unit of transfer data (character or frame)
*
*
Synchronization clock
LSB
MSB
Serial data
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don't care
Note: * High except in continuous transfer/reciver.
Don't care
Figure 28.12 Data Format in Clocked Synchronous Communication
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
In clocked synchronous serial communication, data on the communication line is output from one fall of the synchronization clock to the next fall. Data is guaranteed to be accurate at the start of the synchronization clock. In serial communication, each character is output starting with the LSB and ending with the MSB. After the MSB is output, the communication line remains in the state of the last data. In clocked synchronous mode, the SCIF receives data in synchronization with the rise of the synchronization clock. (1) Data Transfer Format
A fixed 8-bit data format is used. No parity bit can be added. (2) Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCIF_SCK pin can be selected as the SCIF's serial clock, according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source selection, see table 28.7. When the SCIF is operated on an internal clock, the synchronization clock is output from the SCIF_SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When an internal clock is selected in a receive operation only, as long as the RE bit in SCSCR is set to 1, clock pulses are output until the number of receive data bytes in the receive FIFO data register reaches the receive trigger number. (3) SCIF Initialization (Clocked Synchronous Mode):
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0, then initialize the SCIF as described below. When changing the operating mode or transfer format, etc., the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, SCTSR is initialized. Note that clearing the RE bit to 0 does not initialize the RDF, PER, FER, or ORER flag state or change the contents of SCFRDR.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Figure 28.13 shows a sample SCIF initialization flowchart.
Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFCL and RFCL bits in SCFCR to 1 to clear the FIFO buffer After reading BRK, DR, and ER flags in SCFSR, and ORER flag in SCLSR, write 0 to clear them Set CKE1 and CKE0 bits in SCSCR (leaving TE, RE, TIE, and RIE bits cleared to 0) Set data transfer format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Yes Set RTRG1-0 and TTRG1-0 bits in SCFCR, and clear TFCL and RFCL bits to 0 Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits No
[1]
[1] Leave the TE and RE bits cleared to 0 until the initialization almost ends.
[2] Set the CKE1 and CKE0 bits. [3] Set the data transfer/receive format in SCSMR. [4] Write a value corresponding to the bit rate into SCBRR. This is not necessary if an external clock is used. Wait at least one bit interval after this write before moving to the next step. [2] [5] Set the TE or RE bit in SCSCR to 1. Also set the TIE, RIE, and REIE bits to enable the SCIF_TXD, SCIF_RXD, and SCIF_CLK pins to be used. When transmitting, the SCIF_TXD pin will go to the mark state. When receiving in clocked synchronous mode with the synchronization clock output (clock master) selected, a clock starts to be output from the SCIFn_SCK pin at this point.
[3]
[4]
[5]
End of initialization
Figure 28.13 Sample SCIF Initialization Flowchart
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(4)
Serial Data Transmission (Clocked Synchronous Mode)
Figure 28.14 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Initialization Start of transmission
[1]
[1] SCIF initialization: See sample SCIF initialization flowchart in figure 28.13. [2] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE flag to 0. [3] Serial transmission continuation procedeure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, them write data to SCFTDR, and then clear the TDFE flag to 0.
Read TDFE flag in SCFSR
No
[2]
TDFE = 1?
Yes
Write transmit data to SCFTDR and clear TDFE flag and TEND flag in SCFSR to 0
No
All data transmitted?
Yes
[3]
Read TEND flag in SCFSR
No
TEND = 1?
Yes
Clear TE bit in SCSCR to 0
End of transmission Note: In clock synchronous mode, when transmit data is written to the SCFTDR by the DMAC, the TEND flag may no be cleared. Therefore, if the DMAC is used for transmission in clock synchronous mode, read the TEND flag in the following method. 1. Confirm data transfer completion on the DMAC side. 2. Read the TEND flag. 3. Clear the TEND flag to 0 when TEND = 1. 4. Read the TEND flag again. 5. Use the TEND flag read for the second time.
Figure 28.14 Sample Serial Transmission Flowchart
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmitting. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is at least 16 (transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls to or below the transmit trigger number set in SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFOdata-empty interrupt (TXI) request is generated. When the external clock is selected, data is output in synchronization with the input clock. The serial transmit data is sent from the SCIF_TXD pin in the LSB-first order. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the last bit. If data is present, the data is transferred from SCFTDR to SCTSR, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1 after the last bit is sent, and the transmit data pin (SCIF_TXD pin) retains the output state of the last bit. 4. After serial transmission ends, the CLK pin is fixed high. Figure 28.15 shows an example of the operation for transmission in clocked synchronous mode.
Synchronization clock SCIF_SCK Serial data SCIF_TXD TDFE flag TEND flag
TXI interrupt request
LSB Bit 0
Bit 1
MSB Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
Data written to SCFTDR and TDFE flag cleared to 0 by TXI interrupt handler
TXI interrupt request
One frame
Figure 28.15 Sample SCIF Transmission Operation in Clocked Synchronous Mode
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(5)
Serial Data Reception (Clocked Synchronous Mode)
Figures 28.16 and 28.17 show a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. When switching the operating mode from asynchronous mode to clocked synchronous mode without initializing the SCIF, make sure that the ORER flag is cleared to 0.
Initialization Start of reception
[1]
[1] SCIF initialization: See Sample SCIF Initialization Flowchart in figure 28.13. [2] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Transmission/reception cannot be resumed while the ORER flag is set to 1.
[2]
Read ORER flag in SCLSR
ORER = 1? No Read RDF flag in SCFSR No
Yes
Error handling [3]
[3] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt.
RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0
[4]
No
All data received? Yes Clear RE bit in SCSCR to 0 End of reception
[4] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading SCFDR. However, as starting up the DMAC using RXI and reading the value of SCFDR automatically clears bit RDF, clearing bit RDF is not required.
Figure 28.16 Sample Serial Reception Flowchart (1)
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Error handling No
ORER = 1? Yes Overrun error handling
Clear ORER flag in SCLSR to 0 End
Figure 28.17 Sample Serial Reception Flowchart (2) In serial reception, the SCIF operates as described below. 1. The SCIF is initialized internally in synchronization with the input or output of the synchronization clock. 2. The received data is stored in SCRSR in LSB-to-MSB order. After receiving the data, the SCIF checks whether the receive data can be transferred from SCRSR to SCFRDR. If this check is passed, the receive data is stored in SCFRDR. If an overrun error is detected in the error check, reception cannot continue. 3. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR is set to 1 when the ORER flag changes to 1, a break interrupt (BRI) request is generated.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Figure 28.18 shows an example of the operation for reception in clocked synchronous mode.
Synchronization clock Serial data SCIF_RXD RDF flag
Bit 7 LSB Bit 0 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
ORER flag
RXI interrupt request
Data read from RXI interrupt SCFRDR and RDF request flag cleared to 0 by RXI interrupt handler
BRI interrupt request by overrun error
One frame
Figure 28.18 Sample SCIF Reception Operation in Clocked Synchronous Mode
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(6)
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
Figure 28.19 shows a sample flowchart for simultaneous serial data transmission and reception. Use the following procedure for simultaneous serial transmission and reception after enabling the SCIF for both transmission and reception.
Initialization Start of transmission and reception [1] [1] SCIF initialization: See Sample SCIF Initialization Flowchart in figure 28.13. [2] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE flag to 0. The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Transmission/reception cannot be resumed while the ORER flag is set to 1. [4] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission and reception continuation procedure: To continue serial transmission and reception, read 1 from the RDF flag and the receive data in SCFRDR, and clear the RDF flag to 0 before receiving the MSB in the current frame. Similarly, read 1 from the TDFE flag to confirm that writing is possible before transmitting the MSB in the current frame. Then write data to SCFTDR and clear the TDFE flag to 0.
Read TDFE flag in SCFSR No
[2]
TDFE = 1? Yes Write transmit data to SCFTDR, and clear TDFE flag in SCFSR to 0
Read ORER flag in SCLSR Yes [3] Error handling
ORER = 1? No Read RDF flag in SCFSR No
RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 [4]
Note: When switching from a transmit operation or receive operation to simultaneous transmission and reception operations, clear the TE and RE bits to 0, and then set them simultaneously to 1.
No
All data received? Yes Clear TE and RE bits in SCSCR to 0 End of transmission and reception [5]
Figure 28.19 Sample Simultaneous Serial Transmission and Reception Flowchart
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.4.4
SCIF Interrupt Sources and the DMAC
The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receiveerror interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt (BRI) request. Table 28.9 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. If the TDFE flag in SCFSR is set to 1 when a TXI interrupt is enabled by the TIE bit, a TXI interrupt request and a transmit-FIFO-data-empty request for DMA transfer are generated. If the TDFE flag is set to 1 when a TXI interrupt is disabled by the TIE bit, only a transmit-FIFO-dataempty request for DMA transfer is generated. A transmit-FIFO-data-empty request can activate the DMAC to perform data transfer. If the RDF or DR flag in SCFSR is set to 1 when an RXI interrupt is enabled by the RIE bit, an RXI interrupt request and a receive-FIFO-data-full request for DMA transfer are generated. If the RDF or DR flag is set to 1 when an RXI interrupt is disabled by the RIE bit, only a receive-FIFOdata-full request for DMA transfer is generated. A receive-FIFO-data-full request can activate the DMAC to perform data transfer. Note that generation of an RXI interrupt request or a receiveFIFO-data-full request by setting the DR flag to 1 occurs only in asynchronous mode. When the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1, a BRI interrupt request is generated. If transmission/reception is carried out using the DMAC, set and enable the DMAC before making the SCIF settings. Also make settings to inhibit output of RXI and TXI interrupt requests to the interrupt controller. If output of interrupt requests is enabled, these interrupt requests to the interrupt controller can be cleared by the DMAC regardless of the interrupt handler. By setting the REIE bit to 1 while the RIE bit is cleared to 0 in SCSCR, it is possible to output ERI interrupt requests, but not RXI interrupt requests.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Table 28.9 SCIF Interrupt Sources
Interrupt Source ERI RXI BRI TXI Note: * Description Interrupt initiated by receive error flag (ER) Interrupt initiated by receive FIFO data full flag (RDF) or receive data ready flag (DR)* DMAC Activation Not possible Possible Priority on Reset Release High
Interrupt initiated by break flag (BRK) or overrun Not possible error flag (ORER) Interrupt initiated by transmit FIFO data empty flag (TDFE) Possible Low
An RXI interrupt by setting of the DR flag is available only in asynchronous mode.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.4.5
Usage Notes
Note the following when using the SCIF. (1) SCFTDR Writing and the TDFE Flag
The TDFE flag in SCFSR is set when the number of transmit data bytes written in SCFTDR has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in SCFCR. After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again, even after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from SCFDR. (2) SCFRDR Reading and the RDF Flag
The RDF flag in SCFSR is set when the number of receive data bytes in SCFRDR has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR. After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes read in SCFRDR is equal to or greater than the trigger number, the RDF flag will be set to 1 again even if it is cleared to 0. After the receive data is read, clear the RDF flag readout to 0 in order to reduce the number of data bytes in SCFRDR to less than the trigger number. The number of receive data bytes in SCFRDR can be found from SCRFDR. (3) Break Detection and Processing
If a framing error (FER) is detected, break signals can also be detected by reading the SCIF_RXD pin value directly. In the break state the input from the SCIF_RXD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Although the SCIF stops transferring receive data to SCFRDR after receiving a break, the receive operation continues.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(4)
Sending a Break Signal
The input/output condition and level of the SCIF_TXD pin are determined by bits SPB2IO and SPB2DT in SCSPTR. This feature can be used to send a break signal. After the serial transmitter is initialized and until the TE bit is set to 1 (enabling transmission), the SCIF_TXD pin function is not selected and the value of the SPB2DT bit substitutes for the mark state. The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high level) in the beginning. To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), and then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized, regardless of the current transmission state, and 0 is output from the SCIF_TXD pin. (5) Receive Data Sampling Timing and Receive Margin in Asynchronous Mode
In asynchronous mode, the SCIF operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 28.20.
16 clocks 8 clocks
0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5
Base clock -7.5 clocks Receive data (RXD) Synchronization sampling timing Data sampling timing Start bit +7.5 clocks D0 D1
Figure 28.20 Receive Data Sampling Timing in Asynchronous Mode
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Thus, the reception margin in asynchronous mode is given by formula (1).
M= (0.5 1 2N ) - (L - 0.5) F | D - 0.5 | (1 + F) x 100 % .................. (1) N
M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0) L: F: Frame length (L = 9 to 12) Absolute value of clock rate deviation
From equation (1), if F = 0 and D = 0.5, the reception margin is 46.875%, as given by formula (2). When D = 0.5 and F = 0:
M = (0.5 - 1 / (2 x 16) ) x 100% = 46.875% ............................................... (2)
However, this is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. (6) Reception margin and baud rate error
The 46.875% in formula (2) is the reception margin when the baud rate error is 0 (F = 0). In other words, reception is possible even with a misalignment of approximately half a bit if there is no reception or transmission baud rate error. If baud rate error is present in reception or transmission, the error accumulates until the stop bit is received, reducing the reception margin. To calculate the allowable baud rate error, formula (1) can be modified to determine the value of F. If D = 0.5, the result is formula (3). F = { (15/32-M) / (L - 0.5) } x 100 (%) ...... Expression (3) Based on formula (3), the relationship between the allowable baud rate error and the reception margin when the frame length L = 12 are as follows.
Allowable baud rate error (%) Reception margin (%) 4.07 0 3.64 5 3.20 10 2.33 20 1.46 30
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.5
Infrared Data Communication Interface
The IrDA infrared data communication interface converts (modulates) the serial communication data received from the SCIF2 channel into the data format used by the infrared data communication, and transmits the data from the SCIF2_TXD pin to the infrared sensor/emitter. Also, this module converts (demodulates) the infrared communication data transmitted from the infrared sensor/emitter to the SCIF2_RXD pin into the data format used by the serial data communication, and transmits the data to the SCIF2 channel. 28.5.1 Infrared Data Communication Format
Figure 28.21 shows the data format used by the infrared data communication.
Infrared data transmission format
Transmit data from SCIF2 chaannel Transmit data to SCIF2_TXD pin (infrared data output)
SCK 16 cycles
SCK 3 cycles Infrared data receive format
Receive data from SCIF2_RXD pin (infrared data input)
Receive data to SCIF2 chaannel
SCK 3 cycles
SCK 16 cycles
Figure 28.21 Infrared Communication Data Format
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.5.2
Operation of Infrared Data Communication Interface
Figure 28.22 shows a block diagram of the infrared data communication interface. The infrared data communication interface selects whether serial communication data for the SCIF2 channel is modulated/demodulated to the infrared data for transmission or reception. When the IRMOD bit in SCSMRIR is 1, the modulated/demodulated IrDA data is input/output from the SCIF2_TXD/SCIF2_RXD pin. When the IRMOD bit in SCSMRIR is 0, the data for the SCIF2 channel is bypassed to the SCIF2_TXD/SCIF2_RXD pin. When the LOOP bit in SCSMRIR is set to active, output from the infrared data modulation unit is directly input to the demodulation unit (for loopback testing). The selector does not use clocks for its logic. Therefore, the status of the selector after a reset or in standby depends on only the value of SCSMRIR. Note: This module can detect short pulses such as chattering in reception, be sure to secure the shortest pulse width specified by the IrDA standard.
Infrared data communication interface
IRMOD s_txd 0 p_txd SCIF2_TXD
s_txd Serial data transmission
s_txd
Modulation unit
i_txd_n
1 i_txd_n
LOOP IRMOD 1 i_rxd s_rxd Serial data reception SCIF2 Channel 1 0 p_rxd Demodulation unit i_rxdp_n 0 p_rxd p_rxd SCIF2_RXD
Port logic block
Figure 28.22 Block Diagram of Infrared Data Communication Interface
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.6
Baud Rate Generator for External Clock (BRG)
The baud rate generator for external clock (hereafter abbreviated as BRG) is included in the SCIF/IrDA and supplies the IrDA block with a sampling clock (BRGCLK), which is derived from the external clock (SCIF_CLK) or internal clock (Pck0) divided by the division ratio from 1 through 2 to the sixteenth power minus 1. 28.6.1 BRG Block Diagram
Figure 28.23 shows a block diagram of the BRG.
IO-BUS IF
reset_brg
Infrared data Communication Inteface (IrDA)
BRGCLK
Reset controler
Trigger generator
SCIF_SCK
Control register
Base counter
BRG block
SCIF/IrDA
SC_CLK (selected from among SCIF_CLK and Pck0)
Figure 28.23 BRG Block Diagram
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(1)
Reset controller
The reset controller controls resetting of the control register, base counter, and trigger generator. (2) Control register
The control register has the frequency division register and clock select register. For details, see section 28.3, Register Descriptions. (3) Base counter
The base counter is a 16-bit CLK (external clock BRG input) synchronization counter. This counter is used to determine timing of a frequency divided clock when it is generated. (4) Trigger generator
The trigger generator generates rising-edge/falling-edge triggers for a frequency divided clock, taking timing according to values of the frequency division register and base counter. The triggers generate the frequency divided clock. The trigger generator also switches the output between SCIF2_CLK (external clock input) and the frequency divided clock. 28.6.2 (1) Restrictions on the BRG
Notes on Frequency Division Register Settings
1. At the first setting of BSGDL2 after a reset, wait time of one bit period or more is required to ensure the clock settling time.
(Example) Period of one bit when BSGDL2 = 2 3.68 (MHz) x 1/2 x 1/16 = 0.115 (MHz) 8695 (ns)
2. After the setting stated in 1 above, wait time of one bit period or more is required at the maximum bit rate (BSGDL2 = 65535) before the value of BSGDL2 is changed again.
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Set the SCIF registers and BRG registers as shown in the tables below: * Asynchronous mode (SC_CLK external input)
SCIF Register/Bit Name SCSMR.C/A SCSCR.CKE1 Setting Value 0 1 BRG Register Name BSGCKS2 BSGDL2 Setting Value 0000 1 to FFFF
* Asynchronous mode (SCK external input)
SCIF Register/Bit Name SCSMR.C/A SCSCR Setting Value 0 1 BRG Register Name BSGCKS2 BSGDL2 Setting Value 8000 Don't care
* Clock synchronous mode (external input)
SCIF Register/Bit Name SCSMR SCSCR Setting Value 1 1 BRG Register Name BSGCKS2 BSGDL2 Setting Value 8000 Don't care
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
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Section 29 Serial I/O with FIFO (SIOF)
Section 29 Serial I/O with FIFO (SIOF)
This LSI includes a clock-synchronized serial I/O module with FIFO (SIOF) that comprises three channels.
29.1
Features
* Three channels of serial I/O * Serial transfer 16-stage 32-bit FIFOs (transmission and reception are independent of each other) Supports 8-bit data/16-bit data/16-bit stereo audio input/output MSB first for data transmission Supports a maximum of 48-kHz sampling rate Synchronization by either frame synchronization pulse or left/right channel switch Supports CODEC control data interface Connectable to linear, audio, or A-Law or -Law CODEC chip Supports both master and slave modes * Serial clock An external pin input or peripheral clock (Pck0) can be selected as the clock source. * Interrupts: One type * DMA transfer Supports DMA transfer by a transfer request for transmission and reception
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Section 29 Serial I/O with FIFO (SIOF)
Figure 29.1 shows a block diagram of the SIOF.
SIOF interrupt request (SIOFI) Bus interface
Peripheral bus
Control registers
Transmit FIFO (32 bits x16 stages)
Receive FIFO (32 bits x16 stages)
Pck0
Transmit control data
Receive control data
Baud rate generator
1/nMCLK
Timing control
P/S
S/P
SIOF_MCLK
SIOF_SCK SIOF_SYNC
SIOF_TXD
SIOF_RXD
Figure 29.1 Block Diagram of SIOF
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Section 29 Serial I/O with FIFO (SIOF)
29.2
Input/Output Pins
Table 29.1 summarizes the SIOF related external pins. Table 29.1 Pin Configuration
Channel Pin Name Function I/O Description
0
SIOF0_MCLK SIOF0_SCK SIOF0_SYNC SIOF0_TXD SIOF0_RXD
Master clock Serial clock
Input I/O
Master clock input pin Serial clock pin (common to transmission/reception) Frame synchronous signal (common to transmission/reception) Transmit data pin Receive data pin Master clock input pin Serial clock pin (common to transmission/reception) Frame synchronous signal (common to transmission/reception) Transmit data pin Receive data pin Master clock input pin Serial clock pin (common to transmission/reception) Frame synchronous signal (common to transmission/reception) Transmit data pin Receive data pin
Frame synchronous I/O signal Transmit data Receive data Master clock Serial clock Output Input Input I/O
1
SIOF1_MCLK SIOF1_SCK SIOF1_SYNC SIOF1_TXD SIOF1_RXD
Frame synchronous I/O signal Transmit data Receive data Master clock Serial clock Output Input Input I/O
2
SIOF2_MCLK SIOF2_SCK SIOF2_SYNC SIOF2_TXD SIOF2_RXD
Frame synchronous I/O signal Transmit data Receive data Output Input
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Section 29 Serial I/O with FIFO (SIOF)
29.3
Register Descriptions
Table 29.2 shows the SIOF register configuration. Table 29.3 shows the register state in each operating mode. Table 29.2 Register Configuration
Channel Register Name Abbreviation R/W Area P4 Address* Area 7 Address* Access Size
0
Mode register 0 Clock select register 0
SIMDR0 SISCR0
R/W H'FFE3 0000 H'1FE3 0000 16 R/W H'FFE3 0002 H'1FE3 0002 16 R/W H'FFE3 0004 H'1FE3 0004 16 R/W H'FFE3 0006 H'1FE3 0006 16 R/W H'FFE3 0008 H'1FE3 0008 16 R/W H'FFE3 000C H'1FE3 000C 16 R/W H'FFE3 0010 H'1FE3 0010 16 R/W H'FFE3 0014 H'1FE3 0014 16 R/W H'FFE3 0016 H'1FE3 0016 16 W R H'FFE3 0020 H'1FE3 0020 32 H'FFE3 0024 H'1FE3 0024 32
Transmit data assign register SITDAR0 0 Receive data assign register SIRDAR0 0 Control data assign register 0 Control register 0 FIFO control register 0 Status register 0 Interrupt enable register 0 Transmit data register 0 Receive data register 0 Transmit control data register 0 SICDAR0 SICTR0 SIFCTR0 SISTR0 SIIER0 SITDR0 SIRDR0 SITCR0
R/W H'FFE3 0028 H'1FE3 0028 32 R/W H'FFE3 002C H'1FE3 002C 32 R/W H'FFE3 8000 H'1FE3 8000 16 R/W H'FFE3 8002 H'1FE3 8002 16 R/W H'FFE3 8004 H'1FE3 8004 16 R/W H'FFE3 8006 H'1FE3 8006 16 R/W H'FFE3 8008 H'1FE3 8008 16 R/W H'FFE3 800C H'1FE3 800C 16 R/W H'FFE3 8010 H'1FE3 8010 16
Receive control data register SIRCR0 0 1 Mode register 1 Clock select register 1 SIMDR1 SISCR1
Transmit data assign register SITDAR1 1 Receive data assign register SIRDAR1 1 Control data assign register 1 Control register 1 FIFO control register 1 SICDAR1 SICTR1 SIFCTR1
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Section 29 Serial I/O with FIFO (SIOF)
Channel
Register Name
Abbreviation R/W
Area P4 Address*
Area 7 Address*
Access Size
1
Status register 1 Interrupt enable register 1 Transmit data register 1 Receive data register 1 Transmit control data register 1
SISTR1 SIIER1 SITDR1 SIRDR1 SITCR1
R/W H'FFE3 8014 H'1FE3 8014 16 R/W H'FFE3 8016 H'1FE3 8016 16 W R H'FFE3 8020 H'1FE3 8020 32 H'FFE3 8024 H'1FE3 8024 32
R/W H'FFE3 8028 H'1FE3 8028 32 R/W H'FFE3 802C H'1FE3 802C 32 R/W H'FFE4 0000 H'1FE4 0000 16 R/W H'FFE4 0002 H'1FE4 0002 16 R/W H'FFE4 0004 H'1FE4 0004 16 R/W H'FFE4 0006 H'1FE4 0006 16 R/W H'FFE4 0008 H'1FE4 0008 16 R/W H'FFE4 000C H'1FE4 000C 16 R/W H'FFE4 0010 H'1FE4 0010 16 R/W H'FFE4 0014 H'1FE4 0014 16 R/W H'FFE4 0016 H'1FE4 0016 16 W R H'FFE4 0020 H'1FE4 0020 32 H'FFE4 0024 H'1FE4 0024 32
Receive control data register SIRCR1 1 2 Mode register 2 Clock select register 2 SIMDR2 SISCR2
Transmit data assign register SITDAR2 2 Receive data assign register SIRDAR2 2 Control data assign register 2 Control register 2 FIFO control register 2 Status register 2 Interrupt enable register 2 Transmit data register 2 Receive data register 2 Transmit control data register 2 SICDAR2 SICTR2 SIFCTR2 SISTR2 SIIER2 SITDR2 SIRDR2 SITCR2
R/W H'FFE4 0028 H'1FE4 0028 32 R/W H'FFE4 002C H'1FE4 002C 32
Receive control data register SIRCR2 2 Note: *
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
Rev. 1.00 Oct. 01, 2007 Page 1189 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
Table 29.3 Register State in Each Operating Mode
Channel Register Name 0 Mode register 0 Clock select register 0 Power-On Abbreviation Reset SIMDR0 SISCR0 H'8000 H'C000 H'0000 H'0000 H'0000 H'0000 H'1000 H'0000 H'0000 H'xxxx xxxx H'xxxx xxxx Manual Reset H'8000 H'C000 H'0000 H'0000 H'0000 H'0000 H'1000 H'0000 H'0000 H'xxxx xxxx H'xxxx xxxx Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Transmit data assign register 0 SITDAR0 Receive data assign register 0 SIRDAR0 Control data assign register 0 Control register 0 FIFO control register 0 Status register 0 Interrupt enable register 0 Transmit data register 0 Receive data register 0 SICDAR0 SICTR0 SIFCTR0 SISTR0 SIIER0 SITDR0 SIRDR0
Transmit control data register 0 SITCR0 Receive control data register 0 SIRCR0 1 Mode register 1 Clock select register 1 SIMDR1 SISCR1
H'0000 0000 H'0000 0000 Retained H'xxxx xxxx H'8000 H'C000 H'0000 H'0000 H'0000 H'0000 H'1000 H'0000 H'0000 H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'8000 H'C000 H'0000 H'0000 H'0000 H'0000 H'1000 H'0000 H'0000 H'xxxx xxxx H'xxxx xxxx Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Transmit data assign register 1 SITDAR1 Receive data assign register 1 SIRDAR1 Control data assign register 1 Control register 1 FIFO control register 1 Status register 1 Interrupt enable register 1 Transmit data register 1 Receive data register 1 SICDAR1 SICTR1 SIFCTR1 SISTR1 SIIER1 SITDR1 SIRDR1
Transmit control data register 1 SITCR1 Receive control data register 1 SIRCR1
H'0000 0000 H'0000 0000 Retained H'xxxx xxxx H'xxxx xxxx Retained
Rev. 1.00 Oct. 01, 2007 Page 1190 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
Channel Register Name 2 Mode register 2 Clock select register 2
Power-On Abbreviation Reset SIMDR2 SISCR2 H'8000 H'C000 H'0000 H'0000 H'0000 H'0000 H'1000 H'0000 H'0000 H'xxxx xxxx H'xxxx xxxx
Manual Reset H'8000 H'C000 H'0000 H'0000 H'0000 H'0000 H'1000 H'0000 H'0000 H'xxxx xxxx H'xxxx xxxx
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Transmit data assign register 2 SITDAR2 Receive data assign register 2 SIRDAR2 Control data assign register 2 Control register 2 FIFO control register 2 Status register 2 Interrupt enable register 2 Transmit data register 2 Receive data register 2 SICDAR2 SICTR2 SIFCTR2 SISTR2 SIIER2 SITDR2 SIRDR2
Transmit control data register 2 SITCR2 Receive control data register 2 SIRCR2
H'0000 0000 H'0000 0000 Retained H'xxxx xxxx H'xxxx xxxx Retained
Rev. 1.00 Oct. 01, 2007 Page 1191 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
29.3.1
Mode Register (SIMDR)
SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode.
BIt: 15 14 13
SYN CAT
12
REDG
11
10
9
8
7
6
5
SYN CAC
4
SYN CDL
3 -- 0 R
2 -- 0 R
1 -- 0 R
0 -- 0 R
TRMD[1:0] Initial value: R/W: 1 R/W 0 R/W
FL[3:0] 0 R/W 0 R/W 0 R/W 0 R/W
TXDIZ RCIM
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15, 14
Bit Name TRMD[1:0]
Initial Value 10
R/W R/W
Description Transfer Mode Select transfer mode as shown in table 29.4. 00: Slave mode 1 01: Slave mode 2 10: Master mode 1 11: Master mode 2
13
SYNCAT
0
R/W
SIOF_SYNC Pin Valid Timing Indicates the position of the SIOF_SYNC signal to be output as a synchronization pulse. 0: At the start-bit data of frame 1: At the last-bit data of slot
12
REDG
0
R/W
Receive Data Sampling Edge 0: The SIOF_RXD signal is sampled at the falling edge of SIOF_SCK 1: The SIOF_RXD signal is sampled at the rising edge of SIOF_SCK Note: The timing to transmit the SIOF_TXD signal is at the opposite edge of the timing that samples the SIOF_RXD. This bit is valid only in master mode.
11 to 8
FL[3:0]
0000
R/W
Frame Length Specifies the flame length and transfer data format. For details, refer to table 29.7.
Rev. 1.00 Oct. 01, 2007 Page 1192 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
Bit 7
Bit Name TXDIZ
Initial Value 0
R/W R/W
Description SIOF_TXD Pin Output when Transmission is Invalid* 0: High output (1 output) when invalid 1: High-impedance state when invalid Note: Invalid means when disabled, and when a slot that is not assigned as transmit data or control data is being transmitted. Receive Control Data Interrupt Mode 0: Sets the RCRDY bit in SISTR when the contents of SIRCR change. 1: Sets the RCRDY bit in SISTR each time when the SIRCR receives the control data. SIOF_SYNC Pin Polarity Valid when the SIOF_SYNC signal is output as a synchronous pulse. 0: Active-high 1: Active-low Data Pin Bit Delay for SIOF_SYNC Pin Valid when the SIOF_SYNC signal is output as synchronous pulse. Only one-bit delay is valid for transmission in slave mode. This bit should be set to 1. 0: No bit delay 1: 1-bit delay Note: * When this bit is cleared to 0 (no bit delay is selected) in slave mode, the receive data is sampled at the rising edge of SCK. Reserved These bits are always read as 0. The write value should always be 0.
6
RCIM
0
R/W
5
SYNCAC
0
R/W
4
SYNCDL
0
R/W
3 to 0
--
All 0
R
Rev. 1.00 Oct. 01, 2007 Page 1193 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
Table 29.4 shows the operation in each transfer mode. Table 29.4 Operation in Each Transfer Mode
Transfer Mode Slave mode 1 Slave mode 2 Master mode 1 Master mode 2 Note: * Master/Slave Slave Slave Master Master SIOF_SYNC Bit Delay Control Data Method* Slot position Secondary FS Slot position No Not supported
Synchronous pulse SYNCDL bit Synchronous pulse Synchronous pulse L/R
The control data method is valid only when the FL bit is specified as B'1xxx. (x: don't care.)
29.3.2
Clock Select Register (SISCR)
SISCR is a 16-bit readable/writable register that sets the serial clock generation conditions for the master clock. SISCR can be specified when the bits TRMD[1:0] in SIMDR are specified as B'10 or B'11.
BIt: 15 14 13 -- 0 R 0 R/W 12 11 10 BRPS[4:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 BRDV[2:0] 0 R/W 0 R/W 0 R/W 0
MSSEL MSIMM
Initial value: R/W:
1 R/W
1 R/W
Bit 15
Bit Name MSSEL
Initial Value 1
R/W R/W
Description Master Clock Source Selection The master clock is the clock source input to the baud rate generator (prescaler). 0: Uses the input clock signal of the SIOF_MCLK pin as the master clock 1: Uses Pck0 as the master clock
14
MSIMM
1
R/W
Master Clock Direct Selection 0: Uses the output clock of the baud rate generator as the serial clock 1: Uses the master clock itself as the serial clock
13
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1194 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
Bit 12 to 8
Bit Name BRPS[4:0]
Initial Value 00000
R/W R/W
Description Prescalar Setting Set the master clock division ratio according to the count value of the prescalar of the baud rate generator. The range of settings is from 00000 (x 1/1) to 11111 (x 1/32).
7 to 3
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
BRDV[2:0]
000
R/W
Baud rate generator's Division Ratio Setting Set the frequency division ratio for the output stage of the baud rate generator. 000: Prescalar output x 1/2 001: Prescalar output x 1/4 010: Prescalar output x 1/8 011: Prescalar output x 1/16 100: Prescalar output x 1/32 101: Setting prohibited 110: Setting prohibited 111: Prescalar output x 1/1 * Setting 111 is valid only when the bits BRPS[4:0] are set to 00001. The final frequency division ratio of the baud rate generator is determined by the value of BRPS and BRDV (maximum 1/1024).
Rev. 1.00 Oct. 01, 2007 Page 1195 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
29.3.3
Control Register (SICTR)
SICTR is a 16-bit readable/writable register that sets the SIOF operating state.
BIt: 15 14 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 TXE 0 R/W 8 RXE 0 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 0
SCKE FSE Initial value: R/W: 0 R/W 0 R/W
TXRST RXRST
0 R/W
0 R/W
Bit 15
Bit Name SCKE
Initial Value 0
R/W R/W
Description Serial Clock Output Enable This bit is valid in master mode. 0: Disables the SIOF_SCK output (outputs 0) 1: Enables the SIOF_SCK output If this bit is set to 1, the SIOF initializes the baud rate generator and initiates the operation. At the same time, the SIOF outputs the clock generated by the baud rate generator to the SIOF_SCK pin.
14
FSE
0
R/W
Frame Synchronous Signal Output Enable This bit is valid in master mode. 0: Disables the SIOF_SYNC output (outputs 0) 1: Enables the SIOF_SYNC output If this bit is set to 1, the SIOF initializes the frame counter and initiates the operation.
13 to 10 --
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1196 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
Bit 9
Bit Name TXE
Initial Value 0
R/W R/W
Description Transmit Enable 0: Disables data transmission from the SIOF_TXD pin 1: Enables data transmission from the SIOF_TXD pin * * This bit setting becomes valid at the start of the next frame (at the rising edge of the SIOF_SYNC signal). When the 1 setting for this bit becomes valid, the SIOF issues a transmit transfer request according to the setting of the TFWM bit in SIFCTR. When transmit data is stored in the transmit FIFO, transmission of data from the SIOF_TXD pin begins.
This bit is initialized upon a transmit reset. 8 RXE 0 R/W Receive Enable 0: Disables data reception from SIOF_RXD 1: Enables data reception from SIOF_RXD * * This bit setting becomes valid at the start of the next frame (at the rising edge of the SIOF_SYNC signal). When the 1 setting for this bit becomes valid, the SIOF begins the reception of data from the SIOF_RXD pin. When receive data is stored in the receive FIFO, the SIOF issues a reception transfer request according to the setting of the RFWM bit in SIFCTR.
This bit is initialized upon receive reset.
Rev. 1.00 Oct. 01, 2007 Page 1197 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
Bit 7 to 2
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1
TXRST
0
R/W
Transmit Reset 0: Does not reset transmit operation 1: Resets transmit operation * * This bit setting becomes valid immediately. For details of transmit reset, refer to table 29.13. SIOF automatically clears this bit upon the completion of reset. Thus, this bit is always read as 0.
0
RXRST
0
R/W
Receive Reset 0: Does not reset receive operation 1: Resets receive operation * * This bit setting becomes valid immediately. For details of receive reset, refer to table 29.13. SIOF automatically clears this bit upon the completion of reset. Thus, this bit is always read as 0.
Rev. 1.00 Oct. 01, 2007 Page 1198 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
29.3.4
Transmit Data Register (SITDR)
SITDR is a 32-bit write-only register that specifies the SIOF operating status.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SITDL[15:0] Initial value: R/W: BIt: -- W 15 -- W 14 -- W 13 -- W 12 -- W 11 -- W 10 -- W 9 -- W 8 -- W 7 -- W 6 -- W 5 -- W 4 -- W 3 -- W 2 -- W 1 -- W 0
SITDR[15:0] Initial value: R/W: -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W -- W
Bit
Bit Name
Initial Value
R/W
Description Left-Channel Transmit Data Specify data to be output from the SIOF_TXD pin as left-channel data. The position of the left-channel data in the transmit frame is specified by the TDLA bit in SITDAR. * These bits are valid only when the TDLE bit in SITDAR is set to 1.
31 to 16 SITDL[15:0] Undefined W
15 to 0
SITDR[15:0] Undefined W
Right-Channel Transmit Data Specify data to be output from the SIOF_TXD pin as right-channel data. The position of the right-channel data in the transmit frame is specified by the TDRA bit in SITDAR. * These bits are valid only when the TDRE bit and TLREP bit in SITDAR are set to 1 and cleared to 0, respectively.
Rev. 1.00 Oct. 01, 2007 Page 1199 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
29.3.5
Receive Data Register (SIRDR)
SIRDR is a 32-bit read-only register that reads receive data of the SIOF. SIRDR stores data in the receive FIFO.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIRDL[15:0] Initial value: R/W: BIt: -- R 15 -- R 14 -- R 13 -- R 12 -- R 11 -- R 10 -- R 9 -- R 8 -- R 7 -- R 6 -- R 5 -- R 4 -- R 3 -- R 2 -- R 1 -- R 0
SIRDR[15:0] Initial value: R/W: -- R -- R -- R -- R -- R -- R -- R -- R -- R -- R -- R -- R -- R -- R -- R -- R
Bit
Bit Name
Initial Value
R/W
Description Left-Channel Receive Data Store data received from the SIOF_RXD pin as leftchannel data. The position of the left-channel data in the receive frame is specified by the RDLA bit in SIRDAR. * These bits are valid only when the RDLE bit in SIRDAR is set to 1.
31 to 16 SIRDL[15:0] Undefined R
15 to 0
SIRDR[15:0] Undefined R
Right-Channel Receive Data Store data received from the SIOF_RXD pin as rightchannel data. The position of the right-channel data in the receive frame is specified by the RDRA bit in SIRDAR. * These bits are valid only when the RDRE bit in SIRDAR is set to 1.
Rev. 1.00 Oct. 01, 2007 Page 1200 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
29.3.6
Transmit Control Data Register (SITCR)
SITCR is a 32-bit readable/writable register that specifies transmit control data of the SIOF. SITCR can be specified only when the FL bit in SIMDR is specified as 1xxx (x: don't care.). SITCR is initialized by the conditions specified in table 29.3, Register State of SIOF in Each Processing Mode, or by a transmit reset caused by the TXRST bit in SICTR.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SITC0[15:0] Initial value: R/W: BIt: -- R/W 15 -- R/W 14 -- R/W 13 -- R/W 12 -- R/W 11 -- R/W 10 -- R/W 9 -- R/W 8 -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0
SITC1[15:0] Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W
Bit
Bit Name
Initial Value
R/W R/W
Description Control Channel 0 Transmit Data Specify data to be output from the SIOF_TXD pin as control channel 0 transmit data. The position of the control channel 0 data in the transmit or receive frame is specified by the CD0A bit in SICDAR. * These bits are valid only when the CD0E bit in SICDAR is set to 1.
31 to 16 SITC0[15:0] H'0000
15 to 0
SITC1[15:0] H'0000
R/W
Control Channel 1 Transmit Data Specify data to be output from the SIOF_TXD pin as control channel 1 transmit data. The position of the control channel 1 data in the transmit or receive frame is specified by the CD1A bit in SICDAR. * These bits are valid only when the CD1E bit in SICDAR is set to 1.
Rev. 1.00 Oct. 01, 2007 Page 1201 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
29.3.7
Receive Control Data Register (SIRCR)
SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. SIRCR can be specified only when the FL bit in SIMDR is specified as 1xxx (x: don't care.).
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIRC0[15:0] Initial value: R/W: BIt: -- R/W 15 -- R/W 14 -- R/W 13 -- R/W 12 -- R/W 11 -- R/W 10 -- R/W 9 -- R/W 8 -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0
SIRC1[15:0] Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W
Bit
Bit Name
Initial Value
R/W
Description Control Channel 0 Receive Data Store data received from the SIOF_RXD pin as control channel 0 receive data. The position of the control channel 0 data in the transmit or receive frame is specified by the CD0A bit in SICDAR. * These bits are valid only when the CD0E bit in SICDAR is set to 1.
31 to 16 SIRC0[15:0] Undefined R/W
15 to 0
SIRC1[15:0] Undefined R/W
Control Channel 1 Receive Data Store data received from the SIOF_RXD pin as control channel 1 receive data. The position of the control channel 1 data in the transmit or receive frame is specified by the CD1A bit in SICDAR. * These bits are valid only when the CD1E bit in SICDAR is set to 1.
Rev. 1.00 Oct. 01, 2007 Page 1202 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
29.3.8
Status Register (SISTR)
SISTR is a 16-bit readable/writable register that shows the SIOF state. Each bit in this register becomes an SIOF interrupt source when the corresponding bit in SIIER is set to 1.
BIt: 15
--
14
13
12
11
--
10
9
8
7
--
6
--
5
4
3
TFOVF
2
TFUDF
1
0
TCRDY TFEMP TDREQ
RCRDY RFFUL RDREQ
SAERR FSERR
RFUDF RFOVF
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15
Bit Name --
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
14
TCRDY
0
R
Transmit Control Data Ready 0: Indicates that a write to SITCR is disabled 1: Indicates that a write to SITCR is enabled * If SITCR is written when this bit is cleared to 0, SITCR is over-written and the previous contents of SITCR are not output from the SIOF_TXD pin. This bit is valid when the TXE bit in SITCR is set to 1. This bit indicates a state of the SIOF. If SITCR is written, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued.
* * * 13 TFEMP 0 R
Transmit FIFO Empty 0: Indicates that transmit FIFO is not empty 1: Indicates that transmit FIFO is empty * * * This bit is valid when the TXE bit in SICTR is 1. This bit indicates a state; if SITDR is written, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued.
Rev. 1.00 Oct. 01, 2007 Page 1203 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
Bit 12
Bit Name TDREQ
Initial Value 0
R/W R
Description Transmit Data Transfer Request 0: Indicates that the size of empty space in the transmit FIFO does not exceed the size specified by the TFWM bit in SIFCTR. 1: Indicates that the size of empty space in the transmit FIFO exceeds the size specified by the TFWM bit in SIFCTR. A transmit data transfer request is issued when the empty space in the transmit FIFO exceeds the size specified by the TFWM bit in SIFCTR. When using transmit data transfer through the DMAC, this bit is always cleared by one DMAC access. After DMAC access, when conditions for setting this bit are satisfied, the SIOF again indicates 1 for this bit. * * This bit is valid when the TXE bit in SICTR is 1. This bit indicates a state; if the size of empty space in the transmit FIFO is less than the size specified by the TFWM bit in SIFCTR, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued.
* 11 -- 0 R
Reserved This bit is always read as 0. The write value should always be 0.
10
RCRDY
0
R
Receive Control Data Ready 0: Indicates that the SIRCR stores no valid data. 1: Indicates that the SIRCR stores valid data. * * * * If SIRCR is written when this bit is set to 1, SIRCR is modified by the latest data. This bit is valid when the RXE bit in SICTR is set to 1. This bit indicates a state of the SIOF. If SIRCR is read, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued.
Rev. 1.00 Oct. 01, 2007 Page 1204 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
Bit 9
Bit Name RFFUL
Initial Value 0
R/W R
Description Receive FIFO Full 0: Receive FIFO not full 1: Receive FIFO full * * * This bit is valid when the RXE bit in SICTR is 1. This bit indicates a state; if SIRDR is read, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued.
8
RDREQ
0
R
Receive Data Transfer Request 0: Indicates that the size of valid space in the receive FIFO does not exceed the size specified by the RFWM bit in SIFCTR. 1: Indicates that the size of valid space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR. A receive data transfer request is issued when the valid data space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR. When using receive data transfer through the DMAC, this bit is always cleared by one DMAC access. After DMAC access, when conditions for setting this bit are satisfied, the SIOF again indicates 1 for this bit. * * This bit is valid when the RXE bit in SICTR is 1. This bit indicates a state; if the size of valid data space in the receive FIFO is less than the size specified by the RFWM bit in SIFCTR, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued.
* 7, 6 -- All 0 R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1205 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
Bit 5
Bit Name SAERR
Initial Value 0
R/W R/W
Description Slot Assign Error 0: Indicates that no slot assign error occurs 1: Indicates that a slot assign error occurs A slot assign error occurs when the specifications in SITDAR, SIRDAR, and SICDAR overlap. If a slot assign error occurs, the SIOF does not transmit data to the SIOF_TXD pin and does not receive data from the SIOF_RXD pin. Note that the SIOF does not clear the TXE bit or RXE bit in SICTR at a slot assign error. * * * This bit is valid when the TXE bit or RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued.
4
FSERR
0
R/W
Frame Synchronization Error 0: Indicates that no frame synchronization error occurs 1: Indicates that a frame synchronization error occurs A frame synchronization error occurs when the next frame synchronization timing appears before the previous data or control data transfers have been completed. If a frame synchronization error occurs, the SIOF performs transmission or reception for slots that can be transferred. * * * This bit is valid when the TXE or RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued.
Rev. 1.00 Oct. 01, 2007 Page 1206 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
Bit 3
Bit Name TFOVF
Initial Value 0
R/W R/W
Description Transmit FIFO Overflow 0: No transmit FIFO overflow 1: Transmit FIFO overflow A transmit FIFO overflow means that there has been an attempt to write to SITDR when the transmit FIFO is full. When a transmit FIFO overflow occurs, the SIOF indicates overflow, and writing is invalid. * * * This bit is valid when the TXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued.
2
TFUDF
0
R/W
Transmit FIFO Underflow 0: No transmit FIFO underflow 1: Transmit FIFO underflow A transmit FIFO underflow means that loading for transmission has occurred when the transmit FIFO is empty. When a transmit FIFO underflow occurs, the SIOF repeatedly sends the previous transmit data. * * * This bit is valid when the TXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued.
Rev. 1.00 Oct. 01, 2007 Page 1207 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
Bit 1
Bit Name RFUDF
Initial Value 0
R/W R/W
Description Receive FIFO Underflow 0: No receive FIFO underflow 1: Receive FIFO underflow A receive FIFO underflow means that reading of SIRDR has occurred when the receive FIFO is empty. When a receive FIFO underflow occurs, the value of data read from SIRDR is not guaranteed. * * * This bit is valid when the RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued.
0
RFOVF
0
R/W
Receive FIFO Overflow 0: No receive FIFO overflow 1: Receive FIFO overflow A receive FIFO overflow means that writing has occurred when the receive FIFO is full. When a receive FIFO overflow occurs, the SIOF indicates overflow, and receive data is lost. * * * This bit is valid when the RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued.
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Section 29 Serial I/O with FIFO (SIOF)
29.3.9
Interrupt Enable Register (SIIER)
SIIER is a 16-bit readable/writable register that enables the issue of SIOF interrupts. When each bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the SIOF issues an interrupt.
BIt: 15
TD MAE
14
TCR DYE
13
TFE MPE
12
TDR EQE
11
RD MAE
10
9
8
7
--
6
--
5
4
3
2
1
0
RC RF RD RDYE FULE REQE
SA FS TF TF RF RF ERRE ERRE OVFE UDFE UDFE OVFE
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15
Bit Name TDMAE
Initial Value 0
R/W R/W
Description Transmit Data DMA Transfer Request Enable Transmits an interrupt as an interrupt to the CPU/DMA transfer request. The TDREQE bit can be set as transmit interrupts. 0: Used as a CPU interrupt 1: Used as a DMA transfer request to the DMAC
14
TCRDYE
0
R/W
Transmit Control Data Ready Enable 0: Disables interrupts due to transmit control data ready 1: Enables interrupts due to transmit control data ready
13
TFEMPE
0
R/W
Transmit FIFO Empty Enable 0: Disables interrupts due to transmit FIFO empty 1: Enables interrupts due to transmit FIFO empty
12
TDREQE
0
R/W
Transmit Data Transfer Request Enable 0: Disables interrupts due to transmit data transfer requests 1: Enables interrupts due to transmit data transfer requests
11
RDMAE
0
R/W
Receive Data DMA Transfer Request Enable Transmits an interrupt as an interrupt to the CPU/DMA transfer request. The RDREQE bit can be set as receive interrupts. 0: Used as a CPU interrupt 1: Used as a DMA transfer request to the DMAC
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Section 29 Serial I/O with FIFO (SIOF)
Bit 10
Bit Name RCRDYE
Initial Value 0
R/W R/W
Description Receive Control Data Ready Enable 0: Disables interrupts due to receive control data ready 1: Enables interrupts due to receive control data ready
9
RFFULE
0
R/W
Receive FIFO Full Enable 0: Disables interrupts due to receive FIFO full 1: Enables interrupts due to receive FIFO full
8
RDREQE
0
R/W
Receive Data Transfer Request Enable 0: Disables interrupts due to receive data transfer requests 1: Enables interrupts due to receive data transfer requests
7, 6
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
5
SAERRE
0
R/W
Slot Assign Error Enable 0: Disables interrupts due to slot assign error 1: Enables interrupts due to slot assign error
4
FSERRE
0
R/W
Frame Synchronization Error Enable 0: Disables interrupts due to frame synchronization error 1: Enables interrupts due to frame synchronization error
3
TFOVFE
0
R/W
Transmit FIFO Overflow Enable 0: Disables interrupts due to transmit FIFO overflow 1: Enables interrupts due to transmit FIFO overflow
2
TFUDFE
0
R/W
Transmit FIFO Underflow Enable 0: Disables interrupts due to transmit FIFO underflow 1: Enables interrupts due to transmit FIFO underflow
1
RFUDFE
0
R/W
Receive FIFO Underflow Enable 0: Disables interrupts due to receive FIFO underflow 1: Enables interrupts due to receive FIFO underflow
0
RFOVFE
0
R/W
Receive FIFO Overflow Enable 0: Disables interrupts due to receive FIFO overflow 1: Enables interrupts due to receive FIFO overflow
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Section 29 Serial I/O with FIFO (SIOF)
29.3.10 FIFO Control Register (SIFCTR) SIFCTR is a 16-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer.
BIt: 15 14 TFWM[2:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 1 R 0 R 13 12 11 10 TFUA[4:0] 0 R 0 R 0 R 9 8 7 6 RFWM[2:0] 0 R/W 0 R/W 0 R/W 0 R 0 R 5 4 3 2 RFUA[4:0] 0 R 0 R 0 R 1 0
Bit
Bit Name
Initial Value 000
R/W R/W
Description Transmit FIFO Watermark 000: Issue a transfer request when 16 stages of the transmit FIFO are empty. 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Issue a transfer request when 12 or more stages of the transmit FIFO are empty. 101: Issue a transfer request when 8 or more stages of the transmit FIFO are empty. 110: Issue a transfer request when 4 or more stages of the transmit FIFO are empty. 111: Issue a transfer request when 1 or more stages of transmit FIFO are empty. * * A transfer request to the transmit FIFO is issued by the TDREQE bit in SISTR.
15 to 13 TFWM[2:0]
The transmit FIFO is always used as 16 stages of the FIFO regardless of these bit settings. Note: * When the transmit data is DMA-transferred with the TDMAE bit in the SIIER register set to 1, the TFWM[2:0] bits should not be set to B'111. If these bits are set to B'111, a transmit FIFO overflow may occur. 12 to 8 TFUA[4:0] 10000 R Transmit FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'00000 (full) to B'10000 (empty).
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Section 29 Serial I/O with FIFO (SIOF)
Bit 7 to 5
Bit Name RFWM[2:0]
Initial Value 000
R/W R/W
Description Receive FIFO Watermark 000: Issue a transfer request when 1 stage or more of the receive FIFO are valid. 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Issue a transfer request when 4 or more stages of the receive FIFO are valid. 101: Issue a transfer request when 8 or more stages of the receive FIFO are valid. 110: Issue a transfer request when 12 or more stages of the receive FIFO are valid. 111: Issue a transfer request when 16 stages of the receive FIFO are valid. * * A transfer request to the receive FIFO is issued by the RDREQE bit in SISTR. The receive FIFO is always used as 16 stages of the FIFO regardless of these bit settings.
4 to 0
RFUA[4:0]
00000
R
Receive FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'00000 (empty) to B'10000 (full).
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Section 29 Serial I/O with FIFO (SIOF)
29.3.11 Transmit Data Assign Register (SITDAR) SITDAR is a 16-bit readable/writable register that specifies the position of the transmit data in a frame.
BIt: 15
TDLE
14 -- 0 R
13 -- 0 R
12
--
11
10
9
8
7
6
5 -- 0 R
4 -- 0 R
3
2
1
0
TDLA[3:0] 0 R/W 0 R/W 0 R/W 0 R/W
TDRE TLREP
TDRA[3:0] 0 R/W 0 R/W 0 R/W 0 R/W
Initial value: R/W:
0 R/W
0 R
0 R/W
0 R/W
Bit 15
Bit Name TDLE
Initial Value 0
R/W R/W
Description Transmit Left-Channel Data Enable 0: Disables left-channel data transmission 1: Enables left-channel data transmission
14 to 12 --
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
11 to 8
TDLA[3:0]
0000
R/W
Transmit Left-Channel Data Assigns 3 to 0 Specify the position of left-channel data in a transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited * Transmit data for the left channel is specified in the SITDL bit in SITDR.
7
TDRE
0
R/W
Transmit Right-Channel Data Enable 0: Disables right-channel data transmission 1: Enables right-channel data transmission
6
TLREP
0
R/W
Transmit Left-Channel Repeat 0: Transmits data specified in the SITDR bit in SITDR as right-channel data 1: Repeatedly transmits data specified in the SITDL bit in SITDR as right-channel data * * This bit setting is valid when the TDRE bit is set to 1. When this bit is set to 1, the SITDR settings are ignored.
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Section 29 Serial I/O with FIFO (SIOF)
Bit 5, 4
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
3 to 0
TDRA[3:0]
0000
R/W
Transmit Right-Channel Data Assigns 3 to 0 Specify the position of right-channel data in a transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited * Transmit data for the right channel is specified in the SITDR bit in SITDR.
29.3.12 Receive Data Assign Register (SIRDAR) SIRDAR is a 16-bit readable/writable register that specifies the position of the receive data in a frame.
BIt: 15
RDLE
14 -- 0 R
13 -- 0 R
12
--
11
10
9
8
7
RDRE
6 -- 0 R
5 -- 0 R
4 -- 0 R
3
2
1
0
RDLA[3:0] 0 R/W 0 R/W 0 R/W 0 R/W
RDRA[3:0] 0 R/W 0 R/W 0 R/W 0 R/W
Initial value: R/W:
0 R/W
0 R
0 R/W
Bit 15
Bit Name RDLE
Initial Value 0
R/W R/W
Description Receive Left-Channel Data Enable 0: Disables left-channel data reception 1: Enables left-channel data reception
14 to 12 --
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
11 to 8
RDLA[3:0]
0000
R/W
Receive Left-Channel Data Assigns 3 to 0 Specify the position of left-channel data in a receive frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited * Receive data for the left channel is stored in the SIRDL bit in SIRDR.
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Section 29 Serial I/O with FIFO (SIOF)
Bit 7
Bit Name RDRE
Initial Value 0
R/W R/W
Description Receive Right-Channel Data Enable 0: Disables right-channel data reception 1: Enables right-channel data reception
6 to 4
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
3 to 0
RDRA[3:0]
0000
R/W
Receive Right-Channel Data Assigns 3 to 0 Specify the position of right-channel data in a receive frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited * Receive data for the right channel is stored in the SIRDR bit in SIRDR.
29.3.13 Control Data Assign Register (SICDAR) SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a frame. SICDAR can be specified only when the FL bit in SIMDR is specified as 1xxx (x: don't care.).
BIt: 15
CD0E
14 -- 0 R
13 -- 0 R
12
--
11
10
9
8
7
CD1E
6 -- 0 R
5 -- 0 R
4 -- 0 R
3
2
1
0
CD0A[3:0]
CD1A[3:0]
Initial value: R/W:
0 R/W
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15
Bit Name CD0E
Initial Value 0
R/W R/W
Description Control Channel 0 Data Enable 0: Disables transmission and reception of control channel 0 data 1: Enables transmission and reception of control channel 0 data
14 to 12 --
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 29 Serial I/O with FIFO (SIOF)
Bit 11 to 8
Bit Name CD0A[3:0]
Initial Value 0000
R/W R/W
Description Control Channel 0 Data Assigns 3 to 0 Specify the position of control channel 0 data in a receive or transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited * * Transmit data for the control channel 0 data is specified in the SITD0 bit in SITCR. Receive data for the control channel 0 data is stored in the SIRD0 bit in SIRCR.
7
CD1E
0
R/W
Control Channel 1 Data Enable 0: Disables transmission and reception of control channel 1 data 1: Enables transmission and reception of control channel 1 data
6 to 4
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
3 to 0
CD1A[3:0]
0000
R/W
Control Channel 1 Data Assigns 3 to 0 Specify the position of control channel 1 data in a receive or transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited * * Transmit data for the control channel 1 data is specified in the SITD1 bit in SITCR. Receive data for the control channel 1 data is stored in the SIRD1 bit in SIRCR.
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Section 29 Serial I/O with FIFO (SIOF)
29.4
29.4.1 (1)
Operation
Serial Clocks
Master/Slave Modes
The following modes are available as the SIOF clock mode. * Slave mode: SIOF_SCK, SIOF_SYNC input * Master mode: SIOF_SCK, SIOF_SYNC output (2) Baud Rate Generator
In SIOF master mode, the baud rate generator (BRG) is used to generate the serial clock. The division ratio is from 1/1 to 1/1024. Note that, when using master clock directly as the serial clock without division by BRG (division ratio: 1/1), the MSIMM bit in SISCR should be set to 1. Figure 29.2 shows connections for supply of the serial clock.
Baud rate generator Master clock Prescalar Divider
1/1 to 1/1024 Master clock
SIOF_MCLK Pck
Timing control
SCKE
Master
SIOF_SCK
Figure 29.2 Serial Clock Supply Table 29.5 shows an example of serial clock frequency.
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Section 29 Serial I/O with FIFO (SIOF)
Table 29.5 SIOF Serial Clock Frequency
Sampling Rate Frame Length 32 bits 64 bits 128 bits 256 bits 8 kHz 256 kHz 512 kHz 1.024 MHz 2.048 MHz 44.1 kHz 1.4112 MHz 2.8224 MHz 5.6448 MHz 11.2896 MHz 48 kHz 1.536 MHz 3.072 MHz 6.144 MHz 12.288 MHz
29.4.2
Serial Timing
SIOF_SYNC: The SIOF_SYNC is a frame synchronous signal. Depending on the transfer mode, it has the following two functions. * Synchronous pulse: 1-bit-width pulse indicating the start of the frame * L/R: 1/2-frame-width pulse indicating the left-channel stereo data (L) in high level and the right-channel stereo data (R) in low level Figure 29.3 shows the SIOF_SYNC synchronization timing.
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Section 29 Serial I/O with FIFO (SIOF)
(a) Synchronous pulse 1 frame
SIOF_SCK
SIOF_SYNC
SIOF_TXD
SIOF_RXD
Start bit data 1-bit delay (b) L/R 1 frame
SIOF_SCK
SIOF_SYNC SIOF_TXD
SIOF_RXD
Start bit of left channel data (1/2 frame length) No delay
Start bit of right channel data (1/2 frame length)
Figure 29.3 Serial Data Synchronization Timing
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Section 29 Serial I/O with FIFO (SIOF)
(1)
Transmit/Receive Timing
The SIOF_TXD transmit timing and SIOF_RXD receive timing relative to the SIOF_SCK can be set as the sampling timing in the following two ways. The transmit/receive timing is set using the REDG bit in SIMDR. * Falling-edge sampling * Rising-edge sampling Figure 29.4 shows the transmit/receive timing.
(a) Falling-edge sampling REDG = 0 (a) Rising-edge sampling REDG = 1 SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD Receive timing Transmit timing Receive timing Transmit timing
SIOF_SCK SIOF_SYNC
SIOF_TXD SIOF_RXD
Figure 29.4 SIOF Transmit/Receive Timing 29.4.3 Transfer Data Format
The SIOF performs the following transfer. * Transmit/receive data: Transfer of 8-bit data/16-bit data/16-bit stereo data * Control data: Transfer of 16-bit data (uses the specific register as interface) (1) Transfer Mode
The SIOF supports the following four transfer modes as listed in table 29.6. The transfer mode can be specified by the bits TRMD[1:0] in SIMDR.
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Section 29 Serial I/O with FIFO (SIOF)
Table 29.6 Serial Transfer Modes
TRMD[1:0] 00 01 10 11 Note: * Transfer Mode Slave mode 1 Slave mode 2 Master mode 1 Master mode 2 SIOF_SYNC Synchronous pulse Synchronous pulse Synchronous pulse L/R No Bit Delay SYNCDL bit Control Data* Slot position Secondary FS Slot position Not supported
The control data method is valid only when the FL bit is specified as B'1xxx (x: don't care).
(2)
Frame Length
The length of the frame to be transferred by the SIOF is specified by the bits FL[3:0] in SIMDR. Table 29.7 shows the relationship between the bits FL[3:0] settings and frame length. Table 29.7 Frame Length
FL[3:0] 00XX 0100 0101 0110 0111 10XX 1100 1101 1110 1111 Slot Length 8 8 8 8 8 16 16 16 16 16 Number of Bits in a Frame 8 16 32 64 128 16 32 64 128 256 Transfer Data 8-bit monaural data 8-bit monaural data 8-bit monaural data 8-bit monaural data 8-bit monaural data 16-bit monaural data 16-bit monaural stereo data 16-bit monaural stereo data 16-bit monaural stereo data 16-bit monaural stereo data
Note: X: Don't care.
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Section 29 Serial I/O with FIFO (SIOF)
(3)
Slot Position
The SIOF can specify the position of transmit data, receive data, and control data in a frame (common to transmission and reception) by slot numbers. The slot number of each data is specified by the following registers. * Transmit data: SITDAR * Receive data: SIRDAR * Control data: SICDAR Only 16-bit data is valid for control data. In addition, control data is always assigned to the same slot number both in transmission and reception. 29.4.4 (1) Register Allocation of Transfer Data
Transmit/Receive Data
Writing and reading of transmit/receive data is performed for the following registers. * Transmit data writing: SITDR (32-bit access) * Receive data reading: SIRDR (32-bit access) Figure 29.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment.
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Section 29 Serial I/O with FIFO (SIOF)
(a) 16-bit stereo data 31 24 23 L-channel data 16 15 87 R-channel data 0
(b) 16-bit monaural data 31 24 23 Data
16 15
87
0
(c) 8-bit monaural data 31 24 23 Data
16 15
87
0
(d) 16-bit stereo data (left and right same audio output) data 31 24 23 16 15 87 Data
0
Figure 29.5 Transmit/Receive Data Bit Alignment Note: In the figure, only the shaded areas are transmitted or received as valid data. Therefore, access must be made in byte units for 8-bit data, and in word units for 16-bit data. Data in unshaded areas is not transmitted or received. Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR. Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR. To achieve left and right same audio output while stereo is specified for transmit data, specify the TLREP bit in SITDAR. Table 29.8 and table 29.9 show the audio mode specification for transmit data and that for receive data, respectively. Table 29.8 Audio Mode Specification for Transmit Data
Bit Mode Monaural Stereo Left and right same audio output Note: x: Don't care TDLE 1 1 1 TDRE 0 1 1 TLREP x 0 1
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Section 29 Serial I/O with FIFO (SIOF)
Table 29.9 Audio Mode Specification for Receive Data
Bit Mode Monaural Stereo RDLE 1 1 RDRE 0 1
Note: Left and right same audio mode is not supported in receive data. To execute 8-bit monaural transmission or reception, use the left channel.
(2)
Control Data
Control data is written to or read from by the following registers. * Transmit control data write: SITCR (32-bit access) * Receive control data read: SIRCR (32-bit access) Figure 29.6 shows the control data and bit alignment in SITCR and SIRCR.
(a) Control data: One channel 31 24 23 Control data (channel 0) 16 15 87 0
(b) Control data: Two channels 31 24 23 Control data (channel 0)
16 15
87 Control data (channel 1)
0
Figure 29.6 Control Data Bit Alignment The number of channels in control data is specified by the CD0E and CD1E bits in SICDAR. Table 29.10 shows the relationship between the number of channels in control data and bit settings.
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Section 29 Serial I/O with FIFO (SIOF)
Table 29.10 Setting Number of Channels in Control Data
Bit Number of Channels 1 2 CD0E 1 1 CD1E 0 1
Note: To use only one channel in control data, use channel 0.
29.4.5
Control Data Interface
Control data performs control command output to the CODEC and status input from the CODEC. The SIOF supports the following two control data interface methods. * Control by slot position * Control by secondary FS Control data is valid only when data length is specified as 16 bits.
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Section 29 Serial I/O with FIFO (SIOF)
(1)
Control by Slot Position (Master Mode 1, Slave Mode 1)
Control data is transferred for all frames transmitted or received by the SIOF by specifying the slot position of control data. This method can be used in both SIOF master and slave modes. Figure 29.7 shows an example of the control data interface timing by slot position control.
1 frame SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD
L-channel data Control channel 0 R-channel data Control channel 1
Slot No.0
Slot No.1
Slot No.2
Slot No.3 FL[3:0] = 1110 (Frame length: 128 bits), TDRA[3:0] = 0010, TDRE = 1, RDRA[3:0] = 0010, RDRE = 1, CD1A[3:0] = 0011 CD1E = 1,
Specifications: TRMD[1:0] = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 1,
REDG = 0, TDLA[3:0] = 0000, RDLA[3:0] = 0000, CD0A[3:0] = 0001,
Figure 29.7 Control Data Interface (Slot Position) (2) Control by Secondary FS (Slave Mode 2)
The CODEC normally outputs the SIOF_SYNC signal as synchronization pulse (FS). In this method, the CODEC outputs the secondary FS specific to the control data transfer after 1/2 frame time has been passed (not the normal FS output timing) to transmit or receive control data. This method is valid for SIOF slave mode. The following summarizes the control data interface procedure by the secondary FS. * Transmit normal transmit data of LSB = 0 (the SIOF forcibly clears 0). * To execute control data transmission, send transmit data of LSB = 1 (the SIOF forcibly set to 1 by writing SITCR). * The CODEC outputs the secondary FS. * The SIOF transmits or receives (stores in SIRCR) control data (data specified by SITCR) synchronously with the secondary FS.
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Section 29 Serial I/O with FIFO (SIOF)
Figure 29.8 shows an example of the control data interface timing by the secondary FS.
1 frame 1/2 frame SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD
L-channel data
Control channel 0
1/2 frame
Normal FS
Secondary FS
Normal FS
Slot No.0
LSB=1 (Secondary FS request)
Slot No.0 FL[3:0] = 1110 (Frame length: 128 bits), TDRA[3:0] = 0000, TDRE = 0, RDRA[3:0] = 0000, RDRE = 0, CD1A[3:0] = 0000 CD1E = 0,
Specifications:TRMD[1:0] = 01, REDG = 0, TDLA[3:0] = 0000, TDLE = 1, RDLA[3:0] = 0000, RDLE = 1, CD0A[3:0] = 0000, CD0E = 1,
Figure 29.8 Control Data Interface (Secondary FS) 29.4.6 (1) FIFO
Overview
The transmit and receive FIFOs of the SIOF have the following features. * 16-stage 32-bit FIFOs for transmission and reception * The FIFO pointer can be updated in one read or write cycle regardless of access size of the CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.) (2) Transfer Request
The transfer request of the FIFO can be issued to the CPU or DMAC as the following interrupt sources. * FIFO transmit request: TDREQ (transmit interrupt source) * FIFO receive request: RDREQ (receive interrupt source) The request conditions for FIFO transmit or receive can be specified individually. The request conditions for the FIFO transmit and receive are specified by the bits TFWM[2:0] and the bits RFWM[2:0] in SIFCTR, respectively. Table 29.11 and table 29.12 summarize the conditions specified by SIFCTR.
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Section 29 Serial I/O with FIFO (SIOF)
Table 29.11 Conditions to Issue Transmit Request
TFWM[2:0] 000 100 101 110 111 Number of Requested Stages 1 4 8 12 16 Transmit Request Empty area is 16 stages Empty area is 12 stages or more Empty area is 8 stages or more Empty area is 4 stages or more Empty area is 1 stage or more Largest Used Areas Smallest
Table 29.12 Conditions to Issue Receive Request
RFWM[2:0] 000 100 101 110 111 Number of Requested Stages 1 4 8 12 16 Receive Request Valid data is 1 stage or more Valid data is 4 stages or more Valid data is 8 stages or more Valid data is 12 stages or more Valid data is 16 stages Largest Used Areas Smallest
The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the FIFO size (the number of FIFOs). Accordingly, an overflow error or underflow error occurs if data area or empty area exceeds sixteen FIFO stages. The FIFO transmit or receive request is canceled when the above condition is not satisfied even if the FIFO is not empty or full. (3) Number of FIFOs
The number of FIFO stages used in transmission and reception is indicated by the following register. * Transmit FIFO: The number of empty FIFO stages is indicated by the bits TFUA[4:0] in SIFCTR. * Receive FIFO: The number of valid data stages is indicated by the bits RFUA[4:0] in SIFCTR. The above indicate possible data numbers that can be transferred by the CPU or DMAC.
Rev. 1.00 Oct. 01, 2007 Page 1228 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
29.4.7 (1)
Transmit and Receive Procedures
Transmission in Master Mode
Figure 29.9 shows an example of settings and operation for master mode transmission.
No.
Flow Chart SIOF Settings SIOF Operation
Start 1
Set SIMDR, SISCR, SITDAR, SICDAR, SITCR, and SIFCTR Set operating mode, serial clock, slot positions for transmit data, slot position for control data, control data, and FIFO request threshold value Set operation start for baud rate generator
2
Set the SCKE bit in SICTR to 1
3
Start SIOF_SCK output
Output serial clock
4
Set the FSE and TXE bits in SICTR to 1
Set the start for frame synchronous signal output and enable transmission
Output frame synchronous signal and issue transmit transfer request*
5
TDREQ = 1?
No
Yes 6
Set SITDR Set transmit data
7
Transmit SITDR from SIOF_TXD synchronously with SIOF_SYNC
Transmit
Transfer ended?
No
Set to disable transmission End transmission
8
Yes
Clear the TXE bit in SICTR to 0
End
Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the TXE bit should be set to 1.
Figure 29.9 Example of Transmit Operation in Master Mode
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Section 29 Serial I/O with FIFO (SIOF)
(2)
Reception in Master Mode
Figure 29.10 shows an example of settings and operation for master mode reception.
No. Flow Chart Start 1 Set operating mode, serial clock, slot positions for receive data, slot position for control data, and FIFO request threshold value SIOF Settings SIOF Operation
Set SIMDR, SISCR, SIRDAR, SICDAR, and SIFCTR
2
Set the SCKE bit in SICTR to 1
Set operation start for baud rate generator
3
Start SIOFSCK output
Output serial clock
4
Set the FSE and RXE bits in SICTR to 1
Set the start for frame synchronous signal output and enable reception
Output frame synchronous signal
5
Store SIOFRXD receive data in SIRDR synchronously with SIOF_SYNC
Issue receive transfer request according to the receive FIFO threshold value
6
RDREQ = 1? Yes
No
Reception
7
Read SIRDR
Read receive data
Transfer ended? 8 Yes
No Set to disable reception End reception
Clear the RXE bit in SICTR to 0 End
Figure 29.10 Example of Receive Operation in Master Mode
Rev. 1.00 Oct. 01, 2007 Page 1230 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
(3)
Transmission in Slave Mode
Figure 29.11 shows an example of settings and operation for slave mode transmission.
No. Flow Chart Start 1 Set operating mode, serial clock, slot positions for transmit data, slot position for control data, control data, and FIFO request threshold value Issue transmit transfer request to enable transmission when frame synchronous signal is input SIOF Settings SIOF Operation
Set SIMDR, SISCR, SITDAR, SICDAR, SITCR, and SIFCTR
2
Set the TXE bit in SICTR to 1
Set to enable transmission
3
TDREQ = 1? Yes
No
4
Set SITDR
Set transmit data
5
Transmit SITDR from SIOFTXD synchronously with SIOF_SYNC
Transmit
Transfer ended? Yes 6
No Set to disable transmission End transmission
Clear the TXE bit in SICTR to 0 End
Figure 29.11 Example of Transmit Operation in Slave Mode
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Section 29 Serial I/O with FIFO (SIOF)
(4)
Reception in Slave Mode
Figure 29.12 shows an example of settings and operation for slave mode reception.
No. Flow Chart Start 1 Set SIMDR, SISCR, SIRDAR, SICDAR, and SIFCTR SIOF Settings SIOF Operation
Set operating mode, serial clock, slot positions for receive data, slot position for control data, and FIFO request threshold value Set to enable reception Enable reception when the frame synchronous signal is input Issue receive transfer request according to the receive FIFO threshold value
2
Set the RXE bit in SICTR to 1
3
Store SIOFRXD receive data in SIRDR synchronously with SIOF_SYNC
4
RDREQ = 1? Yes
No
Reception
5
Read SIRDR
Read receive data
Transfer ended? 6 Yes
No Set to disable reception End reception
Clear the RXE bit in SICTR to 0 End
Figure 29.12 Example of Receive Operation in Slave Mode
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Section 29 Serial I/O with FIFO (SIOF)
(5)
Transmit/Receive Reset
The SIOF can separately reset the transmit and receive units by setting the following bits to 1. * Transmit reset: TXRST bit in SICTR * Receive reset: RXRST bit in SICTR Table 29.13 shows the details of initialization upon transmit or receive reset. Table 29.13 Transmit and Receive Reset
Type Transmit reset Objects Initialized Stop transmitting form the SIOF_TXD (high level is outputted) Transmit FIFO write pointer TCRDY, TFEMP, and TDREQ bits in SISTR TXE bit in SICTR Receive reset Stop receiving form the SIOF_RXD Receive FIFO write pointer RCRDY, RFFUL, and RDREQ bits in SISTR RXE bit in SICTR
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Section 29 Serial I/O with FIFO (SIOF)
29.4.8
Interrupts
The SIOF has one type of interrupt. (1) Interrupt Sources
Interrupts can be issued by several sources. Each source is shown as an SIOF status in SISTR. Table 29.14 lists the SIOF interrupt sources. Table 29.14 SIOF Interrupt Sources
No. Classification 1 2 3 4 5 6 7 8 Error Control Reception Transmission Bit Name TDREQ TFEMP RDREQ RFFUL TCRDY RCRDY TFUDF TFOVF Function Name Description
Transmit FIFO transfer The transmit FIFO stores data of request specified size or more. Transmit FIFO empty Receive FIFO transfer request Receive FIFO full Transmit control data ready Receive control data ready Transmit FIFO underflow The transmit FIFO is empty. The receive FIFO stores data of specified size or more. The receive FIFO is full. The transmit control register is ready to be written. The receive control data register stores valid data. Serial data transmit timing has arrived while the transmit FIFO is empty.
Transmit FIFO overflow Write to the transmit FIFO is performed while the transmit FIFO is full. Receive FIFO overflow Serial data is received while the receive FIFO is full. Receive FIFO underflow FS error The receive FIFO is read while the receive FIFO is empty. A synchronous signal is input before the specified bit number has been passed (in slave mode). The same slot is specified in both serial data and control data.
9 10 11
RFOVF RFUDF FSERR
12
SAERR
Assign error
Whether an interrupt is issued or not as the result of an interrupt source is determined by the SIIER settings. If an interrupt source is set to 1 and the corresponding bit in SIIER is set to 1, an SIOF interrupt is issued.
Rev. 1.00 Oct. 01, 2007 Page 1234 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
(2)
Regarding Interrupt Source
The transmit sources and receive sources are signals indicating the SIOF state; after being set, if the state changes, they are automatically cleared by the SIOF. When the DMA transfer is used, a DMA transfer request of the FIFO is disabled for one cycle at the end of that DMA transfer. (3) Processing when Errors Occur
On occurrence of each of the errors indicated as a status in SISTR, the SIOF performs the following operations. * Transmit FIFO underflow (TFUDF) The immediately preceding transmit data is again transmitted. * Transmit FIFO overflow (TFOVF) The contents of the transmit FIFO are protected, and the write operation causing the overflow is ignored. * Receive FIFO overflow (RFOVF) Data causing the overflow is discarded and lost. * Receive FIFO underflow (RFUDF) An undefined value is output on the bus. * FS error (FSERR) The internal counter is reset according to the signal in which an error occurs. * Assign error (SAERR) If the same slot is assigned to both serial data and control data, the slot is assigned to serial data. If the same slot is assigned to two control data items, data cannot be transferred correctly.
Rev. 1.00 Oct. 01, 2007 Page 1235 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
29.4.9
Transmit and Receive Timing
Examples of the SIOF serial transmission and reception are shown in figure 29.13 to figure 29.19. (1) 8-bit Monaural Data (Case 1)
Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, an frame length = 8 bits
1 frame
SIOF_SCK
SIOF_SYNC
SIOF_TXD
L-channel data
SIOF_RXD
Slot No.0
1-bit delay
Specifications: TRMD[1:0] = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 0,
REDG = 0, TDLA[3:0] = 0000, RDLA[3:0] = 0000, CD0A[3:0] = 0000,
FL[3:0] = 0000 (frame length: 8 bits) TDRE = 0, TDRA[3:0] = 0000, RDRE = 0, RDRA[3:0] = 0000, CD1E = 0, CD1A[3:0] = 0000
Figure 29.13 Transmit and Receive Timing (8-Bit Monaural Data (1))
Rev. 1.00 Oct. 01, 2007 Page 1236 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
(2)
8-bit Monaural Data (Case 2)
Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, and frame length = 16 bits
1 frame
SIOF_SCK
SIOF_SYNC
SIOF_TXD
L-channel data
SIOF_RXD
Slot No.0 1-bit delay
Slot No.1
Specifications: TRMD[1:0] = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 0,
REDG = 0, FL[3:0] = 0100 (frame length: 16 bits) TDLA[3:0] = 0000, TDRE = 0, TDRA[3:0] = 0000, RDLA[3:0] = 0000, RDRE = 0, RDRA[3:0] = 0000, CD0A[3:0] = 0000, CD1E = 0, CD1A[3:0] = 0000
Figure 29.14 Transmit and Receive Timing (8-Bit Monaural Data (2)) (3) 16-bit Monaural Data
Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, and frame length = 64 bits
1 frame
SIOF_SCK
SIOF_SYNC
SIOF_TXD SIOF_RXD
L-channel data
Slot No.0 1-bit delay Specifications: TRMD[1:0] = 00 or 10, REDG = 0, TDLE = 1, TDLA[3:0] = 0000, RDLE = 1, RDLA[3:0] = 0000, CD0E = 0, CD0A[3:0] = 0000, Slot No.1 Slot No.2 Slot No.3
FL[3:0] = 1101 (frame length: 64 bits) TDRE = 0, TDRA[3:0] = 0000, RDRE = 0, RDRA[3:0] = 0000, CD1E = 0, CD1A[3:0] = 0000
Figure 29.15 Transmit and Receive Timing (16-Bit Monaural Data)
Rev. 1.00 Oct. 01, 2007 Page 1237 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
(4)
16-bit Stereo Data (Case 1)
L/R method, rising edge sampling, slot No.0 used for left channel data, slot No.1 used for right channel data, and frame length = 32 bits
1 frame
SIOF_SCK
SIOF_SYNC
SIOF_TXD
L-channel data
SIOF_RXD
No bit delay
R-channel data Slot No.1
Slot No.0 Specifications: TRMD[1:0] = 11, TDLE = 1, RDLE = 1, CD0E = 0,
REDG = 1, TDLA[3:0] = 0000, RDLA[3:0] = 0000, CD0A[3:0] = 0000,
FL[3:0] = 1100 (frame length: 32 bits) TDRE = 1, TDRA[3:0] = 0001, RDRE = 1, RDRA[3:0] = 0001, CD1E = 0, CD1A[3:0] = 0000
Figure 29.16 Transmit and Receive Timing (16-Bit Stereo Data (1)) (5) 16-bit Stereo Data (Case 2)
L/R method, rising edge sampling, slot No.0 used for left-channel transmit data, slot No.1 used for left-channel receive data, slot No.2 used for right-channel transmit data, slot No.3 used for rightchannel receive data, and frame length = 64 bits
1 frame SIOF_SCK SIOF_SYNC SIOF_TXD L-channel data R-channel data
SIOF_RXD Slot No.0 No bit delay
L-channel data Slot No.1 Slot No.2
R-channel data Slot No.3
Specifications: TRMD[1:0] = 01, TDLE = 1, RDLE = 1, CD0E = 0,
REDG = 1, TDLA[3:0] = 0000, RDLA[3:0] = 0001, CD0A[3:0] = 0000,
FL[3:0] = 1101 (frame length: 64 bits), TDRA[3:0] = 0010, TDRE = 1, RDRA[3:0] = 0011, RDRE = 1, CD1A[3:0] = 0000 CD1E = 0,
Figure 29.17 Transmit and Receive Timing (16-Bit Stereo Data (2))
Rev. 1.00 Oct. 01, 2007 Page 1238 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
(6)
16-bit Stereo Data (Case 3)
Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.1 used for right-channel data, slot No.2 used for control data for channel 0, slot No.3 used for control data for channel 1, and frame length = 128 bits
1 frame
SIOF_SCK
SIOF_SYNC
SIOF_TXD SIOF_RXD
L-channel data
R-channel data
Slot No.0
Slot No.1
Control Control channel 0 channel 1 Slot No.2 Slot No.3 Slot No.4
Slot No.5
Slot No.6
Slot No.7
1 bit delay Specifications: TRMD[1:0] = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 1,
REDG = 0, TDLA[3:0] = 0000, RDLA[3:0] = 0000, CD0A[3:0] =0010,
FL[3:0] = 1110 (frame length: 128 bits), TDRE = 1, TDRA[3:0] = 0001, RDRE = 1, RDRA[3:0] = 0001, CD1E = 1, CD1A[3:0] = 0011
Figure 29.18 Transmit and Receive Timing (16-Bit Stereo Data (3)) (7) 16-bit Stereo Data (Case 4)
Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.2 used for right-channel data, slot No.1 used for control data for channel 0 , slot No.3 used for control data for channel 1, and frame length = 128 bits
1 frame SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD
L-channel data Control channel 0 R-channel data Control channel 1
Slot No.0
Slot No.1
Slot No.2
Slot No.3
Slot No.4
Slot No.5
Slot No.6
Slot No.7
1 bit delay Specifications: TRMD[1:0] = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 1, REDG = 1, TDLA[3:0] = 0000, RDLA[3:0] = 0000, CD0A[3:0] = 0001, FL[3:0] = 1110 (frame length: 128 bits) TDRA[3:0] = 0010, TDRE = 1, RDRA[3:0] = 0010, RDRE = 1, CD1A[3:0] = 0011 CD1E = 1,
Figure 29.19 Transmit and Receive Timing (16-Bit Stereo Data (4))
Rev. 1.00 Oct. 01, 2007 Page 1239 of 1956 REJ09B0256-0100
Section 29 Serial I/O with FIFO (SIOF)
(8)
Synchronization-Pulse Output Mode at End of Each Slot (SYNCAT Bit = 1)
Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.1 used for right-channel data, slot No.2 used for control data for channel 0, slot No.3 used for control data for channel 1, and frame length = 128 bits In this mode, valid data must be set to slot No. 0.
1 frame SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD
L-channel data R-channel data Control channel 0 Control channel 1
Slot No.0
Slot No.1
Slot No.2
Slot No.3
Slot No.4
Slot No.5
Slot No.6
Slot No.7
REDG = 0, Specifications: TRMD[1:0] = 00 or 10, TDLE = 1, TDLA[3:0] = 0000, RDLE = 1, RDLA[3:0] = 0000, CD0E = 1, CD0A[3:0] = 0010,
FL[3:0] = 1110 (frame length: 128 bits), TDRE = 1, TDRA[3:0] = 0001, RDRE = 1, RDRA[3:0] = 0001, CD1E = 1, CD1A[3:0] = 0011
Figure 29.20 Transmit and Receive Timing (16-Bit Stereo Data)
Rev. 1.00 Oct. 01, 2007 Page 1240 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Section 30 SIM Card Module (SIM)
The smart card interface supports IC cards (smart cards) conforming to the ISO/IEC 7816-3 (Identification Card) specification.
30.1
Features
* Communication functions Asynchronous half-duplex transmission Protocol selectable between T = 0 and T = 1 modes Data length: 8 bits Parity bit generation and check Selectable character protection addition time Selectable output clock cycles per etu Transmission of error signal (parity error) in receive mode when T = 0 Detection of error signal and automatic character retransmission in transmit mode when T = 0 Selectable minimum character interval of 11 etus (N = 255) when T = 1 (etu: Elementary Time Unit) Selectable direct convention/inverse convention Output clock can be fixed in high or low state * Freely selectable bit rate by on-chip baud rate generator * Four types of interrupt source Transmit data empty, receive data full, transmit/receive error, transmit complete * DMA transfer Through DMA transfer requests for transmit data empty and receive data full, the direct memory access controller (DMAC) can be started and used for data transfer. * The time waiting for the operation when T = 0, and the time waiting for a character when T = 1 can be observed.
Rev. 1.00 Oct. 01, 2007 Page 1241 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Figure 30.1 shows a block diagram of the smart card interface.
Module data bus
Peripheral bus
Bus interface
Transmit/receive control
SCRDR
SCTDR
SCSMR
SCSCR
SCSSR
SCSCMR
SCSC2R
SCWAIT
SCGRD
SCBRR
SCSMPL
SIM_D
SCRSR
SCTSR Parity generation
Baud rate generator
Pck0
Parity check
SIM_CLK SIM_RST
Serial clock ERI TXI RXI TEI
Receive data full DMA controller interrupt controller
Transmit data empty
[Legend]
SCSCMR : Smart card mode register SCRSR : Receive shift register SCRDR : Receive data register SCTSR : Transmit shift register SCTDR : Transmit dara register SCSMR : Serial mode register SCSCR : Serial control register
SCSC2R : Serial control 2 register SCSSR : Serial status register SCBRR : Bit rate register SCWAIT : Wait time register SCGRD : Guard extension register SCSMPL : Sampling register
Figure 30.1 Smart Card Interface
Rev. 1.00 Oct. 01, 2007 Page 1242 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
30.2
Input/Output Pins
The pin configuration of the smart card interface is shown in table 30.1. Table 30.1 Pin Configuration
Name Transmit/receive data Clock output Smart card reset Note: * Abbreviation SIM_D* SIM_CLK SIM_RST I/O I/O Output Output Function Transmit/receive data input/output Clock output Smart card reset output
In explaining transmit and receive operations, the transmit data and receive data sides shall be referred to as TxD and RxD, respectively.
Rev. 1.00 Oct. 01, 2007 Page 1243 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
30.3
Register Descriptions
Table 30.2 shows the SIM register configuration. Table 30.3 shows the register state in each operating mode. Table 30.2 Register Configuration
Register Name Abbreviation R/W Area P4 Address* Area 7 Address* Access Size
Serial mode register Bit rate register Serial control register Transmit shift register Transmit data register Serial status register Receive shift register Receive data register Smart card mode register Serial control 2 register Wait time register Guard extension register Sampling register Note: *
SCSMR SCBRR SCSCR SCTSR SCTDR SCSSR SCRSR SCRDR SCSCMR SCSC2R SCWAIT SCGRD SCSMPL
R/W R/W R/W R/W R/W R R/W R/W R/W R R/W
H'FFE9 0000 H'1FE9 0000 8 H'FFE9 0002 H'1FE9 0002 8 H'FFE9 0004 H'1FE9 0004 8
H'FFE9 0006 H'1FE9 0006 8 H'FFE9 0008 H'1FE9 0008 8
H'FFE9 000A H'1FE9 000A 8 H'FFE9 000C H'1FE9 000C 8 H'FFE9 000E H'1FE9 000E 8 H'FFE9 0010 H'1FE9 0010 16 H'FFE9 0012 H'1FE9 0012 8 H'FFE9 0014 H'1FE9 0014 16
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
Rev. 1.00 Oct. 01, 2007 Page 1244 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Table 30.3 Register State in Each Operating Mode
Register Name Serial mode register Bit rate register Serial control register Transmit shift register Transmit data register Serial status register Receive shift register Receive data register Smart card mode register Serial control 2 register Wait time register Guard extension register Sampling register Abbreviation SCSMR SCBRR SCSCR SCTSR SCTDR SCSSR SCRSR SCRDR SCSCMR SCSC2R SCWAIT SCGRD SCSMPL Power-On Reset H'20 H'07 H'00 H'FF H'84 H'00 H'01 H'00 H'0000 H'00 H'0173 Manual Reset H'20 H'07 H'00 H'FF H'84 H'00 H'01 H'00 H'0000 H'00 H'0173 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 1245 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
30.3.1
Serial Mode Register (SCSMR)
SCSMR is an 8-bit readable/writable register that selects settings for the communication format of the smart card interface.
Bit: 7 6 5
PE
4
O/E
3
2
1
0
-
Initial value: R/W:
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
1 R
0 R/W
Bit 7, 6
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
5
PE
1
R
Parity Enable This bit is always read as 1. The write value should always be 1.
4
O/E
0
R/W
Parity Mode Selects whether even or odd parity is to be used when adding a parity bit and checking parity. 0: Even parity* 1: Odd parity*
2 1
Notes: 1. When set to even parity, during transmission a parity bit is added such that the sum of 1 bits in the parity bit and transmit characters is even. During reception, a check is performed to ensure that the sum of 1 bits in the parity bit and the receive characters is even. 2. When set to odd parity, during transmission a parity bit is added such that the sum of 1 bits in the parity bit and transmit characters is odd. During reception, a check is performed to ensure that the sum of 1 bits in the parity bit and the receive characters is odd. 3 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1246 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
30.3.2
Bit Rate Register (SCBRR)
SCBRR is an 8-bit readable/writable register that sets the transmit/receive bit rate.
Bit: 7 6 5 4 3 2 1
BRR[2:0]
0
-
Initial value: R/W:
0 R
-
0 R
-
0 R
-
0 R
-
0 R 1 R/W
1 R/W
1 R/W
Bit 7 to 3
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2 1 0
BRR2 BRR1 BRR0
1 1 1
R/W R/W R/W
Set the transmit/receive bit rate 2 to 0.
The SCBRR setting can be determined from the following formula.
sck_frequency =
Pck0 2 (BRR + 1)
The units of Pck0 (peripheral clock 0 frequency) and sck_frequency are MHz.
Rev. 1.00 Oct. 01, 2007 Page 1247 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
30.3.3
Serial Control Register (SCSCR)
SCSCR is an 8-bit readable/writable register that selects transmit or receive operation, the serial clock output, and whether to enable or disable interrupt requests for the smart card interface.
Bit: 7
TIE
6
RIE
5
TE
4
RE
3
WAIT_ IE
2
TEIE
1
0
CKE[1:0]
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name TIE
Initial Value 0
R/W R/W
Description Transmit Interrupt Enable When serial transmit data is transferred from the transmit data register (SCTDR) to the transmit shift register (SCTSR), and the TDRE flag in the serial status register (SCSSR) is set to 1, transmit data empty interrupt (TXI) requests are enabled/disabled. 0: Disables transmit data empty interrupt (TXI) requests* 1: Enables transmit data empty interrupt (TXI) requests Note: * A TXI can be canceled either by clearing the TDRE flag, or by clearing the TIE bit to 0.
6
RIE
0
R/W
Receive Interrupt Enable When serial receive data is transferred from the receive shift register (SCRSR) to the receive data register (SCRDR), and the RDRF flag in SCSSR is set to 1, receive data full interrupt (RXI) requests, and transmit/receive error interrupt (ERI) requests due to parity errors, overrun errors, and error signal status are enabled/disabled. 0: Disables receive data full interrupt (RXI) requests and 12 transmit/receive error interrupt (ERI) requests* * 1: Enables receive data full interrupt (RXI) requests and 2 transmit/receive error interrupt (ERI) requests* Notes: 1. RXI and ERI interrupt requests can be canceled either by clearing the RDRF, PER, ORER or ERS flag, or by clearing the RIE bit to 0. 2. Wait error interrupt (ERI) requests are enabled or disabled by using the WAIT_IE bit in SCSCR.
Rev. 1.00 Oct. 01, 2007 Page 1248 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Bit 5
Bit Name TE
Initial Value 0
R/W R/W
Description Transmit Enable Enables/disables serial transmit operations. 0: Disables transmission*
1 3
1: Enables transmission* *
2
Notes: 1. The TDRE flag in SCSSR is fixed to 1. 2. In this state, if transmit data is written to SCTDR, the transmit operation is initiated. Before setting the TE bit to 1, the serial mode register (SCSMR) and smart card mode register (SCSCMR) must always be set, to determine the transmit format. 3. Even if the TE bit is cleared to 0, the ERS flag is unaffected, and the previous state is retained. 4 RE 0 R/W Receive Enable Enables/disables serial receive operations. 0: Disables reception*
1
1: Enables reception*2 Notes: 1. Clearing the RE bit to 0 has no effect on the RDRF, PER, ERS, ORER, or WAIT_ER flag, and the previous state is retained. 2. If the start bit is detected in this state, serial reception is initiated. Before setting the RE bit to 1, SCSMR and SCSCMR must always be set, to determine the receive format. 3 WAIT_IE 0 R/W Wait Enable Enables/disables wait error interrupt requests. 0: Disables wait error interrupt (ERI) requests 1: Enables wait error interrupt (ERI) requests 2 TEIE 0 R/W Transmit End Interrupt Enable When transmission ends and the TEND flag is set to 1, transmit end interrupt (TEI) requests are enabled/disabled. 0: Disables transmit end interrupt (TEI) requests* 1: Enables transmit end interrupt (TEI) requests* Note: * A TEI can be canceled either by writing transmit data to SCTDR and clearing the TEND bit, or by clearing the TEIE bit to 0 after the TDRE flag in SCSSR is read as 1.
Rev. 1.00 Oct. 01, 2007 Page 1249 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Bit 1, 0
Bit Name CKE[1:0]
Initial Value 00
R/W R/W
Description Clock Enable Select the clock source for the smart card interface, and enable/disable clock output from the SIM_CLK pin. 00: Fix the output pin at low 01: Clock output as the output pin 10: Fix the output pin at high 11: Clock output as the output pin
30.3.4
Transmit Shift Register (SCTSR)
SCTSR is a shift register that transmits serial data. The smart card interface transfers transmit data from the transmit data register (SCTDR) to SCTSR, and then sends the data in order from the LSB or MSB to the SIM_TXD pin to perform serial data transmission. When data transmission of one byte is completed, transmit data is automatically transferred from SCTDR to SCTSR, and transmission is initiated. When the TDRE flag in the serial status register (SCSSR) is set to 1, no data is transferred from SCTDR to SCTSR. Direct reading and writing of SCTSR from the CPU or DMAC is not possible.
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Section 30 SIM Card Module (SIM)
30.3.5
Transmit Data Register (SCTDR)
SCTDR is an 8-bit readable/writable register that stores data for serial transmission. When the smart card interface detects a vacancy in the transmit shift register (SCTSR), transmit data written to SCTDR is transferred to SCTSR, and serial transmission is initiated. During SCTSR serial data transmission, if the next transmit data is written to SCTDR, continuous serial transmission is possible.
Bit: 7 6 5 4 3 2 1 0
SCTD[7:0]
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 7 to 0
Bit Name
Initial Value
R/W R/W
Description Transmit Data Store data for serial transmission.
SCTD[7:0] All 1
Rev. 1.00 Oct. 01, 2007 Page 1251 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
30.3.6
Serial Status Register (SCSSR)
SCSSR is an 8-bit readable/writable register that indicates the operating state of the smart card interface.
Bit: 7
TDRE
6
RDRF
5
ORER
4
ERS
3
PER
2
TEND
1
WAIT_ ER
0
Initial value: R/W:
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R
0 R/W
0 R
Bit 7
Bit Name TDRE
Initial Value 1
R/W R/W
Description Transmit Data Register Empty Indicates that data was transferred from the transmit data register (SCTDR) to the transmit shift register (SCTSR), and that the next serial transmit data can be written to SCTDR. 0: Indicates that valid transmit data is written to SCTDR [Clearing conditions] * * When the TE bit in CCSCR is 1, and data is written to SCTDR When 0 is written to the TDRE bit
1: Indicates that there is no valid transmit data in SCTDR [Setting conditions] * * * On reset When the TE bit in SCSCR is 0 When data is transferred from SCTDR to SCTSR, and data can be written to SCTDR
Rev. 1.00 Oct. 01, 2007 Page 1252 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Bit 6
Bit Name RDRF
Initial Value 0
R/W R/W
Description Receive Data Register Full Indicates that received data is stored in the receive data register (SCRDR). 0: Indicates that no valid received data is stored in SCRDR [Clearing conditions] * * * On reset When data is read from SCRDR When 0 is written to RDRF
1: Indicates that valid received data is stored in SCRDR [Setting condition] When serial reception is completed normally, and received data is transferred from SCRSR to SCRDR. Note: In T = 0 mode, when a parity error is detected during reception, the SCRDR contents and RDRF flag are unaffected, and the previous state is retained. On the other hand, in T = 1 mode, when a parity error is detected during reception, the received data is transferred to SCRDR, and the RDRF flag is set to 1. In both T = 0 and T = 1 modes, even if the RE bit in the serial control register (SCSCR) is cleared to 0, the SCRDR contents and RDRF flag are unaffected, and the previous state is retained.
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Section 30 SIM Card Module (SIM)
Bit 5
Bit Name ORER
Initial Value 0
R/W R/W
Description Overrun Error Indicates that an overrun error occurred during reception, resulting in abnormal termination. 0: Indicates that reception is in progress, or that reception was completed normally*1 [Clearing conditions] * * On reset When 0 is written to the ORER bit
1: Indicates that an overrun error occurred during reception*2 [Setting condition] When the RDRF bit is set to 1 and the next serial reception is completed. Notes: 1. When the RE bit in SCSCR is cleared to 0, the ORER flag is unaffected and the previous state is retained. 2. In SCRDR, the received data before the overrun error occurred is lost, and the data that had been received at the time when the overrun error occurred is retained. Further, with the ORER bit set to 1, subsequent serial reception cannot be continued. 4 ERS 0 R/W Error Signal Status Indicates the status of error signals returned from the receive side during transmission. In T = 1 mode, this flag is not set. 0: Indicates that an error signal indicating detection of a parity error was not sent from the receive side [Clearing conditions] * * On reset When 0 is written to the ERS bit
1: Indicates that an error signal indicating detection of a parity error was sent from the receive side [Setting condition] When an error signal is sampled. Note: Even if the TE bit in SCSCR is cleared to 0, the ERS flag is unaffected, and the previous state is retained.
Rev. 1.00 Oct. 01, 2007 Page 1254 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Bit 3
Bit Name PER
Initial Value 0
R/W R/W
Description Parity Error Indicates that a parity error has occurred during reception, resulting in abnormal termination. 0: Indicates that reception is in progress, or that reception was completed normally*1 [Clearing conditions] * * On reset When 0 is written to the PER bit
2
1: Indicates that a parity error occurred during reception* [Setting condition]
When the sum of 1 bits in the received data and parity bit does not match the even or odd parity specified by the O/E bit in the serial mode register (SCSMR). Notes: 1. When the RE bit in SCSCR is cleared to 0, the PER flag is unaffected, and the previous state is retained. 2. In T = 0 mode, the data received when a parity error occurs is not transferred to SCRDR, and the RDRF flag is not set. On the other hand, in T = 1 mode, the data received when a parity error occurs is transferred to SCRDR, and the RDRF flag is set. When a parity error occurs, the PER flag should be cleared to 0 before the sampling timing for the next parity bit.
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Section 30 SIM Card Module (SIM)
Bit 2
Bit Name TEND
Initial Value 1
R/W R
Description Transmit End Indicates that transmission is ended. The TEND flag is read-only, and cannot be written. 0: Indicates that transmission is in progress [Clearing condition] When transmit data is transferred from SCTDR to SCTSR, and serial transmission is initiated. 1: Indicates that transmission is ended [Setting conditions] * * On reset When the ERS flag is 0 (normal transmission) after one byte of serial character and a parity bit are transmitted
Note: The TEND flag is set 1 etu before the end of the character protection time.
Rev. 1.00 Oct. 01, 2007 Page 1256 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Bit 1
Bit Name WAIT_ER
Initial Value 0
R/W R/W
Description Wait Error Indicates the wait timer error status. 0: Indicates that the interval between the start of two successive characters has not exceeded the etu set by SCWAIT. [Clearing conditions] * * On reset When 0 is written to the WAIT_ER flag
1: Indicates that the interval between the start of two successive characters has exceeded the etu set by SCWAIT. [Setting conditions] * In T = 0 mode, when the interval between the start of a character to be received and immediately preceding transmitted or received character exceeds the (value of 60 x SCWAIT: Operation wait time) etu. In T = 1 mode, when the interval between the start of two successive received characters exceeds the (SCWAIT value: Character protection time) etu. 1. Even if the RE bit in SCSCR is cleared to 0, the WAIT_ER flag is unaffected, and the previous state is retained. 2. In T = 0 mode, even if the setting condition for the WAIT_ER flag is satisfied when the RE bit is set to 1, the WAIT_ER flag may not be set to 1. In this case, the RE bit has been set to 1, then the WAIT_ER flag is set to 1 after 60 x (SCWAIT + n) etu (n 0: depending on the timing for setting the RE bit to 1) since the last transmission or reception. 3. In T = 0 mode, if the WAIT_ER flag does not need to be set to 1 after 60 x (SCWAIT + n) etu since the last transmission or reception, the mode should be changed from T = 0 to T = 1, and changed to T = 0 again by the PB bit in SCSCMR. In T = 1 mode, if the WAIT_ER flag does not need to be set to 1 after (SCWAIT) etu since the last reception, the mode should be changed from T = 1 to T = 0, and changed to T = 1 again by the PB bit in SCSCMR.
*
Notes:
Rev. 1.00 Oct. 01, 2007 Page 1257 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Bit 0
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
30.3.7
Receive Shift Register (SCRSR)
SCRSR is a register that receives serial data. The smart card interface receives serial data input from the SIM_RXD pin in order, from the LSB or MSB, and sets it in SCRSR, converting it to parallel data. When reception of one byte of data is completed, the data is automatically transferred to SCRDR. The CPU or DMAC cannot directly read from or write to SCRSR. 30.3.8 Receive Data Register (SCRDR)
SCRDR is an 8-bit read-only register that stores received serial data. When reception of one byte of serial data is completed, the smart card interface transfers the received serial data from the receive shift register (SCRSR) to SCRDR for storage, and completes the receive operation. Thereafter, SCRSR can receive data. In this way, SCRSR and SCRDR constitute a double buffer, enabling continuous reception of data. SCRDR cannot be written to by the CPU or DMAC.
Bit: 7 6 5 4 3 2 1 0
SCRD[7:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 7 to 0
Bit Name
Initial Value
R/W R
Description Receive Data Store received serial data.
SCRD[7:0] All 0
Rev. 1.00 Oct. 01, 2007 Page 1258 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
30.3.9
Smart Card Mode Register (SCSCMR)
SCSCMR is an 8-bit readable/writable register that selects functions of the smart card interface.
Bit: 7 6
LCB
5
PB
4
3
SDIR
2
SINV
1
RST
0
SMIF
-
Initial value: R/W:
0 R/W
-
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
Bit 7
Bit Name
Initial Value 0
R/W R/W
Description Reserved This bit is always read as 0. The write value should always be 0.
6
LCB
0
R/W
Last Character When this bit is set to 1, the character protection time is 2 etus, and the setting of the guard extension register is invalid. 0: The character protection time is determined by the value of the guard extension register. 1: The character protection time is 2 etus.
5
PB
0
R/W
Protocol Selects the T = 0 or T = 1 protocol. 0: The smart card interface operates according to the T = 0 protocol. 1: The smart card interface operates according to the T = 1 protocol.
4
0
R/W
Reserved This bit is always read as 0. The write value should always be 0.
3
SDIR
0
R/W
Smart Card Data Transfer Direction Selects the format for serial/parallel conversion. 0: Transmits the SCTDR contents in LSB-first. Received data is stored in SCRDR as LSB-first. 1: Transmits the SCTDR contents in MSB-first. Received data is stored in SCRDR as MSB-first.
Rev. 1.00 Oct. 01, 2007 Page 1259 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Bit 2
Bit Name SINV
Initial Value 0
R/W R/W
Description Smart Card Data Inversion Specifies inversion of the data logic level. In combination with the function of bit 3, used for transmission to or reception from the inverse convention card. The SINV bit does not affect the parity bit. 0: Transmits the SCTDR contents without change. Stores received data in SCRDR without change. 1: Inverts the SCTDR contents and transmits it. Inverts received data and stores it in SCRDR.
1
RST
0
R/W
Smart Card Reset Controls the output of the SIM_RST pin of the smart card interface. 0: The SIM_RST pin of the smart card interface outputs low level. 1: The SIM_RST pin of the smart card interface outputs high level.
0
SMIF
1
R/W
Smart Card Interface Mode Select This bit is always read as 1. The write value should always be 1.
Rev. 1.00 Oct. 01, 2007 Page 1260 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
30.3.10 Serial Control 2 Register (SCSC2R) SCSC2R is an 8-bit readable/writable register that enables or disables receive data full interrupt (RXI) requests.
Bit: 7
EIO
6
5
4
3
2
1
0
Initial value: R/W:
0 R/W
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 7
Bit Name EIO
Initial Value 0
R/W R/W
Description Error Interrupt Only When the EIO bit is 1, even if the RIE bit is set to 1, a receive data full interrupt (RXI) request is not sent to the CPU. When the DMAC is used with this setting, the CPU processes only ERI requests. Receive data full interrupt (RXI) requests are determined by the RIE bit setting.
6 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 30 SIM Card Module (SIM)
30.3.11 Guard Extension Register (SCGRD) SCGRD is an 8-bit readable/writable register that sets the time added for character protection.
Bit: 7 6 5 4 3 2 1 0
SCGRD[7:0]
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 to 0
Bit Name SCGRD [7:0]
Initial Value All 0
R/W R/W
Description Guard Extension Indicate the time added for character protection after transmitting a character to the smart card. The interval between the start of two successive characters is 12 etus (no addition) when the value of this register is H'00, is 13 etus when the value is H'01, and so on, up to 266 etus for H'FE. If the value of this register is H'FF, the interval between the start of two successive characters is 11 etus in T = 1 mode and is 12 etus in T = 0 mode.
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Section 30 SIM Card Module (SIM)
30.3.12 Wait Time Register (SCWAIT) SCWAIT is a 16-bit readable/writable register. If the interval between the start of two successive characters exceeds the set value (in etu units), a wait time error is generated.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCWAIT[15:0]
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R/W
Description Wait Time Register * T=0 In this mode, the operation wait time can be set in this register. If the interval between the start of characters to be received and transmitted or received characters immediately before exceeds the (60 x the value set in this register) etu, the WAIT_ER flag is set to 1. However, if SCWAIT is set to H'0000, the WAIT_ER flag is set after 60 etus. * T=1 In this mode, the character wait time can be set in this register. If the interval between the start of two successive received characters exceeds the (the value set in this register) etu, the WAIT_ER flag is set to 1. However, if SCWAIT is set to H'0000, the WAIT_ER flag is set after 1 etu.
15 to 0 SCWAIT [15:0]
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Section 30 SIM Card Module (SIM)
30.3.13 Sampling Register (SCSMPL) SCSMPL is a 16-bit readable/writable register that sets the number of serial clock cycles per etu.
Bit: 15 14 13 12 11 10 9 8 7 6 5
SCSMPL[10:0]
4
3
2
1
0
-
Initial value: R/W: 0 R
-
0 R
-
0 R
-
0 R
-
0 R 0 R/W 0 R/W 1 R/W 0 R/W
1 R/W
1 R/W
1 R/W
0 R/W
0 R/W
1 R/W
1 R/W
Bit 15 to 11
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
10 to 0
SCSMPL [10:0]
H'173
R/W
Setting for Number of Serial Clock Cycles per Etu The number of serial clock cycles per etu is (SCSMPL value + 1). The value written to SCSMPL should always be H'0007 or greater.
Rev. 1.00 Oct. 01, 2007 Page 1264 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
30.4
30.4.1
Operation
Overview
The main functions of the smart card interface are as follows. * One frame consists of 8-bit data and one parity bit. * During transmission, a character protection time, set using SCGRD and the LCB and PB bits in SCSCMR, is inserted between the end of each parity bit and the beginning of the next frame. * During reception in T = 0 mode, when a parity error is detected, low level is output for a duration of 1 etu as an error signal, 10.5 etus after the start bit. * During transmission in T = 0 mode, if an error signal is sampled, after 2 etus or more have elapsed, the same data is automatically transmitted. * Only asynchronous communication functions are supported; there is no clocked synchronous communication function.
Rev. 1.00 Oct. 01, 2007 Page 1265 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
30.4.2
Data Format
Figure 30.2 shows the data format used by the smart card interface. The smart card interface performs a parity check for each frame during reception. During reception in T = 0 mode, if a parity error is detected, an error signal is returned to the transmit side, requesting data retransmission. When the transmit side samples the error signal, it retransmits the same data. During reception in T = 1 mode, if a parity error is detected, an error signal is not returned. During transmission, error signals are not sampled and data is not retransmitted.
When no parity error occurs
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
Transmitter output
When a parity error occurs in T = 0 mode
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE
Transmitter output
Receiver output
When a parity error occurs in T = 1 mode
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
Transmitter output
Ds: Start bit, D0 to D7: Data bits, Dp: Parity bit, DE: Error signal
Figure 30.2 Data Format Used by Smart Card Interface The operation sequence is as follows. 1. When not in use, the data line is in a high-impedance state and fixed at high level by a pull-up resistance.
Rev. 1.00 Oct. 01, 2007 Page 1266 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
2. The transmit side initiates transmission of one frame of data. The data frame begins with the start bit (Ds: low level). This is followed by eight data bits (D0 to D7) and the parity bit (Dp). 3. The smart card interface then returns the data line to high impedance. The data line is held at high level by the pull-up resistance. 4. The receive side performs a parity check. If there is no parity error and reception is normal, reception of the next frame is awaited, without further action. On the other hand, when a parity error has occurred in T = 0 mode, an error signal (DE: low level) is output, requesting data retransmission. After output of an error signal with the specified duration, the receive side again sets the signal line to the high-impedance state. The signal line returns to high level by means of the pull-up resistance. If in T = 1 mode, however, no error signal is output even if a parity error occurs. 5. If the transmit side does not receive an error signal, the next frame is transmitted. On the other hand, if in T = 0 mode and an error signal is received, the data for which the error occurred is retransmitted as in step 2 above. In T = 1 mode, however, error signals are not received and retransmission is not performed. 30.4.3 Register Settings
Table 30.4 shows a map of the bits in the registers used by the smart card interface. Bits for which 0 or 1 is shown must always be set to the value shown. The method for setting the bits other than these is explained below.
Rev. 1.00 Oct. 01, 2007 Page 1267 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Table 30.4 Register Settings for Smart Card Interface
Bit Register SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR SCSC2R SCWAIT SCGRD SCSMPL Bit 7 0 0 TIE Bit 6 0 0 RIE Bit 5 PE 0 TE SCTD5 ORER SCRD5 PB 0 Bit 4 O/E 0 RE Bit 3 0 0 WAIT_IE Bit 2 0 BRR2 TEIE SCTD2 TEND SCRD2 SINV 0 Bit 1 0 BRR1 CKE1 SCTD1 WAIT_ER SCRD1 RST 0 Bit 0 0 BRR0 CKE0 SCTD0 0 SCRD0 1 0
SCTD7 SCTD6 TDRE RDRF
SCTD4 SCTD3 ERS PER
SCRD7 SCRD6 0 EIO LCB 0
SCRD4 SCRD3 0 0 SDIR 0
SCWAIT15 to SCWAIT0 SCGRD7 to SCGRD0 SCSMPL10 to SCSMPL0, bits 11 to 15 are 0
* Serial mode register (SCSMR) setting When the IC card is set for the direct convention, the O/E bit is cleared to 0; for the inverse convention, it is set to 1. * Bit rate register (SCBRR) setting Sets the bit rate. For the method of computing settings, refer to section 30.4.4, Clocks. * Serial control register (SCSCR) settings Each interrupt can be enabled and disabled using the TIE, RIE, TEIE, and WAIT_IE bits. By setting either the TE or RE bit to 1, transmission or reception is selected. The CKE[1] and CKE[0] bits are used to select the clock output state. For details, refer to section 30.4.4, Clocks. * Smart card mode register (SCSCMR) settings When the IC card is set for the direct convention, both the SDIR and SINV bits are cleared to 0; for the inverse convention, both are set to 1. The SMIF bit is always set to 1. Figure 30.3 below shows the register settings and waveform examples at the start character for two types of IC cards (a direct-convention type and an inverse-convention type). For the direct-convention type, the logical level 1 is assigned to the Z state, and the logical level 0 to the A state, and transmission and reception are performed in LSB-first. The data of the above start character is then H'3B. Even parity is used according to the smart card specification, and so the parity bit is 1.
Rev. 1.00 Oct. 01, 2007 Page 1268 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
For the inverse-convention type, the logical level 1 is assigned to the A state, and the logical level 0 to the Z state, and transmission and reception are performed in MSB-first. The data of the start character shown in figure 30.3 is then H'3F. Even parity is used according to the smart card specification, and so the parity bit is 0 corresponding to the Z state. In addition, the only D7 to D0 bits are inverted by the SINV bit. The O/E bit in SCSMR is set to odd parity mode to invert the parity bit. In transmission and reception, the setting condition is similar.
(Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z (Z) Dp state
(a) Direct converntion (SDIR = SINV = O/E = 0)
(Z)
A Ds
Z D7
Z D6
A D5
A D4
A D3
A D2
A D1
A D0
Z (Z) Dp
state
(b) Inverse convention (SDIR = SINV = O/E = 1)
Figure 30.3 Examples of Start Character Waveforms 30.4.4 Clocks
Only the internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock in the smart card interface. The bit rate is set using the bit rate register (SCBRR) and the sampling register (SCSMPL), using the formula indicated below. Examples of bit rates are listed in table 30.5 Here, when the CKE0 bit is set to 1 and the clock output is selected, a clock signal is output from the SIM_CLK pin with frequency equal to (SCSMPL + 1) times the bit rate.
B = Pck0 x 106 /{(S+1) x 2 (N+1)}
where B = Bit rate (bits/s) Pck0 = Peripheral clock0 S = SCSMPL setting (0 S 2047) N = SCBRR setting (0 N 7).
Rev. 1.00 Oct. 01, 2007 Page 1269 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Table 30.5 Example of Bit Rates (bits/s) for SCBRR Settings (Pck0 = 66.6 MHz, SCSMPL = 371)
SCBRR Setting 7 6 5 4 SCK Frequency (MHz) 4.16 4.76 5.55 6.66 Bit Rate (bits/s) 11190 12788 14919 17903
Note: The bit rate is a value that is rounded off below the decimal point.
30.4.5 (1)
Data Transmit/Receive Operation
Initialization
Prior to data transmission and reception, the following procedure should be used to initialize the smart card interface. Initialization is also necessary when switching from transmit mode to receive mode, and when switching from receive mode to transmit mode. An example of the initialization process is shown in the flowchart of figure 30.4. Step (1) to step (7) of figure 30.4 correspond to the following operation. 1. Clear the TE and RE bits in the serial control register (SCSCR) to 0. 2. Clear the error flags PER, ORER, ERS, and WAIT_ER in the serial status register (SCSSR) to 0. 3. Set the parity bit (O/E bit) in the serial mode register (SCSMR). 4. Set the LCB, PB, SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR). 5. Set the value corresponding to the bit rate to the bit rate register (SCBRR). 6. Set the clock source select bits (CKE[1] and CKE[0] bits) in the serial control register (SCSCR). At this time, the TIE, RIE, TE, RE, TEIE, and WAIT_IE bits should be cleared to 0. If the CKE[0] bit is set to 1, a clock signal is output from the SIM_CLK pin. 7. After waiting at least 1 etu, set the TIE, RIE, TE, RE, TEIE, and WAIT_IE bits in SCSCR. Except for self-check, the TE bit and RE bit should not be set simultaneously.
Rev. 1.00 Oct. 01, 2007 Page 1270 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
Initiallzation
Clear the TE and RE bits in SCSCR to 0
(1)
Clear the ERS, PER, ORER, and WAIT_ER flags in SCSSR to 0
(2)
Set the party using the O/E bit in SCSMR.
(3)
Set the LCB, PB, SMIF, SDIR, and SINV bits in SCSCMR
(4)
Set SCBRR
(5)
Set the clock using the CKE1 and CKE0 bits in SCSCR. Clear the TIE, RIE, TE, RE, TEIE, and WAIT_IE flags to 0.
(6)
Wait
Has a 1-bit interval elapsed? Yes
No
Set the TIE,RIE, TE, and RE bits in SCSCR
(7)
End
Figure 30.4 Example of Initialization Flow (2) Serial Data Transmission
Data transmission in smart card mode includes error signal sampling and retransmit processing. An example of transmit processing is shown in figure 30.5. Step (1) to step (6) of figure 30.5 correspond to the following operation.
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Section 30 SIM Card Module (SIM)
Follow the initialization procedure above to initialize the smart card interface. Confirm that the ERS bit (error flag) in SCSSR is cleared to 0. Repeat steps (2) and (3) until it can be confirmed that the TDRE flag in SCSSR is set to 1. Write transmit data to SCTDR, and perform transmission. At this time, the TDRE flag is automatically cleared to 0. When transmission of the start bit is started, the TEND flag is automatically cleared to 0, and the TDRE flag is automatically set to 1. 5. When performing continuous data transmission, return to step (2). 6. When transmission is ended, clear the TE bit to 0. Interrupt processing can be performed in the above series of processing. When the TIE bit is set to 1 to enable interrupt requests and if transmission is started and the TDRE flag is set to 1, a transmit data empty interrupt (TXI) request is issued. When the RIE bit is set to 1 to enable interrupt requests and if an error occurs during transmission and the ERS flag is set to 1, a transmit/receive error interrupt (ERI) request is issued. For details, refer to Interrupt Operations in section 30.4.5, Data Transmit/Receive Operation.
1. 2. 3. 4.
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Section 30 SIM Card Module (SIM)
Initialization
(1)
Start transmission
ERS = 0?
Yes
No
(2)
Error processing
No
TDRE = 1?
Yes
(3)
Write transmit data to SCTDR
(4)
No
All data transmitted?
Yes No
(5)
ERS = 0?
Yes
Error processing
No
TEND = 1? TDRE = 1?
Yes
Clear TE bit in SCSCR to 0
(6)
Transmit end
Figure 30.5 Example of Transmit Processing (3) Serial Data Reception
An example of data receive processing in smart card mode is shown in figure 30.6. Step (1) to step (6) of figure 30.6 correspond to the following operation. 1. Follow the initialization procedure above to initialize the smart card interface.
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Section 30 SIM Card Module (SIM)
2. Confirm that the PER, ORER, and WAIT_ER flags in SCSSR are 0. If one of these flags is set, after performing the prescribed receive error processing, clear the PER, ORER, and WAIT_ER flags to 0. 3. Repeat steps (2) and (3) in the figure until it can be confirmed that the RDRF flag is set to 1. 4. Read received data from SCRDR. 5. When receiving data continuously, return to step (2). 6. When reception is ended, clear the RE bit to 0. Interrupt processing can be performed in the above series of processing. When the RIE bit is set to 1 and the EIO bit is cleared to 0 and if the RDRF flag is set to 1, a receive data full interrupt (RXI) request is issued. If the RIE bit is set to 1, an error occurs during reception, and either the ORER, PER, or WAIT_ER flag is set to 1, a transmit/receive error interrupt (ERI) request is issued. For details, refer to, Interrupt Operations in section 30.4.5, Data Transmit/Receive Operation. If a parity error occurs during reception and the PER flag is set to 1, in T = 0 mode the received data is not transferred to SCRDR, and so this data cannot be read. In T = 1 mode, received data is transferred to SCRDR, and so this data can be read.
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Section 30 SIM Card Module (SIM)
Initialization
(1)
Start reception
Are PER, ORER, and WAIT_ER all 0s? Yes
No
(2)
Error processing No RDRF = 1? Yes (3)
Read received data from SCRDR
(4)
No All data received? Yes (5)
Clear RE bit in SCSCR to 0
(6)
Receive end
Figure 30.6 Example of Receive Processing (4) Switching Modes
When switching from receive mode to transmit mode, after confirming that reception has been completed, start initialization, and then clear the RE bit to 0 and set the TE bit to 1. Completion of reception can be confirmed through the RDRF flag. When switching from transmit mode to receive mode, after confirming that transmission has been completed, start initialization, and then clear the TE bit to 0 and set the RE bit to 1. Completion of transmission can be confirmed through the TDRE and TEND flags.
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Section 30 SIM Card Module (SIM)
(5)
Interrupt Operations
The smart card interface has four types of interrupt requests: transmit data empty interrupt (TXI) requests, transmit/receive error interrupt (ERI) requests, receive data full interrupt (RXI) requests, and transmit end interrupt (TEI) requests. * * * * When the TDRE flag in SCSSR is set to 1, a TXI request is issued. When the RDRF flag in SCSSR is set to 1, an RXI request is issued. When the ERS, ORER, PER, or WAIT_ER flag in SCSSR is set to 1, an ERI request is issued. When the TEND flag in SCSSR is set, a TEI request is issued.
Table 30.6 lists the interrupt sources for the smart card interface. Each of the interrupt requests can be enabled or disabled using the TIE, RIE, TEIE, and WAIT_IE bits in SCSCR and the EIO bit in SCSC2R. In addition, each interrupt request can be sent independently to the interrupt controller. Table 30.6 Interrupt Sources of Smart Card Interface
Operating State Transmit mode Normal operation Flags TDRE TEND Error Receive mode Normal operation Error ERS RDRF ORER, PER WAIT_ER Mask Bits TIE TEIE RIE RIE, EIO RIE WAIT_IE Interrupt Sources TXI TEI ERI RXI ERI ERI
(6)
Data Transfer Using DMAC
The smart card interface enables reception and transmission using the DMAC. In transmission, when the TDRE flag in SCSSR is set to 1, a DMA transfer request for transmit data empty is issued. If a DMA transfer request for transmit data empty is set in advance as a DMAC activation source, the DMAC can be activated and made to transfer data when a DMA transfer request for transmit data empty occurs. When in T = 0 mode and if an error signal is received during transmission, the same data is automatically retransmitted. At the time of this retransmission, no DMA transfer request is issued, and so the number of bytes specified to the DMAC can be transmitted. When using the DMAC for transmit data processing and performing error processing as a result of an interrupt request sent to the CPU, the TIE bit should be cleared to 0 so that no TXI requests are
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Section 30 SIM Card Module (SIM)
generated, and the RIE bit should be set to 1 so that an ERI request is issued. The ERS flag set when an error signal is received is not cleared automatically, and so should be cleared by sending an interrupt request to the CPU. In receive operation, when the RDRF flag in SCSSR is set to 1, a DMA transfer request for receive data full is issued. By setting a DMA transfer request for receive data full in advance as a DMAC activation source, the DMAC can be activated and made to transfer data when a DMA transfer request for receive data full occurs. When in T = 0 mode and if a parity error occurs during reception, a data retransmit request is issued. At this time the RDRF flag is not set, and a DMA transfer request is not issued, so the number of bytes specified to the DMAC can be received. When using the DMAC for receive data processing and performing error processing as a result of an interrupt request sent to the CPU, the RIE bit should be set to 1 and the EIO bit to 1, so that no RXI requests are generated and only ERI requests are generated. The PER, ORER, and WAIT_ER flags that are set by a receive error are not automatically cleared, and so should be cleared by sending an interrupt request to the CPU. When using the DMAC for transmission and reception, the DMAC should always be set first and put into the enabled state, before setting the smart card interface.
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Section 30 SIM Card Module (SIM)
30.5
Usage Notes
The following matters should be noted when using the smart card interface. (1) Receive Data Timing and Receive Margin
When SCSMPL holds its initial value, the smart card interface operates at a basic clock frequency 372 times the transfer rate. During reception, the smart card interface samples the falling edge of the start bit using the serial clock for internal synchronization. Receive data is captured internally at the rising edge of the 186th serial clock pulse. This is shown in figure 30.7.
372 clock pulses 186 clock pulses 0 Basic clock 185 371 0 185 371 0
Received data (RXD)
Start bit D0 D1
Synchronization sampling timing
Data sampling timing
Figure 30.7 Receive Data Sampling Timing in Smart Card Mode Hence the receive margin can be expressed as follows. Formula for receive margin in smart card mode:
M
0.5 1 2N L 0.5 F
D N 0.5
L
F
100
where M: Receive margin (%) N: Ratio of the bit rate to the clock (N = 372) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10)
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Section 30 SIM Card Module (SIM)
F: Absolute value of the deviation of the clock frequency In the above formula, if F = 0 and D = 0.5, then the receive margin is as follows. When D = 0.5, F = 0,
M = (0.5 - 1/2 x 372) x 100% = 49.866%
(2)
Retransmit Operation
Retransmit operations when the smart card interface is in receive mode and in transmit mode are described below. (a) Retransmission when the smart card interface is in receive mode (T = 0) Figure 30.8 shows retransmit operations when the smart card interface is in receive mode. Step (1) to step (5) of figure 30.8 correspond to the following operation. If an error is detected as a result of checking the received parity bit, the PER bit in SCSSR is automatically set to 1. At this time, if the RIE bit in SCSCR is set to enable, an ERI request is issued. The PER bit in SCSSR should be cleared to 0 before the sampling timing for the next parity bit. The RDRF bit in SCSSR is not set for frames in which a parity error occurs. If no error is detected as a result of checking the received parity bit, the PER bit in SCSSR is not set. If no error is detected as a result of checking the received parity bit, it is assumed that reception was completed normally, and the RDRF bit in SCSSR is automatically set to 1. If the RIE bit in SCSCR is 1 and the EIO bit is 0, an RXI request is generated. If a normal frame is received, the pin retains its high-impedance state at the timing for transmission of error signals.
nth transmit frame Retansmit frame (n+1) th transmit frame
1.
2. 3. 4.
5.
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
DE
(DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 DP Ds D0 D1 D2 D3 D4 (5)
RDRF
(2) (4)
PER
(1) (3)
Figure 30.8 Retransmission when Smart Card Interface is in Receive Mode
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Section 30 SIM Card Module (SIM)
(b)
Retransmission when the smart card interface is in transmit mode (T = 0) Figure 30.9 shows retransmit operations when the smart card interface is in transmit mode. Step (1) to step (4) of figure 30.9 correspond to the following operation After completion of transmission of one frame, if an error signal is returned from the receive side, the ERS bit in SCSSR is set to 1. If the RIE bit in SCSCR is set to enable, an ERI request is issued. The ERS bit in SCSSR should be cleared to 0 before the sampling timing for the next parity bit. In T = 0 mode, the TEND bit in SCSSR is not set for a frame when an error signal indicating an error is received. If no error signal is returned from the receive side, the ERS bit in SCSSR is not set. If no error signal is returned from the receive side, it is assumed that transmission of one frame, including retransmission, is completed, and the TEND bit in SCSSR is set to 1. At this time, if the TIE bit in SCSCR is set to enable, a TEI interrupt request is issued.
nth transmit frame Retransmit frame (n+1) th transmit frame
(DE) Ds D0 D1 D2 D3 D4
1.
2. 3. 4.
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP DE
TDRE
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
Transmission from SCTDR to SCTSR TEND
(2)
Transmisson from SCTDR to SCTSR (4) (3)
ERS
(1)
Figure 30.9 Retransmit Standby Mode (Clock Stopped) when Smart Card Interface is in Transmit Mode
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Section 30 SIM Card Module (SIM)
(3)
Standby Mode Switching
When switching between smart card interface mode and standby mode, in order to retain the clock duty, the following switching procedure should be used. Step (1) to step (7) of figure 30.10 correspond to the following operation. * When switching from smart card interface mode to standby mode 1. Write 0 to the TE and RE bits in the serial control register (SCSCR), to stop transmit and receive operations. At the same time, set the CKE1 bit to the value for the output-fixed state in standby mode. 2. Write 0 to the CKE0 bit in SCSCR to stop the clock. 3. Wait for one cycle of the serial clock. During this interval, the duty is retained, and the clock output is fixed at the specified level. 4. Make the transition to standby mode. * To return from standby mode to smart card interface mode 5. Cancel the standby state. 6. Set the CKE1 bit in the serial control register (SCSCR) to the value of the output-fixed state at the beginning of standby (the current SIM_CLK pin state). 7. Write 1 to the CKE0 bit in SCSCR to output a clock signal. Clock signal generation begins at normal duty.
Normal operation Standby mode Normal operation
SIM_CLK
(1) (2) (3)
(4)
(5) (6) (7)
Figure 30.10 Procedure for Stopping Clock and Restarting (4) Power-On and Clock Output
In order to retain the clock duty from power-on, the following switching procedure should be used. 1. The initial state is set to port-input with high impedance. In order to fix the potential, a pull-up resistance/pull-down resistance is used. 2. Use the CKE1 bit in the serial control register (SCSCR) to fix the specified output. 3. Set the CKE0 bit in SCSCR to 1 to start clock output.
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Section 30 SIM Card Module (SIM)
(5)
Pin Connections
An example of pin connections for the smart card interface is shown in figure 30.11. In communication with the smart card, transmission and reception are performed using a single data transmit line. The data transmit line should be pulled up by a resistance on the power supply Vcc side. When using the clock generated by the smart card interface with the IC card, the SIM_CLK pin output is input to the CLK pin of the IC card. If an internal clock of the IC card is used, this connection is not needed.
20 kW
SIM_D
Data line
I/O
Smrat card interface
SIM_CLK
Clock line
CLK
SIM_RST
Reset line
RST
This LSI
Note: For details, refer to ISO/IEC7816-3.
Smart card
Figure 30.11 Example of Pin Connections in Smart Card Interface Note: The transmission/reception in loop can perform self-check when the RE and TE bits are set to 1 without connecting to the IC card. (6) Transmit End Interrupt
In continuous transmission, when the TEIE bit is always set to 1, the TEND bit is set to 1 at a transmit end. Therefore, the unnecessary transmit end interrupt (TEI) request occurs. When SCTSR starts transmitting after the last transmit data is written to SCTDR, the TEIE bit in SCSCR should be set to 1 so that the occurrence of the unnecessary TEI interrupt request can be prevented.
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Section 30 SIM Card Module (SIM)
The waveform of the timing to set the TEIE bit to 1 is shown in figure 30.12.
Transmit frame Transmit frame Last frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
(DE)
TDRE
TEND
Unnecessary TEND set timing
TEIE
TEIE set timing TEIE
Figure 30.12 TEIE Set Timing
Rev. 1.00 Oct. 01, 2007 Page 1283 of 1956 REJ09B0256-0100
Section 30 SIM Card Module (SIM)
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Section 31 Multimedia Card Interface (MMCIF)
Section 31 Multimedia Card Interface (MMCIF)
This LSI supports a multimedia card interface (MMCIF). The MMC mode interface can be utilized. The MMCIF is a clock-synchronous serial interface that transmits/receives data which is distinguished in terms of command and response. A number of commands and responses are predefined in the multimedia card. As the MMCIF specifies a command code and command type/response type upon the issuance of a command, commands extended by the secure multimedia card (Secure-MMC) and additional commands can be supported in the future within the range of combinations of currently defined command types/response types.
31.1
Features
* Interface that complies with the MultiMediaCard System Specification Version 3.1 * MMC mode supported. Interface via the CLK output (transfer clock output) pin, the CMD input/output (command output/response input) pin, and the DAT input/output (data input/output) pin * 16.7-Mbps bit rate (max.) for the card interface (at peripheral clock 1 of 33.3 MHz) * Incorporates 64 data-transfer FIFOs of 16 bits * DMA transfer requests issuance supported. Note that DMA transfer is disabled when the card conforming to the Multimedia Card System Specification (version 2.2 or lower) is connected. * Four interrupt sources FIFO empty/full, command/response/data transfer complete, transfer error, and FIFO ready * Card identification function * Stream transfer unsupported
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Section 31 Multimedia Card Interface (MMCIF)
Figure 31.1 shows a block diagram of the MMCIF.
MMCIF
FIFO
Data transmission/ reception control
Internal bus interface
Peripheral bus
Command transmission control
Port interface
MMC_CLK MMC_CMD
Response reception control
MMC_DAT MMC_ODMOD MMC_VDDON
Interrupt control
FSTAT TRAN ERR FRDY
Card clock generator
MMC_CD
Figure 31.1 MMCIF Block Diagram
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Section 31 Multimedia Card Interface (MMCIF)
31.2
Input/Output Pins
Table 31.1 summarizes the pins of the MMCIF. Table 31.1 Pin Configuration
Pin Name MMC_CLK MMC_CMD MMC_DAT MMC_ODMOD MMC_VDDON MMC_CD Abbrev. (MMC) CLK CMD DAT MMC_ODMOD MMC_VDDON MMC_CD I/O Output Input/Output Input/Output Output Output Input Function Clock output pin Command output/response input pin Data input/output pin Open drain mode control Card power supply control Card identification signal
Note: For easier understanding of transmission and reception, the data transmission side and reception side are specified as MCTXD and MCRXD.
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Section 31 Multimedia Card Interface (MMCIF)
31.3
Register Descriptions
Figure 31.2 shows the MMCIF register configuration. Figure 31.3 shows the register states in each processing mode. Table 31.2 Register Configuration
Register Name Command type register Response type register Abbrev. CMDTYR RSPTYR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Area P4 Address H'FFF9 0018 H'FFF9 0019 H'FFF9 0014 H'FFF9 001A H'FFF9 0000 H'FFF9 0001 H'FFF9 0002 H'FFF9 0003 H'FFF9 0004 H'FFF9 0005 H'FFF9 0020 H'FFF9 0021 H'FFF9 0022 H'FFF9 0023 H'FFF9 0024 H'FFF9 0025 H'FFF9 0026 H'FFF9 0027 H'FFF9 0028 H'FFF9 0029 H'FFF9 002A H'FFF9 002B Area 7 Address H'1FF9 0018 H'1FF9 0019 H'1FF9 0014 H'1FF9 001A H'1FF9 0000 H'1FF9 0001 H'1FF9 0002 H'1FF9 0003 H'1FF9 0004 H'1FF9 0005 H'1FF9 0020 H'1FF9 0021 H'1FF9 0022 H'1FF9 0023 H'1FF9 0024 H'1FF9 0025 H'1FF9 0026 H'1FF9 0027 H'1FF9 0028 H'1FF9 0029 H'1FF9 002A H'1FF9 002B Access Size 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Transfer byte number count register TBCR Transfer block number counter Command register 0 Command register 1 Command register 2 Command register 3 Command register 4 Command register 5 Response register 0 Response register 1 Response register 2 Response register 3 Response register 4 Response register 5 Response register 6 Response register 7 Response register 8 Response register 9 Response register 10 Response register 11 Response register 12 Response register 13 TBNCR CMDR0 CMDR1 CMDR2 CMDR3 CMDR4 CMDR5 RSPR0 RSPR1 RS PR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7 RSPR8 RSPR9 RSPR10 RSPR11 RSPR12 RSPR13
H'FFF9 002C H'1FF9 002C H'FFF9 002D H'1FF9 002D
Rev. 1.00 Oct. 01, 2007 Page 1288 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
Register Name Response register 14 Response register 15 Response register 16 Response register D Command start register Operation control register Command timeout control register Data timeout register Card status register Interrupt control register 0 Interrupt control register 1 Interrupt status register 0 Interrupt status register 1 Transfer clock control register VDD/open drain control register Data register FIFO pointer clear register DMA control register Interrupt control register 2 Interrupt status register 2 Card switch register Switch status register Chattering elimination pulse setting register
Abbrev. RSPR14 RSPR15 RSPR16 RSPRD
R/W R/W R/W R/W R/W
Area P4 Address H'FFF9 002E H'FFF9 002F H'FFF9 0030 H'FFF9 0031 H'FFF9 0006 H'FFF9 000A H'FFF9 0011 H'FFF9 0032 H'FFF9 000B
Area 7 Address H'1FF9 002E H'1FF9 002F H'1FF9 0030 H'1FF9 0031 H'1FF9 0006 H'1FF9 000A H'1FF9 0011 H'1FF9 0032 H'1FF9 000B
Access Size 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8
CMDSTRT R/W OPCR CTOCR DTOUTR CSTR INTCR0 INTCR1 INTSTR0 INTSTR1 CLKON VDCNT DR FIFOCLR DMACR INTCR2 INTSTR2 CSWR SWSR CHATR R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R R/W R/W
H'FFF9 000C H'1FF9 000C H'FFF9 000D H'1FF9 000D H'FFF9 000E H'FFF9 000F H'FFF9 0010 H'FFF9 0012 H'FFF9 0040 H'FFF9 0042 H'FFF9 0044 H'FFF9 0046 H'FFF9 0048 H'FFF9 004A H'1FF9 000E H'1FF9 000F H'1FF9 0010 H'1FF9 0012 H'1FF9 0040 H'1FF9 0042 H'1FF9 0044 H'1FF9 0046 H'1FF9 0048 H'1FF9 004A
H'FFF9 004C H'1FF9 004C H'FFF9 004E H'1FF9 004E
Rev. 1.00 Oct. 01, 2007 Page 1289 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
Table 31.3 Register States in Each Processing Mode
Register Name Command type register Response type register Transfer byte number count register Transfer block number counter Command register 0 Command register 1 Command register 2 Command register 3 Command register 4 Command register 5 Response register 0 Response register 1 Response register 2 Response register 3 Response register 4 Response register 5 Response register 6 Response register 7 Response register 8 Response register 9 Response register 10 Response register 11 Response register 12 Response register 13 Response register 14 Response register 15 Response register 16 Response register D Abbrev. CMDTYR RSPTYR TBCR TBNCR CMDR0 CMDR1 CMDR2 CMDR3 CMDR4 CMDR5 RSPR0 RSPR1 RSPR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7 RSPR8 RSPR9 RSPR10 RSPR11 RSPR12 RSPR13 RSPR14 RSPR15 RSPR16 RSPRD Power-on Manual Reset Reset H'00 H'00 H'00 H'0000 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'0000 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 1290 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
Register Name Command start register Operation control register Command timeout control register Data timeout register Card status register Interrupt control register 0 Interrupt control register 1 Interrupt status register 0 Interrupt status register 1 Transfer clock control register VDD/open drain control register Data register FIFO pointer clear register DMA control register Interrupt control register 2 Interrupt status register 2 Card switch register Switch status register
Abbrev. CMDSTRT OPCR CTOCR DTOUTR CSTR INTCR0 INTCR1 INTSTR0 INTSTR1 CLKON VDCNT DR FIFOCLR DMACR INTCR2 INTSTR2 CSWR SWSR
Power-on Manual Reset Reset H'00 H'00 H'00 H'FFFF H'0x H'00 H'00 H'00 H'00 H'00 H'00 H'xxxx H'00 H'00 H'00 H'0x H'02 H'00 H'13 H'00 H'00 H'00 H'FFFF H'0x H'00 H'00 H'00 H'00 H'00 H'00 H'xxxx H'00 H'00 H'00 H'0x H'02 H'00 H'13
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Chattering elimination pulse setting CHATR register
Rev. 1.00 Oct. 01, 2007 Page 1291 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
31.3.1
Command Type Register (CMDTYR)
CMDTYR specifies the command format in conjunction with RSPTYR. The bits TY1 and TY0 specify the existence and direction of transfer data, and the bits TY6 to TY4, and TY2 specify the additional settings. The bits TY6 to TY4, and TY2 should all be cleared to 0 or only one of them should be set to 1. The bits TY6 to TY4, and TY2 can only be set to 1 if the corresponding settings in the bits TY1 and TY0 allow that setting. If these bits are not set correctly, operation cannot be guaranteed. When transferring a single block, set TY1 and TY0 to 01 or 10, and all of TY6 to TY4, and TY2 to 0.
Bit: 7 -- Initial value: R/W: 0 R 6
TY6
5
TY5
4
TY4
3 -- 0 R
2
TY2
1
TY[1:0]
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
6
TY6
0
R/W
Specifies predefined multiblock transfer. Bits TY1 and TY0 should be set to 01 or 10. When using a command to set this bit, it is necessary to specify the transfer block size and the transfer block number in TBCR and TBNCR, respectively.
5
TY5
0
R/W
Specifies multiblock transfer when using secure MMC. Bits TY1 and TY0 should be set to 01 or 10. When using a command to set this bit, it is necessary to specify the transfer block size and the transfer block number in TBCR and TBNCR, respectively.
4
TY4
0
R/W
Set this bit to 1 when issuing the CMD12 command. Bits TY1 and TY0 should be set to 00. To issue Stop Tran (SPI multiblock write end data token), set this bit to 1 and the bits TY1 and TY0 to 11.
3
0
R
Reserved This bit is always read as 0.The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1292 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
Bit 2
Bit Name TY2
Initial Value 0
R/W R/W
Description Specifies open-ended multiblock transfer. Bits TY1 and TY0 should be set to 01 or 10. The command sequence of the multiblock transfer specified by this bit ends when it is aborted by the CMD12 command.
1, 0
TY[1:0]
0
R/W
These bits specify the existence and direction of transfer data. 00: A command without data transfer 01: A command with read data reception 10: A command with write data transmission 11: Set this bit when transmitting Stop Tran
Table 31.4 summarizes the correspondence between the commands described in the MultiMediaCard System Specification Version 3.1 and the settings of the CMDTYR and RSPTYR registers. 31.3.2 Response Type Register (RSPTYR)
RSPTYR specifies the command format in conjunction with CMDTYR. The bits RTY[2:0] specify the number of response bytes, and the bits RTY5 and RTY4 specify the additional settings.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5
RTY5
4
RTY4
3 -- 0 R
2
1
RTY[2:0]
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7, 6
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
5
RTY5
0
R/W
Set this bit when using a command with an R1b response
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Section 31 Multimedia Card Interface (MMCIF)
Bit 4
Bit Name RTY4
Initial Value 0
R/W R/W
Description Specifies that the command response CRC (other than an R2 response) be checked through CRC7. Bits RTY2 to RTY0 should be set to 100. Reserved This bit is always read as 0. The write value should always be 0.
3
0
R
2 to 0
RTY[2:0]
000
R/W
These bits specify the number of command response bytes. 000: A command requiring no command responses. 001: Setting prohibited. 010: Setting prohibited. 011: Setting prohibited. 100: A command requiring 6-byte command response. Specified by R1, R1b, R3, R4, and R5 responses in MMC mode. 101: A command requiring a 17-byte command response. Specified by the R2 response in MMC mode. 110: Setting prohibited 111: Setting prohibited
Note: The purpose of a CRC check through RTY4 is to check the CRC that is attached to a command response, not to check the bit in the event of a CRC error regarding a command response. A CRC check for an R2 command response in MMC mode cannot be performed.
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Section 31 Multimedia Card Interface (MMCIF)
Table 31.3 summarizes the correspondence between the commands described in the MultiMediaCard System Specification Version 3.1 and the settings of the CMDTYR and RSPTYR registers. Table 31.4 Correspondence between Commands and CMDTYR and RSPTYR Settings * MMC Mode
CMD INDEX CMD0 CMD1 CMD2 CMD3 CMD4 CMD7 CMD9 CMD10 CMD11 CMD12 CMD13 CMD15 CMD16 CMD17 CMD18 CMD20 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 Abbreviation GO_IDLE_STATE SEND_OP_COND ALL_SEND_CID SET_RELATIVE_ADDR SET_DSR SELECT/DESELECT_CARD SEND_CSD SEND_CID READ_DAT_UNTIL_STOP STOP_TRANSMISSION SEND_STATUS GO_INACTIVE_STATE SET_BLOCKLEN READ_SINGLE_BLOCK READ_MULTIPLE_BLOCK WRITE_DAT_UNTIL_STOP SET_BLOCK_COUNT WRITE_BLOCK WRITE_MULTIPLE_BLOCK PROGRAM_CID PROGRAM_CSD SET_WRITE_PROT CLR_WRITE_PROT SEND_WRITE_PROT resp R3 R2 R1 R1b R2 R2 R1 R1b R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R1b R1b R1 1 6 5 CMDTYR 4 3 2 1, 0 00 00 00 00 00 00 00 00 01 00 00 00 00 *
4
RSPTYR 6 5 4 2 to 0 000 100 101 *
4
100 000
1
*
4
100 101 101
* 1 * *
4
100 100 100 000 100 100 100 100 100 100 100 100 100 100 100 100
4
4
*3 *
2
01
* *
4
*
2
01 10 00
4
* *
4
4
* *
2
3
10
* *
4
*
2
10 10 10 00 00 01 1 1
4
* * * * *
4
4
4
4
4
Rev. 1.00 Oct. 01, 2007 Page 1295 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
CMD INDEX CMD32* CMD33* CMD34* CMD35 CMD36 CMD37* CMD38 CMD39 CMD40 CMD42 CMD55 CMD56
1 1
CMDTYR Abbreviation TAG_SECTOR_START TAG_SECTOR_END UNTAG_SECTOR TAG_ERASE_GROUP_START TAG_ERASE_GROUP_END UNTAG_ERASE_GROUP ERASE FAST_IO GO_IRQ_STATE LOCK_UNLOCK APP_CMD GEN_CMD resp R1 R1 R1 R1 R1 R1 R1b R4 R5 R1b R1 R1b 6 5 4 3 2 1, 0 00 00 00 00 00 00 00 00 00 10 00 *
5
RSPTYR 6 5 4 * * *
4
2 to 0 100 100 100 100 100 100 100 100 100 100 100 100
1
4
1
4
* * * 1
4
4
4
* * *
4
4
4
1
* *
4
4
1
*
4
Notes: 1. These commands are not supported after MMCA Ver3.1 specification cards. 2. Set the TY6 bit when the transfer block number is set in advance, set the TY2 bit when the transfer block number is not set. 3. Set this bit when using secure MMC multiple block transaction. 4. Set these bits to 1 when the CRC of a command and response other than R2 is checked. (Checking the CRC of an R2 command and response is not possible). 5. Set these bits to 01 in read and 10 in write access. Blank spaces denote a value of 0.
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Section 31 Multimedia Card Interface (MMCIF)
31.3.3
Transfer Byte Number Count Register (TBCR)
TBCR specifies the number of bytes to be transferred (the block size) for each single block transfer command. TBCR specifies the net number of data block bytes not including the start bit, end bit, and CRC. The multiblock transfer command corresponds to the number of bytes of each data block.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 0 R/W 3 2
C[3:0]
1
0
0 R/W
0 R/W
0 R/W
Bit 7 to 4
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
3 to 0
CS[3:0]
0000
R/W
Transfer Data Block Size 0000: 1 byte 0001: 2 bytes 0010: 4 bytes 0011: 8 bytes 0100: 16 bytes 0101: 32 bytes 0110: 64 bytes 0111: 128 bytes 1000: 256 bytes 1001: 512 bytes 1010: 1024 bytes 1011: 2048 bytes 1100 to 1111: Setting prohibited
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Section 31 Multimedia Card Interface (MMCIF)
31.3.4
Transfer Block Number Counter (TBNCR)
A value other than 0 must be written to the TBNCR register if multiple block transfer is selected by the bits TY5 and TY6 in CMDTYR. Set the transfer block number in TBNCR. Every time a block transfer ends, the value of TBNCR is decremented by one, and the command sequence finishes when the TBNCR value reaches 0.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBNCR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 15 to 0
Bit Name TBNCR
Initial Value All 0
R/W R/W
Description Transfer Block Number Counter [Clearing condition] When a specified block number is transferred or 0 is written to TBNCR.
31.3.5
Command Registers 0 to 5 (CMDR0 to CMDR5)
The CMDR registers are six 8-bit registers. A command is written to CMDR as shown in table 31.5, and the command is transmitted when the START bit in CMDSTRT is set to 1. Table 31.5 CMDR Configuration
Register CMDR0 CMDR[1:4] CMDR5 Contents Start bit, Host bit, and command index Command argument CRC and End bits Operation Write command index Set the Start bit to 0 and the Host bit to 1 Write command arguments. Setting of CRC is unnecessary (automatic calculation). Setting of the End bit is unnecessary.
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Section 31 Multimedia Card Interface (MMCIF)
* CMDR0
Bit: 7
Start
6
Host
5
4
3
INDEX
2
1
0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 to 0
Bit Name Start Host INDEX
Initial Value 0 0 All 0
R/W R/W R/W R/W
Description Start bit (set to 0) Transmission bit (set to 1) Command index
* CMDR1 to CMDR4
Bit: 7 6 5 4 3 2 1 0
CMDR[1:4]n
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 to 0
Bit Name
Initial Value
R/W R/W
Description Command arguments
CMDR[1:4]n All 0
Note: n = 0 to 7
* CMDR5
Bit: 7 6 5 4
CRC
3
2
1
0
End
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 7 to 1 0
Bit Name CRC End
Initial Value All 0 0
R/W R R
Description Setting unnecessary. These bits are always read as 0. Setting unnecessary. This bit is always read as 0.
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Section 31 Multimedia Card Interface (MMCIF)
31.3.6
Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD)
RSPR0 to RSPR16 are 8-bit command response registers. RSPRD is a 5-bit data response register. The number of command response bytes differs according to the command. The number of command response bytes can be specified through RSPTYR in the MMCIF. The command response is shifted-in from the bit 0 in RSPR16, and shifted to the number of command response bytes x 8 bits. Table 31.6 summarizes the correspondence between the number of command response bytes and valid RSPR registers. Table 31.6 Correspondence between Command Response Byte Number and RSPR
MMC Mode Response RSPR registers RSPR0 RSPR1 RSPR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7 RSPR8 RSPR9 RSPR10 RSPR11 RSPR12 RSPR13 RSPR14 RSPR15 RSPR16 6 bytes (R1, R1b, R3, R4, R5) 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 17 bytes (R2) 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte 11th byte 12th byte 13th byte 14th byte 15th byte 16th byte 17th byte
RSPR0 to RSPR16 are simple shift registers with the initial value H'00. A command response that has been shifted in is not automatically cleared, and it is continuously shifted until it is shifted out from bit 7 in RSPR0. To clear unnecessary bytes to H'00, write an arbitrary value to each RSPR.
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Section 31 Multimedia Card Interface (MMCIF)
* RSPR0 to RSPR16
Bit: 7 6 5 4 3 RSPR Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0
Bit 7 to 0
Bit Name RSPR
Initial Value All 0
R/W R/W
Description These bits are cleared to H'00 by writing an arbitrary value. RSPR0 to RSPR16 make up a continuous 17-byte shift registers in which a command response is stored.
* RSPRD
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 0 R/W 0 R/W 4 3 2
RSPR
1
0
0 R/W
0 R/W
0 R/W
Bit 7 to 5
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
4 to 0
RSPR
All 0
R/W
All of these bits are cleared to 00 by writing an arbitrary value. Data response is stored.
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Section 31 Multimedia Card Interface (MMCIF)
31.3.7
Command Start Register (CMDSTRT)
CMDSTRT is an 8-bit readable/writable register that triggers the start of command transmission or Stop Tran transmission, representing the start of a command sequence. The following operations should be completed before the command sequence starts. Command transmission: * Analysis of prior command response, clearing the command response register write if necessary * Analysis/transfer of receive data of prior command if necessary * Preparation of transmit data of the next command if necessary * Setting of CMDTYR, RSPTYR, TBCR, and TBNCR The CMDR0 to CMDR4, CMDTYR, RSPTYR, TBCR, and TBNCR registers should not be changed until command transmission has ended (during the time the CWRE flag in CSTR is set to 1). * Setting of CMDR0 to CMDR4 Stop Tran transmission: * Setting of CMDTYR and RSPTYR The CMDTYR and RSPTYR registers should not be changed until command transmission has ended (during the time the CWRE flag in CSTR is set to 1).
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Section 31 Multimedia Card Interface (MMCIF)
Command sequences are controlled by the sequencers on both the MMCIF side and the MMC card side. Normally, these operate synchronously. However, if an error occurs or a command is aborted, these may become temporarily unsynchronized. Be careful when setting the CMDOFF bit in OPCR, issuing the CMD12 command, or processing an error in MMC mode. A new command sequence should be started only after the end of the command sequence on both the MMCIF and card sides is confirmed.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 START 0 R/W
Bit 7 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
START
0
R/W
Starts command or Stop Tran transmission when 1 is written. This bit is cleared by hardware.
Rev. 1.00 Oct. 01, 2007 Page 1303 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
31.3.8
Operation Control Register (OPCR)
OPCR aborts command operation, and suspends or continues data transfer.
Bit: 7
CMD OFF
6 -- 0 R
5
4
3 -- 0 R
2 -- 0 R
1 -- 0 R
0 -- 0 R
RD_ CONTI DATEN
Initial value: R/W:
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name CMDOFF
Initial Value 0
R/W R/W
Description Command Off Aborts all command operations (MMCIF command sequence) when 1 is written to it after a command is transmitted. This bit is then cleared by hardware. Write enabled period: From command transmission completion to command sequence end Write 0: Operation is not affected. Write 1: Command sequence is forcibly aborted.
6
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
5
RD_CONTI
0
R/W
Read Continue This bit is cleared by hardware when 1 is written and the MMCIF resumes data read. Read data reception is resumed while the sequence has been halted by FIFO full or termination of block reading in multiblock read. Write enabled period: While read data reception is halted Write 0: Operation is not affected. Write 1: Resumes read data reception.
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Section 31 Multimedia Card Interface (MMCIF)
Bit 4
Bit Name DATAEN
Initial Value 0
R/W R/W
Description Data Enable Starts write data transmission by a command with write data. Resumes write data transmission while the sequence has been halted by FIFO empty or termination of block writing in multiblock write. Write enabled period: (1) after receiving a response to a command with write data, (2) while sequence is halted by FIFO empty, (3) when one block writing in multiblock write is terminated Write 0: Operation is not affected. Write 1: Starts or resumes write data transmission.
3 to 0
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
In write data transmission, the contents of the command response and data response should be analyzed, and then transmission should be triggered. In addition, the data transmission should be temporarily halted by FIFO full/empty, and it should resume when the preparation has been completed. In multiblock transfer, the transfer should be temporarily halted at every block break to select whether to continue to the next block or to abort the multiblock transfer command by issuing the CMD12 command or Stop Tran. To continue to the next block, the RD_CONTI and DATAEN bits should be set to 1. To issue the CMD12 command or Stop Tran, the CMDOFF bit should be set to 1 to abort the command sequence on the MMCIF side. When using the auto-mode for predefined multiblock transfer, the setting of the RD_CONTI bit or the DATAEN bit between blocks can be omitted.
Rev. 1.00 Oct. 01, 2007 Page 1305 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
31.3.9
Command Timeout Control Register (CTOCR)
CTOCR specifies the period for generating a timeout for the command response. When the command response is received, CTOCR continues counting the transfer clock and enters the command timeout error state when the number of transfer clock cycles reaches the number specified in CTOCR. When the CTERIE bit in INTCR1 is set to 1, the CTERI flag in INTSTR1 is set. To perform command timeout error handling, the command sequence should be aborted by setting the CMDOFF bit to 1 and then clearing the CTERI flag.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0
CTSEL0
1 R/W
Bit 7 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
CTSEL0
1
R/W
0: 128 transfer clock cycles from command transmission completion to response reception completion 1: 256 transfer clock cycles from command transmission completion to response reception completion
Note: If an R2 response (17-byte command response) in MMC mode is requested and CTSEL0 is cleared to 0, a timeout is generated during response reception. Therefore, set CTSEL0 to 1.
Rev. 1.00 Oct. 01, 2007 Page 1306 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
31.3.10 Data Timeout Register (DTOUTR) DTOUTR specifies the period for generating a data timeout. The 16-bit counter (DTOUTC) and a prescaler count peripheral clock 1 to monitor the data timeout. The prescaler always counts peripheral clock 1, and outputs a count pulse at every 10,000 peripheral clock 1 cycles. The initial value of DTOUTC is 0, and DTOUTC starts counting the prescaler output at the start of the command sequence. DTOUTC is cleared when the command sequence has ended, or when the command sequence has been aborted by setting the CMDOFF bit to 1, after which the DTOUTC stops counting the prescaler output. When the command sequence does not end, DTOUTC continues counting the prescaler output, and enters the data timeout error states when the number of prescaler outputs reaches the number specified in DTOUTR. When the DTERIE bit in INTCR1 is set to 1, the DTERI flag in INTSTR1 is set. To perform data timeout error handling, abort the command sequence by setting the CMDOFF bit to 1, and then clear the DTERI flag. For a command with data busy status, data timeout cannot be monitored since the command sequence is terminated before entering the data busy state. Timeout in the data busy state should be monitored by firmware. Setting DTOUTR to 0 will cause a timeout immediately after the start of the command sequence.
Bit: 15 14 1 R/W 13 1 R/W 12 1 R/W 11 1 R/W 10 1 R/W 9 1 R/W 8 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W
DTOUTR Initial value: 1 R/W: R/W
Bit 15 to 0
Bit Name DTOUTR
Initial Value All 1
R/W R/W
Description Data Timeout Time/10,000 Data timeout time: Peripheral clock 1 cycle x DTOUTR setting value x 10,000.
Rev. 1.00 Oct. 01, 2007 Page 1307 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
31.3.11 Card Status Register (CSTR) CSTR indicates the MMCIF status during command sequence execution.
Bit: 7
BUSY
6
FIFO_ FULL
5
FIFO_ EMPTY
4
3
2
DTBUSY_ TU
1 -- 0 R
0
REQ
CWRE DTBUSY
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
-- R
0 R
Bit 7
Bit Name BUSY
Initial Value 0
R/W R
Description Command Busy Indicates command execution status. When the CMDOFF bit in OPCR is set to 1, this bit is cleared to 0 because the MMCIF command sequence is aborted. 0: Idle state waiting for a command, or data busy state. 1: Command sequence execution in progress.
6
FIFO_FULL 0
R
FIFO Full This bit is set to 1 when the FIFO becomes full while data is being received, and cleared to 0 when RD_CONTI is set to 1 or the command sequence is completed. 0: The FIFO is empty. 1: The FIFO is full.
5
FIFO_EMPTY 0
R
FIFO Empty This bit is set to 1 when the FIFO becomes empty while data is being sent, and cleared to 0 when DATAEN is set to 1 or the command sequence is completed. Indicates whether the FIFO holds data or not. 0: The FIFO includes data. 1: The FIFO is empty.
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Section 31 Multimedia Card Interface (MMCIF)
Bit 4
Bit Name CWRE
Initial Value 0
R/W R
Description Command Register Write Enable Indicates whether the CMDR command is being transmitted or has been transmitted. 0: The CMDR command has been transmitted, or the START bit in CMDSTRT has not been set yet, so the new command can be written. 1: The CMDR command is waiting to be transmitted or is being transmitted. If a new command is written, a malfunction will result.
3
DTBUSY
0
R
Data Busy Indicates command execution status. Indicates that the card is in the busy state after the command sequence of a command without data transfer which includes the busy state in the response has ended or a command with write data has ended. 0: Idle state waiting for a command, or command sequence execution in progress 1: Card is in the data busy state after command sequence termination.
2
DTBUSY_TU Undefined
R
Data Busy Pin Status Monitors the levels of the DAT pin in MMC mode. By reading this bit, whether the card is in the busy state can be monitored after the card in the busy state has been deselected and then selected again afterwards. 0: Card indicates data busy. 1: Card indicates not data busy.
1
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
0
REQ
0
R
Interrupt Request Indicates whether an interrupt is requested. An interrupt request is the logical OR of the INTSTR0, INTSTR1, and INTSTR2 flags. Settings of the INTSTR0, INTSTR1, and INTSTR2 flags are controlled by the enable bits in INTCR0, INTSTR1, and INTCR2. 0: No interrupt requested. 1: Interrupt requested.
Rev. 1.00 Oct. 01, 2007 Page 1309 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
31.3.12 Interrupt Control Registers 0 and 1 (INTCR0, INTCR1) The INTCR registers enable or disable the INTSTR0 and INTSTR1 flags and control the interrupt outputs. * INTCR0
Bit: 7
FEIE
6
FFIE
5
DRPIE
4
DTIE
3
2
1
0
CRPIE CMDIE DBSYIE BTIE
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name FEIE
Initial Value 0
R/W R/W
Description FIFO Empty Flag Enable 0: Disables FIFO empty flag setting. 1. Enables FIFO empty flag setting.
6
FFIE
0
R/W
FIFO Full Flag Enable 0: Disables FIFO full flag setting. 1: Enables FIFO full flag setting.
5
DRPIE
0
R/W
Data Response End Flag Enable 0: Disables data response end flag setting. 1: Enables data response end flag setting.
4
DTIE
0
R/W
Data Transfer End Flag Enable 0: Disables data transfer end flag setting. 1: Enables data transfer end flag setting.
3
CRPIE
0
R/W
Command Response End Flag Enable 0: Disables command response end flag setting. 1: Enables command response end flag setting.
2
CMDIE
0
R/W
Command Output End Flag Enable 0: Disables command output end flag setting. 1: Enables command output end flag setting.
1
DBSYIE
0
R/W
Data Busy End Flag Enable 0: Disables data busy end flag setting. 1: Enables data busy end flag setting.
Rev. 1.00 Oct. 01, 2007 Page 1310 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
Bit 0
Bit Name BTIE
Initial Value 0
R/W R/W
Description Multiblock Transfer End Flag Enable. 0: Disables multiblock transfer end flag setting 1: Enables multiblock transfer end flag setting
* INTCR1
Bit: 7 6 5 4 -- 0 R 3 2 1 0
CTERIE
INTRQ2E INTRQ1E INTRQ0E WRERIE CRCERIE DTERIE
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name INTRQ2E
Initial Value 0
R/W R/W
Description ERR Interrupt Enable 0: Disables ERR interrupt. 1: Enables ERR interrupt.
6
INTRQ1E
0
R/W
TRAN Interrupt Enable 0: Disables TRAN interrupt. 1: Enables TRAN interrupt.
5
INTRQ0E
0
R/W
FSTAT Interrupt Enable 0: Disables FSTAT interrupt. 1: Enables FSTAT interrupt.
4
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
3
WRERIE
0
R/W
Write Error Flag Enable 0: Disables write error flag setting. 1: Enables write error flag setting.
2
CRCERIE
0
R/W
CRC Error Flag Enable 0: Disables CRC error flag setting. 1: Enables CRC error flag setting.
1
DTERIE
0
R/W
Data Timeout Error Flag Enable 0: Disables data timeout error flag setting. 1: Enables data timeout error flag setting.
Rev. 1.00 Oct. 01, 2007 Page 1311 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
Bit 0
Bit Name CTERIE
Initial Value 0
R/W R/W
Description Command Timeout Error Flag Enable 0: Disables command timeout error flag setting. 1: Enables command timeout error flag setting.
31.3.13 Interrupt Status Registers 0 and 1 (INTSTR0, INTSTR1) The INTSTR registers control MMCIF interrupts. * INTSTR0
Bit:
7
FEI
6
FFI
5
DRPI
4
DTI
3
CRPI
2
CMDI
1
DBSYI
0
BTI
Initial value: 0 0 0 0 0 0 0 0 R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Bit 7
Bit Name FEI
Initial Value 0
R/W
Description
Interrupt output FSTAT
R/(W)* FIFO Empty Flag [Setting 1 condition] When FIFO becomes empty while FEIE = 1 and write data is being transmitted (when the FIFO_EMPTY bit in CSTR is set) [Clearing 0 condition] Write 0 after reading FEI = 1.
6
FFI
0
R/(W)* FIFO Full Flag [Setting 1 condition] When FIFO becomes full while FFIE = 1 and read data is being received (when the FIFO_FULL bit in CSTR is set) [Clearing 0 condition] Write 0 after reading FFI = 1.
FSTAT
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Section 31 Multimedia Card Interface (MMCIF)
Bit 5
Bit Name DRPI
Initial Value 0
R/W
Description
Interrupt output TRAN
4
DTI
0
3
CRPI
0
2
CMDI
0
R/(W)* Data Response Flag [Setting 1 condition] When the CRC status is received while DRPIE = 1. [Clearing 0 condition] Write 0 after reading DRPI = 1. R/(W)* Data Transfer End Flag [Setting 1 condition] When the number of bytes of data transfer specified in TBCR ends while DTIE = 1. [Clearing 0 condition] Write 0 after reading DTI = 1. R/(W)* Command Response Receive End Flag [Setting 1 condition] When command response reception ends while CRPIE = 1. [Clearing 0 condition] Write 0 after reading CRPI = 1. R/(W)* Command Transmit End Flag [Setting 1 condition] When command transmission ends while CMDIE = 1. [Clearing 0 condition] Write 0 after reading CMDI = 1. R/(W)* Data Busy End Flag [Setting 1 condition] When data busy state is canceled while DBSYIE = 1 [Clearing 0 condition] Write 0 after reading DBSYI = 1.
TRAN
TRAN
TRAN
1
DBSYI
0
TRAN
0
BTI
0
R/(W)* Multiblock Transfer End Flag [Setting 1 condition] When the number of bytes of data transfer specified in TBCR ends after TBNCR is decremented to 0 while BTIE = 1. [Clearing 0 condition] Write 0 after reading BTI = 1.
TRAN
Note:
*
Cleared by writing 0 after reading 1
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Section 31 Multimedia Card Interface (MMCIF)
* INTSTR1
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 2 1 0
WRERI CRCERI DTERI CTERI
0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)*
Bit 7 to 4
Bit Name --
Initial Value All 0
R/W R
Description
Interrupt output
3
WRERI
0
2
CRCERI
0
Reserved These bits are always read as 0. The write value should always be 0. R/(W)* Write Error Flag ERR [Setting 1 condition] When a status error (write error) for transmit data response is detected while WREIE = 1. [Clearing 0 condition] Write 0 after reading WREI = 1. Note: When the write error occurs, abort the command sequence by setting the CMDOFF bit to 1. R/(W)* CRC Error Flag ERR [Setting 1 condition] When a CRC error for command response or receive data or a CRC status error for transmit data response is detected while CRCERIE = 1. For the command response other than R2, CRC is checked when the RTY4 in RSPTYR is enabled. For the R2 command response, CRC is not checked, thus this flag is not set. [Clearing 0 condition] Write 0 after reading CRCERI = 1. Note: When the CRC error occurs, abort the command sequence by setting the CMDOFF bit to 1.
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Section 31 Multimedia Card Interface (MMCIF)
Bit 1
Bit Name DTERI
Initial Value 0
R/W
Description
Interrupt output
0
CTERI
0
R/(W)* Data Timeout Error Flag ERR [Setting 1 condition] When a data timeout error specified in DTOUTR occurs while DTERIE = 1. [Clearing 0 condition] Write 0 after reading DTERI = 1. Note: When the data timeout error occurs, abort the command sequence by setting the CMDOFF bit to 1 and then clear the DTERI flag. R/(W)* Command Timeout Error Flag ERR [Setting 1 condition] When a command timeout error specified in TOCR occurs while CTERIE = 1. [Clearing condition] Write 0 after reading CTERI = 1. Note: When the command timeout error occurs, abort the command sequence by setting the CMDOFF bit to 1 and then clear the CTERI flag.
Note:
*
Cleared by writing 0 after reading 1
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Section 31 Multimedia Card Interface (MMCIF)
31.3.14 Transfer Clock Control Register (CLKON) CLKON controls the transfer clock frequency and clock ON/OFF. Bits CSEL[3:0] must be set to 0001 for the peripheral clock of 33.3 MHz in order to achieve a 16.7-Mbps transfer clock in the MMCIF. At this time, use a sufficiently slow clock for transfer in open-drain type output in MMC mode. In a command sequence, do not perform clock ON/OFF or frequency modification.
Bit: 7
CLKON
6 -- 0 R
5 -- 0 R
4 -- 0 R
3
2
1
0
CSEL[3:0]
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name CLKON
Initial Value 0
R/W R/W
Description Clock On 0: Fixes the transfer clock output from the MMC_CLK pin to low level. 1: Outputs the transfer clock from the MMC_CLK pin.
6 to 4
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
3 to 0
CSEL[3:0]
0000
R/W
Transfer Clock Frequency Select
0000: Setting prohibited 0001: Uses the 1/2-divided system clock as a transfer clock. 0010: Uses the 1/4-divided system clock as a transfer clock. 0011: Uses the 1/8-divided system clock as a transfer clock. 0100: Uses the 1/16-divided system clock as a transfer clock. 0101: Uses the 1/32-divided system clock as a transfer clock. 0110: Uses the 1/64-divided system clock as a transfer clock. 0111: Uses the 1/128-divided system clock as a transfer clock. 1000: Uses the 1/256-divided system clock as a transfer clock. 1001 to 1111: Setting prohibited
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Section 31 Multimedia Card Interface (MMCIF)
31.3.15 VDD/Open-Drain Control Register (VDCNT) VDCNT can use the MMC_ODMOD pin to control open-drain in MMC mode. MMC_VDDON output is available for ON/OFF of the card power supply (VDD).
Bit: 7 6 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R
VDDON ODMOD
Initial value: R/W:
0 R/W
0 R/W
Bit 7
Bit Name VDDON
Initial Value 0
R/W R/W
Description Available as a control signal for card power supply (VDD) 0: Low level signal is output to MMC_VDDON. 1: High level signal is output to MMC_VDDON.
6
ODMOD
0
R/W
Available to control open-drain of CMD output in MMC mode 0: Low level signal is output to MMC_ODMOD. 1: High level signal is output to MMC_ODMOD.
5 to 0
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 31 Multimedia Card Interface (MMCIF)
31.3.16 Data Register (DR) DR is a register to read/write the FIFO data. Word- or byte-access is possible.
Bit: 15 14 13 12 11 10 9 8 DR Initial value: -- R/W: R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 6 5 4 3 2 1 0
Bit 15 to 0 (7 to 0)
Bit Name DR
Initial Value
Undefined
R/W R/W
Description Register to read/write FIFO data. Word- or byte-access is possible. However, address 2n + 1 cannot be accessed in bytes.
31.3.17 FIFO Pointer Clear Register (FIFOCLR) The FIFO write/read pointer is cleared by writing an arbitrary value to FIFOCLR.
Bit: 7 6 5 4 3 2 1 0
FIFOCLR
Initial value: R/W:
-- W
-- W
-- W
-- W
-- W
-- W
-- W
-- W
Bit 7 to 0
Bit Name FIFOCLR
Initial Value
Undefined
R/W W
Description The FIFO pointer is cleared by writing an arbitrary value to this register.
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Section 31 Multimedia Card Interface (MMCIF)
31.3.18 DMA Control Register (DMACR) DMACR sets DMA request signal output. DMAEN enables or disables a DMA request signal. The DMA request signal is output based on a value that has been set to SET[2:0]. This register should be set before a multiblock transfer command (CMD18 or CMD25) is executed. Auto mode cannot be used for open-ended multiblock transfers.
Bit: 7
DMAEN
6
AUTO
5 -- 0 R
4 -- 0 R
3 -- 0 R
2
1
SET[2:0]
0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6
Bit Name DMAEN AUTO
Initial Value 0 0
R/W R/W R/W
Description 0: Disables output of DMA request signal. 1: Enables output of DMA request signal. Auto Mode for pre-define multiblock transfer using DMA transfer. For details on auto mode operation, see section 14, Direct Memory Access Controller (DMAC). 0: Disable auto mode 1: Enable auto mode
5 to 3
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
SET[2:0]
000
R/W
Sets DMA request signal assert condition.
000: Not output 001: Remaining data in FIFO is 1/4 or less of FIFO capacity. 010: Remaining data in FIFO is 1/2 or less of FIFO capacity. 011: Remaining data in FIFO is 3/4 or less of FIFO capacity. 100: Remaining data in FIFO is 1 byte or more. 101: Remaining data in FIFO is 1/4 or more of FIFO capacity. 110: Remaining data in FIFO is 1/2 or more of FIFO capacity. 111: Remaining data in FIFO is 3/4 or more of FIFO capacity.
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Section 31 Multimedia Card Interface (MMCIF)
31.3.19 Interrupt Control Register 2 (INTCR2) INTCR2 controls the enable/disable of interrupts.
Bit: 7
INTREQ3E
6 -- 0 R
5 -- 0 R
4 -- 0 R
3 -- 0 R
2 -- 0 R
1
CDIE
0
FRDYIE
Initial value: R/W:
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name INTRQ3E
Initial Value 0
R/W R/W
Description FRDY Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled
6 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1
CDIE
0
R/W
Card Detection Flag Enable 0: Setting of card detection flag disabled 1: Setting of card detection flag enabled
0
FRDYIE
0
R/W
FIFO Ready Completion Flag Enable 0: Setting of FIFO ready completion flag disabled 1: Setting of FIFO ready completion flag enabled
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Section 31 Multimedia Card Interface (MMCIF)
31.3.20 Interrupt Status Register 2 (INTSTR2) INTSTR2 controls the interrupt output of the MMCIF. FRDYI is set even in the set condition after a clear. To clear FRDYI, disable the flag setting through FRDYIE in INTCR2.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2
CDI
1
FRDY_ TU
0
FRDYI
0 R/(W)*
1 R
0 R/(W)*
Bit 7 to 3
Bit Name --
Initial Value All 0
R/W R
Description
Interrupt output
2
CDI
0
1
FRDY_TU
1
0
FRDYI
0
Reserved These bits are always read as 0. The write value should always be 0. R/(W)* Card Identification Flag FRDY Identifies insert/pullout of card (variation between high and low of card identification signal) [Setting 1 condition] When insert/pullout of card is identified while CDIE = 1. [Clearing 0 condition] Write 0 after reading CDI = 1. R When the set condition of FRDYI is met Read value 0: Remaining data in FIFO meets the assert condition specified by DMACR. 1: Remaining data in FIFO does not meet the assert condition specified by DMACR. R/(W)* FIFI Ready Completion Flag FRDY [Setting 1 condition] When the DMAEN bit is set while FRDYIE = 1 and the remaining data in FIFO does not meet the assert condition specified by DMACR. [Clearing 0 condition] Write 0 after reading FRDYI = 1.
Note:
*
Cleared by writing 0 after reading 1
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Section 31 Multimedia Card Interface (MMCIF)
31.3.21 Card Switch Register (CSWR) CSWR indicates the state of the card identification signal.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 1 R 0 CDB* 0 R
Bit 7 to 2
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1
1
R
Reserved This bit is always read as 1. The write value should always be 1.
0
CDB*
0
R
Card Identification State Indication Indicates insert/pullout of card 0: Card not inserted (mmc_cd = 1) 1: Card inserted (mmc_cd = 0)
Note:
*
mmc_cd = 0 indicates the card is inserted. The polarity of the card identification state indication changes depending on the connector types.
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Section 31 Multimedia Card Interface (MMCIF)
31.3.22 Switch Status Register (SWSR) SWSR controls the peripheral clock 1 and the internally divided clock when the card is identified.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2
GATE_ CDB
1 -- 0 R
0 -- 0 R
0 R/W
Bit 7 to 3
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2
GATE_CDB 0
R/W
Clock Control at Card Identification Stops the clock supply to FF that is not required at card identification 0: Peripheral clock 1 and internal divided clock operating 1: Peripheral clock 1 and internal divided clock halted
1, 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 31 Multimedia Card Interface (MMCIF)
31.3.23 Chattering Elimination Pulse Setting Register (CHATR) CHATR specifies the cycle of the chattering elimination pulse to eliminate the chattering that arises in the card identification signal.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 1 R/W 0 R/W 4 3 2 CHAT 0 R/W 1 R/W 1 R/W 1 0
Bit 7 to 5 4 to 0
Bit Name CHAT
Initial Value 000 10011
R/W R R/W
Description The read value is 0. The write value should be 0. Frequency for Chattering Elimination Pulse Cycle 00000 to 01000 and 11000 to 11111: setting prohibited
Chattering elimination pulse cycle Term (sec) = 2char/Pck1 frequency (MHz) Pck1: Peripheral clock 1 Chattering: An unstable state in which ON and OFF repeatedly occur immediately after the switching of the card identification signal.
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Section 31 Multimedia Card Interface (MMCIF)
Table 31.7 List of Chattering Elimination Pulse Cycles
Decimal Notation (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) Chattering Elimination Pulse Cycle 2
chat
chat 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111
Pck1 = 33 MHz 0.015 (ms) 0.031 (ms) 0.061 (ms) 0.123 (ms) 0.246 (ms) 0.492 (ms) 0.983 (ms) 1.966 (ms) 3.932 (ms) 7.864 (ms) 15.729 (ms) 31.457 (ms) 62.915 (ms) 125.829 (ms) 251.658 (ms)
512 1024 2048 4096 8192 16384 32768 65536 131072 262144 524288 1048576 2097152 4194304 8388608
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Section 31 Multimedia Card Interface (MMCIF)
31.4
Operation
The multimedia card is an external storage media that can be easily connected or disconnected. The MMCIF controls data transfer with the multimedia card and operates in MMC mode. Insert a card and supply power to it. Then operate the MMCIF by applying the transfer clock after setting an appropriate transfer clock frequency. In this case, MMC_VDDON and MMC_ODMOD are available for card power supply control and open-drain mode control, respectively. A series of operations starting with sending out commands, receiving a command response, data transmit/receive, receiving data responses, etc. is called the command sequence. The command response starts with sending out commands by setting the START bit in CMDSTRT and ends with the completion of all data transmit/receive and responses. The multimedia card may go into the data busy state in which the card receives only special commands caused by writing to or erasing the flash memory in the card. The data busy state is indicated by a `0' output from the card through the DAT pin. Notes: Do not connect or disconnect the card during command sequence execution or in the data busy state. 31.4.1 Operations in MMC Mode
MMC mode is an operating mode in which the transfer clock is output from the MMC_CLK pin, command transmission/response reception occurs via the MMC_CMD pin, and data is transmitted/received via the MMC_DAT pin. In this pin configuration, the next command can be issued while data is being transmitted or received. This feature is utilized for multiblock or stream transfer. The CMD12 command is an example of where the current command sequence is aborted. In MMC mode, broadcast commands that simultaneously issue commands to multiple cards are supported. After information from the inserted cards is recognized through a broadcast command, a relative address is given to each card. One card is selected by the relative address with other cards deselected, and then various commands are issued to the selected card. Commands in MMC mode are basically classified into three types: broadcast, relative address, and flash memory operation commands. The card can be operated by issuing these commands appropriately according to the card state.
Rev. 1.00 Oct. 01, 2007 Page 1326 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
(1)
Operation of Broadcast Commands
CMD0, CMD1, CMD2, and CMD4 are broadcast commands. These commands and the CMD3 command make up a sequence where relative addresses are assigned to individual cards. In this sequence, the CMD output format is open drain and the command response is wired-OR. The transfer clock frequency should be set low enough by dividing the transfer clock for the CLKON register by 28. * All cards are initialized to the idle state by CMD0. * The operation condition registers (OCR) of all cards are read via wired-OR and cards that cannot operate are deactivated by CMD1. The cards that are not deactivated enter the ready state. * The card identification (CID) of each card in the ready state is read via wired-OR through CMD2. Each card compares its own CID and data on the CMD, and if they differ, the card immediately aborts the CID output. One card that has completed its output enters the acknowledge state. When the R2 response is necessary, set the CTOCR register to H'01. * A relative address (RCA) is given to the card in the acknowledge state through CMD3. A card that can acquire an RCA enters the standby state. * By repeating CMD2 and CMD3, an RCA is given to all cards in the ready state to put the cards in the standby state. Note: When requesting the R2 response (a 17-byte command response) in MMC mode, set CTSEL0 to 1. Setting CTSEL0 to 0 causes a timeout while receiving the response. (2) Operation of Relative Address Commands
CMD7, CMD9, CMD10, CMD13, CMD15, CMD39, and CMD55 are relative address commands that address the card through its RCA. The relative address commands are used to read card administration information and original information, and to change the specific card states. CMD7 sets one addressed card to the transfer state, and the other cards to the standby state. Only the card in the transfer state can execute flash-memory operation commands, other than broadcast or relative-address commands.
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Section 31 Multimedia Card Interface (MMCIF)
(3)
Operation of Commands Not Requiring Command Response
Some broadcast commands do not require a command response. Figure 31.2 shows an example of the command sequence for commands that do not require a command response. Figure 31.3 shows the operational flow for commands that do not require a command response. * Create settings to issue the command. * Set the START bit in CMDSTRT to 1 to start command transmission. * The end of the command sequence is detected by poling the BUSY flag in CSTR or through the command output end interrupt (CMDI).
Input/output pins CLK
CMD
Command output (48 bits)
DAT CMDSTRT (START) INTSTR0 (CMDI) CSTR (CWRE) Command transmission period (BUSY) Command sequence period
(REQ)
Command transmission started
Command transmission ended
Figure 31.2 Example of Command Sequence for Commands Not Requiring Command Response
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Section 31 Multimedia Card Interface (MMCIF)
Start of command sequence
Set command data to CMDR0 to CMDR4
Set command type to CMDTYR
Set command response type to RSPTYR
Set the START bit in CMDSTRT to 1
(CMDI) interrupt detected? Yes End of command sequence
No
Figure 31.3 Example of Operational Flow for Commands Not Requiring Command Response (4) Operation of Commands without Data Transfer
Broadcast, relative address, and flash memory operation commands include a number of commands that do not include data transfer. Such commands execute the desired data transfer using command arguments and command responses. For a command that is related to timeconsuming processing such as flash memory write/erase, the card indicates the data busy state via the DAT. Figures 31.4 and 31.5 show examples of the command sequence for commands without data transfer. Figure 31.6 shows the operational flow for commands without data transfer. * Create settings to issue the command. * Set the START bit in CMDSTRT to 1 to start command transmission. * Command transmission completion can be confirmed through the command transmit end interrupt (CMDI). * The command response is received from the card.
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Section 31 Multimedia Card Interface (MMCIF)
* If the card returns no command response, the command response is detected through the command timeout error (CTERI). * The end of the command sequence is detected by poling the BUSY flag in CSTR or through the command response receive end interrupt (CRPI). * Check whether the state is data busy or not through the DTBUSY_TU bit in CSTR. If data busy is detected, the end of data busy state is detected through the data busy end interrupt (DBSYI). * Write the CMDOFF bit to 1 when a CRC error (CRCERI) or command timeout error (CTERI) occurs.
Input/output pins CLK CMD Command output (48 bits) Command response reception (No busy state)
DAT CMDSTRT (START) INTSTR0 (CMDI)
(CRPI) (DBSYI)
Command transmission started
Response reception completed
CSTR
(CWRE)
Command transmission period
(BUSY)
(DTBUSY_TU)
Command sequence execution period
(DTBUSY) (REQ)
Figure 31.4 Example of Command Sequence for Commands without Data Transfer (No Data Busy State)
Rev. 1.00 Oct. 01, 2007 Page 1330 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
Input/output pins CLK CMD Command output (48 bits) Command response reception (Busy state)
DAT
CMDSTRT (START) INTSTR0 (CMDI)
(CRPI) (DBSYI)
Command transmission started
Response reception completed Busy state completed
CSTR (CWRE) (BUSY)
(DTBUSY_TU)
Command transmission period Command sequence execution period
Data busy period
(REQ)
Figure 31.5 Example of Command Sequence for Commands without Data Transfer (with Data Busy State)
Rev. 1.00 Oct. 01, 2007 Page 1331 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
Start of command sequence
Set command data to CMDR0 to CMDR4
Set command type to CMDTYR
Set command response type to RSPTYR
Set the START bit in CMDSTRT to 1
* CRCERI interrupt detected? No
CRPI interrupt detected? Yes
R1b response? Yes
DTBUSY detected? Yes
No DBSYI interrupt detected? Yes End of command sequence
Yes
No
No
No
CTERI interrupt detected?
No
Yes
Set the CMDOFF to 1
Note: In R2 command response case, determine whether or not error exists through CRC check by software. Hardware executes no CRC check.
Figure 31.6 Example of Operational Flow for Commands without Data Transfer
Rev. 1.00 Oct. 01, 2007 Page 1332 of 1956 REJ09B0256-0100
Section 31 Multimedia Card Interface (MMCIF)
(5)
Commands with Read Data
Flash memory operation commands include a number of commands involving read data. Such commands confirm the card status through the command argument and command response, and receive card information and flash memory data from the MMC_DAT pin. In multiblock transfer, there are two methods of transfer: the open-ended and pre-defined methods. The open-ended method suspends operation at each block transfer and waits for an instruction as to whether to continue the command sequence. The pre-defined method starts transferring with the block number set beforehand. When the FIFO is full between blocks in multiblock transfer, the command sequence is suspended. Once the command sequence is suspended, any necessary processing of the data in FIFO must be done before the command sequence is continued. Figures 31.7 to 31.9 show examples of the command sequence for commands with read data. Figures 31.10 to 31.12 show the operational flows for commands with read data. * Create settings to issue the command, and clear FIFO. * Set the START bit in CMDSTRT to 1 to start command transmission. * Command transmission completion can be confirmed through the command transmit end interrupt (CMDI). * The command response is received from the card. * If the card returns no command response, the command response is detected through the command timeout error (CTERI). * Read data is received from the card. * The inter-block suspension in multiblock transfer and suspension due to FIFO full are detected through the data transfer end interrupt (DTI) and FIFO full interrupt (FFI), respectively. To continue the command sequence, the RD_CONTI bit in OPCR should be set to 1. To end the command sequence, the CMDOFF bit in OPCR should be set to 1, and CMD12 should be issued. Unless the sequence is suspended in a pre-defined multiblock transfer, CMD12 is not needed. * The end of the command sequence is detected by poling the BUSY flag in CSTR or the data transfer end interrupt (DTI).
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Section 31 Multimedia Card Interface (MMCIF)
* Write 1 to the CMDOFF bit when a CRC error (CRCERI) or command timeout error (CTERI) occurs in the command response reception. * Clear the FIFO by writing 1 to the CMDOFF bit when a CRC error (CRCERI) or data timeout error (DTERI) occurs in the read data reception. Note: In multiblock transfer, when the command sequence is ended (write 1 to the CMDOFF bit) before command response reception (CRPI), the command response may not be received correctly. Therefore, to receive the command response, the command sequence must be continued (set the RD_CONTI bit to 1) until the command response reception ends.
Input/output pins CLK CMD17 (READ_SINGLE_BLOCK) CMD DAT CMDSTRT (START) OPCR (RD_CONTI) (CMDOFF) INTSTR0 (CMDI) (CRPI) (DTI) (FFI) CSTR (CWRE) Single block read command execution sequence Command transmission started Read data Command Command response
(BUSY) (FIFO_FULL) (REQ)
Figure 31.7 Example of Command Sequence for Commands with Read Data (Block Size FIFO Size)
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Section 31 Multimedia Card Interface (MMCIF)
Input/output pins CLK CMD17 (READ_SINGLE_BLOCK) CMD DAT CMDSTRT (START) OPCR (RD_CONTI) (CMDOFF) INTSTR0 (CMDI) (CRPI) (DTI) (FFI) CSTR (CWRE) Single block read command execution sequence Command transmission started Command Command response Read data
Transfer clock transmission halted Block data reception suspended
Transfer clock transmission resumed Block data reception resumed
Read data
Reading data from FIFO
(BUSY) (FIFO_FULL) (REQ)
Figure 31.8 Example of Command Sequence for Commands with Read Data (Block Size > FIFO Size)
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Section 31 Multimedia Card Interface (MMCIF)
Input/output pins CLK
CMD
CMD18 (READ_MULTIPLE_BLOCK)
Command
Command response
Transfer clock transmission halted
Transfer clock transmission resumed
CMD12 (STOP_TRANSMISSION)
DAT CMDSTRT (START)
OPCR
(RD_CONTI)
Read data
Read data
Read data
Command
Command response
Command transmission started
Block data reception ended
(CMDOFF) INTSTR0 (CMDI)
(CRPI) (DTI) (FFI)
CSTR (CWRE) (BUSY)
(FIFO_FULL)
Multiblock read command execution sequence
Stop command execution sequence
(REQ)
Figure 31.9 Example of Command Sequence for Commands with Read Data (Multiblock Transfer)
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Section 31 Multimedia Card Interface (MMCIF)
Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normally ended? Yes Execute CMD17 (CMDR to CMDSTRT) No
CRCERI interrupt detected? No CRPI interrupt detected? Yes Read response register
Yes
No
CTERI interrupt detected? No Yes
No
Response status normally ended? Yes Yes DTERI interrupt detected? No No Cap Len - Cap x n (FFI) Yes Yes CRCERI interrupt detected? No DTERI interrupt detected? No No No DTI interrupt detected? FFI interrupt detected? Yes Read data from FIFO Read data from FIFO Set the RD_CONTI to 1 End of command sequence [Legend] Len: Block length [Byte] Cap: FIFO size [Byte] n (FFI): Number of FFI from read sequence starts Clear FIFO Yes Set the CMDOFF to 1 Yes
Set the CMDOFF to 1
Figure 31.10 Example of Operational Flow for Commands with Read Data (Single Block Transfer)
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Section 31 Multimedia Card Interface (MMCIF)
Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normally ended? Yes Execute CMD18 (CMDR to CMDSTRT) No
CRCERI interrupt detected? No CRPI interrupt detected? Yes Read response register Response status normally ended? Yes 1
Yes
No
No CTERI interrupt detected? No Yes
2
Figure 31.11 (1) Example of Operational Flow for Commands with Read Data (Open-ended Multiblock Transfer)
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Section 31 Multimedia Card Interface (MMCIF)
1
2
DTERI interrupt detected? No
No
Cap Len (1 + n (DTI)) - Cap x n (FFI)
Yes
Yes
CRCERI interrupt detected?
Yes
No
DTERI interrupt detected?
Yes
No
No DTI interrupt detected? Yes
No
No
FFI interrupt detected?
Next block read? Yes
Yes
Read data from FIFO
Set the RD_CONTI to 1
Read data from FIFO
Set the CMDOFF to 1
Execute CMD12
Set the CMDOFF to 1
Execute CMD12
Clear FIFO
Set the CMDOFF to 1
End of command sequence
[Legend] Len: Block length [Byte] Cap: FIFO size [Byte] n (FFI): Number of FFI from read sequence starts n (DTI): Number of DTI from read sequence start
Figure 31.11 (2) Example of Operational Flow for Commands with Read Data (Open-ended Multiblock Transfer)
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Section 31 Multimedia Card Interface (MMCIF)
Start of command sequence Clear FIFO
Set the number of transfer block size to TBCR
Execute CMD16 CMD16 normally ended? Yes
Set the number of transfer block TBCR
No
Execute CMD23 CMD23 normally ended? Yes Execute CMD18 (CMDR to CMDSTRT) No
CRCERI interrupt detected? No CRPI interrupt detected? Yes Read response register Response status normally ended? Yes
1
Yes
No
CTERI interrupt detected?
No
No
Yes
2
Figure 31.12 (1) Example of Operational Flow for Commands with Read Data (Pre-defined Multiblock Transfer)
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Section 31 Multimedia Card Interface (MMCIF)
1
2
Yes DTERI interrupt detected? No No
Cap Len (1 + n (DTI)) - Cap x n (FFI)
Yes Yes CRCERI interrupt detected? No Yes DTERI interrupt detected? No No No FFI interrupt detected? Yes No TBNCR value = n (DTI)? Yes No DTI interrupt detected? Yes
BTI interrupt detected? Yes
Read data from FIFO Set the RD_CONTI to 1
Read data from FIFO Set the CMDOFF to 1 Set the CMDOFF to 1 Execute CMD12 Clear FIFO Set the CMDOFF to 1
End of command sequence [Legend] Len: Block length [Byte] Cap: FIFO size [Byte] n (FFI): Number of FFI from read sequence starts n (DTI): Number of DTI from read sequence start
Figure 31.12 (2) Example of Operational Flow for Commands with Read Data (Pre-defined Multiblock Transfer)
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Section 31 Multimedia Card Interface (MMCIF)
(6)
Commands with Write Data
Flash memory operation commands include a number of commands involving write data. Such commands confirm the card status through the command argument and command response, and transmit card information and flash memory data via the MMC_DAT pin. For a command that is related to time-consuming processing such as flash memory write, the card indicates the data busy state to the MMC_DAT pin. In multiblock transfer, there are two methods of transfer: the open-ended and pre-defined methods. The open-ended method suspends operation at each block transfer and waits for an instruction as to whether to continue the command sequence. The pre-defined method starts transferring with the block number set beforehand. When the FIFO is empty between blocks in multiblock transfer, the command sequence is suspended. Once the command sequence is suspended, any necessary processing of data in FIFO must be done before the command sequence is continued. Figures 31.13 to 31.15 show examples of the command sequence for commands with write data. Figures 31.16 to 31.18 show the operational flows for commands with write data. * * * * * * * Create settings to issue a command, and clear FIFO. Set the START bit in CMDSTRT to 1 to start command transmission. The command response is received from the card. If the card returns no command response, the command response is detected through the command timeout error (CTERI). Set the write data to FIFO. Set the DATAEN bit in OPCR to 1 to start write data transmission. Inter-block suspension in multiblock transfer and suspension by the FIFO empty are detected through the data response completion flag (DRPI) and FIFO empty flag (FEI), respectively. To continue the command sequence, fill FIFO with write data and set the DATAEN bit in OPCR to 1. To end the command sequence, the CMDOFF bit in OPCR should be set to 1 and CMD12 should be issued. Unless the sequence is suspended in pre-defined multiblock transfer, CMD12 is not needed. The end of the command sequence is detected by poling the BUSY flag in CSTR, data response completion flag (DRPI), or pre-defined multiblock transfer completion (BTI). After the data transfer end (after DPRI detection), the data busy state is checked through DTBUSY in CSTR. If the card is in the data busy state, the release of the data busy state is detected through the data busy end flag (DBSYI).
* *
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Section 31 Multimedia Card Interface (MMCIF)
* Write the CMDOFF bit to 1 when a CRC error (CRCERI) or command timeout error (CTERI) occurs in the command response reception. * Write the CMDOFF bit to 1 when a CRC error (CRCERI) or data timeout error (DTERI) occurs in the write data transmission.
Input/output pins CLK
CMD24 (WRITE_SINGLE_BLOCK)
CMD DAT CMDSTRT (START) OPCR
(DATAEN) (CMDOFF)
Command Command response Command transmission started Write data Status
Busy
INTSTR0 (CMDI)
(CRPI) (DTI)
(DRPI)
(DBSYI) (FEI) CSTR (CWRE)
(BUSY)
(FIFO_EMPTY)
Single block write command execution sequence
(DTBUSY_TU)
(REQ)
Figure 31.13 Example of Command Sequence for Commands with Write Data (Block Size FIFO Size)
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Section 31 Multimedia Card Interface (MMCIF)
Input/output pins CLK
CMD24 (WRITE_SINGLE_BLOCK)
CMD DAT CMDSTRT (START) OPCR
(DA TA EN)
Transfer clock transmission halted
Write data
Transfer clock transmission resumed
Write data
Command Command response Command transmission started
Busy Block data transmission Block data transmission resumed suspended
Writing data to FIFO
(CMDOFF) INTSTR0 (CMDI)
(CRPI) (DTI) (DRPI) (DBSYI) (FEI)
CSTR (CWRE) (BUSY)
(FIFO_EMPTY)
(DTBUSY) Single block write command execution sequence
(DTBUSY_TU)
(REQ)
Figure 31.14 Example of Command Sequence for Commands with Write Data (Block Size > FIFO Size)
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Section 31 Multimedia Card Interface (MMCIF)
Input/output pins CLK
CMD25 WRITE_MULTIPE_BLOCK
CMD12 (STOP_TRANSMISSION)
CMD
Command
DAT CMDSTRT (START)
OPCR (DATAEN)
Command response
Write data
Status
Write data
Write data
Command
Command response
Command transmission started Block data transmission started Next block data transmission started Block data reception ended
(CMDOFF) INTSTR0 (CMDI)
(CRPI) (DTI) (DRPI) (DBSYI) (FEI) CSTR (CWRE)
(BUSY)
(FIFO_EMPTY)
(DTBUSY)
Stop command execution sequence
(DTBUSY_TU)
(REQ)
Figure 31.15 Example of Command Sequence for Commands with Write Data (Multiblock Transfer)
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Section 31 Multimedia Card Interface (MMCIF)
Start of command sequence
Clear FIFO
Set the number of transfer block size to TBCR
Execute CMD16
CMD16 normally ended? Yes No
Execute CMD24 (CMDR to CMDSTRT)
CRPI interrupt detected? Yes
No
No
Read response register
Response status normally ended? Yes
Writing data to FIFO
Set the DATAEN to 1
No
CTERI interrupt detected?
No
Yes
FEI interrupt detected? Yes
No Cap x n (FEI) Len
Yes
No
DTI interrupt detected?
Yes
Yes
CRCERI interrupt detected?
No
Yes
DTERI interrupt detected?
No
No DRPI interrupt detected? Yes
Set the CMDOFF to 1
DTBUSY detected?
No
Yes
No
DBSYI interrupt detected? Yes
[Legend] Len: Block length [Byte] Cap: FIFO size [Byte] n (FEI): Number of FEI from write sequence starts
End of command sequence
Figure 31.16 Example of Operational Flow for Commands with Write Data (Single Block Transfer)
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Section 31 Multimedia Card Interface (MMCIF)
Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 No
CMD16 normally ended? Yes Execute CMD25 (CMDR to CMDSTRT)
CRCERI interrupt detected? No CRPI interrupt detected? Yes
Yes
No
No
Read response register
CTERI interrupt detected?
Response status normally ended? Yes
No
Yes
1
2
Figure 31.17 (1) Example of Operational Flow for Commands with Write Data (Open-ended Multiblock Transfer)
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Section 31 Multimedia Card Interface (MMCIF)
1
*
2
Writing data to FIFO Set the DATAEN to 1
No
FEI interrupt detected? Yes
No
Cap x n (FEI) - Len (1 + n (DRPI)) Len Yes
No
DTI interrupt detected? Yes Yes CRCERI interrupt detected? No Yes DTERI interrupt detected? No
No
DRPI interrupt detected? Yes DTBUSY detected? Yes No
No
DBSYI interrupt detected? Yes No Next block write? Yes Set the CMDOFF to 1 Execute CMD12 Set the CMDOFF to 1
End of command sequence
Note: * [Legend] Len: Cap: n (FEI): n (DRPI):
Write data for block size (block size < or = FIFO size) or for FIFO size (block size > FIFO size). Block length [Byte] FIFO size [Byte] Number of FEI from write sequence starts Number of DRPI from write sequence starts
Figure 31.17 (2) Example of Operational Flow for Commands with Write Data (Open-ended Multiblock Transfer)
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Section 31 Multimedia Card Interface (MMCIF)
Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normally ended? Yes Set the number of block to TBNCR
Execute CMD 23
CMD 23 normally ended?
No
No
Yes
Execute CMD25 (CMDR to CMDSTRT)
CRCERI interrupt detected? No CRPI interrupt detected? Yes
Yes
No
No
Read response register
CTERI interrupt detected?
Response status normally ended? Yes
No
Yes
1
2
Figure 31.18 (1) Example of Operational Flow for Commands with Write Data (Pre-defined Multiblock Transfer)
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Section 31 Multimedia Card Interface (MMCIF)
1
Writing data to FIFO
Set the DATAEN to 1
No
2
*
FEI interrupt detected? Yes
No
Cap x n (FEI) - Len (1 + n (DRPI)) Len Yes
DTI interrupt detected?
No
Yes
Yes
CRCERI interrupt detected?
No
Yes
DTERI interrupt detected?
No
No DRPI interrupt detected? Yes
DTBUSY detected?
No
Yes
No
DBSYI interrupt detected? Yes
No TBNCR = n (DRPI)? Yes
No
BTI interrupt detected? Yes
Set the CMDOFF to 1
Set the CMDOFF to 1
Execute CMD12
Set the CMDOFF to 1
End of command sequence
Note: * [Legend] Len: Cap: n (FEI): n (DRPI):
Write data for block size (block size < or = FIFO size) or for FIFO size (block size > FIFO size). Block length [Byte] FIFO size [Byte] Number of FEI from write sequence starts Number of DRPI from write sequence starts
Figure 31.18 (2) Example of Operational Flow for Commands with Write Data (Pre-defined Multiblock Transfer)
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Section 31 Multimedia Card Interface (MMCIF)
31.5
31.5.1
Operations when Using DMAC
Operation in Read Sequence
To transfer data using the DMAC, set MMCIF (DMACR) after setting the DMAC. Transmit the read command after setting DMACR. When using DMA, next block read is resumed automatically when the AUTO bit in DMACR is set to 1 under the condition that normal read is detected after a block transfer end of a pre-defined multiblock transfer. Figure 31.19 shows an example of the operational flow for a pre-defined multiblock read in MMC mode using auto-mode. * * * * * * * * Clear FIFO. Set the block number to TBNCR. Set DMACR. Read command transmission is started. Command response and read data are received from card. When the card does not return the command response, the command response is detected by the command timeout error (CTERI). The end of the command sequence is detected by poling the BUSY flag in CSTR or through the pre-defined multiblock transfer end flag (BTI). An error in a command sequence (during data reception) is detected through the CRC error flag or data timeout flag. When these flags are detected, set the CMDOFF bit in OPCR to 1, issue CMD12, and suspend the command sequence. The data remains in FIFO after the read sequence end. Set the SET[2:0] bits in DMACR to 100 to read all data left in FIFO if necessary. Confirm the DMAC transfer completion and clear the DMAEN bit in DMACR to 0. Set the CMDOFF bit to 1 and clear DMACR to H'00 when a CRC error (CRCERI) or command timeout error (CTERI) occurs in the command response reception. Set the CMDOFF bit to 1, clear DMACR to H'00, and clear FIFO when a CRC error (CRCERI) or data timeout error (DTERI) occurs in the read data reception.
* * * *
Note: * In multiblock transfer, when the command sequence is ended (1 is written to the CMDOFF bit) before command response reception ends (CRPI), the command response may not be received correctly. Therefore, to receive the command response, the command sequence must be continued (set the RD_CONTI bit to 1) until the command response reception ends. Access from the DMAC to FIFO must be done in bytes or words.
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Section 31 Multimedia Card Interface (MMCIF)
Start of command sequence Clear FIFO
Set the number of transfer block size to TBCR
Execute CMD16 CMD16 normally ended? Yes
Set the number of transfer block to TBCR Execute CMD 23 No
No
CMD 23 normally ended?
Yes
Set DMAC-related condition Set DMACR (MMCIF)
Execute CMD 18 (CMDR to CMDSTRT)
CRCERI interrupt detected? No
Yes
CRPI interrupt detected? Yes Read response register
No
CTERI interrupt detected?
No
Response status normally ended? Yes
1
No
Yes
2
Figure 31.19 (1) Example of Operational Flow for Auto-mode Pre-defined Multiblock Read Transfer
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Section 31 Multimedia Card Interface (MMCIF)
1
2
CRCERI interrupt detected? No
DTERI interrupt detected?
No
Yes
Yes
No
BTI interrupt detected? Yes
Set the DMACR to H'84
No DMA transfer ended? Yes
Set the CMDOFF to 1
Set the CMDOFF to 1
Execute CMD12
Set the CMDOFF to 1
Clear the DMACR to H'00
Clear the DMACR to H'00
Clear FIFO
Clear the DMACR to H'00
End of command sequence
Figure 31.19 (2) Example of Operational Flow for Auto-mode Pre-defined Multiblock Read Transfer
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Section 31 Multimedia Card Interface (MMCIF)
31.5.2
Operation in Write Sequence
To transfer data using the DMAC, set MMCIF (DMACR) after setting the DMAC. When using DMA, it is possible to process the inter-block interrupt by hardware in pre-defined multiblock transfer by setting the AUTO bit in DMACR to 1. Figure 31.20 shows an example of the operational flow for a pre-defined multiblock write sequence in MMC mode using auto-mode. * * * * * * * * * Clear FIFO. Set the block number to TBNCR. Set the START bit in CMDSTRT to 1 and command transmission will begin. Command response is received from the card. If the card does not return the command response, the command response is detected through the command timeout error (CTERI). Set the DMACR and write data in FIFO. Confirm the DMAC transfer completion and clear the DMAEN bit in DMACR to 0. The end of the command sequence is detected by poling the BUSY flag in CSTR or through the pre-defined multiblock transfer end flag (BTI). An error in a command sequence (during data transmission) is detected through the CRC error flag (CRCERI) or data timeout error flag. When these flags are detected, set the CMDOFF bit in OPCR to 1, issue CMD12, and suspend the command sequence. Confirm there is no data busy condition. Detect the data busy state through the data busy end flag (DBSYI). Detect whether the current state is the data busy state through the DTBUSY bit in CSTR after the data transfer end (after DRPI detection). If it is still the data busy state, use the DBSYI flag to confirm the end of the data busy condition. Set the CMDOFF bit to 1 and end the command sequence. Set the CMDOFF bit to 1 when a CRC error (CRCERI) or command timeout error (CTERI) occurs in the command response reception. Set the CMDOFF bit to 1, clear the DMACR to H'00, and clear FIFO when a CRC error (CRCERI) or data timeout error (DTERI) occurs in the write data transmission.
* *
* * *
Note: Access from the DMAC to FIFO must be done in bytes or words.
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Section 31 Multimedia Card Interface (MMCIF)
Start of command sequence Clear FIFO
Set the number of transfer block size to TBCR
Execute CMD16 No
CMD16 normally ended? Yes
Set the number of block to TBNCR
Execute CMD 23
CMD 23 normally ended?
Yes
No
Set DMAC-related condition Set DMACR (MMCIF)
Execute CMD 25 (CMDR to CMDSTRT)
CRCERI interrupt detected? No
Yes
CRPI interrupt detected? Yes Read response register
No
CTERI interrupt detected?
No
Response status normally ended? Yes
1
No
Yes
2
Figure 31.20 (1) Example of Operational Flow for Auto-mode Pre-defined Multiblock Write Transfer
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Section 31 Multimedia Card Interface (MMCIF)
1
2
No DMA transfer ended? Yes Clear the DMACR to H'00
CRCERI or WRERI interrupt detected?
Yes
No DTERI interrupt detected? No No BTI interrupt detected? Yes No DTBUSY detected? Yes No DBSYI interrupt detected? Yes Set the CMDOFF to 1 Set the CMDOFF to 1 Execute CMD12 or Stop Tran Clear the DMACR to H'00 Clear FIFO Set the CMDOFF to 1 Yes
End of command sequence
Figure 31.20 (2) Example of Operational Flow for Auto-mode Pre-defined Multiblock Write Transfer
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Section 31 Multimedia Card Interface (MMCIF)
31.6
MMCIF Interrupt Sources
Table 31.8 lists the MMCIF interrupt sources. The interrupt sources are classified into four groups, and four interrupt vectors are assigned. Each interrupt source can be individually enabled by the enable bits in INTCR0 to INTCR2. Disabled interrupt sources do not set a flag. Table 31.8 MMCIF Interrupt Sources
Name ERR Interrupt source Write error CRC error* Data timeout error Command timeout error FSTAT FIFO empty FIFO full TRAN Data response Data transfer end Command response end Command output end Data busy end Block transfer end FRDY Note: * FIFO ready Card identification Interrupt flag WRERI CRCERI DTERI CTERI FEI FFI DRPI DTI CRPI CMDI DBSYI BTI FRDYI CDI
Excluding the CRC error in the R2 command response
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Section 31 Multimedia Card Interface (MMCIF)
31.7
Procedure to Apply the Card Detection Function
Figure 31.21 shows the operation flow to apply the card detection function.
Start
Set CHATR
Sets cycle for chattering elimination pulse Confirms if card has been inserted to connector If card is already inserted, go to MMCIF initialization. If card is not inserted, go to card identification wait. CDIE setting Peripheral clock 1 and internal divided clock are halted to stop unnecessary FF operation.
Read CDB Peripheral clock 1 and internal divided clock are in operation
Yes Card identified? No Set card insert wait
Peripheral clock 1 and internal divided clock halted
Card identification waiting state
Wait for card to be inserted to connector
Only card identification function is operating
Card identified (inserted)
Card is inserted to connector.
CDI interrupt Peripheral clock 1 and internal divided clock operating Read CDB
Interrupt generated Peripheral clock 1 and internal divided clock are operated to end card identification.
MMCIF initialization MMCIF initial setting Selects frequency
MMCIF registers are initialized to enter operation state Selects frequency of transfer clock between MMCIF and card Issues commands (CMD0 to CMD3) for identifying card to transfer data
Card identification mode Communication with card
Data transfer
Data transfer between MMCIF and card Note: Card identification clock is always operating
Figure 31.21 Operation Flow to Apply the Card Identification Function
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Section 32 PC Card Controller (PCC)
Section 32 PC Card Controller (PCC)
The PC card controller (PCC) controls the external buffer, interrupts, and exclusive ports of the PC card interface to be connected to this LSI. Using the PCC enables two slots of PC cards that conform to the PCMCIA Rev. 2.1/JEIDA Ver. 4.2 standard to be easily connected to this LSI.
32.1
Features
* As a PC card interface to be connected to physical area 6, an IC memory card interface and an I/O card interface are supported. * Outputs control signals for the external buffer (PCC_DRV). * Supports a preemptive operating system by switching attribute memory, common memory, and I/O space by using addresses. * Provides a segment bit (an address bit for the PC card) for common memory, enabling access to a 64-Mbyte space fully conforming to PCMCIA specifications. * Disables the PCC operation and supports only a bus interface of a PC card interface (by using the P0USE bit of PCC0GCR).
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Section 32 PC Card Controller (PCC)
Figure 32.1 shows a block diagram of the PC card controller.
PC card controller (PCC) PCC_WAIT PCC_RESET
Register selection
PCC_IOIS16(WP) PCC_RDY(IREQ) Area 6 PCC_BVD1(STSCHG) PCC_BVD2(SPKR)
Internal bus control signal Internal data bus
Bus interface
Battery dead
Area 6 internal interrrupt signal
register(0:3) and register control
PCC_CD1 PCC_CD2 PCC_VS1 PCC_VS2
Battery warning RDY/BSY signal change Card detection signal change STSCHG signal change IREQ signal Software interrupt
Area 6: An IC memory card interface and an I/O card interface are supported.
Figure 32.1 PC Card Controller Block Diagram 32.1.1 PCMCIA Support
This LSI supports an interface based on PCMCIA specifications for physical areas 6. Interfaces supported are the IC memory card interface and I/O card interface defined in the PCMCIA Rev. 2.1/JEIDA Ver. 4.2 standard. Both the IC memory card interface and I/O card interface are supported in area 6.
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Interrupt controller
PCC_REG
Area 6 PC card interface signal
PCC_DRV
Section 32 PC Card Controller (PCC)
Table 32.1 Features of the PCMCIA Interface
Item Access Data bus Memory type Common memory capacity Attribute memory capacity I/O space capacity Others Feature Random access 8/16 bits Masked ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM Maximum 64 Mbytes (Supports full PCMCIA specifications by using a segment bit (an address bit for the PC card)) Maximum 32 Mbytes Maximum 32 Mbytes Dynamic bus sizing for I/O bus width* The PCMCIA interface can be accessed from the addressconversion region and non-address-conversion region. * Dynamic bus sizing for the I/O bus width is supported only in little-endian mode.
Note:
This LSI can directly access 32- and 64-Mbyte physical areas in a 64-Mbyte memory space and an I/O space of the PC card (continuous 32/16-Mbyte area mode). This LSI provides a segment bit (an address bit for the PC card) in the general control register for area 6 to support a common memory space with full PCMCIA specifications (64 Mbytes). Continuous 32-Mbyte Area Mode: Setting 0 (initial value) in bit 3 (P0MMOD) of the general control register enables the continuous 32-Mbyte area mode. In this mode, the attribute memory space and I/O memory space are 32 Mbytes and the common memory space is 64 Mbytes. In the common memory space, set 1 in bit 2 (P0PA25) of the general control register to access an address of more than 32 Mbytes. By this operation, 1 is output to A25 pin, enabling an address space of more than 32 Mbytes to be accessed. When an address of 32 Mbytes or less is accessed, no setting is required (initial value: 0). This bit does not affect access to attribute memory space or I/O memory space. Figure 32.2 shows the relationship between the memory space of this LSI and the memory and I/O spaces of the PC card in the continuous 32-Mbyte area mode. Although memory space and I/O space are supported in area 6. In area 6, set 1 in bit 0 (P0REG) of the general control register to access the common memory space of the PC card, and set 0 in bit 0 to access the attribute memory space (initial value: 0). By this operation, the set value is output to PCC_REG pin, enabling any space to be accessed. When the I/O space is accessed in area 6, the output of PCC_REG pin is always 0 regardless of the value of bit 0 (P0REG). See the register descriptions in section 32.3, Register Descriptions for details of register settings.
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Section 32 PC Card Controller (PCC)
SH7763 memory space
PC card address space
General control register bit settings P0MMOD = 0 P0PA24 = x
Attribute memory
H'18000000
Area 6 Attribute memory/ common memory/ 32 Mbytes P0REG 32 Mbytes
P0PA25 = x P0REG = 0 (attribute) P0PA25 = 0 P0REG = 1 (common memory) P0PA25 = 0 P0REG = 1 (common memory) P0PA25 = x P0REG = x Pin PCCREG is always 0
H'1A000000
I/O space 32 Mbytes
P0PA25
Common memory Total 64 Mbytes
X: Don't cera
I/O space 32Mbytes
Figure 32.2 Continuous 32-Mbyte Area Mode Continuous 16-Mbyte Area Mode: Setting 1 in bit 3 (P0MMOD) of the general control register enables the continuous 16-Mbyte area mode. In this mode, the attribute memory space and I/O memory space are 16 Mbytes, and the common memory space is 64 Mbytes. In the common memory space, set the PC card address in bit 2 (P0PA25) and bit 1 (P0PA24) of the general control register to access an address of more than 16 Mbytes. By this operation, values are output to A25 and A24 pins, enabling an address space of more than 16 Mbytes to be accessed (initial value: 0 for P0PA25 and P0PA24). When an address of 16 Mbytes or less is accessed, no settings are required. This bit does not affect access to attribute memory space or I/O memory space. Figure 32.3 shows the relationship between the memory space of this LSI and the memory and I/O spaces of the PC card in the continuous 16-Mbyte area mode. Although memory space and I/O space are supported in area 6. The attribute memory space, common memory space, and I/O space of the PC card are provided as 16-Mbyte physical spaces in this mode. Therefore, this LSI automatically controls PCC_REG pin (the value of bit 0 (P0REG) in the general control register is ignored). In area 6, the output of PCC_REG pin is 0 when the attribute memory space or I/O space is accessed, and 1 when the common memory space is accessed. See the register descriptions in section 32.3, Register Descriptions for details of register settings.
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Section 32 PC Card Controller (PCC)
SH7763 memory space
PC card address space
General control register bit settings P0MMOD = 1 P0REG = x
Attribute memory 16 Mbytes P0PA25 = x, P0PA24 = x (Pin PCCREG is always 0)
H'18000000
Area 6 H'1A000000
Attribute memory 16 Mbytes Common memory 16 Mbytes I/O space 16 Mbytes
P0PA25 = 0, P0PA24 = 0 P0PA25 P0PA24 P0PA25 = 0, P0PA24 = 1
Common memory (Pin PCCREG is always 1)
P0PA25 = 1, P0PA24 = 0
Not used
Total 64 Mbytes P0PA25 = 1, P0PA24 = 1
I/O space 16 Mbytes (Pin PCCREG is always 0) P0PA25 = x, P0PA24 = x
x: Don't care
Figure 32.3 Continuous 16-Mbyte Area Mode (Area 6)
Rev. 1.00 Oct. 01, 2007 Page 1363 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
32.2
Input/Output Pins
PCC related external pins are listed below. Table 32.2 PCC Pin Configuration
Pin Name Hardware wait request pin Abbreviation PCC_WAIT I/O Input Input Description Hardware wait request signal Write protection signal from PC card when IC memory interface is connected Signal to indicate 16-bit I/O from PC card when I/O card interface is connected PCMCIA ready pin PCC_RDY Input Ready/busy signal form PC card when IC memory interface is connected Interrupt request signal from PC card when I/O card interface is connected PCMCIA BVD1 pin PCC_BVD1 Input Buttery voltage detect 1 signal from PC card when IC memory interface is connected Card status change signal from PC card when I/O card interface is connected PCMCIA BVD2 pin PCC_BVD2 Input Buttery voltage detect 2 signal from PC card when IC memory interface is connected Digital sound signal from PC card when I/O card interface is connected PCMCIA CD1 pin PCMCIA CD2 pin PCMCIA VS1 pin PCMCIA VS2 pin PCMCIA REG pin PCMCIA buffer control pin PCMCIA reset pin PCC_CD1 PCC_CD2 PCC_VS1 PCC_VS2 PCC_REG PCC_DRV PCC_RESET Input Input Input Input Card detect 1 signal from PC card Card detect 2 signal from PC card Voltage sense 1 signal from PC card Voltage sense 2 signal from PC card
PCMCIA 16-bit input/output PCC_IOIS16 pin
Output Area indicate signal for PC card Output Buffer control signal Output Reset signal for PC card
Rev. 1.00 Oct. 01, 2007 Page 1364 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
32.3
Register Descriptions
Table 32.3 shows the PCC register configuration. Table 32.4 shows the register state in each operating mode. Table 32.3 Register Configuration
Register Name Abbreviation R/W Area P4 Address* Area 7 Address* Access Size
Area 6 interface status register Area 6 general control register Area 6 card status change register Area 6 card status change interrupt enable register Note: *
PCC0ISR PCC0GCR PCC0CSCR
R R/W R/W
H'FFE9 8000 H'1FE9 8000 8 H'FFE9 8002 H'1FE9 8002 8 H'FFE9 8004 H'1FE9 8004 8 H'FFE9 8006 H'1FE9 8006 8
PCC0CSCIER R/W
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
Table 32.4 Register State in Each Operating Mode
Register Name Abbreviation Power-On Reset Manual Reset Sleep Standby
Area 6 interface status register Area 6 general control register Area 6 card status change register Area 6 card status change interrupt enable register
PCC0ISR PCC0GCR PCC0CSCR
Undefined Undefined Retained H'00 H'00 H'00 H'00 H'00 Retained Retained Retained
Retained Retained Retained Retained
PCC0CSCIER H'00
Rev. 1.00 Oct. 01, 2007 Page 1365 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
32.3.1
Area 6 Interface Status Register (PCC0ISR)
PCC0ISR is an 8-bit read-only register which is used to read the status of the PC card connected to area 6. The initial value of PCC0ISR depends on the PC card status.
Bit: 7
P0RDY/ IREQ
6
5
4
3
2
1
0
P0BVD1/ P0STSCHG
Initial value: R/W:
-
R
P0MWP P0VS2 P0VS1 P0CD2 P0CD1 P0BVD2/ P0SPKR
-
R
-
R
-
R
-
R
-
R
-
R
-
R
Bit 7
Bit Name P0RDY/ IREQ
Initial Value R/W Undefined* R
Description PCC0 Ready The value of RDY/BSC pin of the PC card connected to area 6 is read when the IC memory card interface is connected. The value of IREQ pin of the PC card connected to area 6 is read when the I/O card interface is connected. This bit cannot be written to. Indicates that the value of RDY/BSC pin is 0 when the PC card connected to area 6 is the IC memory card interface type. Indicates that the value of IREQ pin is 0 when the PC card connected to area 6 is the I/O card interface type. Indicates that the value of RDY/BSC pin is 1 when the PC card connected to area 6 is the IC memory card interface type. Indicates that the value of IREQ pin is 1 when the PC card connected to area 6 is the I/O card interface type.
Rev. 1.00 Oct. 01, 2007 Page 1366 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Bit 6
Bit Name P0MWP
Initial Value R/W Undefined* R
Description PCC0 Write Protect The value of WP pin of the PC card connected to area 6 is read when the IC memory card interface is connected. 0 is read when the I/O card interface is connected. This bit cannot be written to. Indicates that the value of WP pin is 0 when the PC card connected to area 6 uses the IC memory card interface. The value of bit 6 is always 0 when the PC card connected to area 6 is the I/O card interface type. Indicates that the value of WP pin is 1 when the PC card connected to area 6 is the IC memory card interface type.
5
P0VS2
Undefined*
R
PCC0 Voltage Sense 2 The value of VS2 pin of the PC card connected to area 6 is read. This bit cannot be written to. 0: The value of VS2 pin of the PC card connected to area 6 is 0 1: The value of VS2 pin of the PC card connected to area 6 is 1
4
P0VS1
Undefined*
R
PCC0 Voltage Sense 1 The value of VS1 pin of the PC card connected to area 6 is read. This bit cannot be written to. 0: The value of VS1 pin of the PC card connected to area 6 is 0 1: The value of VS1 pin of the PC card connected to area 6 is 1
3
P0CD2
Undefined*
R
PCC0 Card Detect 2 The value of CD2 pin of the PC card connected to area 6 is read. This bit cannot be written to. 0: The value of CD2 pin of the PC card connected to area 6 is 0 1: The value of CD2 pin of the PC card connected to area 6 is 1
Rev. 1.00 Oct. 01, 2007 Page 1367 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Bit 2
Bit Name P0CD1
Initial Value R/W Undefined* R
Description PCC0 Card Detect 1 The value of CD1 pin of the PC card connected to area 6 is read. This bit cannot be written to. 0: The value of CD1 pin of the PC card connected to area 6 is 0 1: The value of CD1 pin of the PC card connected to area 6 is 1
1 0
P0BVD2/ P0SPKR
Undefined*
R R
PCC0 Battery Voltage Detect 2 and 1 The values of BVD2 and BVD1 pins of the PC card connected to area 6 are read when the IC memory card interface is connected. The values of SPKR and STSCHG pins of the PC card connected to area 6 are read when the I/O card interface is connected. These bits cannot be written to. * IC memory interface 11: The battery voltage of the PC card connected to area 6 is normal (Battery Good) 01: The battery must be changed although data is guaranteed for the PC card connected to area 6 (Battery Warning) x0: The battery voltage is abnormal and data is not guaranteed for the PC card connected to area 6 (Battery Dead) * I/O card interface 0: The value of SPKR or STSCHG pin of the PC card connected to area 6 is 0 1: The value of SPKR or STSCHG pin of the PC card connected to area 6 is 1
P0BVD1/ Undefined* P0STSCHG
Note:
*
Differs according to the PC card status.
Rev. 1.00 Oct. 01, 2007 Page 1368 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
32.3.2
Area 6 General Control Register (PCC0GCR)
PCC0GCR is an 8-bit readable/writable register which controls the external buffer, resets, address A25 and A24 pins, and PCC_REG pin, and sets the PC card type for the PC card connected to area 6. PCC0GCR is initialized by a power-on reset but retains its value in a manual reset and in software standby mode.
Bit: 7 6 5 4 3 2 1 0
P0DRVE P0PCCR P0PCCT P0USE P0MMOD P0PA25 P0PA24 P0REG
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name P0DRVE
Initial Value R/W 0 R/W
Description PCC0 Buffer Control Controls the external buffer for the PC card connected to area 6. 0: High-level setting for control PCC_DRV pin of the external buffer for the PC card connected to area 6 1: Low-level setting for control PCC_DRV pin of the external buffer for the PC card connected to area 6
6
P0PCCR
0
R/W
PCC0 Card Reset Controls resets for the PC card connected to area 6. 0: Low-level setting for reset PCC_RESET pin for the PC card connected to area 6 1: High-level setting for reset PCC_RESET pin for the PC card connected to area 6
5
P0PCCT
0
R/W
PCC0 Card Type Specifies the type of the PC card connected to area 6. Cleared to 0 when the PC card is the IC memory card interface type; set to 1 when the PC card is the I/O card interface type. 0: The PC card connected to area 6 is handled as the IC memory card interface type 1: The PC card connected to area 6 is handled as the I/O card interface type
Rev. 1.00 Oct. 01, 2007 Page 1369 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Bit 4
Bit Name P0USE
Initial Value R/W 0 R/W
Description PCC0 Use/Not Use Specifies that the PC Card Controller to be worked or not worked. 0: PC Card Controller doesn't work 1: PC Card Controller works Note: When setting P0USE to 1, following settings are required. When P0USE is set to 1 and P0PCCT is set to 0, bits 21 and 20 (SA1 and SA0) in the CS6BWCR register of BSC should be set to 0. When P0USE and P0PCCT are set to 1, bits 21 and 20 (SA1 and SA0) in the CS6BWCR register of BSC should be set to 1. Before P0USE is set to 1, bits 15 to 12 (TYPE3 to TYPE0) in CS6BBCR of BSC should be set to 0101.
3
P0MMOD
0
R/W
PCC0 Mode Controls PCC_REG and A24 pins for the PC card connected to area 6. Specifies either A24 of the address to be accessed or bit P0REG for outputting to PCC_REG pin. When the common memory space is accessed, specifies either A24 of the address to be accessed or bit P0PA24 for outputting to A24 pin. By this operation, continuous 32 or 16 Mbytes can be selected for the address area of the common memory space of the PC card. 0: Bit P0REG is output to PCC_REG pin, and A24 of address to be accessed is output to A24 pin (continuous 32-Mbyte area mode) 1: A24 of address to be accessed is output to PCC_REG pin. When the common memory space is accessed, P0PA24 is output to A24 pin (continuous 16-Mbyte area mode)
Rev. 1.00 Oct. 01, 2007 Page 1370 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Bit 2
Bit Name P0PA25
Initial Value R/W 0 R/W
Description PC Card Address Controls A25 pin for the PC card connected to area 6. When the common memory space is accessed for the PC card connected to area 6, this bit is output to A25 pin. When the attribute memory space or I/O space is accessed, this bit is meaningless. 0: When the common memory space is accessed for the PC card connected to area 6, 0 is output to A25 pin 1: When the common memory space is accessed for the PC card connected to area 6, 1 is output to A25 pin
1
P0PA24
0
R/W
PC Card Address Controls A24 pin for the PC card connected to area 6. When bit P0MMOD is 1 and the common memory space is accessed for the PC card connected to area 6, this bit is output to A24 pin. When bit P0MMOD is 0 or the attribute memory space or I/O space is accessed, this bit is meaningless. 0: When bit P0MMOD is 1 and the common memory space is accessed for the PC card connected to area 6, 0 is output to A24 pin 1: When bit P0MMOD is 1 and the common memory space is accessed for the PC card connected to area 6, 1 is output to A24 pin
0
P0REG
0
R/W
PCC0REG Space Indication Controls PCC_REG pin for the PC card connected to area 6. When bit P0MMOD is 0, this bit is output to PCC_REG pin for the PC card connected to area 6. When bit P0MMOD is 1 or the I/O card interface is accessed, this bit is meaningless. 0: When bit P0MMOD is 0 and the PC card connected to area 6 is accessed, 0 is output to PCC_REG pin 1: When bit P0MMOD is 0 and the PC card connected to area 6 is accessed, 1 is output to PCC_REG pin
Rev. 1.00 Oct. 01, 2007 Page 1371 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
32.3.3
Area 6 Card Status Change Register (PCC0CSCR)
PCC0CSCR is an 8-bit readable/writable able register. PCC0CSCR bits are set to 1 by interrupt sources of the PC card connected to area 6 (only bit 7 can be set to 1 as required). PCC0CSCR is initialized by a power-on reset but retains its value in a manual reset and in software standby mode.
Bit: 7
P0SCDI
6
5
4
3
2
1
P0BW
0
P0BD
-
0 R
P0IREQ P0SC P0CDC P0RC
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name P0SCDI
Initial Value R/W 0 R/W
Description PCC0 Software Card Detect Change Interrupt A PCC0 software card detect change interrupt can be generated by writing 1 to this bit. When this bit is set to 1, the same interrupt as the PCC0 card detect change interrupt (bit 3 set status) occurs if bit 3 (PCC0 card detect change enable) in the area 6 card status change interrupt enable register (PCC0CSCIER) is set to 1. If bit 3 is cleared to 0, no interrupt occurs. 0: No software card detect change interrupt occurs for the PC card connected to area 6 1: Software card detect change interrupt occurs for the PC card connected to area 6
6
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1372 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Bit 5
Bit Name P0IREQ
Initial Value R/W 0 R/W
Description PCC0IREQ Request Indicates the interrupt request for the IREQ pin of the PC card when the PC card connected to area 6 is the I/O card interface type. The P0IREQ bit is set to 1 when an interrupt request signal in pulse mode or level mode is input to the IREQ pin. The mode is selected by bits 5 and 6 (PCC0IREQ interrupt enable bits) in the area 6 card status change interrupt enable register (PCC0CSCIER). This bit can be cleared to 0 only in pulse mode. Write 0 to bit 5 to clear the bit to 0. This bit is not changed if 1 is written. In level mode, bit 5 is a read-only bit which reflects the IREQ pin state (if the IREQ pin is low, 1 is read). This bit always reads 0 on the IC memory card interface. 0: No interrupt request on the IREQ pin of the PC card when the PC card is on the I/O card interface 1: An interrupt request on the IREQ pin of the PC card has occurred when the PC card is on the I/O card interface
4
P0SC
0
R/W
PCC0 Status Change Indicates a change in the value of the STSCHG pin of the PC card when the PC card connected to area 6 is the I/O card interface type. When the STSCHG pin is changed from 1 to 0, the SC bit is set to 1. When STSCHG pin is not changed, the P0SC bit remains at 0. Write 0 to bit 4 when this bit is set to 1 in order to clear this bit to 0. This bit is not changed if 1 is written. This bit always reads 0 on the IC memory card interface. 0: STSCHG pin of the PC card is not changed when the PC card is on the I/O card interface 1: STSCHG pin of the PC card is changed from 1 to 0 when the PC card is on the I/O card interface
Rev. 1.00 Oct. 01, 2007 Page 1373 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Bit 3
Bit Name P0CDC
Initial Value R/W 0 R/W
Description PCC0 Card Detect Change Indicates a change in the value of the CD1 and CD2 pins in the PC card connected to area 6. When the CD1 and CD2 values are changed, the P0CDC bit is set to 1. When the values are not changed, the P0CDC bit remains at 0. Write 0 to bit 3 in order to clear this bit to 0. This bit is not changed if 1 is written. 0: CD1 and CD2 pins in the PC card are not changed 1: CD1 and CD2 pins in the PC card are changed
2
P0RC
0
R/W
PCC0 Ready Change Indicates a change in the value of the RDY/BSY pin of the PC card when the PC card connected to area 6 is the IC memory card interface type. When the RDY/BSY pin is changed from 0 to 1, the P0RC bit is set to 1. When the RDY/BSY pin is not changed, the P0RC bit remains at 0. Write 0 to bit 2 in order to clear this bit to 0. This bit is not changed if 1 is written. This bit always reads 0 on the I/O card interface. 0: RDY/BSY pin in the PC card is not changed when the PC card is on the IC memory card interface 1: RDY/BSY pin in the PC card is changed from 0 to 1 when the PC card is on the IC memory card interface
Rev. 1.00 Oct. 01, 2007 Page 1374 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Bit 1
Bit Name P0BW
Initial Value R/W 0 R/W
Description PCC0 Battery Warning Indicates whether the BVD2 and BVD1 pins of the PC card are in the state in which "the battery must be changed although the data is guaranteed" when the PC card connected to area 6 is on the IC memory card interface. When the BVD2 and BVD1 pins are 0 and 1, respectively, the P0BW bit is set to 1; in other cases, the P0BW bit remains at 0. This bit is updated when the BVD2 and BVD1 pins are changed. Write 0 to bit 1 in order to clear this bit to 0. This bit is not changed if 1 is written. This bit always reads 0 on the I/O card interface. 0: BVD2 and BVD1 of the PC card are not in the battery warning state when the PC card is in the IC memory card interface 1: BVD2 and BVD1 of the PC card are in the battery warning state and "the battery must be changed although the data is guaranteed" when the PC card is on the IC memory card interface
0
P0BD
0
R/W
PCC0 Battery Dead Indicates whether the BVD2 and BVD1 pins of the PC card are in the state in which "the battery must be changed since the data is not guaranteed" when the PC card connected to area 6 is on the IC memory card interface. When the BVD2 and BVD1 pins are 1 and 0 or 0 and 0, the P0BD bit is set to 1; in other cases, the P0BD bit remains at 0. This bit is updated when the BVD2 and BVD1 pins are changed. Write 0 to bit 0 in order to clear this bit to 0. This bit is not changed if 1 is written. This bit always reads 0 on the I/O card interface. 0: BVD2 and BVD1 of the PC card are not in the state in which "the battery must be changed since the data is not guaranteed" when the PC card is on the IC memory card interface 1: BVD2 and BVD1 of the PC card are in the state in which "the battery must be changed since the data is not guaranteed" when the PC card is on the IC memory card interface
Rev. 1.00 Oct. 01, 2007 Page 1375 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
32.3.4
Area 6 Card Status Change Interrupt Enable Register (PCC0CSCIER)
The area 6 card status change interrupt enable register (PCC0CSCIER) is an 8-bit readable/writable register. PCC0CSCIER enables or disables interrupt requests for interrupt sources for the PC card connected to area 6. When a PCC0CSCIER is set to 1, the corresponding interrupt is enabled, and when the bit is cleared to 0, the interrupt is disabled. PCC0CSCIER is initialized by a power-on reset but retains its value in a manual reset and in software standby mode.
Bit: 7
P0CRE
6
5
4
3
2
1
0
IREQE[1:0]
P0SCE P0CDE P0RE P0BWE P0BDE
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name P0CRE
Initial Value R/W 0 R/W
Description PCC0 Card Reset Enable When this bit is set to 1, and when the CD1 and CD2 pins detect that a PC card is connected to area 6, the area 6 general control register (PCC0GCR) is initialized. 0: The area 6 general control register (PCC0GCR) is not initialized even if a PC card is detected in area 6 1: The area 6 general control register (PCC0GCR) is initialized when a PC card is detected connected to area 6
Rev. 1.00 Oct. 01, 2007 Page 1376 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Bit 6, 5
Bit Name
Initial Value R/W R/W
Description PCC0IREQ Request Enable These bits enable or disable IREQ pin interrupt requests and select the interrupt mode when the PC card connected to area 6 is the I/O card interface type. Note that bit 5 (P0IREQ) in the area 6 card status change register (PCC0CSCR) is cleared if the values in bits 6 and 5 in this register are changed. These bits have no meaning on the IC memory card interface. 00: IREQ requests are not accepted for the PC card connected to area 6. Bit 5 in the status change register (PCC0CSCR) functions as a read-only bit that indicates the inverse of the IREQ pin signal. 01: The level-mode IREQ interrupt request signal is accepted for the PC card connected to area 6. In level mode, an interrupt occurs when level 0 of the signal input from the IREQ pin is detected. 10: The pulse-mode IREQ interrupt request signal is accepted for the PC card connected to area 6. In pulse mode, an interrupt occurs when a falling edge from 1 to 0 of the signal input from the IREQ pin is detected. 11: The pulse-mode IREQ interrupt request signal is accepted for the PC card connected to area 6. In pulse mode, an interrupt occurs when a rising edge from 0 to 1 of the signal input from the IREQ pin is detected.
IREQE[1:0] 00
Rev. 1.00 Oct. 01, 2007 Page 1377 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Bit 4
Bit Name P0SCE
Initial Value R/W 0 R/W
Description PCC0 Status Change Enable When the PC card connected to area 6 is on the I/O card interface, bit 4 enables or disables the interrupt request when the value of the BVD1 pin (STSCHG pin) is changed. This bit has no meaning in the IC memory card interface. 0: No interrupt occurs for the PC card connected to area 6 regardless of the value of the BVD1 pin (STSCHG pin) 1: An interrupt occurs for the PC card connected to area 6 when the value of the BVD1 pin (STSCHG pin) is changed from 1 to 0
3
P0CDE
0
R/W
PCC0 Card Detect Change Enable Bit 3 enables or disables the interrupt request when the values of the CD1 and CD2 pins are changed. 0: No interrupt occurs for the PC card connected to area 6 regardless of the values of the CD1 and CD2 pins 1: An interrupt occurs for the PC card connected to area 6 when the values of the CD1 and CD2 pins are changed
2
P0RE
0
R/W
PCC0 Ready Change Enable When the PC card connected to area 6 is on the IC memory card interface, bit 2 enables or disables the interrupt request when the value of the RDY/BSY pin is changed. This bit has no meaning on the I/O card interface. 0: No interrupt occurs for the PC card connected to area 6 regardless of the value of the RDY/BSY pin 1: An interrupt occurs for the PC card connected to area 6 when the value of the RDY/BSY pin is changed from 0 to 1
Rev. 1.00 Oct. 01, 2007 Page 1378 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Bit 1
Bit Name P0BWE
Initial Value R/W 0 R/W
Description PCC0 Battery Warning Enable When the PC card connected to area 6 is on the IC memory card interface, bit 1 enables or disables the interrupt request when the BVD2 and BVD1 pins are in the state in which "the battery must be changed although the data is guaranteed". This bit has no meaning on the I/O card interface. 0: No interrupt occurs when the BVD2 and BVD1 pins are in the state in which "the battery must be changed although the data is guaranteed" 1: An interrupt occurs when the BVD2 and BVD1 pins are in the state in which "the battery must be changed although the data is guaranteed"
0
P0BDE
0
R/W
PCC0 Battery Dead Enable When the PC card connected to area 6 is on the IC memory card interface, bit 0 enables or disables the interrupt request when the BVD2 and BVD1 pins are in the state in which "the battery must be changed since the data is not guaranteed". This bit has no meaning on the I/O card interface. 0: No interrupt occurs when the BVD2 and BVD1 pins are in the state in which "the battery must be changed since the data is not guaranteed" 1: An interrupt occurs when the BVD2 and BVD1 pins are in the state in which "the battery must be changed since the data is not guaranteed"
Rev. 1.00 Oct. 01, 2007 Page 1379 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
32.4
32.4.1
Operation
PC card Connection Specification (Interface Diagram, Pin Correspondence)
A25 to A0 PCC0DRV D7 to D0
G DIR G
A25 to A0
D15 to D0 RDWR
D15 to D0
CE1B CE2B RD WE IORD IOWR PCC_RESET PCC_REG
G
CE1 CE2 OE WE/PGM (IORD) (IOWR) RESET REG
PCC_WAIT PCC_IOIS16 PCC_RDY PCC_BVD1 PCC_BVD2
G
WAIT WP(IOIS16) RDY/BSY(IREQ) BVD1(STSCHG) BVD2(SPKR)
PCC_CD1/CD2 PCC_VS1/VS2
CD1 CD2 VS1 VS2
Figure 32.4 SH7763 Interface
Rev. 1.00 Oct. 01, 2007 Page 1380 of 1956 REJ09B0256-0100
Area 6 PC card (memory or I/O)
SH7763
D15 to D8 G DIR
Section 32 PC Card Controller (PCC)
Table 32.5 PCMCIA Support Interface
IC Memory Card Interface Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Signal Name GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE/PGM RDY/BSY VCC VPP1 I/O I/O I/O I/O I/O I I I I I I I I I O I/O Function Ground Data Data Data Data Data Card enable Address Output enable Address Address Address Address Address Write enable Ready/busy Power supply Programming power supply I/O Card Interface Signal Name GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE/PGM IREQ VCC VPP1 I/O I/O I/O I/O I/O I I I I I I I I I O I/O Function Ground Data Data Data Data Data Card enable Address Output enable Address Address Address Address Address Write enable Interrupt request Power supply Programming and peripheral power supply I I I I I I I Address Address Address Address Address Address Address This LSI Corresponding Pin -- D3 D4 D5 D6 D7 CE1B A10 RD A11 A9 A8 A13 A14 WE PCC_RDY -- --
19 20 21 22 23 24 25
A16 A15 A12 A7 A6 A5 A4
I I I I I I I
Address Address Address Address Address Address Address
A16 A15 A12 A7 A6 A5 A4
A16 A15 A12 A7 A6 A5 A4
Rev. 1.00 Oct. 01, 2007 Page 1381 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
IC Memory Card Interface Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Signal Name A3 A2 A1 A0 D0 D1 D2 WP GND GND CD1 D11 D12 D13 D14 D15 CE2 VS1 RFU RFU A17 A18 A19 A20 A21 VCC I I I I I O I/O I/O I/O I/O I/O I O I/O I I I I I/O I/O I/O O Function Address Address Address Address Data Data Data Write protect Ground Ground Card detection Data Data Data Data Data Card enable Voltage sense Reserved Reserved Address Address Address Address Address Power supply
I/O Card Interface Signal Name A3 A2 A1 A0 D0 D1 D2 IOIS16 GND GND CD1 D11 D12 D13 D14 D15 CE2 VS1 IORD IOWR A17 A18 A19 A20 A21 VCC O I/O I/O I/O I/O I/O I O I I I I I I I I/O I I I I I/O I/O I/O O Function Address Address Address Address Data Data Data 16-bit I/O port Ground Ground Card detection Data Data Data Data Data Card enable Voltage sense I/O read I/O write Address Address Address Address Address Power supply
This LSI Corresponding Pin A3 A2 A1 A0 D0 D1 D2 PCC_IOIS16 -- -- PCC_CD1 D11 D12 D13 D14 D15 CE2B PCC_VS1 IORD IOWR A17 A18 A19 A20 A21 --
Rev. 1.00 Oct. 01, 2007 Page 1382 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
IC Memory Card Interface Pin 52 Signal Name VPP2 I/O Function Programming power supply
I/O Card Interface Signal Name VPP2 I/O Function Programming and peripheral power supply I I I I O I O O I Address Address Address Address Voltage sense Reset Wait request Input acknowledge Attribute memory space select Digital sound signal Card status change
This LSI Corresponding Pin --
53 54 55 56 57 58 59 60 61
A22 A23 A24 A25 VS2 RESET WAIT RFU REG
I I I I O I O
Address Address Address Address Voltage sense Reset Wait request Reserved
A22 A23 A24 A25 VS2 RESET WAIT INPACK REG
A22 A23 A24 A25 PCC_VS2 PCC_RESET PCC_WAIT -- PCC_REG
I
Attribute memory space select Battery voltage detection Battery voltage detection Data Data Data Card detection Ground
62
BVD2
O
SPKR
O
PCC_BVD2
63
BVD1
O
STSCHG
O
PCC_BVD1
64 65 66 67 68
D8 D9 D10 CD2 GND
I/O I/O I/O O
D8 D9 D10 CD2 GND
I/O I/O I/O O
Data Data Data Card detection Ground
D8 D9 D10 PCC_CD2 --
Rev. 1.00 Oct. 01, 2007 Page 1383 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
32.4.2 (1)
PC Card Interface Timing
Memory Card Interface Timing
Tpcm1
CLKOUT
"0"
Tpcm2
PCC_DRV
A25 to A0
CExx
RDWR
PCC_REG
RD (read)
D15 to D0 (write)
WE (read) D15 to D0 (write) "0" PCC_RESET
Figure 32.5 PCMCIA Memory Card Interface Basic Timing
Rev. 1.00 Oct. 01, 2007 Page 1384 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Tpcm0 CLKOUT
Tpcm0w
Tpcm1
Tpcm1w
Tpcm1w
Tpcm2
Tpcm2w
PCC_DRV
"0"
A25 to A0
CExx
RDWR
PCC_REG
RD (read)
D15 to D0 (write) WE (read) D15 to D0 (write)
PCC_WAIT "0" PCC_RESET
Figure 32.6 PCMCIA Memory Card Interface Wait Timing
Rev. 1.00 Oct. 01, 2007 Page 1385 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
(2)
I/O Card Interface Timing
Tpcm1
CLKOUT
"0"
Tpcm2
PCC_DRV
A25 to A0
CExx
RDWR
PCC_REG IORD (read) D15 to D0 (write) IOWR (read) D15 to D0 (write) "0" PCC_RESET
Figure 32.7 PCMCIA I/O Card Interface Basic Timing
Rev. 1.00 Oct. 01, 2007 Page 1386 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Tpci0 CLKOUT
Tpci0w
Tpci1
Tpci1w
Tpci1w
Tpci2
Tpci2w
PCC_DRV
"0"
A25 to A0
CExx
RDWR
PCC_REG
IORD (read)
D15 to D0 (write) IOWR (read) D15 to D0 (write)
PCC_WAIT
PCC_IOIS16 "0" PCC_RESET
Figure 32.8 PCMCIA I/O Card Interface Wait Timing
Rev. 1.00 Oct. 01, 2007 Page 1387 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
Tpci0 CLKOUT
Tpci1
Tpci1w
Tpci2
Tpci1
Tpci1w
Tpci2
Tpci2w
PCC_DRV
"0"
A25 to A1
A0
CExx
RDWR
PCC_REG IORD (read)
D15 to D0 (write) IOWR (read) D15 to D0 (read)
PCC0WAIT
IOIS16 "0" PCC_RESET
Figure 32.9 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface
Rev. 1.00 Oct. 01, 2007 Page 1388 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
32.5
(1)
Usage Notes
External Bus Frequency Limit when Using PC Card
According to the PC card standard, the attribute memory access time is specified as 600 ns (3.3 V)/300 ns (5 V). Therefore, when this LSI accesses attribute memory, the bus cycle must be coordinated with the PC card interface timing. In this LSI, the timing can be adjusted by setting the TED, TEH, and PCW values in the CS6BWCR register, allowing a PC card to be used within the above frequency ranges. The common memory access time and I/O access time (based on the IORD and IOWR signals) are also similarly specified (see table below), and a PC card must be used within the above ranges in order to satisfy all these specifications.
PC Card Space Attribute memory Common memory I/O space (-IORD/-IOWR pulse width) Access Time (5 V Operation) 300 ns 250 ns 165 ns Access Time (3.3 V Operation) 600 ns 600 ns 165 ns
(2)
Pin Function Control and Card Type Switching
When setting pin function controller pin functions to dedicated PC card use ("other function"), the disabled state should first be set in the card status change interrupt enable register (PCC0CSCIER). Also, the card status change register (PCC0CSCR) must be cleared after the setting has been made. However, this restriction does not apply to the card detection pins (CD1, CD2). When changing the card type bit (P0PCCT) in the area 6 general control register (PCC0GCR), the disabled state should first be set in the card status change interrupt enable register (PCC0CSCIER). Also, the card status change register (PCC0CSCR) must be cleared after the setting has been made. Reason: When PC card controller settings are modified, the functions of PC card pins that generate various interrupts change, with the result that unnecessary interrupts may be generated.
Rev. 1.00 Oct. 01, 2007 Page 1389 of 1956 REJ09B0256-0100
Section 32 PC Card Controller (PCC)
(3)
Setting Procedure when Using PC Card Controller
The following steps should be followed when using a card controller: 1. 2. 3. 4. Set bit 12 (MAP) in the common control register (CMNCR) of bus state controller to 1. Set bits 15 to 12 (TYPE3 to TYPE0) in the bus control register for CS6B (CS6BBCR) of the bus state controller to B0101. Set bit 4 (P0USE) in the area 6 general control register in the PC card controller to 1. Set the pin function controller to custom PC card pin functions ("other functions").
Rev. 1.00 Oct. 01, 2007 Page 1390 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Section 33 Audio Codec Interface (HAC)
The HAC, the audio codec digital controller interface, supports bidirectional data transfer compliant with Audio Codec 97 (AC'97) Version 2.1. The HAC provides serial transmission to /reception from the AC97 codec. Each channel of the HAC can be connected to a single audio codec device. The HAC carries out data extraction from/insertion into audio frames. For data slots within both receive and transmit frames, the PIO transfer by the CPU or the DMA transfer by the DMAC can be used.
33.1
Features
The HAC has the following features: * * * * * * * * Supports Digital interface to a single AC'97 version 2.1 Audio Codec PIO transfer of status slots 1 and 2 in Rx frames PIO transfer of command slots 1 and 2 in Tx frames PIO transfer of data slots 3 and 4 in Rx frames PIO transfer of data slots 3 and 4 in Tx frames Selectable 16-bit or 20-bit DMA transfer of data slots 3 and 4 in Rx frames Selectable 16-bit or 20-bit DMA transfer of data slots 3 and 4 in Tx frames Accommodates various sampling rates by qualifying slot data with tag bits and monitoring the Tx frame request bits of Rx frames * Generates data ready, data request, overrun and underrun interrupts * Supports cold reset, warm reset, and power-down mode
Rev. 1.00 Oct. 01, 2007 Page 1391 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Figure 33.1 shows a block diagram of the HAC.
HAC receiver
Internal bus interface (Reception) Data[19:0] Data[19:0] Data[19:0] Data[19:0]
CSAR RX buffer CSDR RX buffer PCML RX buffer
PCMR RX buffer
HAC_ SD_IN (0/1)
Shift register for slot 1
Shift register for slot 2
Shift register for slot 3
Shift register for slot 4
Data[31:0]
Control signal
Slot3, slot4 request signal
DMA control
DMA request
Bit control signal
HAC transmitter Internal bus interface (Transmission)
Data[19:0] Data[19:0] Data[19:0]
Data[19:0]
Interrupt request
HAC_ SD_OUT (0/1)
Shift register for slot 1
Shift register for slot 2
Shift register for slot 3
Shift register for slot 4
CSAR TX buffer
CSDR TX buffer
PCML TX buffer
PCMR TX buffer
Data[31:0]
HAC_SYNC (0/1) HAC_RES Control signal
DMA control
DMA request
Interrupt request
Figure 33.1 Block Diagram
33.2
Input/Output Pins
Table 33.1 describes the HAC pin configuration. Table 33.1 Pin Configuration
Pin Name HAC_BITCLK HAC_SD_IN HAC_SD_OUT HAC_SYNC HAC_RES I/O Input Input Output Output Output Function HAC serial data clock HAC serial data incoming to Rx frame HAC serial data outgoing from Tx frame HAC frame sync HAC reset (negative logic signal)
Rev. 1.00 Oct. 01, 2007 Page 1392 of 1956 REJ09B0256-0100
Peripheral bus
HAC_BITCLK
Section 33 Audio Codec Interface (HAC)
33.3
Register Descriptions
Table 33.2 shows the HAC register configuration. Table 33.3 shows the register state in each operating mode. Table 33.2 Register Configuration
Register Name Control and status register Command/status address register Command/status data register PCM left channel register PCM right channel register TX interrupt enable register TX status register RX interrupt enable register RX status register HAC control register Abbrev. HACCR HACCSAR HACCSDR HACPCML HACPCMR HACTIER HACTSR HACRIER HACRSR HACACR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P4 Address* H'FFEB 0008 H'FFEB 0020 H'FFEB 0024 H'FFEB 0028 H'FFEB 002C H'FFEB 0050 H'FFEB 0054 H'FFEB 0058 H'FFEB 005C H'FFEB 0060 Area 7 Address* H'1FEB 0008 H'1FEB 0020 H'1FEB 0024 H'1FEB 0028 H'1FEB 002C H'1FEB 0050 H'1FEB 0054 H'1FEB 0058 H'1FEB 005C H'1FEB 0060 Size 32 32 32 32 32 32 32 32 32 32
Note:
*
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
Table 33.3 Register State in Each Operating Mode
Register Name Control and status register Command/status address register Command/status data register PCM left channel register PCM right channel register TX interrupt enable register TX status register RX interrupt enable register RX status register HAC control register Abbrev. HACCR HACCSAR HACCSDR HACPCML HACPCMR HACTIER HACTSR HACRIER HACRSR HACACR Power-on Reset H'0000 0200 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'F000 0000 H'0000 0000 H'0000 0000 H'8400 0000 Manual Reset H'0000 0200 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'F000 0000 H'0000 0000 H'0000 0000 H'8400 0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 1393 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.3.1
Control and Status Register (HACCR)
HACCR is a 32-bit read/write register for controlling input/output and monitoring the interface status.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
15
CR 0 R
14
-
0 R
-
13
0 R
-
0 R
12
11
0 W
10
0 W
9
8
7
6
5
ST 0 W
4
3
2
1
0
CDRT WMRT
-
1 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
Bit 31 to 16 15
Bit Name CR
Initial Value All 0 0
R/W R R
Description Reserved Always 0 for read and write. Codec Ready 0: The HAC-connected codec is not ready. 1: The HAC-connected codec is ready.
14 to 12 11
CDRT
All 0 0
R W
Reserved Always read as 0. Write prohibited. HAC Cold Reset Use a cold reset only after power-on, or only to exit from the power-down mode by the power-down command. [Write] 0: Always write 0 to this bit before writing 1 again. 1: Performs a cold reset on the HAC. [Read] Always read as 0.
Rev. 1.00 Oct. 01, 2007 Page 1394 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Bit 10
Bit Name WMRT
Initial Value 0
R/W W
Description HAC Warm Reset Use a warm reset only after power-up, or only to exit from the power-down mode by the power-down command. [Write] 0: Always write 0 to this bit before writing 1 again. 1: Performs a warm reset on the HAC. [Read] Always read as 0.
9 8 to 6 5
ST
1 All 0 0
R R W
Reserved Always 1 for read and write. Reserved Always 0 for read and write. Start Transfer [Write] 1: Starts data transmission/reception. 0: Stops data transmission/reception at the end of the current frame. Do not take this action to terminate transmission/reception in normal operation. [Read access] Always read as 0.
4 to 0
All 0
R
Reserved Always 0 for read and write.
To place the off-chip codec device into the power-down mode, write 1 to bit 12 of the register index 26 in the off-chip codec via the HAC. When entering the power-down mode, the off-chip codec stops HAC_BITCLK and suspends the normal operation. The off-chip codec acts in the same manner at power-on. To resume the normal operation, perform a cold reset or a warm reset on the off-chip codec.
Rev. 1.00 Oct. 01, 2007 Page 1395 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.3.2
Command/Status Address Register (HACCSAR)
HACCSAR is a 32-bit read/write register that specifies the address of the codec register to be read /written. When requesting a write to/read from a codec register, write the command register address to HACCSAR. Then the HAC transmits this register address to the codec via slot 1. After the codec has responded to a read request (HACRSR.STARY = 1), the status address received via slot 1 can be read out from HACCSAR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 RW 0 R/W 3 18 17 CA/SA[6:4] 0 R/W 2 0 R/W 1 0 R/W 0 16
-
Initial value: R/W: Bit: 0 R 15
-
0 R 14
-
0 R 13
-
0 R 12
-
0 R 11
-
0 R 10
-
0 R 9
-
0 R 8
-
0 R 7
-
0 R 6
-
0 R 5
-
0 R 4
CA/SA[3:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R
SLREQ[3:12] 0 R 0 R 0 R 0 R 0 R 0 R
-
0 R
-
0 R
Bit 31 to 20 19
Bit Name RW
Initial Value All 0 0
R/W R R/W
Description Reserved Always 0 for read and write. Codec Read/Write Command 0: Notifies the off-chip codec device of a write access to the register specified in the address field (CA6/SA6 to CA0/SA0). Write the data to HACCSDR in advance. When HACACR.TX12_ATOMIC is 1, the HAC transmits HACCSAR and HACCSDR as a pair in the same Tx frame. When HACACR.TX12_ATOMIC is 0, transmission of HACCSAR and HACCSDR in the same Tx frame is not guaranteed. 1: Notifies the off-chip codec device of a read access to the register specified in the address field (CA6/SA6 to CA0/SA0).
Rev. 1.00 Oct. 01, 2007 Page 1396 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Bit 18 to 12
Bit Name
Initial Value
R/W R/W
Description Codec Control Register Addresses 6 to 0 /Codec Status Register Addresses 6 to 0 [Write] Specify the address of the codec register to be written. [Read] Indicate the status address received via slot 1, corresponding to the codec register whose data has been returned in HACCSDR.
CA/SA[6:0] All 0
11 to 2
SLREQ [3:12]
All 0
R
Slot Requests 3 to 12 Valid only in the Rx frame. Indicate whether the codec is requesting slot data in the next Tx frame. Automatically set by hardware, and correspond to bits 11 to 2 of slot 1 in the Rx frame. 0: Slot data is requested. 1: Slot data is not requested.
1, 0
All 0
R
Reserved Always 0 for read and write.
Rev. 1.00 Oct. 01, 2007 Page 1397 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.3.3
Command/Status Data Register (HACCSDR)
HACCSDR is a 32-bit read/write data register used for accessing the codec register. Write the command data to HACCSDR. The HAC then transmits the data to the codec via slot 2. After the codec has responded to a read request (HACRSR.STDRY = 1), the status data received via slot 2 can be read out from HACCSDR. In both read and write, HACCSAR stores the related codec register address.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
Initial value: R/W: Bit:
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R 0 R/W
CD/SD[15:12] 0 R/W 0 R/W 0 R/W 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CD/SD[11:0]
-
0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R
-
0 R
-
0 R
-
0 R
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 20 19 to 4
Bit Name
Initial Value All 0
R/W R R/W
Description Reserved Always 0 for read and write. Command Data 15 to 0/Status Data 15 to 0 Write data to these bits and then write the codec register address in HACCSAR. The HAC then transmits the data to the codec. Read these bits to get the contents of the codec register indicated by HACCSAR. Reserved Always 0 for read and write.
CD/SD[15:0] All 0
3 to 0
All 0
R
Rev. 1.00 Oct. 01, 2007 Page 1398 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.3.4
PCM Left Channel Register (HACPCML)
HACPCML is a 32-bit read/write data register used for accessing the left channel of the codec in digital audio recording or stream playback. To transmit the PCM playback left channel data to the codec, write the data to HACPCML. To receive the PCM record left channel data from the codec, read HACPCML. The data is left justified to accommodate a codec with ADC/DAC resolution of 20 bits or less.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
Initial value: R/W: Bit: 0 R 15
-
0 R 14
-
0 R 13
-
0 R 12
-
0 R 11
-
0 R 10
-
0 R 9
-
0 R 8
-
0 R 7
-
0 R 6
-
0 R 5
-
0 R 4 0 R/W 3
D[19:16] 0 R/W 2 0 R/W 1 0 R/W 0
D[15:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 31 to 20 19 to 0
Bit Name D[19: 0]
Initial Value All 0 All 0
R/W R R/W
Description Reserved Always 0 for read and write. Data 19 to 0 Write the PCM playback left channel data to these bits. The HAC then transmits the data to the codec on an on-demand basis. Read these bits to get the PCM record left channel data from the codec.
In 16-bit packed DMA mode, HACPCML is defined as follows:
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R/W 15 0 R/W 30 0 R/W 14 0 R/W 29 0 R/W 13 0 R/W 28 0 R/W 12 0 R/W 27 0 R/W 11 0 R/W 26 0 R/W 10 0 R/W 25 0 R/W 9 0 R/W 24 0 R/W 8 0 R/W 23 0 R/W 7 0 R/W 22 0 R/W 6 0 R/W 21 0 R/W 5 0 R/W 20 0 R/W 4 0 R/W 19 0 R/W 3 0 R/W 18 0 R/W 2 0 R/W 17 0 R/W 1 0 R/W 16 0 R/W 0 0 R/W
LD[15:0]
RD[15:0]
Rev. 1.00 Oct. 01, 2007 Page 1399 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Bit 31 to 16
Bit Name LD[15:0]
Initial Value All 0
R/W R/W
Description Left Data 15 to 0 Write the PCM playback left channel data to these bits. The HAC then transmits the data to the codec on an on-demand basis. Read these bits to get the PCM record left channel data from the codec.
15 to 0
RD[15:0]
All 0
R/W
Right Data 15 to 0 Write the PCM playback right channel data to these bits. The HAC then transmits the data to the codec on an on-demand basis. Read these bits to get the PCM record right channel data from the codec.
Rev. 1.00 Oct. 01, 2007 Page 1400 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.3.5
PCM Right Channel Register (HACPCMR)
HACPCMR is a 32-bit read/write register used for accessing the right channel of the codec in digital audio recording or stream playback. To transmit the PCM playback right channel data to the codec, write the data to HACPCMR. To receive the PCM record right channel data from the codec, read HACPCMR. The data is left justified to accommodate a codec with ADC/DAC resolution of 20-bit or less.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R 0 R/W
D[19:16] 0 R/W 0 R/W 0 R/W 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D[15:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 31 to 20 19 to 0
Bit Name D[19:0]
Initial Value All 0 All 0
R/W R R/W
Description Reserved Always 0 for read and write. Data 19 to 0 Write the PCM playback right channel data to these bits. The HAC then transmits the data to the codec on an on-demand basis. Read these bits to get the PCM record right channel data from the codec.
Rev. 1.00 Oct. 01, 2007 Page 1401 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.3.6
TX Interrupt Enable Register (HACTIER)
HACTIER is a 32-bit read/write register that enables or disables HAC TX interrupts.
Bit:
31
30
29
PLTF RQIE
28
PRTF RQIE
27
26
25
24
23
22
21
20
19
18
17
16
-
Initial value: R/W: Bit: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R 0
0 R/W
0 R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
Initial value: R/W: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
PLT PRT FUNIE FUNIE
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
0 R/W
0 R/W
Bit 31, 30 29
Bit Name
Initial Value All 0
R/W R R/W
Description Reserved Always 0 for read and write. PCML TX Request Interrupt Enable 0: Disables PCML TX request interrupts 1: Enables PCML TX request interrupts
PLTFRQIE 0
28
PRTFRQIE 0
R/W
PCMR TX Request Interrupt Enable 0: Disables PCMR TX request interrupts 1: Enables PCMR TX request interrupts
27 to 10 9
All 0
R R/W
Reserved Always 0 for read and write. PCML TX Underrun Interrupt Enable 0: Disables PCML TX underrun interrupts 1: Enables PCML TX underrun interrupts
PLTFUNIE 0
8
PRTFUNIE 0
R/W
PCMR TX Underrun Interrupt Enable 0: Disables PCMR TX underrun interrupts 1: Enables PCMR TX underrun interrupts
7 to 0
All 0
R
Reserved Always 0 for read and write.
Rev. 1.00 Oct. 01, 2007 Page 1402 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.3.7
TX Status Register (HACTSR)
HACTSR is a 32-bit read/write register that indicates the status of the HAC TX controller. Writing 0 to the bit will initialize it.
Bit:
31 30 29 CMD CMD PLT AMT DMT FRQ
1 R/W 1 R/W 1 R/W
28 PRT FRQ
1 R/W
27
-
0 R
26
-
0 R
25
-
0 R
24
-
0 R
23
-
0 R
22
-
21
-
20
-
19
-
0 R
18
-
17
-
16
-
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R 0
15
14
13
12
11
10
-
Initial value: R/W: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
9 PLT FUN 0 R/W
8 PRT FUN 0 R/W
7
6
5
4
3
2
1
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
Bit 31
Bit Name CMDAMT
Initial Value 1
R/W R/W*
2
Description Command Address Empty 0: CSAR Tx buffer contains untransmitted data. 1: CSAR Tx buffer is empty and ready to store data.*1
30
CMDDMT
1
R/W*2
Command Data Empty 0: CSDR Tx buffer contains untransmitted data. 1: CSDR Tx buffer is empty and ready to store data.*1
29
PLTFRQ
1
R/W*2
PCML TX Request 0: PCML Tx buffer contains untransmitted data. 1: PCML TX buffer is empty and needs to store data. In DMA mode, writing to HACPCML will automatically clear this bit to 0.
28
PRTFRQ
1
R/W*2
PCMR TX Request 0: PCMR Tx buffer contains untransmitted data. 1: PCMR TX buffer is empty and needs to store data. In DMA mode, writing to HACPCMR will automatically clear this bit to 0.
27 to 10
All 0
R
Reserved Always 0 for read and write.
Rev. 1.00 Oct. 01, 2007 Page 1403 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Bit 9
Bit Name PLTFUN
Initial Value 0
R/W R/W*
2
Description PCML TX Underrun 0: No PCML TX underrun has occurred. 1: PCML TX underrun has occurred because the codec has requested slot 3 data but new data is not written to PCML.
8
PRTFUN
0
R/W*2
PCMR TX Underrun 0: No PCMR TX underrun has occurred. 1: PCMR TX underrun has occurred because the codec has requested slot 4 data but new data is not written to PCMR.
7 to 0
All 0
R
Reserved Always 0 for read and write.
Notes: 1. CMDAMT and CMDDMT have no associated interrupts. Poll these bits until they are read as 1 before writing a new command to HACCSAR/HACCSDR. When bit 19 (RW) of HACCSAR is 0 and TX12_ATOMIC is 1, take the following steps: 1. Initialize CMDDMT and CMDAMT before first accessing a codec register after HAC initialization by any reset event. 2. After making the settings in HACCSDR and HACCSAR, poll CMDDMT and CMDAMT until they are cleared to 1, and then initialize these bits. 3. Now the next write to a register is available. 2. These bits are read/write. Writing 0 to the bit initializes it but writing 1 has no effect.
Rev. 1.00 Oct. 01, 2007 Page 1404 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.3.8
RX Interrupt Enable Register (HACRIER)
HACRIER is a 32-bit read/write register that enables or disables HAC RX interrupts.
Bit:
31
30
29
28
27
26
25
24
23
22
STAR YIE
21
STDR YIE
20
PLRF RQIE
19
PRRF RQIE
18
17
16
-
Initial value: R/W: Bit: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R 0
0 R/W
0 R/W
0 R/W
0 R/W
15
14
13
PLRF OVIE
12
PRRF OVIE
11
10
9
8
7
6
5
4
3
2
1
-
Initial value: R/W: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
0 R/W
0 R/W
Bit 31 to 23 22
Bit Name STARYIE
Initial Value All 0 0
R/W R R/W
Description Reserved Always 0 for read and write. Status Address Ready Interrupt Enable 0: Disables status address ready interrupts. 1: Enables status address ready interrupts. Status Data Ready Interrupt Enable 0: Disables status data ready interrupts. 1: Enables status data ready interrupts. PCML RX Request Interrupt Enable 0: Disables PCML RX request interrupts. 1: Enables PCML RX request interrupts. PCMR RX Request Interrupt Enable 0: Disables PCMR RX request interrupts. 1: Enables PCMR RX request interrupts. Reserved Always 0 for read and write. PCML RX Overrun Interrupt Enable 0: Disables PCML RX overrun interrupts. 1: Enables PCML RX overrun interrupts. PCMR RX Overrun Interrupt Enable 0: Disables PCMR RX overrun interrupts. 1: Enables PCMR RX overrun interrupts. Reserved Always 0 for read and write.
21
STDRYIE
0
R/W
20
PLRFRQIE 0
R/W
19
PRRFRQIE 0
R/W
18 to 14 13
All 0
R R/W
PLRFOVIE 0
12
PRRFOVIE 0
R/W
11 to 0
All 0
R
Rev. 1.00 Oct. 01, 2007 Page 1405 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.3.9
RX Status Register (HACRSR)
HACRSR is a 32-bit read/write register that indicates the status of the HAC RX controller. Writing 0 to the bit will initialize it.
Bit:
31
30
29
28
27
26
25
24
23
-
Initial value: R/W: Bit: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
22 STA RY 0 R/W 6
21 STD RY 0 R/W 5
20 PLR FRQ 0 R/W 4
19 PRR FRQ 0 R/W 3
18
17
16
-
0 R
-
0 R
-
0 R 0
15
14
-
Initial value: R/W: 0 R
-
0 R
13 PLR FOV 0 R/W
12 PRR FOV 0 R/W
11
10
9
8
7
2
1
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
Bit 31 to 23 22
Bit Name STARY
Initial Value All 0 0
R/W R R/W
Description Reserved Always 0 for read and write. Status Address Ready 0: HACCSAR (status address) is not ready. 1: HACCSAR (status address) is ready.
21
STDRY
0
R/W
Status Data Ready 0: HACCSDR (status data) is not ready. 1: HACCSDR (status data) is ready.
20
PLRFRQ
0
R/W
PCML RX Request 0: PCML RX data is not ready. 1: PCML RX data is ready and must be read. In DMA mode, reading HACPCML automatically clears this bit to 0.
19
PRRFRQ
0
R/W
PCMR RX Request 0: PCMR RX data is not ready. 1: PCMR RX data is ready and must be read. In DMA mode, reading HACPCMR automatically clears this bit to 0.
18 to 14
All 0
R
Reserved Always 0 for read and write.
Rev. 1.00 Oct. 01, 2007 Page 1406 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Bit 13
Bit Name PLRFOV
Initial Value 0
R/W R/W
Description PCML RX Overrun 0: No PCML RX data overrun has occurred. 1: PCML RX data overrun has occurred because the HAC has received new data from slot 3 before PCML data is not read out.
12
PRRFOV
0
R/W
PCMR RX Overrun 0: No PCMR RX data overrun has occurred. 1: PCMR RX data overrun has occurred because the HAC has received new data from slot 4 before PCMR data is not read out.
11 to 0 Note: *
All 0
R
Reserved Always 0 for read and write.
This register is read/write. Writing 0 to the bit initializes it but writing 1 has no effect.
33.3.10 HAC Control Register (HACACR) HACACR is a 32-bit read/write register used for controlling the HAC interface.
Bit:
31
30
DMA RX16
29
DMA TX16
28
27
26
TX12_ ATOMIC
25
24
RXD MAL_ EN
23
TXD MAL_ EN
22
RXD MAR_ EN
21
TXD MAR_ EN
20
19
18
17
16
-
Initial value: R/W: Bit: 1 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R 0
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
Initial value: R/W: 0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
-
0 R
Bit 31 30
Bit Name DMARX16
Initial Value 1 0
R/W R R/W
Description Reserved Always 1 for read and write.. 16-bit RX DMA Enable 0: Disables 16-bit packed RX DMA mode. Enables the RXDMAL_EN and RXDMAR_EN settings. 1: Enables 16-bit packed RX DMA mode. Disables the RXDMAL_EN and RXDMAR_EN settings.
Rev. 1.00 Oct. 01, 2007 Page 1407 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Bit 29
Bit Name DMATX16
Initial Value 0
R/W R/W
Description 16-bit TX DMA Enable 0: Disables 16-bit packed TX DMA mode. Enables the TXDMAL_EN and TXDMAR_EN settings. 1: Enables 16-bit packed TX DMA mode. Disables the TXDMAL_EN and TXDMAR_EN settings.
28, 27 26
TX12_ATOMIC
All 0 1
R R/W
Reserved Always 0 for read and write. TX Slot 1 and 2 Atomic Control 0: Transmits TX data in HACCSAR and that in HACCSDR separately. (Setting prohibited) 1: Transmits TX data in HACCSAR and that in HACCSDR in the same frame if bit 19 in HACCSAR is 0 (write). (HACCSAR must be written last.)
25 24
0 0
R R/W
Reserved Always 0 for read and write. RX DMA Left Enable 0: Disables 20-bit RX DMA for HACPCML. 1: Enables 20-bit RX DMA is for HACPCML.
RXDMAL_EN
23
TXDMAL_EN
0
R/W
TX DMA Left Enable 0: Disables 20-bit TX DMA for HACPCML. 1: Enables 20-bit TX DMA for HACPCML.
22
RXDMAR_EN
0
R/W
RX DMA Right Enable 0: Disables 20-bit RX DMA for HACPCMR. 1: Enables 20-bit RX DMA for HACPCMR.
21
TXDMAR_EN
0
R/W
TX DMA Right Enable 0: Disables 20-bit TX DMA for HACPCMR. 1: Enables 20-bit TX DMA for HACPCMR.
20 to 0
All 0
R
Reserved Always 0 for read and write.
Rev. 1.00 Oct. 01, 2007 Page 1408 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.4
AC 97 Frame Slot Structure
Figure 33.2 shows the AC97 frame slot structure. This LSI supports slots 0 to 4 only. Slots 5 to 12 are out of scope.
Slot No. HAC_SYNC 0 1 2 3 4 5 6 7 8 9 10 11 12
HAC_SD_OUT (transmit)
TAG
CMD Addr
CMD Data
PCML PCMR LINE1 PCM PCML PCMR PCM Front Front DAC Center Surr Surr LFE
PCM Right LINE1 PCM MIC ADC Reser ved Reser ved
LINE2 HSET IO DAC DAC CTRL
HAC_SD_IN (receive)
TAG
Status Status PCM Addr Data Left
Reser LINE2 HSET IO ved ADC Status ADC
Figure 33.2 AC97 Frame Slot Structure Table 33.4 AC97 Transmit Frame Structure
Slot 0 1 2 3 4 5 6 7 8 9 10 11 12 Notes: * Name SDATA_OUT TAG Control CMD Addr write port Control DATA write port PCM L DAC playback PCM R DAC playback Modem Line 1 DAC PCM Center PCM Surround L PCM Surround R PCM LFE Modem Line 2 DAC Modem handset DAC Modem IO control Description Codec IDs and Tags indicating valid data Read/write command and register address Register write data Left channel PCM output data Right channel PCM output data Modem 1 output data (unsupported)* Center channel PCM data (unsupported)* Surround left channel PCM data (unsupported)* Surround right channel PCM data (unsupported)* LFE channel PCM data (unsupported)* Modem 2 output data (unsupported)* Modem handset output data (unsupported)* Modem control IO output (unsupported)*
There is no register for unsupported functions.
Rev. 1.00 Oct. 01, 2007 Page 1409 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Table 33.5 AC97 Receive Frame Structure
Slot 0 1 2 3 4 5 6 7 to 9 10 11 12 Notes: * Name SDATA_IN TAG Status ADDR read port Status DATA read port PCM L ADC record PCM R ADC record Modem Line 1 ADC Dedicated Microphone ADC Reserved Modem Line 2 ADC Modem handset input DAC Modem IO status Description Tags indicating valid data Register address and slot request Register read data Left channel PCM input data Right channel PCM input data Modem 1 input data (unsupported)* Optional PCM data (unsupported)* Reserved Modem 2 input data (unsupported)* Modem handset input data (unsupported)* Modem control IO input (unsupported)*
There is no register for unsupported functions.
33.5
33.5.1
Operation
Receiver
The HAC receiver receives serial audio data input on the HAC_SD_IN pin, synchronous to HAC_BITCLK. From slot 0, the receiver extracts tag bits that indicate which other slots contain valid data. It will update the receive data only when receiving valid slot data indicated by the tag bits. Supporting data only in slots 1 to 4, the receiver ignores tag bits and data related to slots 5 to 12. It loads valid slot data to the corresponding shift register to hold the data for PIO or DMA transfer, and sets the corresponding status bits. It is possible to read 20-bit data within a 32-bit register using PIO. In the case of RX overrun, the new data will overwrite the current data in the RX buffer of the HAC.
Rev. 1.00 Oct. 01, 2007 Page 1410 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.5.2
Transmitter
The HAC transmitter outputs serial audio data on the HAC_SDOUT pin, synchronous to The transmitter sets the tag bits in slot 0 to indicate which slots in the current frame contain valid data. It loads data slots to the current TX frame in response to the corresponding slot request bits from the previous RX frame. The transmitter supports data only in slots 1 to 4. The TX buffer holds data that has been transferred using PIO or DMA, and sets the corresponding status bit. It is possible to write 20-bit data within a 32-bit register using PIO. In the case of a TX underrun, the HAC will transmit the current TX buffer data until the next data arrives. 33.5.3 DMA
The HAC supports DMA transfer for slots 3 and 4 of both the RX and TX frames. Specify the slot data size for DMA transfer, 16 or 20 bits, with the DMARX16 and DMATX16 bits in HACACR. When the data size is 20 bits, transfer of data slots 3 and 4 requires two local bus access cycles. Since each of the receiver and transmitter has its DMA request, the stereo mode generates a DMA request for slots 3 and 4 separately. The mono mode generates a DMA request for just one slot. When the data size is 16 bits, data from slots 3 and 4 are packed into a single 32-bit quantity (left data and right data are in PCML), which requires only one local bus access cycle. It may be necessary to halt a DMA transfer before the end count is reached, depending on system applications. If so, clear the corresponding DMA bit in HACACR to 0 (DMA disabled). To resume a DMA transfer, reprogram the DMAC and then set the corresponding DMA bit to 1 (DMA enabled). 33.5.4 Interrupts
Interrupts can be used for flag events from the receiver and transmitter. Make the setting for each interrupt in the corresponding interrupt enable register. Interrupts include a request to the CPU to read/write slot data, overrun and underrun. To get the interrupt source, read the status register. Writing 0 to the bit will clear the corresponding interrupt.
Rev. 1.00 Oct. 01, 2007 Page 1411 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.5.5
Initialization Sequence
Figure 33.3 shows an example of the initialization sequence.
Start
HAC cold reset (HACCR = H'0000 0A00)
Start DMA transfer (Receiver/Transmitter) (HACCR = H'0000 0020) HAC module initialiation
TX, RX enable (set HACACR = H'03E0 0000: 20-bit DMATX, slot 1 and slot 2 are atomic control)
Codec ready? (HACCR = H'0000 8000)
No
Yes Set DMAC
Set read address H'26 (Power-down Ctrl/Stat) (HACCSAR = H'000A 6000)
External codec device initialiation
External codec internal status ADC, DAC, Analog, REF = ready? ()HACCSDR = H'0000 00F0
No
Yes Set read volume and sampling rate (1) HACACR = H'0000 0000 (2) Set HACCSAR and HACCSDR (3) HACACR = H'01E0 0000
Note: Refer to section 14, Direct Memory Access Controller (DMAC).
Figure 33.3 Initialization Sequence
Rev. 1.00 Oct. 01, 2007 Page 1412 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Write to codec.
Necessary setting: ACR.TX12_ATOMIC = 1
Write 0 to TSR. CMDAMT. Write 0 to TSR. CMDDMT.
Clear RetryCnt to 0.
Write Data to CSDR.
Write Addr to CSDR.
Clear LoopCnt to 0.
TSR.CMDAMT = 1& TSR. CMDDMT = 1 Yes
No Wait for 1 s LoopCnt ++
E1 < LoopCnt 1 Yes
RetryCnt ++
No
5 < RetryCnt Yes Return Error
No
Notes: E1: Number required for the target system. (21 < E1 <1000)
Input: Addr: Address of the codec register to be written to Data: Data to be written to the codec register RetryCnt: Software counter for error detection LoopCnt: Software counter for wait insertion
Figure 33.4 Sample Flowchart for Off-Chip Codec Register Write
Rev. 1.00 Oct. 01, 2007 Page 1413 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Read coded.
input: RegN ()address of the coded register to be read)
RegN = Last_Reg? No
Yes
Read_codec_aux (RegV)
RegV = H'7C (Vender ID1)
Error
Dummy read Yes Last_Reg: Address of the register read last time.
No
Error
Read_codec_aux (RegN) : Data acquisition Yes
When extrnal codec register are read in saquence, data in the last register that was read may be read again in some codec devices. In this case, use the read procedure shown in this flowchart.
Error
No
Data return
Error
Read_codec_aux
Input: RegN (address of the codec register to be read)
Send_read_request (RegN)
Yes
Error
No
Send_read_request (RegN)
Yes
Error
No
Get_codec_data (RegN) : Data 1 acquisition
Dummy processing (Discard the first data)
Yes
Error
No
Get_codec_data (RegN) : Data 2 acquisition
Yes
Error
No
Data 2 return
Error
Figure 33.5 Sample Flowchart for Off-Chip Codec Register Read (1)
Rev. 1.00 Oct. 01, 2007 Page 1414 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Send_read_request
Input: RegN (address of the codec register to be read)
Write 0 to RSR. STARY. Write 0 to RSR. STDRY.
Set RegN to CSAR.
WaitLoop_CMDAMT
Error
Yes
No
Return
Error
Get_codec_data
Input: RegN (address of the codec register to be read)
Clear LoopCnt2 to 0.
WaitLoop_RSR
Error
No
Assign HACCSAR read value to Addr.
Yes
Error
Addr (R) = RegN?
No
Yes
Assign HACCSDR read value to DataT.
Wait for 5ms LoopCnt2 ++
E2 < LoopCnt 2
No
Yes
DataT return
Error
Notes: E2: Number required for the target system (13 < E2) LoopCnt2: Software counter for wait insertion Addr: Variable to hold CSAR read value DataT: Variable to hold CSDR read value
Figure 33.6 Sample Flowchart for Off-Chip Codec Register Read (2)
Rev. 1.00 Oct. 01, 2007 Page 1415 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
WaitLoop_CMDAMT
Clear LoopCnt3 to 0.
TSR.CMDAMT = 1
No
Yes
Write 0 to TSR. CMDAMT.
Wait for 1s LoopCnt3 ++
Return
E3 < LoopCnt 3 Yes
Error
No
WaitLoop_RSR
Clear LoopCnt4 to 0.
RSR.STARY = 1 & RSR.STDRY = 1
No
Yes
Write 0 to RSR.STARY Write 0 to RSR.STDRY
Wait for 1s LoopCnt4 ++
E4 < LoopCnt 4
No
Return
Yes
Error
Notes: E3 and E4: Number required for the target system (21 < E3, 21 < E4 < 1000) LoopCnt3: Software counter for wait insertion LoopCnt4: Software counter for wait insertion
Figure 33.7 Sample Flowchart for Off-Chip Codec Register Read (3)
Rev. 1.00 Oct. 01, 2007 Page 1416 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
33.5.6
Notes
The HAC_SYNC signal is generated by the HAC to indicate the position of slot 0 within a frame. 33.5.7 Reference
AC'97 Component Specification, Revision 2.1
Rev. 1.00 Oct. 01, 2007 Page 1417 of 1956 REJ09B0256-0100
Section 33 Audio Codec Interface (HAC)
Rev. 1.00 Oct. 01, 2007 Page 1418 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
Section 34 Serial Sound Interface (SSI)
The serial sound interface (SSI) is a module designed to send or receive audio data interface with a variety of devices offering Philips format compatibility. It also provides additional modes for other common formats, as well as support for a multi-channel mode.
34.1
Features
The SSI has the following features. * Number of channels: Four channel * Operating modes: Non-compressed mode The non-compressed mode supports all serial audio streams divided into channels. * The SSI module is configured as any of a transmitter or receiver. The serial bus format can be used. * Asynchronous transfer between the buffer and the shift register * Division ratios of the serial bus interface clock can be selected. * Data transmission/reception can be controlled from the DMAC or interrupt.
Rev. 1.00 Oct. 01, 2007 Page 1419 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
Figure 34.1 is a block diagram of the SSI module.
Control circuit PAD A SSI0_SDATA SSI0_WS MS
Register SSICR/SSISR/ SSITDR/SSIRDR
Data buffer
Barrel shifter
Shift register Bit counter
LS
Serial clock control Divider
SSI0_SCK SSI ch0 SSI1_SDATA SSI1_WS SSI1_SCK A
Divider
SSI ch1
SSI2_SDATA SSI2_WS SSI2_SCK A
Divider
SSI ch2
SSI3_SDATA SSI3_WS SSI3_SCK SSI_CLK A
Divider
SSI ch3
Figure 34.1 Block Diagram of SSI Module
Rev. 1.00 Oct. 01, 2007 Page 1420 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
34.2
Input/Output Pins
Table 34.1 lists the pin configurations relating to the SSI module. Table 34.1 Pin Configuration
Channel Pin Name I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Divider input clock (oversampling clock 256/384/512fs input) Word select Serial data input/output Serial bit clock Word select Serial data input/output Serial bit clock Word select Serial data input/output Serial bit clock Word select Serial data input/output Serial bit clock
Common SSI_CLK 0 SSI0_WS SSI0_SDATA SSI0_SCK 1 SSI1_WS SSI1_SDATA SSI1_SCK 2 SSI2_WS SSI2_SDATA SSI2_SCK 3 SSI3_WS SSI3_SDATA SSI3_SCK
Rev. 1.00 Oct. 01, 2007 Page 1421 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
34.3
Register Descriptions
Table 34.2 shows the SSI register configuration. Table 34.3 shows the register state in each operating mode. Table 34.2 Register Configuration
Channel Register Name 0 Control register 0 Status register 0
Abbreviation R/W
Area P4 Address H'FFE5 0000 H'FFE5 0004 H'FFE5 0008
Area 7 Address H'1FE5 0000 H'1FE5 0004 H'1FE5 0008
Access Size
SSICR0 SSISR0
R/W R/W* R/W R R/W R/W* R/W R R/W R/W* R/W R R/W R/W* R/W R
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Transmit data register 0 SSITDR0 Receive data register 0 1 Control register 1 Status register 1 SSIRDR0 SSICR1 SSISR1
H'FFE5 000C H'1FE5 000C H'FFE5 8000 H'FFE5 8004 H'FFE5 8008 H'1FE5 8000 H'1FE5 8004 H'1FE5 8008
Transmit data register 1 SSITDR1 Receive data register 1 2 Control register 2 Status register 2 SSIRDR1 SSICR2 SSISR2
H'FFE5 800C H'1FE5 800C H'FFE6 0000 H'FFE6 0004 H'FFE6 0008 H'1FE6 0000 H'1FE6 0004 H'1FE6 0008
Transmit data register 2 SSITDR2 Receive data register 2 3 Control register 3 Status register 3 SSIRDR2 SSICR3 SSISR3
H'FFE6 000C H'1FE6 000C H'FFE6 8000 H'FFE6 8004 H'FFE6 8008 H'1FE6 8000 H'1FE6 8004 H'1FE6 8008
Transmit data register 3 SSITDR3 Receive data register 3 Note: * SSIRDR3
H'FFE6 800C H'1FE6 800C
Bits 27 and 26 in the status register are readable/writable bits, and the other bits are read-only bits. For details, refer to section 34.3.2, Status Register (SSISR).
Rev. 1.00 Oct. 01, 2007 Page 1422 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
Table 34.3 Register State in Each Operating Mode
Channel Register Name Power-On Abbreviation Reset Manual Reset Sleep Standby
0
Control register 0 Status register 0
SSICR0 SSISR0
H'0000 0000 H'0000 0000 Retained Retained H'0010 A003 H'0x10 A00x Retained Retained H'0000 0000 H'0000 0000 Retained Retained H'0000 0000 H'0000 0000 Retained Retained H'0000 0000 H'0000 0000 Retained Retained H'0010 A003 H'0x10 A00x Retained Retained H'0000 0000 H'0000 0000 Retained Retained H'0000 0000 H'0000 0000 Retained Retained H'0000 0000 H'0000 0000 Retained Retained H'0010 A003 H'0x10 A00x Retained Retained H'0000 0000 H'0000 0000 Retained Retained H'0000 0000 H'0000 0000 Retained Retained H'0000 0000 H'0000 0000 Retained Retained H'0010 A003 H'0x10 A00x Retained Retained H'0000 0000 H'0000 0000 Retained Retained H'0000 0000 H'0000 0000 Retained Retained
Transmit data register 0 SSITDR0 Receive data register 0 SSIRDR0 1 Control register 1 Status register 1 SSICR1 SSISR1
Transmit data register 1 SSITDR1 Receive data register 1 SSIRDR1 2 Control register 2 Status register 2 SSICR2 SSISR2
Transmit data register 2 SSITDR2 Receive data register 2 SSIRDR2 3 Control register 3 Status register 3 SSICR3 SSISR3
Transmit data register 3 SSITDR3 Receive data register 3 SSIRDR3
Rev. 1.00 Oct. 01, 2007 Page 1423 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
34.3.1
Control Register (SSICR)
SSICR is a 32-bit readable/writable register that controls the IRQ, selects each polarity status, and sets operating mode.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R/W 30 0 R 14 0 R/W 29 0 R 13 0 R/W 28
DMEN
27
UIEN
26
OIEN
25
IIEN
24
DIEN
23 0 R/W 7 0 R
22 0 R/W 6 0 R/W
21 0 R/W 5
CKDV
20
DWL[2:0]
19 0 R/W 3
MUEN
18 0 R/W 2 0 R
17
SWL[2:0]
16 0 R/W 0
EN
CHNL[1:0]
0 R/W 12 0 R/W
0 R/W 11 0 R/W
0 R/W 10 0 R/W
0 R/W 9 0 R/W
0 R/W 8
DEL
0 R/W 4 0 R/W
0 R/W 1
TRMD
SCKD SWSD SCKP SWSP SPDP
SDTA PDTA
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 29
Bit Name
Initial Value 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
28
DMEN
0
R/W
DMA Enable Enables or disables the DMA request. 0: DMA request disabled. 1: DMA request enabled.
27
UIEN
0
R/W
Underflow Interrupt Enable 0: Underflow interrupt disabled 1: Underflow interrupt enabled
26
OIEN
0
R/W
Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled
Rev. 1.00 Oct. 01, 2007 Page 1424 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
Bit 25
Bit Name IIEN
Initial Value 0
R/W R/W
Description Idle Mode Interrupt Enable 0: Idle interrupt disabled 1: Idle interrupt enabled
24
DIEN
0
R/W
Data Interrupt Enable 0: Data interrupt disabled 1: Data interrupt enabled
23, 22
CHNL[1:0] 00
R/W
Channels These bits indicate the number of channels in each system word. 00: 1 channel per system word 01: 2 channels per system word 10: 3 channels per system word 11: 4 channels per system word
21 to 19
DWL[2:0]
000
R/W
Data Word Length These bits indicate the encoded number of bits in a data word. 000: 8 Bits 001: 16 Bits 010: 18 Bits 011: 20 Bits 100: 22 Bits 101: 24 Bits 110: 32 Bits 111: Setting prohibited
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Section 34 Serial Sound Interface (SSI)
Bit 18 to 16
Bit Name SWL[2:0]
Initial Value 000
R/W R/W
Description System Word Length These bits indicate the encoded number of bits in a system word. 000: 8 Bits 001: 16 Bits 010: 24 Bits 011: 32 Bits 100: 48 Bits 101: 64 Bits 110: 128 Bits 111: 256 Bits
15
SCKD
0
R/W
Serial Bit Clock Direction 0: Serial clock input, slave mode 1: Serial clock output, master mode Note: The SCKD and SWSD bits can be set both 0s or 1s ((0,0) or (1,1)). Other settings are prohibited.
14
SWSD
0
R/W
Serial WS Direction 0: Serial word select input, slave mode 1: Serial word select output, master mode Note: The SCKD and SWSD bits can be set both 0s or 1s ((0,0) or (1,1)). Other settings are prohibited.
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Section 34 Serial Sound Interface (SSI)
Bit 13
Bit Name SCKP
Initial Value 0
R/W R/W
Description Serial Clock Polarity 0: SSI_WS and SSI_SDATA change on falling edge of SSI_SCK (sampled on rising edge of SCK) 1: SSI_WS and SSI_SDATA change on rising edge of SSI_SCK (sampled on falling edge of SCK) SCKP = 0
SSI_SDATA input sampling timing in receive mode (TRMD = 0) SSI_SDATA output change timing in transmit mode (TRMD = 1) SSI_WS input sampling in slave mode (SWSD = 0) SSI_WS output change timing in master mode (SWSD = 1) SSI_SCK rising edge SSI_SCK falling edge SSI_SCK rising edge SSI_SCK falling edge
SCKP = 1
SSI_SCK falling edge SSI_SCK rising edge SSI_SCK falling edge SSI_SCK rising edge
12
SWSP
0
R/W
Serial WS Polarity 0: SSI_WS is low for the first channel, high for the second channel 1: SSI_WS is high for the first channel, low for the second channel
11
SPDP
0
R/W
Serial Padding Polarity 0: Padding bits are low 1: Padding bits are high When MUEN = 1, padding bits are low. (The MUTE function is given priority)
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Section 34 Serial Sound Interface (SSI)
Bit 10
Bit Name SDTA
Initial Value 0
R/W R/W
Description Serial Data Alignment 0: Serial data is transmitted/ received first, followed by padding bits. 1: Padding bits are transmitted/ received first, followed by serial data.
9
PDTA
0
R/W
Parallel Data Alignment When the data word length is 32, 16 or 8 bit, this configuration field has no meaning. This bit applies to SSIRDR in receive mode and SSITDR in transmit mode. 0: Parallel data (SSITDR, SSIRDR) is left-aligned 1: Parallel data (SSITDR, SSIRDR) is right-aligned. * DWL = 000 (with a data word length of 8 bits), the PDTA setting is ignored.
All data bits in SSIRDR or SSITDR are used on the audio serial bus. Four data words are transmitted or received at each 32-bit access. The first data word is derived from bits 7 to 0, the second from bits 15 to 8, the third from bits 23 to 16 and the last data word is derived from bits 31 to 24. * DWL = 001 (with a data word length of 16 bits), the PDTA setting is ignored.
All data bits in SSIRDR or SSITDR are used on the audio serial bus. Two data words are transmitted or received at each 32-bit access. The first data word is derived from bits 15 to 0 and the second data word is derived from bits 31 to 16.
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Section 34 Serial Sound Interface (SSI)
Bit 9 (cont.)
Bit Name PDTA
Initial Value 0
R/W R/W
Description * DWL = 010, 011, 100, 101 (with a data word length of 18, 20, 22 or 24 bits), PDTA = 0 (left-aligned)
The data bits used in SSIRDR or SSITDR are the following: Bits 31 down to (32 minus the number of bits in the data word length specified by DWL). That is, If DWL = 011, the data word length is 20 bits; therefore, bits 31 to 12 in either SSIRDR or SSITDR are used. All other bits are ignored or reserved. * DWL = 010, 011, 100, 101 (with a data word length of 18, 20, 22 or 24 bits), PDTA = 1 (right-aligned)
The data bits used in SSIRDR or SSITDR are the following: Bits (the number of bits in the data word length specified by DWL minus 1) to 0 i.e. if DWL = 011, then DWL = 20 and bits 19 to 0 are used in either SSIRDR or SSITDR. All other bits are ignored or reserved. * DWL = 110 (with a data word length of 32 bits), the PDTA setting is ignored.
All data bits in SSIRDR or SSITDR are used on the audio serial bus. 8 DEL 0 R/W Serial Data Delay 0: 1 clock cycle delay between SSI_WS and SSI_SDATA 1: No delay between SSI_WS and SSI_SDATA Reserved This bit is always read as 0. The write value should always be 0.
7
0
R
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Section 34 Serial Sound Interface (SSI)
Bit 6 to 4
Bit Name CKDV
Initial Value All 0
R/W R/W
Description Serial Oversampling Clock Division Ratio These bits define the division ratio between oversampling Clock (SSI_CLK) and the serial bit clock. These bits are ignored if SCKD = 0. The Serial Bit Clock is used for the shift register and is provided on the SSI_SCK pin.
000: (Serial bit clock frequency = oversampling clock frequency/1) 001: (Serial bit clock frequency = oversampling clock frequency/2) 010: (Serial bit clock frequency = oversampling clock frequency/4) 011: (Serial bit clock frequency = oversampling clock frequency/8) 100: (Serial bit clock frequency = oversampling clock frequency/16) 101: (Serial bit clock frequency = oversampling clock frequency/6) 110: (Serial bit clock frequency = oversampling clock frequency/12) 111: Setting prohibited
3
MUEN
0
R/W
Mute Enable 0: The SSI module is not muted 1: The SSI module is muted
2
0
R
Reserved This bit is always read as 0. The write value should always be 0.
1
TRMD
0
R/W
Transmit/Receive Mode Select 0: The SSI module is in receive mode 1: The SSI module is in transmit mode
0
EN
0
R/W
SSI Module Enable 0: The SSI module is disabled 1: The SSI module is enabled
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Section 34 Serial Sound Interface (SSI)
34.3.2
Status Register (SSISR)
SSISR is configured by status flags that indicate the operating status of the SSI module and bits that indicate the current channel number and word number.
Bit: 31
30
29
28
27
26
OIRQ
25
IIRQ
24
DIRQ
23 0
R
22 0
R
21 0
R
20 1
R
19 0
R
18 0
R
17 0
R
16 0
R 0
IDST
DMRQ UIRQ
Initial value: R/W: Bit:
R
R
R
0
R
0
1
0
1
0
R
0
R
R/W* R/W*
15
14
0 R
13
1 R
12
0 R
11
0 R
10
0 R
9
0 R
8
0 R
7
0 R
6
0 R
5
0 R
4
0 R
3
2
1
SWNO
CHNO[1:0]
Initial value: R/W:
1 R
0 R
0 R
1 R
1 R
Bit 31 to 29
Bit Name
Initial Value
R/W R
Description Reserved These bits are always read as an undefined value. The write value should always be 0.
28
DMRQ
0
R
DMA Request Status Flag This status flag allows the CPU to see the status of the DMA request of SSI module. TRMD = 0 (Receive Mode): * * If DMRQ = 1 then SSIRDR has unread data. If SSIRDR is read then DMRQ = 0 until there is new unread data. If DMRQ = 1, SSITDR requests data to be written to continue the transmission onto the audio serial bus. Once data is written to SSITDR then DMRQ = 0 until further transmit data is requested.
TRMD = 1 (Transmit Mode): * *
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Section 34 Serial Sound Interface (SSI)
Bit 27
Bit Name UIRQ
Initial Value 0
R/W R/W*
1
Description Underflow Error Interrupt Status Flag This status flag indicates that the data has been supplied at a lower rate than the required rate. This bit is set to 1 regardless of the setting of UIEN bit. In order to clear it to 0, write 0 in it. If UIRQ = 1 and UIEN = 1, then an interrupt will be generated. When TRMD = 0 (Receive Mode): If UIRQ = 1, it indicates that SSIRDR was read out before DMRQ and DIRQ bits would indicate the existence of new unread data. In this instance, the same received data may be stored twice by the host, which can lead to destruction of multi-channel data. When TRMD = 1 (Transmit Mode): If UIRQ = 1, it indicates that the transmitted data was not written in SSITDR. By this, the same data may be transmitted one time too often, which can lead to destruction of multi-channel data. Consequently, erroneous SSI data will be output, which makes this error more serious than underflow in the receive mode. Note: When underflow error occurs, the data in the data buffer will be transmitted until the next data is written in.
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Section 34 Serial Sound Interface (SSI)
Bit 26
Bit Name OIRQ
Initial Value 0
R/W R/W*
1
Description Overflow Error Interrupt Status Flag This status flag indicates that the data has been supplied at a higher rate than the required rate. This bit is set to 1 regardless of the setting of OIEN bit. In order to clear it to 0, write 0 in it. If OIRQ = 1 and OIEN = 1, then an interrupt will be generated. When TRMD = 0 (Receive Mode): If OIRQ = 1, it indicates that the previous unread data had not been read out before new unread data was written in SSIRDR. This may cause the loss of data, which can lead to destruction of multi-channel data. Note: When overflow error occurs, the data in the data buffer will be overwritten by the next data sent from the SSI interface. When TRMD = 1 (Transmit Mode): If OIRQ = 1, it indicates that SSITDR had data written in before the data in SSITDR was transferred to the shift register. This may cause the loss of data, which can lead to destruction of multi-channel data.
25
IIRQ
0*2
R
Idle Mode Interrupt Status Flag This status flag indicates whether the SSI module is in the idle status. This bit is set to 1 regardless of the setting of IIEN bit, so that polling will be possible. The interrupt can be masked by clearing IIEN bit to 0, but writing 0 in this bit will not clear the interrupt. If IIRQ = 1 and IIEN = 1, then an interrupt will be generated. 0: The SSI module is not in the idle status. 1: The SSI module is in the idle status.
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Section 34 Serial Sound Interface (SSI)
Bit 24
Bit Name DIRQ
Initial Value 0
R/W R
Description Data Interrupt Status Flag This status flag indicates that the SSI module requires that data be either read out or written in. This bit is set to 1 regardless of the setting of DIEN bit, so that polling will be possible. The interrupt can be masked by clearing DIEN bit to 0, but writing 0 in this bit will not clear the interrupt. If DIRQ = 1 and DIEN = 1, then an interrupt will be generated. When TRMD = 0 (Receive Mode): 0: No unread data exists in SSIRDR. 1: Unread data exists in SSIRDR. When TRMD = 1 (Transmit Mode): 0: The transmit buffer is full. 1: The transmit buffer is empty, and requires that data be written in SSITDR.
23 to 4
H'10A00 R
Reserved These bits are always read as H'10A00. The write value should always be 0.
3, 2
CHNO[1:0] 00
R
Channel Number The number indicates the current channel. When TRMD = 0 (Receive Mode): This bit indicates to which channel the current data in SSIRDR belongs. When the data in SSIRDR is updated by transfer from the shift register, this value will change. When TRMD = 1 (Transmit Mode): This bit indicates the data of which channel should be written in SSITDR. When data is copied to the shift register, regardless whether the data is written in SSITDR, this value will change.
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Section 34 Serial Sound Interface (SSI)
Bit 1
Bit Name SWNO
Initial Value 1
R/W R
Description Serial Word Number The number indicates the current word number. When TRMD = 0 (Receive Mode): This bit indicates which system word the current data in SSIRDR is. Regardless whether the data has been read out from SSIRDR, when the data in SSIRDR is updated by transfer from the shift register, this value will change. When TRMD = 1 (Transmit Mode): This bit indicates which system word should be written in SSITDR. When data is copied to the shift register, regardless whether the data is written in SSITDR, this value will change.
0
IDST
1*2
R
Idle Mode Status Flag Indicates that the serial bus activity has ceased. This bit is cleared if EN = 1 and the Serial Bus is currently active. This bit can be set to 1 automatically under the following conditions. SSI = Serial bus master transmitter (SWSD = 1 and TRMD = 1): This bit is set to 1 if no more data has been written to SSITDR and the current system word has been completed. It can also be set to 1 by clearing the EN bit after sufficient data has been written to SSITDR to complete the system word currently being output. SSI = Serial bus master receiver (SWSD = 1 and TRMD = 0): This bit is set to 1 if the EN bit is cleared and the current system word is completed. SSI = slave transmitter/ receiver (SWSD = 0): This bit is set to 1 if the EN bit is cleared and the current system word is completed. Note: If the external device stops the serial bus clock before the current system word is completed then this bit will never be set.
Rev. 1.00 Oct. 01, 2007 Page 1435 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
Note:
1. These bits are readable/writable bits. If writing 0, these bits are initialized, although writing 1 is ignored. 2. At manual reset, the bit is undefined.
34.3.3
Transmit Data Register (SSITDR)
SSITDR is a 32-bit register that stores data to be transmitted. Data written to SSITDR is transferred to the shift register as it is required for transmission. If the data word length is less than 32 bits then its alignment should be as defined by the PDTA control bit. Reading this register will return the data in the buffer.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R/W 15 0 R/W 30 0 R/W 14 0 R/W 29 0 R/W 13 0 R/W 28 0 R/W 12 0 R/W 27 0 R/W 11 0 R/W 26 0 R/W 10 0 R/W 25 0 R/W 9 0 R/W 24 0 R/W 8 0 R/W 23 0 R/W 7 0 R/W 22 0 R/W 6 0 R/W 21 0 R/W 5 0 R/W 20 0 R/W 4 0 R/W 19 0 R/W 3 0 R/W 18 0 R/W 2 0 R/W 17 0 R/W 1 0 R/W 16 0 R/W 0 0 R/W
34.3.4
Receive Data Register (SSIRDR)
SSIRDR is a 32-bit register that stores the received data. Data in SSIRDR is transferred from the shift register as each data word is received. If the data word length is less than 32 bits then its alignment should be as defined by the PDTA control bit in SSICR.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 0 R 16 0 R 0 0 R
Rev. 1.00 Oct. 01, 2007 Page 1436 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
34.4
34.4.1
Operation
Bus Format
The SSI module can operate as a transmitter or a receiver and can be configured into many serial bus formats in either mode. The bus formats can be one of eight major modes as shown in table 34.4. Table 34.4 Bus Formats of SSI Module
CHNL[1:0] DWL[2:0] SWL[2:0]
SWSD
SWSP
MUEN
SCKD
TPMD
Bus Format
Non-Compressed Slave Receiver Non-Compressed Slave Transmitter Non-Compressed Master Receiver Non-Compressed Master Transmitter
0 1 0 1
0 0 1 1
0 0 1 1
Control bits
Configuration bits
Rev. 1.00 Oct. 01, 2007 Page 1437 of 1956 REJ09B0256-0100
SCKP
SPDP
PDTA
SDTA
OIEN
DIEN
UIEN
DEL
IIEN
EN
Section 34 Serial Sound Interface (SSI)
34.4.2
Non-Compressed Modes
The non-compressed mode is designed to support all serial audio streams which are split into channels. It can support Philips, Sony and Matsushita modes as well as many more variants on these modes. (1) Slave Receiver
This mode allows the SSI module to receive serial data from another device. The clock and word select signals used for the serial data stream are also supplied from an external device. If these signals do not conform to the format as specified in the SSI module then operation is not guaranteed. (2) Slave Transmitter
This mode allows the SSI module to transmit serial data to another device. The clock and word select signals used for the serial data stream are also supplied from an external device. If these signals do not conform to the format as specified in the SSI module then operation is not guaranteed. (3) Master Receiver
This mode allows the SSI module to receive serial data from another device. The clock and word select signals are internally derived from the HAC_BIT_CLK input clock. The format of these signals is as defined in the SSI module. If the incoming data does not conform to the defined format then operation is not guaranteed. (4) Master Transmitter
This mode allows the SSI module to transmit serial data to another device. The clock and word select signals are internally derived from the HAC_BIT_CLK input clock. The format of these signals is as defined in the configuration bits in the SSI module. (5) Configuration Fields - Word Length Related
All configuration bits relating to the word length of SSICR are valid in non-compressed modes. There are many configurations that the SSI module can support and it is not sensible to show all of the Serial Data formats in this document. Some of the combinations are shown below for the popular formats by Philips, Sony, and Matsushita.
Rev. 1.00 Oct. 01, 2007 Page 1438 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
1. Philips Format Figures 34.2 and 34.3 show the supported Philips protocol both with padding and without. Padding occurs when the data word length is smaller than the system word length.
SCKP = 0, SWSP = 0, DEL = 0, CHNL = 00 System word length = data word length
SSI_SCK
SSI_WS
LSB +1
LSB +1
SSI_SDATA
prev. sample MSB
LSB MSB
LSB next sample
System word 1 = data word 1
System word 2 = data word 2
Figure 34.2 Philips Format (with no Padding)
SCKP = 0, SWSP = 0, DEL = 0, CHNL = 00, SPDP = 0, SDTA = 0 System word length > data word length
SSI_SCK
SSI_WS
SSI_SDATA
MSB
LSB
MSB
LSB
Next
Data word 1 System word 1
Padding
Data word 2 System word 2
Padding
Figure 34.3 Philips Format (with Padding) Figure 34.4 shows the format used by Sony. Figure 34.5 shows the format used by Matsushita. Padding is assumed in both cases, but may not be present in a final implementation if the system word length equals the data word length.
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Section 34 Serial Sound Interface (SSI)
2. Sony Format
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 00, SPDP = 0, SDTA = 0 System word length > data word length
SSI_SCK
SSI_WS
SSI_SDATA
MSB Data word 1
LSB Padding
MSB
LSB
Next Padding
Data word 2 System word 2
System word 1
Figure 34.4 Sony Format (with Serial Data First, Followed by Padding Bits) 3. Matsushita Format
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 00, SPDP = 0, SDTA = 1 System word length > data word length SSI_SCK
SSI_WS
SSI_SDATA
Prev.
MSB
LSB
MSB
LSB
Padding
Data word 1 System word 1
Padding
Data word 2 System word 2
Figure 34.5 Matsushita Format (with Padding Bits First, Followed by Serial Data) (6) Multi-Channel Formats
Some devices extend the definition of the specification by Philips and allow more than 2 channels to be transferred within two system words. The SSI module supports the transfer of 2, 3 and 4 channels by the use of the CHNL, SWL and DWL bits. It is important that the system word length (SWL) is greater than or equal to the number of channels (CHNL) times the data word length (DWL). Table 34.5 shows the number of padding bits for each of the valid configurations. If a setup is not valid it does not have a number in the following table and has instead a dash.
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Section 34 Serial Sound Interface (SSI)
Table 34.5 Number of Padding Bits for Each Valid Configuration
Padding Bits Per System Word
DWL[2:0] 000 Decoded Word 8 Length 8 16 24 32 48 64 128 256 8 16 24 32 48 64 128 256 8 16 24 32 48 64 128 256 8 16 24 32 48 64 128 256 0 8 16 24 40 56 120 248 -- 0 8 16 32 48 112 240 -- -- 0 8 24 40 104 232 -- -- -- 0 16 32 96 224
001
010
011
100
101
110
CHNL [1:0] 00
Decoded Channels per System Word
SWL [2:0] 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
16 -- 0 8 16 32 48 112 240 -- -- -- 0 16 32 96 224 -- -- -- -- 0 16 80 208 -- -- -- -- -- 0 64 192
18 -- -- 6 14 30 46 110 238 -- -- -- -- 12 28 92 220 -- -- -- -- -- 10 74 202 -- -- -- -- -- -- 56 184
20 -- -- 4 12 28 44 108 236 -- -- -- -- 8 24 88 216 -- -- -- -- -- 4 68 196 -- -- -- -- -- -- 48 176
22 -- -- 2 10 26 42 106 234 -- -- -- -- 4 20 84 212 -- -- -- -- -- -- 62 190 -- -- -- -- -- -- 40 168
24 -- -- 0 8 24 40 104 232 -- -- -- -- 0 16 80 208 -- -- -- -- -- -- 56 184 -- -- -- -- -- -- 32 160
32 -- -- -- 0 16 32 96 224 -- -- -- -- -- 0 64 192 -- -- -- -- -- -- 32 160 -- -- -- -- -- -- 0 128
1
01
2
10
3
11
4
000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
Rev. 1.00 Oct. 01, 2007 Page 1441 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
In the case of the SSI module configured as a transmitter then each word that is written to SSITDR is transmitted in order on the serial audio bus. In the case of the SSI module configured as a receiver each word received on the Serial Audio Bus is presented for reading in order by SSIRDR. Figures 34.6 to 34.8 show how 2, 3 and 4 channels are transferred on the serial audio bus. Figures 34.6 to 34.8 show how data on multiple channels (2, 3 or 4 channels) is transferred on the serial audio bus. Figure 34.6 shows the data transfer using no padding bits. Figure 34.7 shows the data transfer in which data is left-aligned with padding bits. Figure 34.8 shows the data transfer in which data is right-aligned with padding bits. This selection is purely arbitrary.
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 01, SPDP = don't care, SDTA = don't care System word length = data word length x 2
SSI_SCK SSI_WS
SSI_SDATA
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
Data word 1
Data word 2
Data word 3
Data word 4
Data word 1
Data word 2
Data word 3
Data word 4
System word 1
System word 2
System word 1
System word 2
Figure 34.6 Multichannel Format (2 Channels, No Padding)
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 10, SPDP = 1, SDTA = 0 System word length = data word length x 3
SSI_SCK SSI_WS SSI_SDATA
MSB LSB MSB
LSB MSB
LSB
MSB
LSB MSB
LSB MSB
LSB
MSB
Padding
Data word 1
Data word 2
System word 1
Data word 3
Data word 4
Data word 5
Data word 6
System word 2
Figure 34.7 Multichannel Format (3 Channels with High Padding)
Rev. 1.00 Oct. 01, 2007 Page 1442 of 1956 REJ09B0256-0100
Padding
Section 34 Serial Sound Interface (SSI)
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 11, SPDP = 0, SDTA = 1 System word length = data word length x 4
SSI_SCK SSI_WS SSI_SDATA
Padding
MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
Data word 1
Data word 2
Data word 3
Data word 4
Padding
Data word 5
Data word 6
Data word 7
Data word 8
System word 1
System word 2
Figure 34.8 Multichannel Format (4 Channels, with Padding Bits First, Followed by Serial Data, with Padding)
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Section 34 Serial Sound Interface (SSI)
(7)
Configuration Fields - Signal Format Fields
There are several more configuration bits in non-compressed mode which will now be demonstrated. These bits are NOT mutually exclusive, however some configurations will probably not be useful for any other device. They are demonstrated by referring to the following basic sample format shown in figure 34.9.
SWL = 6 bits (not attainable in SSI module, demonstration only) DWL = 4 bits (not attainable in SSI module, demonstration only) CHNL = 00, SCKP = 0, SWSP = 0, SPDP = 0, SDTA = 0, PDTA = 0, DEL = 0, MUEN = 0 4-bit data samples continuously written to SSITDR are transmitted onto the serial audio bus.
SSI_SCK
SSI_WS
1st channel
2nd channel
SSI_SDATA
TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31
Key for this and following diagrams:
Arrow head indicates sampling point of receiver
TDn
Bit n in SSITDR
0
1
means a low level on the serial bus (padding or mute)
means a high level on the serial bus (padding)
Figure 34.9 Basic Sample Format (Transmit Mode with Example System/Data Word Length)
Rev. 1.00 Oct. 01, 2007 Page 1444 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
In figure 34.9, system word length of 6 bits and a data word length of 4 bits are used. Neither of these are possible with the SSI module but are used only for clarification of the other configuration bits. 1. Inverted Clock
As basic sample format configuration except SCKP = 1
SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31
Figure 34.10 Inverted Clock 2. Inverted Word Select
As basic sample format configuration except SWSP = 1
SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31
Figure 34.11 Inverted Word Select 3. Inverted Padding Polarity
As basic sample format configuration except SPDP = 1 SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA TD28
1
1
TD31 TD30 TD29 TD28
1
1
TD31 TD30 TD29 TD28
1
1
TD31
Figure 34.12 Inverted Padding Polarity
Rev. 1.00 Oct. 01, 2007 Page 1445 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
4. Padding Bits First, Followed by Serial Data, with Delay
As basic sample format configuration except SDTA = 1
SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
Figure 34.13 Padding Bits First, Followed by Serial Data, with Delay 5. Padding Bits First, Followed by Serial Data, without Delay
As basic sample format configuration except SDTA = 1 and DEL = 1 SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
Figure 34.14 Padding Bits First, Followed by Serial Data, without Delay 6. Serial Data First, Followed by Padding Bits, without Delay
As basic sample format configuration except DEL = 1 SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30
Figure 34.15 Serial Data First, Followed by Padding Bits, without Delay
Rev. 1.00 Oct. 01, 2007 Page 1446 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
7. Parallel Right Aligned with Delay
As basic sample format configuration except PDTA = 1 SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
TD0
0
0
TD3
TD2
TD1
TD0
0
0
TD3
TD2
TD1
TD0
0
0
TD3
Figure 34.16 Parallel Right Aligned with Delay 8. Mute Enabled
As basic sample format configuration except MUEN = 1 (TD data ignored) SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 34.17 Mute Enabled
Rev. 1.00 Oct. 01, 2007 Page 1447 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
34.4.3
Operation Modes
There are three modes of operation: configuration, enabled and disabled. Figure 34.18 shows the transition diagram between these operation modes.
Reset Module configration (after reset)
EN = 0 (IDST = 1)
EN = 1 (IDST = 0)
Module disabled (waiting until bus inactive)
Module enabled (normal tx/rx) EN = 0 (IDST = 0)
Figure 34.18 Transition Diagram between Operation Modes
Rev. 1.00 Oct. 01, 2007 Page 1448 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
(1)
Configuration Mode
This mode is entered after the module is released from reset. All required settings in the control register should be defined in this mode, before the SSI module is enabled by setting the EN bit. Setting the EN bit causes the SSI module to enter the module enabled mode. (2) Module Enabled Mode
Operation of the module in this mode depends on the selected operating mode. For details, see section 34.4.4, Transmit Operation and section 34.4.5, Receive Operation. 34.4.4 Transmit Operation
Transmission can be controlled in one of two ways: either DMA or an interrupt driven. DMA driven is preferred to reduce the CPU load. In DMA control mode, an underflow or overflow of data or DMAC transfer end is notified by using an interrupt. The alternative is using the interrupts that the SSI module generates to supply data as required. This mode has a higher interrupt load as the SSI module is only double buffered and will require data to be written at least every system word period. When disabling the SSI module, the SSI clock* must be supplied continuously until the module enters in the idle state, indicated by the IIRQ bit. Figure 34.19 shows the transmit operation in the DMA controller mode. Figure 34.20 shows the transmit operation in the Interrupt controller mode. Note: * SCKD = 0: Clock input through the SSI_SCK pin SCKD = 1: Clock input through the SSI_CLK pin
Rev. 1.00 Oct. 01, 2007 Page 1449 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
(1)
Transmission Using DMA Controller
Start Release reset, specify configuration bits in SSICR
Setup DMA controller to provide data as required for transmission
Enable SSI module, enable DMA, enable error interrupts
Wait for interrupt from DMAC or SSI
Specify TRMD, EN, SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL
EN = 1, DMEN = 1, UIEN = 1, OIEN = 1
SSI error interrupt?
No
Yes
No
Has DMAC Tx data been completed?
Yes
Yes
More data to be send?
No
Disable SSI module, disable DMA disable error interrupt, enable Idle interrupt
Wait for idle interrupt from SSI module
Reset SSI module if required
End*
EN = 0, DMEN = 0 UIEN = 0, OIEN = 0, IIEN = 1
Note: * When SSI error interrupt occurs (underflow/overflow), back to start and execute flow again.
Figure 34.19 Transmission Using DMA Controller
Rev. 1.00 Oct. 01, 2007 Page 1450 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
(2)
Transmission using Interrupt Data Flow Control
Start Release reset, specify configuration bits in SSICR
Enable SSI module, enable DMA, enable error interrupts
For n = ( (CHNL + 1) x 2) Loop
Specify TRMD, EN, SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL
EN = 1, DIEN = 1, UIEN = 1, OIEN = 1
Wait for interrupt from SSI
Use SSI status register bits to realign data after underflow/overflow
Data interrupt?
Yes
Load data of channel n
No
Next Channel
Yes
More data to be send?
No
Disable SSI module, disable DMA disable error interrupt, enable Idle interrupt
Wait for Idle interrupt from SSI module
Reset SSI module if required End
EN = 0, DIEN = 0 UIEN = 0, OIEN = 0, IIEN = 1
Figure 34.20 Transmission using Interrupt Data Flow Control
Rev. 1.00 Oct. 01, 2007 Page 1451 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
34.4.5
Receive Operation
As with transmission the reception can be controlled in one of two ways: either DMA or an interrupt driven. Figures 34.21 and 34.22 show the flow of operation. When disabling the SSI module, the SSI clock must be supplied continuously until the module enters in the idle state, which is indicated by the IIRQ bit. Note: * SCKD = 0: Clock input through the SSI_SCK pin SCKD = 1: Clock input through the SSI_CLK pin
Rev. 1.00 Oct. 01, 2007 Page 1452 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
(1)
Reception Using DMA Controller
Start Release reset, specify configuration bits in SSICR
Setup DMA controller to provide data as required for transmission
Enable SSI module, enable DMA, enable error interrupts
Wait for interrupt from DMAC or SSI
Specify TRMD, EN, SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL
EN = 1, DMEN = 1, UIEN = 1, OIEN = 1
SSI error interrupt?
No
Yes
No
Has DMAC Tx data been completed?
Yes
Yes
More data to be send?
No
Disable SSI module, disable DMA disable error interrupt, enable Idle interrupt
Wait for idle interrupt from SSI module
Reset SSI module if required
End*
EN = 0, DMEN = 0 UIEN = 0, OIEN = 0, IIEN = 1
Note: * When SSI error interrupt occurs (underflow/overflow), back to start and execute flow again.
Figure 34.21 Reception using DMA Controller
Rev. 1.00 Oct. 01, 2007 Page 1453 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
(2)
Reception using Interrupt Data Flow Control
Start
Specify TRMD, EN, SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL
Release reset, specify configuration bits in SSICR
Enable SSI module, enable data interrupt, enable error interrupts
EN = 1, DIEN = 1, UIEN = 1, OIEN = 1
Wait for interrupt from SSI
SSI Error interrupt?
Yes
Use SSI status register bits to realign data after underflow/overflow
No
Read data from receive data register
Yes
More data to be received?
No
Disable SSI module, disable data interrupt disable error IRQ, enable idle IRQ
EN = 0, DIEN = 0 UIEN = 0, OIEN = 0, IIEN = 1
Wait for idle interrupt from SSI module
Reset SSI module if required
End
Figure 34.22 Reception using Interrupt Data Flow Control
Rev. 1.00 Oct. 01, 2007 Page 1454 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
When an underflow or overflow error condition is met, the CHNO[1:0] and SWNO bits can be used to recover the SSI module to a known status. When an underflow or overflow occurs, the host CPU can read the number of channels and the number of system words to determine what point the serial audio stream has reached. In the transmitter case, the host CPU can skip forward through the data it wants to transmit until it finds the sample data that matches what the SSI module is expecting to transmit next, and so resynchronize with the audio data stream. In the receiver case, the host CPU can skip forward storing null sample data until it is ready to store the sample data that the SSI module is indicating that it will receive next to ensure consistency of the number of received data, and so resynchronize with the audio data stream. 34.4.6 Serial Clock Control
This function is used to control and select which clock is used for the serial bus interface. If the serial clock direction is set to input (SCKD = 0), the SSI module is in clock slave mode, then the bit clock that is used in the shift register is derived from the SSI_SCK pin. If the serial clock direction is set to output (SCKD = 1), the SSI Module is in clock master mode, and the shift register uses the bit clock derived from the SSI_CLK input pin or its clock divided. This input clock is then divided by the ratio in the serial oversampling clock division ratio (CKDV) bit in SSICR and used as the bit clock in the shift register. In either case, the SSI_SCK pin output is the same as the bit clock.
Rev. 1.00 Oct. 01, 2007 Page 1455 of 1956 REJ09B0256-0100
Section 34 Serial Sound Interface (SSI)
34.5
34.5.1
Usage Note
Restrictions when an Overflow Occurs during Receive DMA Operation
If an overflow occurs during receive DMA operation, the module must be reactivated. The receive buffer of SSI has 32-bit common register both left channel and right channel. If an overflow occurs under the condition of control register (SSICR) data-word length (DWL2 to DWL0) is 32-bit and system-word length (SWL2 to SWL0) is 32-bit, SSI has received the data at right channel that should be received at left channel. If an overflow occurs through an overflow error interrupt or overflow error status flag (the OIRQ bit in SSISR), disable the DMA transfer of the SSI to halt its operation by writing 0 to the EN bit and DMEN bit in SSICR (then terminate the DMA setting). And clear the overflow status flag by writing 0 to the OIRQ bit, set the DMA again and transfer restart. 34.5.2 Restrictions for Operation in Slave Mode
To terminate data transfer while this LSI is used in slave mode, clear the EN bit in SSICR to 0 to terminate data transfer before the word select signal supply is stopped. In slave mode, data transfer is terminated if the EN bit (settings for terminating data transfer) is cleared and the falling edge of the word select signal (SSI_WS) is detected. If the word select signal supply is stopped before EN bit clear, the falling edge of the word select signal cannot be detected, and thereby data transfer is not terminated properly.
Rev. 1.00 Oct. 01, 2007 Page 1456 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Section 35 USB Host Controller (USBH)
The USB host controller embedded in this LSI has a root hub and a one-port USB transceiver, and operates in Full speed mode. Open HCI interfaces and registers are also embedded in this LSI. For the development of software, refer to the Open HCI specifications as well.
35.1
* * * * *
Features
Support the Open HCI interface. Support the USB host interface. Root Hub function (although it supports only one port) Operate in Full speed mode (12Mbps) and low speed mode (1.5 Mbps) Support Overcurrent detection and Power source enable management.
Rev. 1.00 Oct. 01, 2007 Page 1457 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
A block diagram of the USBH is shown in figure 35.1.
Peripheral bus 0 SuperHyway bridge bus
USB Host module HCI I/F slave
OHCI register Control Control
Control
32
Application slave interface I/F
Application master interface data
32 FIFO (output) 4 bytes FIFO (input) 4 bytes
List processor
HCI I/F master
Control
Root hub setting
data
48MHz
Root hub Host SIE OHCI Root hub register XVR
USB_CLK (48MHz)
Divider
12MHz
USBP USBM USB_PWREN USB_OVRCRT
XVR : USB transceiver
Figure 35.1 Block Diagram of USBH
Rev. 1.00 Oct. 01, 2007 Page 1458 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.2
Pin Description
Table 35.1 shows the pin configuration of the USB host module. Table 35.1 USB Host Pin Assignment
Name USBP USBM USB_PWREN USB_OVRCRT Function D+ DI/O I/O I/O Function USB port D+ USB port DUSB port power source enable management USB port overcurrent detection This is used to detect an overcurrent at low level and normal operation at high level. Input USB clock input pin (48 MHz input)*
USB port power source Output enable USB port overcurrent detection Clock pin I/O
USB_CLK Note: *
USB_CLK should be slower than Pck0.
Rev. 1.00 Oct. 01, 2007 Page 1459 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3
Register Description
Table 35.2 shows the USBH register configuration. Table 35.3 shows the register state in each operating mode. Other than the ConfigulationControl register, all registers conform to the OpenHCIs specification. For details, refer to the OpenHCI Rev1.0. The Configuration Control register is only for this LSI. Table 35.2 Register Configuration
Register Name HcRevision register HcControl register HcCommandStatus register HcInterruptStatus register HcInterruptEnable register HcInterruptDisable register HcHCCA register HcPeriodCurrentED register HcControlHeadED register HcControlCurrentED register HcBulkHeadED register HcBulkCurrentED register HcDoneHead register HcFmInterval register HcFmRemaining register HcFmNumber register HcPeriodicStart register HcLSThreshold register HcRhDescriptorA register HcRhDescriptorB register Abbreviation R/W USBHR USBHC USBHCS USBHIS USBHIE USBHID USBHHCCA USBHPCED USBHCHED USBHCCED USBHBHED USBHBCED USBHDHED USBHFI USBHFR USBHFN USBHPS USBHLST USBHRDA USBHRDB R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W Area P4 Address* H'FFEC 8000 H'FFEC 8004 H'FFEC 8008 H'FFEC 800C H'FFEC 8010 H'FFEC 8014 H'FFEC 8018 H'FFEC 801C H'FFEC 8020 H'FFEC 8024 H'FFEC 8028 H'FFEC 802C H'FFEC 8030 H'FFEC 8034 H'FFEC 8038 H'FFEC 803C H'FFEC 8040 H'FFEC 8044 H'FFEC 8048 H'FFEC 804C Area 7 Address* H'1FEC 8000 H'1FEC 8004 H'1FEC 8008 H'1FEC 800C H'1FEC 8010 H'1FEC 8014 H'1FEC 8018 H'1FEC 801C H'1FEC 8020 H'1FEC 8024 H'1FEC 8028 H'1FEC 802C H'1FEC 8030 H'1FEC 8034 H'1FEC 8038 H'1FEC 803C H'1FEC 8040 H'1FEC 8044 H'1FEC 8048 H'1FEC 804C Access Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Rev. 1.00 Oct. 01, 2007 Page 1460 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Register Name HcRhStatus register HcRhPortStatus[2] register ConfigurationControl register Note: *
Abbreviation R/W USBHRS USBHRPS2 USBHSC R/W R/W R/W
Area P4 Address* H'FFEC 8050 H'FFEC 8058 H'FFEC 80F0
Area 7 Address* H'1FEC 8050 H'1FEC 8058 H'1FEC 80F0
Access Size 32 32 32
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
Table 35.3 Register State in Each Operating Mode
Register Name HcRevision register HcControl register HcCommandStatus register HcInterruptStatus register HcInterruptEnable register HcInterruptDisable register HcHCCA register HcPeriodCurrentED register HcControlHeadED register HcControlCurrentED register HcBulkHeadED register HcBulkCurrentED register HcDoneHead register HcFmInterval register HcFmRemaining register HcFmNumber register HcPeriodicStart register HcLSThreshold register HcRhDescriptorA register HcRhDescriptorB register HcRhStatus register Abbreviation USBHR USBHC USBHCS USBHIS USBHIE USBHID USBHHCCA USBHPCED USBHCHED USBHCCED USBHBHED USBHBCED USBHDHED USBHFI USBHFR USBHFN USBHPS USBHLST USBHRDA USBHRDB USBHRS Power-On Reset Manual Reset Sleep Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
H'00000010 H'00000010 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00002EDF H'00002EDF Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained H'00000628 H'00000628 Retained H'02001002 H'02001002 Retained H'00000000 H'00000000 Retained H'00000000 H'00000000 Retained
Rev. 1.00 Oct. 01, 2007 Page 1461 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Register Name HcRhPortStatus[2] register ConfigurationControl register
Abbreviation USBHRPS2 USBHSC
Power-On Reset
Manual Reset
Sleep Retained Retained
Standby Retained Retained
H'00000100 H'00000100 H'00000001 H'00000001
35.3.1
HcRevision Register (USBHR)
Bit :
31
--
30
-- 0 --
29
-- 0 --
28
-- 0 --
27
-- 0 --
26
-- 0 --
25
-- 0 --
24
-- 0 --
23
-- 0 --
22
-- 0 --
21
-- 0 --
20
-- 0 --
19
-- 0 --
18
-- 0 --
17
-- 0 --
16
-- 0 --
Initial value : R/W : Bit : Initial value : R/W :
0 --
15
-- 0 --
14
-- 0 --
13
-- 0 --
12
-- 0 --
11
-- 0 --
10
-- 0 --
9
-- 0 --
8
-- 0 --
7
0 R
6
0 R
5
0 R
4
1 R
3
0 R
2
0 R
1
0 R
0
0 R
REV[7:0]
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved. These bits are always read as 0. The write value should always be 0
7 to 0
REV[7:0]
H'10
R
Revision Indicates the OpenHCI Specification revision number implemented by the Hardware. (X.Y = H'XY) USB Host Controller supports the Open HCI1.0 specification.
Rev. 1.00 Oct. 01, 2007 Page 1462 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.2
HcControl Register (USBHC)
Bit : 31 -- 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 0 R/W 25 -- 0 R 9 0 R/W 24 -- 0 R 8 IR 0 R/W 23 -- 0 R 7 0 R/W 22 -- 0 R 6 0 R/W 21 -- 0 R 5 BLE 0 R/W 20 -- 0 R 4 CLE 0 R/W 19 -- 0 R 3 IE 0 R/W 18 -- 0 R 2 PLE 0 R/W 17 -- 0 R 1 0 R/W 16 -- 0 R 0 0 R/W
Initial value : R/W : Bit : Initial value : R/W :
0 R 15 -- 0 R
RWE RWC
HCFS[1:0]
CBSR[1:0]
Bit 31 to 11
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0
10
RWE
0
R/W
RemoteWakeupConnectedEnable If a remote wakeup signal is supported, this bit enables that operation. Since remote wakeup signal is not supported, this bit is ignored.
9
RWC
0
R/W
RemoteWakeupConnected This bit indicates whether the Host Controller(HC) supports a remote wakeup signal.
8
IR
0
R/W
InterruptRouting This bit specifies interrupt routing: 0: Interrupts routed to normal interrupt processing unit (INT). 1: Interrupts routed to SMI.
7, 6
HCFS[1:0]
All 0
R/W
HostControllerFunctionalState These bits set the Host Controller state. The state encodings are: 00: UsbReset 01: UsbResume 10: UsbOperational 11: UsbSuspend The Host Controller may force a state change from UsbSuspend to UsbResume after detecting resume signaling from a downstream port.
Rev. 1.00 Oct. 01, 2007 Page 1463 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Bit 5
Bit Name BLE
Initial Value 0
R/W R/W
Description BulkListEnable When set, this bit enables processing of the Bulk list.
4
CLE
0
R/W
ControlListEnable This bit is set to enable the processing of the control list in the next frame. If cleared by HCD, the processing of the control list is not carried out after next SOF. The host controller must check this bit whenever the list will be processed. When disabling, HDC can correct the list. When USBHCCED indicates ED to be deleted, HCD should hasten the pointer by updating USBHCCED before re-enabling the list processing. 0: Control list processing is not carried out 1: Control list processing is carried out
3
IE
0
R/W
IsochronousEnable When clear, this bit disables the Isochronous List when the Periodic List is enabled (so Interrupt EDs may be serviced). While processing the Periodic List, the Host Controller will check this bit when it finds an isochronous ED.
2
PLE
0
R/W
PeriodicListEnable When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
1, 0
CBSR[1:0]
00
R/W
ControlBulkServiceRatio Specify the number of Control Endpoints serviced for every Bulk Endpoint. Encoding is N-1 where N is the number of Control Endpoints (i.e. '00' = 1 Control Endpoint; '11' = 4 Control Endpoints)
Rev. 1.00 Oct. 01, 2007 Page 1464 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.3
HcCommandStatus Register (USBHCS)
Bit : 31 -- 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 BLF 0 R/W 17 16
SOC[1:0] 0 R 1 CLF 0 R/W 0 R 0 HCR 0 R/W
Initial value : R/W : Bit : Initial value : R/W :
0 R 15 -- 0 R
Bit 31 to 18
Bit Name
Initial Value R/W All 0 R
Description Reserved These bits are always read as 0. The write value should always be 0
17, 16
SOC[1:0]
All 0
R
ScheduleOverrunCount These bits increment every time the SchedulingOverrun bit in HcInterruptStatus is set. The count wraps from 11 to 00.
15 to 3
All 0
R
Reserved These bits are always read as 0. The write value should always be 0
2
BLF
0
R/W
BulkListFilled When set, this bit indicates there is an active ED on the Bulk List. The bit can be set by either software or the Host Controller. The bit is cleared by the Host Controller each time it begins processing the head of the Bulk List.
1
CLF
0
R/W
ControlListFilled When set, this bit indicates there is an active ED on the Control List. The bit can be set by either software or the Host Controller. The bit is cleared by the Host Controller each time it begins processing the head of the Control List.
Rev. 1.00 Oct. 01, 2007 Page 1465 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Bit 0
Bit Name HCR
Initial Value R/W 0 R/W
Description HostControllerReset This bit is set to initiate a software reset. This bit is cleared by the Host Controller upon completion of the reset operation.
35.3.4
HcInterruptStatus Register (USBHIS)
All bits are set by hardware and cleared by software. These bits in this register can be cleared by writing 1 to bit positions to be cleared.
Bit : Initial value : R/W : Bit : Initial value : R/W : 31 -- 0 R 15 -- 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 0 R/W 21 -- 0 R 5 0 R/W 20 -- 0 R 4 UE 0 R/W 19 -- 0 R 3 RD 0 R/W 18 -- 0 R 2 SF 0 R/W 17 -- 0 R 1 WDH 0 R/W 16 -- 0 R 0 SO 0 R/W
RHSC FNO
Bit 31 to 7
Bit Name
Initial Value R/W All 0 R
Description Reserved These bits are always read as 0. The write value should always be 0
6
RHSC
0
R/W
RootHubStatusChange This bit is set when the content of HcRhStatus register or the content of any HcRhPortStatus register has changed.
5
FNO
0
R/W
FrameNumberOverflow This bit is set when bit 15 of FrameNumber changes value from 0 to 1 or from 1 to 0.
4
UE
0
R/W
UnrecoverableError This bit is set when HC detects a system error that is not USB related.
3
RD
0
R/W
ResumeDetected This bit is set when the Host Controller detects resume signaling on a downstream port.
Rev. 1.00 Oct. 01, 2007 Page 1466 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Bit 2
Bit Name SF
Initial Value R/W 0 R/W
Description StartofFrame This bit is set when the Frame manager signals a Start of Frame's event.
1
WDH
0
R/W
WritebackDoneHead This bit is set after the Host Controller has written the value of HcDoneHead register to HccaDoneHead.
0
SO
0
R/W
SchedulingOverrun This bit is set when the List Processor determines a Schedule Overrun has occurred.
Rev. 1.00 Oct. 01, 2007 Page 1467 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.5
HcInterruptEnable Register (USBHIE)
Writing 1 to a bit in this register sets the corresponding bit, while writing a 0 to a bit leaves the bit unchanged.
Bit : 31 MIE Initial value : 0 R/W : R/W Bit : Initial value : R/W : 15 -- 0 R 30 OC 0 R/W 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 0 R/W 21 -- 0 R 5 0 R/W 20 -- 0 R 4 UE 0 R/W 19 -- 0 R 3 RD 0 R/W 18 -- 0 R 2 SF 0 R/W 17 -- 0 R 1 WDH 0 R/W 16 -- 0 R 0 SO 0 R/W
RHSC FNO
Bit 31
Bit Name MIE
Initial Value 0
R/W R/W
Description MasterInterruptEnable This bit is a global interrupt enable. Writing 1 allows interrupts to be enabled via the specific enable bits listed below.
30
OC
0
R/W
OwnershipChangeEnable 0: Ignored 1: Interrupt due to Ownership Change is enabled.
29 to 7
All 0
R
Reserved These bits are always read as 0. The write value should always be 0
6
RHCS
0
R/W
RootHubStatusChangeEnable 0: Ignored 1: Interrupt due to Root Hub Status Change is enabled.
5
FNO
0
R/W
FrameNumberOverflowEnable 0: Ignored 1: Interrupt due to Frame Number Overflow is enabled.
4 3
UE RD
0 0
R/W R/W
UnrecoverableErrorEnable This function is not supported. Writing is ignored. ResumeDetectedEnable 0: Ignored 1: Interrupt due to Resume Detected is enabled.
Rev. 1.00 Oct. 01, 2007 Page 1468 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Bit 2
Bit Name SF
Initial Value 0
R/W R/W
Description StartOfFrameEnable 0: Ignored 1: Interrupt due to Start of Frame is enabled.
1
WDH
0
R/W
WritebackDoneHeadEnable 0: Ignored 1: Interrupt due to Writeback Done Head is enabled.
0
SO
0
R/W
SchedulingOverrunEnable 0: Ignored 1: Interrupt due to Scheduling Overrun is enabled.
35.3.6
HcInterruptDisable Register (USBHID)
Writing 1 to a bit in this register clears the corresponding bit, while writing 0 to a bit leaves the bit unchanged.
Bit : 31 MIE Initial value : 0 R/W : R/W Bit : Initial value : R/W : 15 -- 0 R 30 OC 0 R/W 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 0 R/W 21 -- 0 R 5 0 R/W 20 -- 0 R 4 UE 0 R/W 19 -- 0 R 3 RD 0 R/W 18 -- 0 R 2 SF 0 R/W 17 -- 0 R 1 WDH 0 R/W 16 -- 0 R 0 SO 0 R/W
RHSC FNO
Bit 31
Bit Name MIE
Initial Value R/W 0 R/W
Description MasterInterruptDisable This bit is a global interrupt disable. Writing 1 disables all interrupts.
30
OC
0
R/W
OwnershipChangeDisable 0: Ignored 1: Interrupt due to Ownership Change is disabled.
29 to 7
All 0
R
Reserved These bits are always read as 0. The write value should always be 0
Rev. 1.00 Oct. 01, 2007 Page 1469 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Bit 6
Bit Name RHSC
Initial Value R/W 0 R/W
Description RootHubStatusChangeDisable 0: Ignored 1: Interrupt due to Root Hub Status Change is disabled.
5
FNO
0
R/W
FrameNumberOverflowDisable 0: Ignored 1: Interrupt due to Frame Number Overflow is disabled.
4 3
UE RD
0 0
R/W R/W
UnrecoverableErrorDisable This function is not supported. Writing is ignored. ResumeDetectedDisable 0: Ignored 1: Interrupt due to Resume Detected is disabled.
2
SF
0
R/W
StartOfFrameDisable 0: Ignored 1: Interrupt due to Start of Frame is disabled.
1
WDH
0
R/W
WritebackDoneHeadDisable 0: Ignored 1: Interrupt due to Writeback Done Head is disabled.
0
SO
0
R/W
SchedulingOverrunDisable 0: Ignored 1: Interrupt generation due to Scheduling Overrun is disabled.
Rev. 1.00 Oct. 01, 2007 Page 1470 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.7
HcHCCA Register (USBHHCCA)
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCCA[23:8] Initial value : 0 R/W : R/W Bit : 15 0 R/W 14 0 R/W 0 R/W 13 0 R/W 0 R/W 12 0 R/W 0 R/W 11 0 R/W 0 R/W 10 0 R/W 0 R/W 9 0 R/W 0 R/W 8 0 R/W 0 R/W 7 -- 0 R 0 R/W 6 -- 0 R 0 R/W 5 -- 0 R 0 R/W 4 -- 0 R 0 R/W 3 -- 0 R 0 R/W 2 -- 0 R 0 R/W 1 -- 0 R 0 R/W 0 -- 0 R
HCCA[7:0] Initial value : 0 R/W : R/W
Bit 31 to 8 7 to 0
Bit Name HCCA
Initial Value R/W All 0 All 0 R/W R
Description HCCA Pointer to HCCA base address. Reserved These bits are always read as 0. The write value should always be 0
35.3.8
HcPeriodCurrentED Register (USBHPCED)
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCED[27:12] Initial value : R/W : Bit : Initial value : R/W : 0 R 15 0 R 0 R 14 0 R 0 R 13 0 R 0 R 12 0 R 0 R 11 0 R 0 R 10 0 R 0 R 9 0 R 0 R 8 0 R 0 R 7 0 R 0 R 6 0 R 0 R 5 0 R 0 R 4 0 R 0 R 3 -- 0 R 0 R 2 -- 0 R 0 R 1 -- 0 R 0 R 0 -- 0 R
PCED[11:0]
Bit 31 to 4
Bit Name PCED
Initial Value R/W All 0 R
Description PeriodCurrentED Pointer to the current Periodic List ED. (Within Graphics Memory [Unified Memory] space)
3 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0
Rev. 1.00 Oct. 01, 2007 Page 1471 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.9
HcControlHeadED Register (USBHCHED)
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHED[27:12] Initial value : 0 R/W : R/W Bit : 15 0 R/W 14 0 R/W 0 R/W 13 0 R/W 0 R/W 12 0 R/W 0 R/W 11 0 R/W 0 R/W 10 0 R/W 0 R/W 9 0 R/W 0 R/W 8 0 R/W 0 R/W 7 0 R/W 0 R/W 6 0 R/W 0 R/W 5 0 R/W 0 R/W 4 0 R/W 0 R/W 3 -- 0 R 0 R/W 2 -- 0 R 0 R/W 1 -- 0 R 0 R/W 0 -- 0 R
CHED[11:0] Initial value : 0 R/W : R/W
Bit 31 to 4 3 to 0
Bit Name CHED
Initial Value R/W All 0 All 0 R/W R
Description ControlHeadED Pointer to the Control List Head ED. Reserved These bits are always read as 0. The write value should always be 0
35.3.10 HcControlCurrentED Register (USBHCCED)
Bit :
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CCED[27:12] Initial value : 0 R/W : R/W Bit : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
15
14
0 R/W
13
0 R/W
12
0 R/W
11
0 R/W
10
0 R/W
9
0 R/W
8
0 R/W
7
0 R/W
6
0 R/W
5
0 R/W
4
0 R/W
3
-- 0 R
2
-- 0 R
1
-- 0 R
0
-- 0 R
CCED[11:0] Initial value : 0 R/W : R/W
Bit 31 to 4 3 to 0
Bit Name CCED
Initial Value R/W All 0 All 0 R/W R
Description ControlCurrentED Pointer to the current Control List ED. Reserved These bits are always read as 0. The write value should always be 0
Rev. 1.00 Oct. 01, 2007 Page 1472 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.11 HcBulkHeadED Register (USBHBHED)
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BHED[27:12] Initial value : 0 R/W : R/W Bit : 15 0 R/W 14 0 R/W 0 R/W 13 0 R/W 0 R/W 12 0 R/W 0 R/W 11 0 R/W 0 R/W 10 0 R/W 0 R/W 9 0 R/W 0 R/W 8 0 R/W 0 R/W 7 0 R/W 0 R/W 6 0 R/W 0 R/W 5 0 R/W 0 R/W 4 0 R/W 0 R/W 3 -- 0 R 0 R/W 2 -- 0 R 0 R/W 1 -- 0 R 0 R/W 0 -- 0 R
BHED[11:0] Initial value : 0 R/W : R/W
Bit 31 to 4 3 to 0
Bit Name BHED
Initial Value All 0 All 0
R/W R/W R
Description BulkHeadED Pointer to the Bulk List Head ED. Reserved These bits are always read as 0. The write value should always be 0
35.3.12 HcBulkCurrentED Register (USBHBCED)
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BCED[27:12] Initial value : 0 R/W : R/W Bit : 15 0 R/W 14 0 R/W 0 R/W 13 0 R/W 0 R/W 12 0 R/W 0 R/W 11 0 R/W 0 R/W 10 0 R/W 0 R/W 9 0 R/W 0 R/W 8 0 R/W 0 R/W 7 0 R/W 0 R/W 6 0 R/W 0 R/W 5 0 R/W 0 R/W 4 0 R/W 0 R/W 3 -- 0 R 0 R/W 2 -- 0 R 0 R/W 1 -- 0 R 0 R/W 0 -- 0 R
BCED[11:0] Initial value : 0 R/W : R/W
Bit 31 to 4 3 to 0
Bit Name BCED
Initial Value All 0 All 0
R/W R/W R
Description BulkCurrentED Pointer to the current Bulk List ED. Reserved These bits are always read as 0. The write value should always be 0
Rev. 1.00 Oct. 01, 2007 Page 1473 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.13 HcDoneHead Register (USBHDHED)
Bit : Initial value : R/W : Bit : Initial value : R/W : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DH[27:12] 0 R 15 0 R 0 R 14 0 R 0 R 13 0 R 0 R 12 0 R 0 R 11 0 R 0 R 10 0 R 0 R 9 0 R 0 R 8 0 R 0 R 7 0 R 0 R 6 0 R 0 R 5 0 R 0 R 4 0 R 0 R 3 -- 0 R 0 R 2 -- 0 R 0 R 1 -- 0 R 0 R 0 -- 0 R
DH[11:0]
Bit 31 to 4 3 to 0
Bit Name DH
Initial Value R/W All 0 All 0 R R
Description DoneHead Pointer to the current Done List Head ED. Reserved These bits are always read as 0. The write value should always be 0
Rev. 1.00 Oct. 01, 2007 Page 1474 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.14 HcFmInterval Register (USBHFI)
Bit : 31 FIT Initial value : 0 R/W : R/W Bit : Initial value : R/W : 15 -- 0 R 0 R/W 14 -- 0 R 1 R/W 0 R/W 1 R/W 1 R/W 1 R/W 0 R/W 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSMPS[14:0] 0 R/W 8 0 R/W 7 1 R/W 0 R/W 6 1 R/W 0 R/W 5 0 R/W 0 R/W 4 1 R/W 0 R/W 3 1 R/W 0 R/W 2 1 R/W 0 R/W 1 1 R/W 0 R/W 0 1 R/W
FI[13:0]
Bit 31
Bit Name FIT
Initial Value 0
R/W R/W
Description FrameIntervalToggle This bit is toggled by Host Control Driver (HCD) whenever it loads a new value into FrameInterval bit.
30 to 16
FSMPS
All 0
R/W
FSLargestDataPacket These bits specify a value which is loaded into the Largest Data Packet Counter at the beginning of each frame.
15, 14
00
R
Reserved These bits are always read as 0. The write value should always be 0
13 to 0
FI
H'2EDF
R/W
FrameInterval These bits specify the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is specified.
Rev. 1.00 Oct. 01, 2007 Page 1475 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.15 HcFrameRemaining Register (USBHFR)
Bit : Initial value : R/W : Bit : Initial value : R/W : 31 FRT 0 R 15 -- 0 R 30 -- 0 R 14 -- 0 R 0 R 0 R 0 R 0 R 0 R 0 R 29 -- 0 R 13 28 -- 0 R 12 27 -- 0 R 11 26 -- 0 R 10 25 -- 0 R 9 24 -- 0 R 8 23 -- 0 R 7 0 R 22 -- 0 R 6 0 R 21 -- 0 R 5 0 R 20 -- 0 R 4 0 R 19 -- 0 R 3 0 R 18 -- 0 R 2 0 R 17 -- 0 R 1 0 R 16 -- 0 R 0 0 R
FR[13:0]
Bit 31
Bit Name FRT
Initial Value 0
R/W R
Description FrameRemainingToggle This bit is loaded with FrameIntervalToggle when FrameRemaining is loaded.
30 to 14
All 0
R
Reserved These bits are always read as 0. The write value should always be 0
13 to 0
FR
All0
R
FrameRemaining These bits are the 14-bit down counter used to time a frame. When the Host Controller is in the USB OPERATIONAL state, the counter decrements each 12 MHz clock period. When the count reaches 0, the end of a frame has been reached. The counter reloads with FrameInterval at that time. In addition, the counter reloads when the Host Controller transitions into USB OPERATIONAL.
Rev. 1.00 Oct. 01, 2007 Page 1476 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.16 HcFmNumber Register (USBHFN)
Bit : Initial value : R/W : Bit : Initial value : R/W : 31 -- 0 R 15 0 R 30 -- 0 R 14 0 R 29 -- 0 R 13 0 R 28 -- 0 R 12 0 R 27 -- 0 R 11 0 R 26 -- 0 R 10 0 R 25 -- 0 R 9 0 R 24 -- 0 R 8 0 R 23 -- 0 R 7 0 R 22 -- 0 R 6 0 R 21 -- 0 R 5 0 R 20 -- 0 R 4 0 R 19 -- 0 R 3 0 R 18 -- 0 R 2 0 R 17 -- 0 R 1 0 R 16 -- 0 R 0 0 R
FN[15:0]
Bit 31 to 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0
15 to 0
FN
All 0
R/W
FrameNumber These bits are the 16-bit up counter. The count is incremented coincident with the loading of FrameRemaining bit. The count will roll over from H'FFFF to H'0000
Rev. 1.00 Oct. 01, 2007 Page 1477 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.17 HcPeriodicStart Register (USBHPS)
Bit : Initial value : R/W : Bit : Initial value : R/W : 31 -- 0 R 15 -- 0 R 30 -- 0 R 14 -- 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 29 -- 0 R 13 28 -- 0 R 12 27 -- 0 R 11 26 -- 0 R 10 25 -- 0 R 9 24 -- 0 R 8 23 -- 0 R 7 0 R/W 22 -- 0 R 6 0 R/W 21 -- 0 R 5 0 R/W 20 -- 0 R 4 0 R/W 19 -- 0 R 3 0 R/W 18 -- 0 R 2 0 R/W 17 -- 0 R 1 0 R/W 16 -- 0 R 0 0 R/W
PS[13:0]
Bit 31 to 14
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0
13 to 0
PS
All 0
R/W
PeriodicStart These bits set a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
Rev. 1.00 Oct. 01, 2007 Page 1478 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.18 HcLSThreshold Register (USBHLST) (Not supporting LowSpeed mode)
Bit : Initial value : R/W : Bit : Initial value : R/W : 31 -- 0 R 15 -- 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 0 R/W 1 R/W 1 R/W 0 R/W 0 R/W 27 -- 0 R 11 26 -- 0 R 10 25 -- 0 R 9 24 -- 0 R 8 23 -- 0 R 7 22 -- 0 R 6 0 R/W 21 -- 0 R 5 1 R/W 20 -- 0 R 4 0 R/W 19 -- 0 R 3 1 R/W 18 -- 0 R 2 0 R/W 17 -- 0 R 1 0 R/W 16 -- 0 R 0 0 R/W
LST[11:0]
Bit 31 to 12
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0
11 to 0
LST
H'628
R/W
LSThreshold These bits are a value used by the Frame manager to determine whether or not a low speed transaction can be started in the current frame.
Rev. 1.00 Oct. 01, 2007 Page 1479 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.19 HcRhDescriptorA Register (USBHRDA) (Only one port is supported by this LSI.) This register is only reset by a power-on reset. It is written during system initialization to configure the Root Hub. These bits should not be written during normal operation.
Bit : 31 30 29 28 27 26 25 24 23 -- 0 R/W 10 0 R 1 R/W 9 NPS 0 R/W 0 R/W 8 PSM 0 R/W 0 R 0 R 0 R 0 R 7 22 -- 0 R 6 21 -- 0 R 5 20 -- 0 R 4 0 R 19 -- 0 R 3 0 R 18 -- 0 R 2 0 R 17 -- 0 R 1 1 R 16 -- 0 R 0 0 R
POTPGT[7:0] Initial value : 0 R/W : R/W Bit : Initial value : R/W : 15 -- 0 R 0 R/W 14 -- 0 R 0 R/W 13 -- 0 R 0 R/W 12 1 R/W 0 R/W 11 0 R/W
NOCP OCPM DT
NDP[7:0]
Bit 31 to 24
Bit Name POTPGT
Initial Value H'02
R/W R/W
Description PowerOnToPowerGoodTime USB Host Controller power switching is effective within 2 ms. The bit value is represented as the number of 2 ms intervals. Only bits 25 and 24 can be written to. The remaining bits are read only as '0'. It is not expected that these bits be written to anything other than 1h, but limited adjustment is allowed. These bits should be written to support the system implementation. These bits should always be written to a non-zero value.
23 to 13
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
12
NOCP
1
R/W
NoOverCurrentProtection USB Host Controller implements global overcurrent reporting 0: Over-current status is reported 1: Over-current status is not reported This bit should be written to support the external system port over-current implementation.
Rev. 1.00 Oct. 01, 2007 Page 1480 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Bit 11
Bit Name OCPM
Initial value 0
R/W R/W
Description OverCurrentProtectionMode USB Host Controller implements global over-current reporting 0: Global Over-Current is reported. 1: Individual Over-Current is reported.This bit is only valid when NoOverCurrentProtection bit is cleared. Write 0 to this bit.
10 9
DT NPS
0 0
R R/W
DeviceType USB Host Controller is not a composite device. NoPowerSwitching USB Host Controller implements global power switching. 0: Ports are power switched. 1: Ports are always powered on.This bit should be written to support the external system port power switching implementation.
8
PSM
0
R/W
PowerSwitchingMode USB Host Controller implements a global power switching mode. 0: Global Switching 1: Individual SwitchingThis bit is only valid when NoPowerSwitching is cleared. Write 0 to this bit.
7 to 0
NDP
H'02
R
NumberDownstreamPorts USB Host Controller supports one downstream port. (Only one port is supported although two ports are mentioned.)
Rev. 1.00 Oct. 01, 2007 Page 1481 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.20 HcRhDescriptorB Register (USBHRDB) (Only one port is supported by this LSI.) This register is only reset by a power-on reset. It is written during system initialization to configure the Root Hub. These bits should not be written during normal operation.
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PPCM[15:0] Initial value : 0 R/W : R/W Bit : 15 0 R/W 14 0 R/W 0 R/W 13 0 R/W 0 R/W 12 0 R/W 0 R/W 11 0 R/W 0 R/W 10 0 R/W 0 R/W 9 0 R/W 0 R/W 8 0 R/W 0 R/W 7 0 R/W 0 R/W 6 0 R/W 0 R/W 5 0 R/W 0 R/W 4 0 R/W 0 R/W 3 0 R/W 0 R/W 2 0 R/W 0 R/W 1 0 R/W 0 R/W 0 0 R/W
DR[15:0] Initial value : 0 R/W : R/W
Bit 31 to 16
Bit Name PPCM
Initial value R/W All 0 R/W
Description PortPowerControlMask USB Host Controller implements global-power switching. These bits are only valid if NoPowerSwitching is cleared and PowerSwitchingMode bit is set (individual port switching). When set, the port only responds to individual port power switching commands (Set/ClearPortPower). When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower). 0: Device not removable 1: Global-power switching is masked Port Bit relationship 0: Reserved 1: Port 1 2: Port 2 : 15: Port 15 Unimplemented ports are reserved. These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1482 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Bit 15 to 0
Bit Name DR
Initial value R/W All 0 R/W
Description DeviceRemovableUSB Host Controller ports default to removable devices. 0: Device removable 1: Device not removable Port Bit relationship 0: Reserved 1: Port 1 2: Port 2 : 15: Port 15 Unimplemented ports are reserved. These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1483 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.21 HcRhStatus Register (USBHRS) This register is reset by the UsbReset state.
Bit : Initial value : R/W : Bit : 31 CRWE W 15 DRWE Initial value : 0 R/W : R/W 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 16
OCIC LPSC 0 R/W 1 OCI 0 R 0 R/W 0 LPS 0 R/W
Bit 31
Bit Name CRWE
Initial value
R/W Description W (write) ClearRemoteWakeupEnable Writing 1 to this bit clears DeviceRemoteWakeupEnable bit. Writing 0 has no effect
30 to 18
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
17
OCIC
0
R/W OverCurrentIndicatorChange This bit is set when OverCurrentIndicator changes. Writing 1 clears this bit. Writing 0 has no effect.
16
LPSC
0
R/W (read) LocalPowerStatusChange Not supported by this LSI. The read value should always be 0. (write) SetGlobalPower Write 1 issues a SetGlobalPower command to the ports. Writing 0 has no effect.
15
DRWE
0
R/W (read) DeviceRemoteWakeupEnable This bit enables ports' ConnectStatusChange as a remote wakeup event. 0: disabled 1: enabled (write) SetRemoteWakeupEnable Writing 1 sets DeviceRemoteWakeupEnable bit. Writing 0 has no effect.
Rev. 1.00 Oct. 01, 2007 Page 1484 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Bit 14 to 2
Bit Name
Initial value All 0
R/W Description R Reserved These bits are always read as 0. The write value should always be 0.
1
OCI
0
R
OverCurrentIndicator This bit reflects the state of the OVRCUR pin. This bit is only valid if NoOverCurrentProtection and OverCurrentProtectionMode bits are cleared. 0: No over-current condition 1: Over-current condition
0
LPS
0
R/W (read) LocalPowerStatus Not Supported by this LSI. The read value should be 0. (write) ClearGlobalPower Writing 1 issues a ClearGlobalPower command to the ports. Writing 0 has no effect.
Rev. 1.00 Oct. 01, 2007 Page 1485 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.3.22 HcRhPortStatus[2] Register (USBHRPS2) This register is reset by the UsbReset state.
Bit : Initial value : R/W : Bit : Initial value : R/W : 31 -- 0 R 15 -- 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- R/W 24 -- 0 R 8 0 R/W 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 19 18 17 16
PRSC OCIC PSSC PESC CSC 0 R/W 4 0 R/W 0 R/W 3 0 R/W 0 R/W 2 0 R/W 0 R/W 1 PES 0 R/W 0 R/W 0 CCS 0 R/W
LSDA PPS
PRS POCI PSS
Bit 31 to 21
Bit Name
Initial value All 0
R/W Description R Reserved These bits are always read as 0. The write value should always be 0.
20
PRSC
0
R/W PortResetStatusChange This bit indicates that the port reset signal has completed. 0: Port reset is not complete. 1: Port reset is complete.
19
OCIC
0
R/W PortOverCurrentIndicatorChange This bit is set when OverCurrentIndicator changes. Writing 1 clears this bit. Writing 0 has no effect.
18
PSSC
0
R/W PortSuspendStatusChange This bit indicates the completion of the selective resume sequence for the port. 0: Port is not resumed. 1: Port resume is complete.
17
PESC
0
R/W PortEnableStatusChange This bit indicates that the port has been disabled due to a hardware event (PortEnableStatus bit is cleared). 0: Port has not been disabled. 1: PortEnableStatus bit has been cleared.
Rev. 1.00 Oct. 01, 2007 Page 1486 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Bit 16
Bit Name Initial value R/W CSC 0 R/W
Description ConnectStatusChange This bit indicates a connection or disconnection event has been detected. Writing 1 clears this bit. Writing 0 has no effect. 0: No connect/disconnect event. 1: Hardware detection of connect/disconnect event. Note: If DeviceRemoveable is set, this bit resets to 1.
15 to 10
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9
LSDA
Undefined*
R/W
(read) LowSpeedDeviceAttached This bit defines the speed (and bus idle) of the attached device. It is only valid when CurrentConnectStatus is set. 0: Full Speed device 1: Low Speed device (write) ClearPortPower Writing 1 clears PortPowerStatus bit. Writing 0 has no effect
8
PPS
0
R/W
(read) PortPowerStatus This bit reflects the power state of the port regardless of power switching mode. 0: Port power is off. 1: Port power is on. Note: If NoPowerSwitching bit is set, the read value should always be 0. (write) SetPortPower Writing 1 sets PortPowerStatus bit. Writing 0 has no effect.
7 to 5
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1487 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Bit 4
Bit Name Initial value R/W PRS 0 R/W
Description (read) PortResetStatus 0: Port reset signal is not active. 1: Port reset signal is active. (write) SetPortReset Writing 1 sets PortResetStatus bit. Writing 0 has no effect.
3
POCI
0
R/W
(read) PortOverCurrentIndicator USB Host Controller supports global over-current reporting. This bit reflects the state of the OVRCUR pin dedicated to this port. This bit is only valid if NoOverCurrentProtection bit is cleared and OverCurrentProtectionMode is set. 0: No over-current condition 1: Over-current condition (write) ClearSuspendStatus Writing 1 initiates the selective resume sequence for the port. Writing 0 has no effect.
2
PSS
0
R/W
(read) PortSuspendStatus 0: Port is not suspended 1: Port is selectively suspended (write) SetPortSuspend Writing 1 sets PortSuspendStatus bit. Writing 0 has no effect.
1
PES
0
R/W
(read) PortEnableStatus 0: Port disabled. 1: Port enabled. (write) SetPortEnable Writing 1 sets PortEnableStatus bit. Writing 0 has no effect.
Rev. 1.00 Oct. 01, 2007 Page 1488 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Bit 0
Bit Name Initial value R/W CCS 0 R/W
Description (read) CurrentConnectStatus 0: No device connected. 1: Device connected. Note: If DeviceRemoveable bit is set (not removable) this bit is always read as 1. (write) ClearPortEnable Writing 1 clears PortEnableStatus bit. Writing 0 has no effect.
Note:
*
Will have an effect on the status of the transceiver.
35.3.23 ConfigurationControl Register (USBHSC)
Bit : Initial value : R/W : Bit : Initial value : R/W : 31 -- 0 R 15 -- 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16 -- 0 R 0 PS 1 R/W
Bit 31 to 1
Bit Name
Initial value R/W All 0 R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
PS
1
R/W
Port Switch 0: Host 1: Function
Note: When the function module and the host module are switched by Port Switch bit, if the USB_PWREN pin is used, use the procedure below.
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Section 35 USB Host Controller (USBH)
Situation Switch to the function module (This module is selected in USB Function as default value after power-on sequence)
Procedure Check the status as follows:* * Set the PortSwitch bit to 1 after matching the polarity between the PULLUPE bit in the USB function module and the PortPowerStatus bit in the USB host module. There is no need to match the polarity if the PULLUPE bit is already ON after the USB function module is started.
*
Rev. 1.00 Oct. 01, 2007 Page 1490 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.4
35.4.1 (1)
Functional Description
General Functionality
USB Host Module
The USB Host module includes the integrated Root Hub with an external port as well as the List Processing (LP), the Serial Interface Engine (SIE) and USB clock divider. The interface combines the responsibility for executing bus transactions requested by the HC as well as the hub and port management specified by USB. Application interface converts HCI interface to Peripheral bus interface and SuperHyway bridge bus interface. USB Host module supports OpenHCI registers. Data transfer is performed on SuperHyway bridge bus interface between External memory and USB host module. Registers in USB host module are controlled via Peripheral bus interface. Endpoint Descriptor(ED) and Transfer Descriptor(TD) need to be stored in External memory before the data transaction begins. 1. List Processor The List Processor consists of four main blocks. The four blocks are the List Control block, the ED block, the TD block, and the Request block. The first three blocks operate in a lock step fashion with the List Control block triggering the ED block, which in turn triggers the TD block. These blocks are responsible for issuing their own bus master requests to the Request block which interfaces to the Host Controller Bus Master. 2. Serial Interface Engine (SIE) The SIE is responsible for managing all transactions to the USB. It controls the bus protocol, packet generation/extraction, data parallel-to-serial conversion, CRC coding, bit stuffing, and NRZI encoding. All transactions on the USB are requested by the List Processor and Frame Manager. After the List Processor retrieves all information necessary to initiate communication to a USB device, it generates a request to the SIE accompanied by endpoint-specific control information required to generate proper protocol and packet formats to establish the desired communication pipe. The data buffer provides a data path for the data packets and controls the number of bytes transferred. The FM generates SOF events each millisecond for which the SIE generates an SOF token. The List Processor requests are ignored to allow the SOF to be serviced with the highest priority and without any delay.
Rev. 1.00 Oct. 01, 2007 Page 1491 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
3. Root Hub (Only one port is supported by this LSI.) The Root Hub is a collection of ports which are individually controlled and a hub which maintains control/status over functions common to all ports. The typical command request interface to the hub is emulated by the Host Controller Device(HCD) which communicates directly through the system bus (PCI) to the hub and port controls. The remainder of this section will divide the discussion into hub and port design responsibilities. The Root Hub descriptor registers, HcRhDescriptorA and HcRhDescriptorB, are implemented R/W to allow multiple configuration with minimal changes to the current implementation. Hub and port indicate the control and the status through the HcRhStatus and HcRhPortStatus Registers. Each port has its own HcRhPortStatus Registers. A command structure is defined through these registers which software uses to control the hub and ports. By writing 1 to bit locations specified in section 35.3, Register Description, the following commands can be executed. The command functions are discussed in the following sections. * Hub Control The HC states also reflect the hub state. For example, when the HC is suspended, USB SUSPEND, the Root Hub is suspended. When the HC is in USB RESUME, the hub generates the appropriate bus signaling. USB RESET resets the Root Hub. The following sections describe hub and bus related controls and status. * Port Control The Port is responsible for all activities associated with driving and monitoring bus states. The HCD controls this behavior through the register command interface. * Clock Generation The USB interface is sourced by a 48 MHz clock which allows for a 4x data rate oversampling to maintain the receiver phase lock. This clock also sources all USB related clock rates (12 MHz). * Static SOF Clock As the USB system host, the system frame counter is maintained at a constant 1 ms interval. This requires a static 12 MHz clock. This is created by dividing down the 48 MHz internal clock source. The clock is enabled when the HC is not in the USB SUSPEND state. * Data Rate Clock The SIE requires that the transmit and receive clocks operate at 12 Hz. During FS transmissions, the data rate clock is equivalent to the static 12 MHz SOF clock. When receiving data, the data rate clock must match that of the source. Working in conjunction with the phase lock circuitry, the data rate clock is adjusted to maintain a 1 to 1 ratio of data bits and data clocks. This will result in periodic adjustment of the internal 48 MHz internal clock periods to maintain synchronization with the data source. When the packet is complete the data rate clock is re-linked to the static 12 MHz clock discussed above.
Rev. 1.00 Oct. 01, 2007 Page 1492 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
35.5
Connection Example of an External Circuit
Signal should be 3.3V (Also refer to the DC Characteristics section) This LSI USB_OVRCRT USB_PWREN
Power control LSI
5V GND
22
USBP
15k
D+
22
USBN
15k
D-
USB connector
Figure 35.2 Connection Example of External Circuit
35.6
35.6.1
Usage Notes
External memory that USBH accesses
In access from the USBH to the external memory controlled by LBSC, some access size combinations are not supported by the LBSC. Therefore, when a local bus area such as SRAM area is specifies as the external memory to be accessed by the USBH, the memory access by the USBH may stop. To avoid this, specify a DDR-SDRAM area as the external memory accessed by the USBH. 35.6.2 Issuing USB Bus Reset
When connection of an USB device is detected, do not use the HCFS[1:0] bits in the HcControl register to issue a USB Reset. Be sure to use the PRS bit (Port Reset) in the HcRhPortStatus register to issue a USB Reset.
Rev. 1.00 Oct. 01, 2007 Page 1493 of 1956 REJ09B0256-0100
Section 35 USB Host Controller (USBH)
Rev. 1.00 Oct. 01, 2007 Page 1494 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Section 36 USB Function Controller (USBF)
This LSI incorporates an USB function controller (USBF).
36.1
Features
* UDC (USB device controller) conforming to USB1.1 processes incorporated USB protocol automatically. Automatic processing of USB standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) * Transfer speed: Full-speed * Endpoint configuration: An arbitrary endpoint configuration can be set The arbitrary endpoint can be configured by setting the correspondence between the endpoint (the endpoint number used by the USB host) and the EP FIFO number that is provided by this USB function controller (the transfer method and direction are fixed).
EP FIFO Number Endpoint 0 Abbreviation Transfer Type EP0s EP0i EP0o Endpoint 1 Endpoint 2 Endpoint 3 Endpoint 4 Endpoint 5 EP1 EP2 EP3 EP4 EP5 Setup Control-in Control-out Bulk-out Bulk-in Interrupt Isochronous-out Isochronous-in Maximum Packet Size 8 8 8 64 64 8 64 64 FIFO Buffer Capacity (Byte) DMA Transfer 8 8 8 128 128 8 128 128 Possible Possible
* Interrupt requests: generates various interrupt signals necessary for USB transmission/reception * Clock: External input (48 MHz) * Power-down mode Power consumption can be reduced by stopping UDC internal clock when USB cable is disconnected Automatic transition to/recovery from suspend state * Supports self-powered mode
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Section 36 USB Function Controller (USBF)
Figure 36.1 shows the block diagram of USBF.
Peripheral bus
USB function controller
Interrupt requests DMA transfer requests
Status and control registers
UDC
Transceiver
USBP
USBM
Clock (48 MHz)
FIFO
[Legend] UDC: USB device controller
Figure 36.1 Block Diagram of USBF
Rev. 1.00 Oct. 01, 2007 Page 1496 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.2
Input/Output Pins
Table 36.1 lists the pin configuration of USBF. Table 36.1 Pin Configuration and Functions
Name Overcurrent pin / VBUS pin Clock pin Power enable pin P pin M pin Note: * Pin Name USB_OVRCRT/VSBF_VBUS USB_CLK USB_PWREN/USBF_UPLUP USBP USBM USB_CLK should be slower than Pck0. I/O Input Input Output I/O I/O Function USB port over-current detection/ USB cable connection monitor pin USB clock input pin (48 MHz input)* USB port power enable control/ Pull-up control output pin D+ D-
Rev. 1.00 Oct. 01, 2007 Page 1497 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3
Register Descriptions
Tables 36.2 (1) and (2) show the USBF register configuration when accessed in 8-bit units and 32bit units, respectively Table 36.3 shows the register state in each operating mode. Table 36.2 (1)
Register Name Interrupt flag register 0 Interrupt flag register 1 Interrupt flag register 2 Interrupt flag register 3 Interrupt enable register 0 Interrupt enable register 1 Interrupt enable register 2 Interrupt enable register 3 Interrupt select register 0 Interrupt select register 1 Interrupt select register 2 Interrupt select register 3 EP0i data register EP0o data register EP0s data register EP1 data register EP2 data register EP3 data register EP4 data register EP5 data register EP0o receive data size register
Register Configuration (Access Size = 8 bits)
Abbreviation IFR0 IFR1 IFR2 IFR3 IER0 IER1 IER2 IER3 ISR0 ISR1 ISR2 ISR3 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2 EPDR3 EPDR4 EPDR5 EPSZ0o Area P4 Address* H'FFEC 0001 H'FFEC 0005 H'FFEC 0009 H'FFEC 000D H'FFEC 0011 H'FFEC 0015 H'FFEC 0019 H'FFEC 001D H'FFEC 0021 H'FFEC 0025 H'FFEC 0029 H'FFEC 002D H'FFEC 0031 H'FFEC 0035 H'FFEC 0039 H'FFEC 0041 H'FFEC 0051 H'FFEC 0061 H'FFEC 0071 H'FFEC 0081 H'FFEC 0091 H'FFEC 0095 H'FFEC 0099 H'FFEC 009D Area 7 Address* H'1FEC 0001 H'1FEC 0005 H'1FEC 0009 H'1FEC 000D H'1FEC 0011 H'1FEC 0015 H'1FEC 0019 H'1FEC 009D H'1FEC 0021 H'1FEC 0025 H'1FEC 0029 H'1FEC 002D H'1FEC 0031 H'1FEC 0035 H'1FEC 0039 H'1FEC 0041 H'1FEC 0051 H'1FEC 0061 H'1FEC 0071 H'1FEC 0081 H'1FEC 0091 H'1FEC 0095 H'1FEC 0099 H'1FEC 009D Access size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
EP1 receive data size register EPSZ1 EP4 receive data size register EPSZ4 Data status register DASTS
Rev. 1.00 Oct. 01, 2007 Page 1498 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Register Name FIFO clear register 0 FIFO clear register 1 Endpoint stall register 0 Endpoint stall register 1 Trigger register DMA transfer setting register Configuration value register Control register 0 Time stamp register H Time stamp register L Endpoint information register Interrupt flag register 4 Interrupt enable register 4 Interrupt select register 4 Control register 1 Timer register H Timer register L Set time out register H Set time out register L
Abbreviation FCLR0 FCLR1 EPSTL0 EPSTL1 TRG DMA CVR CTLR0 TSRH TSRL EPIR IFR4 IER4 ISR4 CTLR1 TMRH TMRL STOH STOL
Area P4 Address* H'FFEC 00A1 H'FFEC 00A5 H'FFEC 00A9 H'FFEC 00AD H'FFEC 00B1 H'FFEC 00B5 H'FFEC 00B9 H'FFEC 00BD H'FFEC 00C1 H'FFEC 00C5 H'FFEC 00C9 H'FFEC 00D1 H'FFEC 00D5 H'FFEC 00D9 H'FFEC 00DD H'FFEC 00E1 H'FFEC 00E5 H'FFEC 00E9 H'FFEC 00ED
Area 7 Address* H'1FEC 00A1 H'1FEC 00A5 H'1FEC 00A9 H'1FEC 00AD H'1FEC 00B1 H'1FEC 00B5 H'1FEC 00B9 H'1FEC 00BD H'1FEC 00C1 H'1FEC 00C5 H'1FEC 00C9 H'1FEC 00D1 H'1FEC 00D5 H'1FEC 00D9 H'1FEC 00DD H'1FEC 00E1 H'1FEC 00E5 H'1FEC 00E9 H'1FEC 00ED
Access size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Rev. 1.00 Oct. 01, 2007 Page 1499 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Table 36.2 (2)
Register Name
Register Configuration (Access Size = 32 bits)
Abbreviation IFR0 IFR1 IFR2 IFR3 IER0 IER1 IER2 IER3 ISR0 ISR1 ISR2 ISR3 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2 EPDR3 EPDR4 EPDR5 EPSZ0o Area P4 Address* H'FFEC 0000 H'FFEC 0004 H'FFEC 0008 H'FFEC 000C H'FFEC 0010 H'FFEC 0014 H'FFEC 0018 H'FFEC 001C H'FFEC 0020 H'FFEC 0024 H'FFEC 0028 H'FFEC 002C H'FFEC 0030 H'FFEC 0034 H'FFEC 0038 H'FFEC 0040 H'FFEC 0050 H'FFEC 0060 H'FFEC 0070 H'FFEC 0080 H'FFEC 0090 H'FFEC 0094 H'FFEC 0098 H'FFEC 009C H'FFEC 00A0 H'FFEC 00A4 H'FFEC 00A8 H'FFEC 00AC H'FFEC 00B0 Area 7 Address* H'1FEC 0000 H'1FEC 0004 H'1FEC 0008 H'1FEC 000C H'1FEC 0010 H'1FEC 0014 H'1FEC 0018 H'1FEC 001C H'1FEC 0020 H'1FEC 0024 H'1FEC 0028 H'1FEC 002C H'1FEC 0030 H'1FEC 0034 H'1FEC 0038 H'1FEC 0040 H'1FEC 0050 H'1FEC 0060 H'1FEC 0070 H'1FEC 0080 H'1FEC 0090 H'1FEC 0094 H'1FEC 0098 H'1FEC 009C H'1FEC 00A0 H'1FEC 00A4 H'1FEC 00A8 H'1FEC 00AC H'1FEC 00B0 Access size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Interrupt flag register 0 Interrupt flag register 1 Interrupt flag register 2 Interrupt flag register 3 Interrupt enable register 0 Interrupt enable register 1 Interrupt enable register 2 Interrupt enable register 3 Interrupt select register 0 Interrupt select register 1 Interrupt select register 2 Interrupt select register 3 EP0i data register EP0o data register EP0s data register EP1 data register EP2 data register EP3 data register EP4 data register EP5 data register EP0o receive data size register
EP1 receive data size register EPSZ1 EP4 receive data size register EPSZ4 Data status register FIFO clear register 0 FIFO clear register 1 Endpoint stall register 0 Endpoint stall register 1 Trigger register DASTS FCLR0 FCLR1 EPSTL0 EPSTL1 TRG
Rev. 1.00 Oct. 01, 2007 Page 1500 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Register Name DMA transfer setting register Configuration value register Control register 0 Time stamp register H Time stamp register L Endpoint information register Interrupt flag register 4 Interrupt enable register 4 Interrupt select register 4 Control register 1 Timer register H Timer register L Set time out register H Set time out register L Note: *
Abbreviation DMA CVR CTLR0 TSRH TSRL EPIR IFR4 IER4 ISR4 CTLR1 TMRH TMRL STOH STOL
Area P4 Address* H'FFEC 00B4 H'FFEC 00B8 H'FFEC 00BC H'FFEC 00C0 H'FFEC 00C4 H'FFEC 00C8 H'FFEC 00D0 H'FFEC 00D4 H'FFEC 00D8 H'FFEC 00DC H'FFEC 00E0 H'FFEC 00E4 H'FFEC 00E8 H'FFEC 00EC
Area 7 Address* H'1FEC 00B4 H'1FEC 00B8 H'1FEC 00BC H'1FEC 00C0 H'1FEC 00C4 H'1FEC 00C8 H'1FEC 00D0 H'1FEC 00D4 H'1FEC 00D8 H'1FEC 00DC H'1FEC 00E0 H'1FEC 00E4 H'1FEC 00E8 H'1FEC 00EC
Access size 32 32 32 32 32 32 32 32 32 32 32 32 32 32
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
Rev. 1.00 Oct. 01, 2007 Page 1501 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Table 36.3 Register State in Each Operating Mode
Register Name Abbreviation Power-On Reset Manual Reset Sleep Standby
Interrupt flag register 0 Interrupt flag register 1 Interrupt flag register 2 Interrupt flag register 3 Interrupt enable register 0 Interrupt enable register 1 Interrupt enable register 2 Interrupt enable register 3 Interrupt select register 0 Interrupt select register 1 Interrupt select register 2 Interrupt select register 3 EP0i data register EP0o data register EP0s data register EP1 data register EP2 data register EP3 data register EP4 data register EP5 data register EP0o receive data size register EP1 receive data size register EP4 receive data size register Data status register FIFO clear register 0 FIFO clear register 1 Endpoint stall register 0 Endpoint stall register 1 Trigger register
IFR0 IFR1 IFR2 IFR3 IER0 IER1 IER2 IER3 ISR0 ISR1 ISR2 ISR3 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2 EPDR3 EPDR4 EPDR5 EPSZ0o EPSZ1 EPSZ4 DASTS FCLR0 FCLR1 EPSTL0 EPSTL1 TRG
H'xxxx xx10 H'xxxx xx10 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx03 H'xxxx xx03 Retained H'xxxx xx1F H'xxxx xx1F Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx Retained Retained Retained Retained Retained Retained Retained Retained
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained H'xxxx xx00 H'xxxx xx00 Retained
Rev. 1.00 Oct. 01, 2007 Page 1502 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Register Name
Abbreviation
Power-On Reset
Manual Reset Sleep
Standby
DMA transfer setting register Configuration value register Control register 0 Time stamp register H Time stamp register L Endpoint information register Interrupt flag register 4 Interrupt enable register 4 Interrupt select register 4 Control register 1 Timer register H Timer register L Set time out register H Set time out register L
DMA CVR CTLR0 TSRH TSRL EPIR IFR4 IER4 ISR4 CTLR1 TMRH TMRL STOH STOL
H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xxxx H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx02 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00 H'xxxx xx00
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 1503 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.1
Interrupt Flag Register 0 (IFR0)
IFR0 is an interrupt flag register for EP0i, EP1, EP2, bus reset, and setup command reception. When each flag is set to 1 and interrupt is enabled in the corresponding bit of IER0, an interrupt request (USBF10 or USB11) specified by the corresponding bit in ISR0 is issued to INTC. Clearing the flag is performed by writing 0. Writing 1 is not valid and nothing is changed. To clear bits, access the register so that 0 should be only to the bits for the interrupt sources to be cleared and that 1 should be written to the other bits. Do not use a bit field declaration of the C language to clear bits. EP2 EMPTY and EP1 FULL are status bits that indicate the FIFO states of EP1 and EP2, respectively. Therefore, EP2 EMPTY and EP1 FULL cannot be cleared.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
BRST
-- -- R 6
EP1 FULL
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
EP0I TR
-- -- R 0
EP0I TS
EP2 EP2 SETUP EP0O TR EMPTY TS TS
0 R/W
0 R
0 R/W
1 R
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value Undefined
R/W Description R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7
BRST
0
R/W Bus Reset [Setting condition] When a bus reset signal is detected on the USB bus. [Clearing conditions] * * When reset When 0 is written to by CPU
Rev. 1.00 Oct. 01, 2007 Page 1504 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Bit 6
Bit Name EP1 FULL
Initial Value 0
R/W Description R EP1 (Bulk-out) FIFO Full [Setting condition] The FIFO buffer of EP1 has a dual-buffer configuration, and this bit is set when at least one of the FIFO buffer is full. [Setting conditions] * When reset * When both FIFO buffers are empty. Note: EP1 FULL is a status bit, and cannot be cleared.
5
EP2 TR
0
R/W EP2 (Bulk-in) Transfer Request [Setting condition] When an IN token is received from the host to EP2 and both of FIFO buffers are empty. [Clearing conditions] * * When reset When 0 is written to by CPU
4
EP2 EMPTY
1
R
EP2 (Bulk-in) FIFO Empty [Setting conditions] * * When reset The FIFO buffer of EP2 has a dual-buffer configuration, and this bit is set when at least one of the FIFO buffer is empty.
[Clearing condition] When both of FIFO buffers are not empty. Note: EP2 EMPTY is a status bit, and cannot be cleared.
Rev. 1.00 Oct. 01, 2007 Page 1505 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Bit 3
Bit Name SETUP TS
Initial Value 0
R/W Description R/W Setup Command Receive Complete [Setting condition] When 8-byte data that decodes the command by the function is normally received from the host to EP0s and an ACK handshake is returned to the host from the function. [Clearing conditions] * * When reset When 0 is written to by CPU
2
EP0o TS
0
R/W EP0o Receive Complete [Setting condition] When data is normally received from the host to EP0o and an ACK handshake is returned from the function to the host. [Clearing conditions] * * When reset When 0 is written to by CPU
1
EP0i TR
0
R/W EP0i Transfer Request [Setting condition] When IN token is issued from the host to EP0i and the FIFO buffer is empty. [Clearing conditions] * * When reset When 0 is written to by CPU
0
EP0i TS
0
R/W EP0i Transmit Complete [Setting condition] When data to be transmitted to the host is written to EP0i, then data is normally transferred from the function to the host, and an ACK handshake is returned. [Clearing conditions] * * When reset When 0 is written to by CPU
Rev. 1.00 Oct. 01, 2007 Page 1506 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.2
Interrupt Flag Register 1 (IFR1)
IFR1 is an interrupt flag register for VBUS and EP3. When each flag is set to 1 and an interrupt is enabled in the corresponding bit of IER1, an interrupt request (USBFI0 or USBFI1) specified by the corresponding bit in ISR1 is issued to INTC. Clearing the flag is performed by writing 0. Writing 1 is not valid and nothing is changed. To clear bits, access the register so that 0 should be written only to the bits for the interrupt sources to be cleared and that 1 should be written to the other bits. Do not use a bit field declaration of the C language to clear bits.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3
VBUS MN
-- -- R 2
EP3 TR
-- -- R 1
EP3 TS
-- -- R 0
VBUSF
0 R
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value Undefined
R/W Description R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 4
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
3
VBUS MN 0
R
USB Connection Status Status bit to monitor the USBF_VBUS pin state. Reflects the state of the USBF_VBUS pin. 0: Disconnected 1: Connected
Rev. 1.00 Oct. 01, 2007 Page 1507 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Bit 2
Bit Name EP3 TR
Initial Value 0
R/W R/W
Description EP3 (Interrupt) Transfer Request [Setting condition] When an IN token is issued from the host to EP3 and the FIFO buffer is empty. [Clearing conditions] * * When reset When 0 is written to by CPU
1
EP3 TS
0
R/W
EP3 (Interrupt) Transmit Complete [Setting condition] When data to be transmitted to the host is written to EP3, then data is normally transferred from the host to the function, and an ACK handshake is returned. [Clearing conditions] * * When reset When 0 is written to by CPU
0
VBUSF
0
R/W
USB Disconnection Detection The USBF_VBUS pin of this module is used for detecting connection/disconnection. [Setting condition] When the function is connected to the USB bus or disconnected from it. [Clearing conditions] * * When reset When 0 is written to by CPU.
Rev. 1.00 Oct. 01, 2007 Page 1508 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.3
Interrupt Flag Register 2 (IFR2)
IFR2 is an interrupt flag register for SURSS, SURSF, CFDN, SOF SETC, and SETI. When each flag is set to 1 and an interrupt is enabled in the corresponding bit of IER2, an interrupt request (USBFI0 or USBFI1) specified by the corresponding bit in ISR2 is issued to INTC. Clearing the flag is performed by writing 0. Writing 1 is not valid and nothing is changed. To clear bits, access the register so that 0 should be written only to the bits for the interrupt sources to be cleared and that 1 should be written to the other bits. Do not use a bit field declaration of the C language to clear bits.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
SOF
-- -- R 1
SETC
-- -- R 0
SETI
SURSS SURSF CFDN
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value Undefined
R/W Description R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7, 6
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
5
SURSS
0
R
Suspend/Resume Status Status bit indicating the state of the bus 0: Normal state 1: Suspend state
Rev. 1.00 Oct. 01, 2007 Page 1509 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Bit 4
Bit Name SURSF
Initial Value 0
R/W Description R/W Suspend/Resume Detection [Setting condition] When the bus transits from the normal state to the suspend state or from the suspend state to the normal state. [Clearing conditions] * * When reset When 0 is written to by CPU
3
CFDN
0
R/W End Point Information Load Complete [Setting condition] When the end point information written in EPIR is completed to be set (loaded) in this controller. Note: This controller operates normally as USB after the setting of the end point information is completed. [Clearing conditions] * * When reset When 0 is written to by CPU
2
SOF
0
R/W SOF Packet [Setting condition] When the valid SOF packet is detected. [Clearing conditions] * * When reset When 0 is written to by CPU
1
SETC
0
R/W Set Configuration Command Detection [Setting condition] When the valid Set Configuration command is detected. [Clearing conditions] * * When reset When 0 is written to by CPU
Rev. 1.00 Oct. 01, 2007 Page 1510 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Bit 0
Bit Name SETI
Initial Value 0
R/W Description R/W Set Interface Command Detection [Setting condition] When the valid Set Interface command is detected. [Clearing conditions] * * When reset When 0 is written to by CPU
36.3.4
Interrupt Flag Register 3 (IFR3)
IFR3 is an interrupt flag register for EP4 TS, EP4 TF, EP5 TS, and EP5 TR. When each flag is set to 1 and an interrupt is enabled in the corresponding bit of IER3, an interrupt request (USBFI0 or USBFI1) specified by the corresponding bit in ISR3 is issued to INTC. Clearing the flag is performed by writing 0. Writing 1 is not valid and nothing is changed. To clear bits, access the register so that 0 should be written only to the bits for the interrupt sources to be cleared and that 1 should be written to the other bits. Do not use a bit field declaration of the C language to clear bits.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3 EP5 TR 0 R/W
-- -- R 2 EP5 TS 0 R/W
-- -- R 1 EP4 TF 0 R/W
-- -- R 0 EP4 TS 0 R/W
Bit
Bit Name
Initial Value Undefined
R/W Description R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 4
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1511 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Bit 3
Bit Name EP5 TR
Initial Value 0
R/W Description R/W EP5 (Isochronous-in) Transmit Request Flag indicating the FIFO state of EP5. After the SOF packet is received, the FIFO buffer is switched automatically. The FIFO buffer which has transmitted data to the host in the previous frame (before SOF reception) can be written to by the CPU. This bit indicates the transmit state in the previous frame. [Setting condition] The FIFO buffer to be transmitted is empty when an IN token is issued from the host to EP5. [Clearing conditions] * * When reset When 0 is written to by CPU
2
EP5 TS
0
R/W EP5 (Isochronous-in) Normal Transmission Flag indicating the FIFO state of EP5. After the SOF packet is received, the FIFO buffer is switched automatically. The FIFO buffer which has transmitted data to the host in the previous frame (before SOF reception) can be written to by the CPU. This bit indicates the transmit state in the previous frame. [Setting condition] When a transmission was carried out normally in the previous frame. [Clearing conditions] * * When reset When 0 is written to by CPU
Rev. 1.00 Oct. 01, 2007 Page 1512 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Bit 1
Bit Name EP4 TF
Initial Value 0
R/W Description R/W EP4 (Isochronous-out) Abnormal Reception Flag indicating the FIFO state of EP4. Indicates the state of the FIFO buffer that was readable after the data reception is completed and the next SOF packet is received. [Setting condition] When the transfer data from the host is abnormally received (packet error) by EP4. [Clearing conditions] * * When reset When 0 is written to by CPU
0
EP4 TS
0
R/W EP4 (Isochronous-out) Normal Reception Flag indicating the FIFO state of EP4. Indicates the state of the FIFO buffer that was readable after the data reception is completed and the next SOF packet is received. [Setting condition] When the transfer data from the host is normally received by EP4. [Clearing conditions] * * When reset When 0 is written to by CPU
Rev. 1.00 Oct. 01, 2007 Page 1513 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.5
Interrupt Flag Register 4 (IFR4)
IFR4 is an interrupt flag register for for TMOUT. When each flag is set to 1 and an interrupt is enabled in the corresponding bit of IER4, an interrupt request (USBFI0 or USBFI1) specified by the corresponding bit in ISR4 is issued to INTC. Clearing the flag is performed by writing 0. Writing 1 is not valid and nothing is changed. To clear bits, access the register so that 0 should be written only to the bits for the interrupt sources to be cleared and that 1 should be written to the other bits. Do not use a bit field declaration of the C language to clear bits.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3 -- 0 R
-- -- R 2 -- 0 R
-- -- R 1 -- 0 R
-- -- R 0
TMOUT
0 R/W
Bit
Bit Name
Initial Value Undefined
R/W Description R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
TMOUT
0
R/W Time Out [Setting condition] When the value of the timer register (TMR) is reached to that of the set time out register (STO). [Clearing conditions] * * When reset When 0 is written to by CPU
Rev. 1.00 Oct. 01, 2007 Page 1514 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.6
Interrupt Select Register 0 (ISR0)
ISR0 selects the interrupt request source (USBFI1 or USBFI0) to issue the interrupt requests indicated in IFR0 to INTC. When the corresponding bit in ISR0 is cleared to 0, the USBFI0 interrupt request is issued to INTC. When the bit is set to 1, the USBFI1 interrupt request is issued to INTC. In the initial value, each of interrupt source of the IFR0 is USBFI1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
BRST IS
-- -- R 6
EP1 FULL IS
-- -- R 5
EP2 TR IS
-- -- R 4
EP2 EMPTY IS
-- -- R 3
SETUP TS IS
-- -- R 2
EP0o TR IS
-- -- R 1
EP0i TR IS
-- -- R 0
EP0i TS IS
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value
R/W
Description Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
Undefined R
7 6 5 4 3 2 1 0
BRST IS EP1 FULL IS EP2 TR IS
0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
BRST Interrupt Select EP1 FULL Interrupt Select EP2 TR Interrupt Select EP2 EMPTY Interrupt Select SETUP Interrupt Select EP0o TS Interrupt Select EP0i TR Interrupt Select EP0i TS Interrupt Select
EP2 EMPTY IS 0 SETUP TS IS EP0o TS IS EP0i TR IS EP0i TS IS 0 0 0 0
Rev. 1.00 Oct. 01, 2007 Page 1515 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.7
Interrupt Select Register 1 (ISR1)
ISR1 selects the interrupt request source (USBFI1 or USBFI0) to issue the interrupt requests indicated in IFR1 to INTC. When the corresponding bit in ISR1 is cleared to 0, the USBFI0 interrupt request is issued to INTC. When the bit is set to 1, the USBFI1 interrupt request is issued to INTC. In the initial value, each of interrupt source of the IFR1 is USBFI1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3 -- 0 R
-- -- R 2
EP3 TR IS
-- -- R 1
-- -- R 0
EP3 VBUSF TS IS IS
1 R/W
1 R/W
1 R/W
Bit
Bit Name
Initial Value R/W Undefined R
Description Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 3
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
2 1 0
EP3 TR IS EP3 TS IS VBUSF IS
1 1 1
R/W R/W R/W
EP3 TR Interrupt Select EP3 TS Interrupt Select VBUSF Interrupt Select
Rev. 1.00 Oct. 01, 2007 Page 1516 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.8
Interrupt Select Register 2 (ISR2)
ISR2 selects the interrupt request source (USBFI1 or USBFI0) to issue the interrupt requests indicated in IFR2 to INTC. When the corresponding bit in ISR2 is cleared to 0, the USBFI0 interrupt request is issued to INTC. When the bit is set to 1, the USBFI1 interrupt request is issued to INTC. In the initial value, each of interrupt source of the IFR2 is USBFI1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
SURSE CFDN SOFE SETC SETIE IS IS IS IS IS
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit
Bit Name
Initial Value R/W Undefined R
Description Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 5
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4 3 2 1 0
SURSE IS CFDN IS SOFE IS SETCE IS SETIE IS
1 1 1 1 1
R/W R/W R/W R/W R/W
SURSE Interrupt Select CFDN Interrupt Select SOFE Interrupt Select SETCE Interrupt Select SETIE Interrupt Select
Rev. 1.00 Oct. 01, 2007 Page 1517 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.9
Interrupt Select Register 3 (ISR3)
ISR3 selects the interrupt request source (USBFI1 or USBFI0) to issue the interrupt requests indicated in IFR3 to INTC. When the corresponding bit in ISR3 is cleared to 0, the USBFI0 interrupt request is issued to INTC. When the bit is set to 1, the USBFI1 interrupt request is issued to INTC. In the initial value, each of interrupt source of the IFR3 is USBFI1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
EP5 TR EP5 TS EP4 TF EP4 TS IS IS IS IS
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value R/W Undefined R
Description Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 4
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
3 2 1 0
EP5 TR IS EP5 TS IS EP4 TF IS EP4 TS IS
0 0 0 0
R/W R/W R/W R/W
EP5 TR Interrupt Select EP5 TS Interrupt Select EP4 TF Interrupt Select EP4 TS Interrupt Select
Rev. 1.00 Oct. 01, 2007 Page 1518 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.10 Interrupt Select Register 4 (ISR4) ISR4 selects the interrupt request source (USBFI1 or USBFI0) to issue the interrupt requests indicated in IFR4 to INTC. When the corresponding bit in ISR4 is cleared to 0, the USBFI0 interrupt request is issued to INTC. When the bit is set to 1, the USBFI1 interrupt request is issued to INTC. In the initial value, each of interrupt source of the IFR4 is USBFI1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3 -- 0 R
-- -- R 2 -- 0 R
-- -- R 1 -- 0 R
-- -- R 0
TMOUT IS
0 R/W
Bit
Bit Name
Initial Value R/W Undefined R
Description Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
TMOUT IS
0
R/W
TMOUT Interrupt Select
Rev. 1.00 Oct. 01, 2007 Page 1519 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.11 Interrupt Enable Register 0 (IER0) IER0 enables the interrupt requests of the interrupt flag register 0. When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, the INTN interrupt request (USBFI0 or USBFI1) set in the ISR0 is issued.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
EP0i TR IE
-- -- R 0
EP0i TS IE
EP2 SETUP EP0o BRST EP1 EP2 IE FULL IE TR IE EMPTY IE TS IE TS IE
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 6 5 4 3 2 1 0
BRST IE EP1 FULL IE EP2 TR IE EP2 EMPTY IE
0 0 0 0
R/W BRST Interrupt Enable R/W EP1 FULL Interrupt Enable R/W EP2 TR Interrupt Enable R/W EP2 EMPTY Interrupt Enable R/W SETUP TS Interrupt Enable R/W EP0o TS Interrupt Enable R/W EP0i TR Interrupt Enable R/W EP0i TS Interrupt Enable
SETUP TS IE 0 EP0o TS IE EP0i TR IE EP0i TS IE 0 0 0
Rev. 1.00 Oct. 01, 2007 Page 1520 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.12 Interrupt Enable Register 1 (IER1) IER1 enables the interrupt requests of the IFR1. When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, the interrupt request (USBFI0 or USBFI1) set in the ISR1 is issued.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3 -- 0 R
-- -- R 2
EP3 TR IE
-- -- R 1
-- -- R 0
EP3 VBUSF TS IE IE
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 3
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
2 1 0
EP3 TR IE EP3 TS IE VBUSF IE
0 0 0
R/W EP3 TR Interrupt Enable R/W EP3 TS Interrupt Enable R/W VBUSF Interrupt Enable
Rev. 1.00 Oct. 01, 2007 Page 1521 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.13 Interrupt Enable Register 2 (IER2) IER2 enables the interrupt requests of the IFR2. When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, the interrupt request (USBFI0 or USBFI1) set in the ISR2 is issued.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
SURSE CFDN SOFE SETCE SETIE IE IE IE IE IE
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 5
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4 3 2 1 0
SURSE IE CFDN IE SOFE IE SETCE IE SETIE IE
0 0 0 0 0
R/W SURSE Interrupt Enable R/W CFDN Interrupt Enable R/W SOFE Interrupt Enable R/W SETCE Interrupt Enable R/W SETIE Interrupt Enable
Rev. 1.00 Oct. 01, 2007 Page 1522 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.14 Interrupt Enable Register 3 (IER3) IER3 enables the interrupt requests of the IFR3. When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, the interrupt request (USBFI0 or USBFI1) set in the ISR3 is issued.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
EP5 TR EP5 TS EP4 TE EP4 TS IE IE IE IE
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 4
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
3 2 1 0
EP5 TR IE EP5 TS IE EP4 TF IE EP4 TS IE
0 0 0 0
R/W EP5 TR Interrupt Enable R/W EP5 TS Interrupt Enable R/W EP4 TF Interrupt Enable R/W EP4 TS Interrupt Enable
Rev. 1.00 Oct. 01, 2007 Page 1523 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.15 Interrupt Enable Register 4 (IER4) IER4 enables the interrupt requests of the IFR4. When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, the interrupt request (USBFI0 or USBFI1) set in the ISR4 is issued.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3 -- 0 R
-- -- R 2 -- 0 R
-- -- R 1 -- 0 R
-- -- R 0
TMOUT IE
0 R/W
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
TMOUT IE
0
R/W TMOUT Interrupt Enable
Rev. 1.00 Oct. 01, 2007 Page 1524 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.16 EP0i Data Register (EPDR0i) EPDR0i is an 8-byte transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit data for control-in. Transmit data is fixed by writing one packet of data and setting EP0iPKTE in the trigger register. When an ACK handshake is returned from the host after the data has been transmitted, EP0iTS in interrupt flag register 0 is set. This FIFO buffer can be initialized by means of EP0iCLR in the FCLR0 register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
D[7:0] -- W -- W -- W -- W -- W -- W -- W -- W
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 0
D[7:0]
Undefined
W
Data register for control-in transfer
Rev. 1.00 Oct. 01, 2007 Page 1525 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.17 EP0o Data Register (EPDR0o) EPDR0o is an 8-byte receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive data other than setup commands. When data is received normally, EP0oTS in interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP0o receive data size register. After the data has been read, setting EP0oRDFN in the trigger register enables the next packet to be received. This FIFO buffer can be initialized by means of BP0oCLR in the FCLR0 register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
D[7:0] -- R -- R -- R -- R -- R -- R -- R -- R
Bit
Bit Name
Initial Value R/W Description Undefined Undefined R R Reserved These bits are always read as undefined value. Data register for control-out transfer
31 to 8 7 to 0 D[7:0]
Rev. 1.00 Oct. 01, 2007 Page 1526 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.18 EP0s Data Register (EPDR0s) EPDR0s is a data register specifically for endpoint 0 setup command. EPDR0s holds 8-byte command data sent in the setup stage. However, only the command to be processed by a microprocessor (firmware) is received. The command data to be processed automatically by this module is not stored. Since the setup command mast be received, previous data in the buffer is over written with new data. In other words, when the reception of data in the setup stage starts during read, reception has priority and read data is invalid.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
D[7:0] -- R -- R -- R -- R -- R -- R -- R -- R
Bit
Bit Name
Initial Value R/W Undefined Undefined R R
Description Reserved These bits are always read as undefined value. Data register for storing the setup command at the control-out transfer
31 to 8 7 to 0 D[7:0]
Note: The EPDR0s register should be read in longword units or eight consecutive times in byte units. If reading is stopped before it completes, data received in the subsequent setup stage is not read successfully.
Rev. 1.00 Oct. 01, 2007 Page 1527 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.19 EP1 Data Register (EPDR1) EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. The number of receive byte is displayed in the EP1 receive data size register. The buffer on read side can be received again by writing EP1RDFN in the trigger register to 1 after data is read. The receive data of this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized by means of EP1CLR in the FCLR0 register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
D[7:0] -- R -- R -- R -- R -- R -- R -- R -- R
Bit
Bit Name
Initial Value R/W Undefined Undefined R R
Description Reserved These bits are always read as undefined value. Data register for endpoint1 transfer
31 to 8 7 to 0 D[7:0]
Rev. 1.00 Oct. 01, 2007 Page 1528 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.20 EP2 Data Register (EPDR2) EPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. EPDR2 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO buffer and EP2PKTE in the trigger register is set, one packet of transmit data is fixed, and the dual-FIFO buffer is switched over. Transmit data for this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized by means of EP2CLR in the FCLR0 register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
D[7:0] -- W -- W -- W -- W -- W -- W -- W -- W
Bit
Bit Name
Initial Value R/W Undefined R
Description Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 0
D[7:0]
Undefined
W
Data register for endpoint 2 transfer
Rev. 1.00 Oct. 01, 2007 Page 1529 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.21 EP3 Data Register (EPDR3) EPDR3 is an 8-byte transmit FIFO buffer for endpoint 3. EPDR4 holds one packet of transmit data for the interrupt transfer of endpoint 3. Transmit data is fixed by writing one packet of data and setting EP3PKTE in the trigger register. When an ACK handshake is returned from the host after the data has been transmitted, EP3TS in interrupt flag register 1 is set. This FIFO buffer can be initialized by means of EP3CLR in the FCLR0 register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
D[7:0] -- W -- W -- W -- W -- W -- W -- W -- W
Bit
Bit Name
Initial Value R/W Undefined R
Description Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 0
D[7:0]
Undefined
W
Data register for endpoint 3 transfer
Rev. 1.00 Oct. 01, 2007 Page 1530 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.22 EP4 Data Register (EPDR4) EPDR4 is a 128-byte receive FIFO buffer for endpoint 4. EPDR4 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. The number of receive byte is displayed in the EP4 receive data size register. The receive data is fixed when an SOF packet is received. Accordingly, all receive data must be read until the next SOF packet is received. When the next SOF packet is received, the FIFO side is automatically switched over, and the previous data will not be possible to be read. This FIFO buffer can be initialized by means of EP4CLR in the FCLR1 register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
D[7:0] -- R -- R -- R -- R -- R -- R -- R -- R
Bit
Bit Name
Initial Value R/W Description Undefined Undefined R R Reserved These bits are always read as undefined value. Data register for endpoint 4 transfer
31 to 8 7 to 0 D[7:0]
Rev. 1.00 Oct. 01, 2007 Page 1531 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.23 EP5 Data Register (EPDR5) EPDR5 is a 128-byte transmit FIFO buffer for endpoint 5. EPDR5 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO buffer and an SOF packet is received, one packet of transmit data is fixed, and the dual-FIFO buffer is switched over. This FIFO buffer can be initialized by means of EP5CLR and EP5CCLR in the FCLR1 register. (EP5CLR initializes both FIFOs and EP5CCLR initializes one FIFO which is connected to the CPU.)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
D[7:0] -- W -- W -- W -- W -- W -- W -- W -- W
Bit
Bit Name
Initial Value Undefined
R/W Description R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 0
D[7:0]
Undefined
W
Data register for endpoint 5 transfer
Rev. 1.00 Oct. 01, 2007 Page 1532 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.24 EP0o Receive Data Size Register (EPSZ0o) EPSZ0o is a receive data size resister for endpoint 0o. EPSZ0o indicates the number of bytes received from the host.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R 1 --
-- -- R
Bit:
15 --
14 -- -- R
13 -- -- R
12 -- -- R
11 -- -- R
10 -- -- R
9 -- -- R
8 -- -- R
7
--
6
--
5
--
4
--
3
--
2
--
0
--
Initial value: R/W:
-- R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 0
All 0
R
Number of receive data for endpoint 0
Rev. 1.00 Oct. 01, 2007 Page 1533 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.25 EP1 Receive Data Size Register (EPSZ1) EPSZ1 is a receive data size resister for endpoint 1. EPSZ1 indicates the number of bytes received from the host. FIFO of endpoint 1 has a dual-buffer configuration. The size of the received data indicated by this register is the size of the currently selected side (can be read by CPU).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R 1 --
-- -- R
Bit:
15 --
14 -- -- R
13 -- -- R
12 -- -- R
11 -- -- R
10 -- -- R
9 -- -- R
8 -- -- R
7
--
6
--
5
--
4
--
3
--
2
--
0
--
Initial value: R/W:
-- R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit
Bit Name
Initial Value R/W Description Undefined All 0 R R Reserved These bits are always read as undefined value. Number of received bytes for endpoint 1
31 to 8 7 to 0
Rev. 1.00 Oct. 01, 2007 Page 1534 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.26 EP4 Receive Data Size Register (EPSZ4) EPSZ4 is a receive data size resister for endpoint 4. EPSZ4 indicates the number of bytes received from the host. FIFO of endpoint 4 has a dual-buffer configuration. The size of the received data indicated by this register is the size of the currently selected side (can be read by CPU).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R 1 --
-- -- R
Bit:
15 --
14 -- -- R
13 -- -- R
12 -- -- R
11 -- -- R
10 -- -- R
9 -- -- R
8 -- -- R
7
--
6
--
5
--
4
--
3
--
2
--
0
--
Initial value: R/W:
-- R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 0
All 0
R
Number of received bytes for endpoint 4
Rev. 1.00 Oct. 01, 2007 Page 1535 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.27 Trigger Register (TRG) TRG generates one-shot triggers FIFO for each endpoint of EP0s, EP0i, EP0o, EP1, EP2, and EP3. The packet enable trigger for the IN FIFO register and read complete trigger for the OUT FIFO register are triggers to be given.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R 1
-- -- R
Bit:
15 --
14 -- -- R
13 -- -- R
12 -- -- R
11 -- -- R
10 -- -- R
9 -- -- R
8 -- -- R
7
--
6
5
4
3
--
2
0
EP3 EP1 EP2 PKTE RDFN PKTE
EP0s EP0o EP0i RDFN RDFN PKTE
Initial value: R/W:
-- R
0 W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 6 5 4 3 2 1 0
EP3 PKTE EP1 RDFN EP2 PKTE EP0s RDFN EP0o RDFN EP0i PKTE
0 0 0 0 0 0 0 0
W W W W W W W W
Reserved The write value should always be 0. EP3 Packet Enable EP1 Read Complete EP2 Packet Enable Reserved The write value should always be 0. EP0s Read Complete EP0o Read Complete EP0i Packet Enable
Rev. 1.00 Oct. 01, 2007 Page 1536 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.28 Data Status Register (DASTS) DASTS indicates whether the IN FIFO data register contains valid data. DASTS is set to 1 when data written to IN FIFO is enabled by writing PKTE in TRG to 1, and cleared when all data has been transmitted to the host. In case of a dual-configuration FIFO for endpoint 2, this bit is cleared to 0 when both sides are empty.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R
-- -- R 1 --
-- -- R
Bit:
15 --
14 -- -- R
13 -- -- R
12 -- -- R
11 -- -- R
10 -- -- R
9 -- -- R
8 -- -- R
7
--
6
--
5
EP3 DE
4
EP2 DE
3
--
2
--
0
EP0i DE
Initial value: R/W:
-- R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit
Bit Name
Initial Value R/W Description Undefined All 0 0 0 All 0 0 R R R R R R Reserved These bits are always read as undefined value. Reserved These bits are always read as 0. EP3 Data Enable EP2 Data Enable Reserved These bits are already read as 0. EP0i data enable
31 to 8 7, 6 5 4 3 to 1 0 EP3 DE EP2 DE EP0iDE
Rev. 1.00 Oct. 01, 2007 Page 1537 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.29 FIFO Clear Register 0 (FCLR0) FCLR is a one shot register to clear the FIFO buffers for endpoints 0 to 3. Writing 1 to a bit clears the data in the corresponding FIFO buffer. In case of reception FIFO, by writing data in the FIFO buffer, the data by which PKTE in TRG is not written to 1 and the data enabled by writing 1 can be cleared. In case of OUT FIFO, the data of which reception has not been completed can be cleared. Both sides of the dual-configuration FIFO buffers (EP1 or EP3) can be cleared. The corresponding interrupt flag is not cleared by this clear instruction. Do not clear a FIFO buffer during transmission and reception.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- -- W
-- -- R 6 EP3 CLR -- W
-- -- R 5 EP1 CLR -- W
-- -- R 4 EP2 CLR -- W
-- -- R 3 -- -- W
-- -- R 2 -- -- W
-- -- R
-- -- R
0 1 EP0o EP0i CLR CLR -- -- W W
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 6 5 4 3, 2
EP3 CLR EP1 CLR EP2 CLR
Undefined Undefined Undefined Undefined Undefined
W W W W W
Reserved The write value should always be 0. EP3 Clear EP1 Clear EP2 Clear Reserved The write value should always be 0.
1 0
EP0o CLR EP0i CLR
Undefined Undefined
W W
EP0o Clear EP0i Clear
Rev. 1.00 Oct. 01, 2007 Page 1538 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.30 FIFO Clear Register 1 (FCLR1) FCLR is a one shot register to clear the FIFO buffers for endpoints 4 and 5. Writing 1 to a bit clears the data in the corresponding FIFO buffer. The corresponding interrupt flag is not cleared by this clear instruction. Do not clear a FIFO buffer during transmission and reception.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- -- W
-- -- R 6 -- -- W
-- -- R 5 -- -- W
-- -- R 4 EP5 CCLR -- W
-- -- R 3 -- -- W
-- -- R 2 -- -- W
-- -- R 1 EP5 CLR -- W
-- -- R 0 EP4 CLR -- W
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 5 4 3, 2 1 0
EP5 CCLR EP5 CLR EP4 CLR
Undefined Undefined Undefined Undefined Undefined
W W W W W
Reserved The write value should always be 0. EP5 CPU Clear Reserved The write value should always be 0. EP5 Clear EP4 Clear
Rev. 1.00 Oct. 01, 2007 Page 1539 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.31 DMA Transfer Setting Register (DMA) DMA is set when the dual address transfer is used to the data register for endpoints 1 and 2 to which transfer is possible by DMA. The USB_PWREN/USBF_UPLUP pin level can be controlled by the bit 2.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3 -- 0 R
-- -- R 2
-- -- R 1
-- -- R 0
EP1 PULLUP EP2 DMAE DMAC E
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 3
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
2
PULLUP E
0
R/W Pull-up Enable Controls connection notification to USB host/hub. 0: USB_PWREN/USBF_UPLUP pin goes high 1: USB_PWREN/USBF_UPLUP pin goes low
1 0
EP2 DMAE EP1 DMAE
0 0
R/W EP2DMA Enable Enables DMA transfer for EP2. R/W EP1DMAE Enable Enables DMA transfer for EP1.
Rev. 1.00 Oct. 01, 2007 Page 1540 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.32 Endpoint Stall Register 0 (EPSTL0) EPSTL stalls each endpoint. The endpoint in which the stall bit is set to 1 returns a stall handshake to the host from the next transfer when 1 is written to. The stall bit for endpoint 0 is cleared automatically on reception of 8 byte command data for which decoding is performed by the function and the EP0 STL bit is cleared. When the SETUPTS flag bit in the IFR0 register is set to 1, a write of the EP0 STL bit to 1 is ignored. For detailed operation, see section 36.8, Stall Operations.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3 EP3 STL 0 R/W
-- -- R 2 EP2 STL 0 R/W
-- -- R 1 EP1 STL 0 R/W
-- -- R 0 EP0 STL 0 R/W
Bit
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
31 to 8
7 to 4
All 0
R
Reserved This bit is always read as 0. The write value should always be 0.
3 2 1 0
EP3 STL EP2 STL EP1 STL EP0 STL
0 0 0 0
R/W EP3 Stall Sets EP3 stall R/W EP2 Stall Sets EP2 stall R/W EP1 Stall Sets EP1 stall R/W EP0 Stall Sets EP0 stall
Rev. 1.00 Oct. 01, 2007 Page 1541 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.33 Endpoint Stall Register 1 (EPSTL1) EPSTL stalls each endpoint. The endpoint in which the stall bit is set to 1 returns a stall handshake to the host from the next transfer when 1 is written to. For detailed operation, see section 36.8, Stall Operations.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3 -- 0 R
-- -- R 2 -- 0 R
-- -- R 1 EP5 STL 0 R/W
-- -- R 0 EP4 STL 0 R/W
Bit 31 to 8
Bit Name
Initial Value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
7 to 2
All 0
R
Reserved This bit is always read as 0. The write value should always be 0.
1 0
EP5 STL EP4 STL
0 0
R/W EP5 Stall Sets EP5 stall R/W EP4 Stall Sets EP4 stall
Rev. 1.00 Oct. 01, 2007 Page 1542 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.34 Configuration Value Register (CVR) CVR is a register to store the Configuration/Interface/value to be set when the Set Configuration/Set Interface command is normally received.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3 -- 0 R
-- -- R 2
-- -- R 1 ALTV[2:0]
-- -- R 0
CNFV[1:0] 0 R 0 R
INTV[1:0] 0 R 0 R
0 R
0 R
0 R
Bit 31 to 8 7, 6
Bit Name CNFV[1:0]
Initial Value R/W Description Undefined 00 R R Reserved These bits are always read as undefined value. Configuration Value The configuration setting value is stored when the Set Configuration command has been received. CNFV is updated when the SETC bit in the interrupt flag register is set to 1.
5, 4
INTV[1:0]
00
R
Interface Value The interface setting value is stored when the Set Interface command has been received. INTV is updated when the SETI bit in the interrupt flag register is set to 1.
3
0
R
Reserved This bit is always read as 0.
2 to 0
ALTV[2 : 0]
000
R
Alternate Value The alternate setting value is stored when the Set interface command has been received. ALTV is updated when the SETI bit in the interrupt flag register is set to 1.
Rev. 1.00 Oct. 01, 2007 Page 1543 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.35 Time Stamp Register (TSRH/TSRL) TSR is a register to store the current time stamp value. The time stamp is updated when the SOF bit in IFR0 is set to 1. The value of the time stamp when the SOF mark function is enabled and the SOF packet is broken remains as previous one. TSR is handled as an 11-bit (TSR[10:0]) register in the USBF which consists of TSR[10:8] bits in TSRH and TSR[7:0] bits in TSRL. Although TSRH can be read directly, TSRL is read via an 8-bit temporary register. Therefore, the registers should be accessed in the order of TSRH and TSRL in byte units. TSRL cannot be read singly. * TSRH
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3 -- 0 R
-- -- R 2
-- -- R 1 TSR[10:8]
-- -- R 0
0 R
0 R
0 R
Bit 31 to 8 7 to 3 2 to 0
Bit Name TSR[10:8]
Initial Value R/W Description Undefined All 0 All 0 R R R Reserved These bits are always read as undefined value. Reserved These bits are always read as 0. Upper Three Bits of Time Stamp Data
Rev. 1.00 Oct. 01, 2007 Page 1544 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
* TSRL
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
TSR[7:0] 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit
Bit name
Initial value R/W Undefined All 0 R R
Description Reserved These bits are always read as undefined value. Lower Eight Bits of Time Stamp Data
31 to 8 7 to 0 TSR[7:0]
Rev. 1.00 Oct. 01, 2007 Page 1545 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.36 Control Register 0 (CTLR0) CTLR0 sets functions of ASCE, PWMD, RSME, and RWUP.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4
RWUPS
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0 -- 0 R
RSME PWMD ASCE 0 R/W 0 R/W 0 R/W
0 R
Bit 31 to 8
Bit name
Initial value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
7 to 5
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
RWUPS
0
R
Remote Wakeup Status Status bit to indicate that the remote wakeup from the host is enabled/disabled. Indicates 0 when the remote wakeup is disabled with Device Remote Wakeup by the Set Feature/Clear Feature request and indicates 1 when it is enabled.
3
RSME
0
R/W Resume Enable Bit to clear the suspend state (performs the remote wakeup) When this bit is written to 1, a resume register is set. When this bit will be used, be sure to hold to 1 for one clock or more at 12 MHz in minimum and then clear to 0 again.
2
PWMD
0
R/W Power Mode Sets USBF power mode. 0: Self-powered 1: Bus-powered
Rev. 1.00 Oct. 01, 2007 Page 1546 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Bit 1
Bit name ASCE
Initial value R/W Description 0 R/W Automatic Stall Clear Enable When this bit is set to 1, the stall handshake is returned to the host and the stall setting bit (EPSTLR/EPXSTL) of the returned endpoint is automatically cleared. Control in a unit of endpoint is disabled as this bit is common for all endpoints. When this bit is set to 0, be sure to clear the stall setting bit of each endpoint by using software. This bit should be set to 1 before each stall bit in EPSTL is set to 1.
0
0
R
Reserved This bit is always read as 0. The write value should always be 0.
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Section 36 USB Function Controller (USBF)
36.3.37 Control Register 1 (CTLR1) CTLR1 makes settings of internal timer which is used in the isochronous transfer.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7 -- 0 R
-- -- R 6 -- 0 R
-- -- R 5 -- 0 R
-- -- R 4 -- 0 R
-- -- R 3 -- 0 R
-- -- R 2 -- 0 R
-- -- R
-- -- R
0 1 TMR TMR ACLR EN 1 0 R/W R/W
Bit 31 to 8
Bit name
Initial value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
7 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1
TMRACLR
1
R/W Timer Auto Clear Selects method to clear TMR (timer register). 0: Not cleared. When clearing TMR, write 0 to TMR by CPU. 1: Automatically cleared every time when SOF is received.
0
TMREN
0
R/W Timer Enable TMREN is TMR (timer register) enable bit. 0: Timer operation is disabled 1: Timer operation is enabled
Rev. 1.00 Oct. 01, 2007 Page 1548 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.38 Endpoint Information Register (EPIR) EPIR is a register to set the configuration information for each endpoint. 5 bytes of the information are required for one endpoint and the formats are listed in tables 36.4 and 36.5. Write the data in order from endpoint 0. Do not write more than 5 (bytes) x 10 (endpoints) = 50 bytes. Write this information once at power-on reset. Do not write it again afterwards. Write data of one endpoint is described below. EPIR writes data in the same address in order. Therefore though there is only one EPIR register, write data for registration number N (N is from 0 to 9) is listed as EPIRN0 to EPIRN4 (EPIR [registration number] [write order]) for the purpose of explaining. Write data in order from EPIR00. * EPIRN0:
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
D[7:4] -- W -- W -- W -- W
D[3:2] -- W -- W
D[1:0] -- W -- W
Bit 31 to 8
Bit Name
Initial value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
7 to 4 3, 2 1, 0
D[7:4] D[3:2] D[1:0]
Undefined Undefined Undefined
W W W
Endpoint Number Settable range: 0 to 5 Configuration Number to which Endpoint Belongs Settable range: 0 or 1 Interface Number to which Endpoint Belongs Settable range: 0 to 3
Rev. 1.00 Oct. 01, 2007 Page 1549 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
* EPIRN1:
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3 D3 -- W
-- -- R 2
-- -- R 1 D[2:0]
-- -- R 0
D[7:6] -- W -- W
D[5:4] -- W -- W
-- W
-- W
-- W
Bit 31 to 8
Bit Name
Initial value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
7,6 5, 4
D[7:6] D[5:4]
Undefined Undefined
W W
Alternate Number to which Endpoint Belongs Settable range: 0 or 1 Transfer Method of Endpoint Settable range: 0: Control 1: Isochronous 2: Bulk 3: Interrupt
3
D3
Undefined
W
Transfer Direction of Endpoint Settable range: 0: Out 1: In
2 to 0
D[2:0]
Undefined
W
Reserved The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1550 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
* EPIRN2:
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4 D[7:1]
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0 D0
-- W
-- W
-- W
-- W
-- W
-- W
-- W
-- W
Bit 31 to 8
Bit Name
Initial value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
7 to 1 0
D[7:1] D0
Undefined Undefined
W W
Maximum Packet Size of Endpoint Settable range: 0 to 64 Reserved The write value should always be 0.
* EPIRN3:
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
D[7:0] -- W -- W -- W -- W -- W -- W -- W -- W
Bit 31 to 8
Bit Name
Initial value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
7 to 0
D[7:0]
Undefined
W
Reserved The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1551 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
* EPIRN4:
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15 -- Initial value: R/W: -- R
-- -- R 14 -- -- R
-- -- R 13 -- -- R
-- -- R 12 -- -- R
-- -- R 11 -- -- R
-- -- R 10 -- -- R
-- -- R 9 -- -- R
-- -- R 8 -- -- R
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
D[7:0] -- W -- W -- W -- W -- W -- W -- W -- W
Bit 31 to 8
Bit Name
Initial value R/W Description Undefined R Reserved These bits are always read as undefined value. Write value should always be 0.
7 to 0
D[7:0]
Undefined
W
Endpoint FIFO Number Settable range: 0 to 5
An endpoint number is an endpoint number used by the USB host. The endpoint FIFO number corresponds to the endpoint number which is described in this manual. When each endpoint number and endpoint FIFO number corresponds to each other, transfer can be performed between the USB host and the endpoint FIFO. Note that the setting values are limited as described below. * Since each endpoint FIFO is optimized by a dedicated hardware corresponding to each transfer method, transfer direction, and maximum packet size, set the endpoint FIFO with a transfer method, transfer direction, and maximum packet size shown in the table below. Example: Endpoint FIFO number 1 cannot be set as other than bulk transfer, OUT, and maximum packet size (64 bytes). Although endpoint FIFO number 4 cannot be set as other than isochronous transfer and OUT, maximum packet size can be set in the range of 0 to 64 bytes. * Endpoint 0 and endpoint FIFO number 0 must correspond. * The maximum packet size of endpoint FIFO number 0 can be set to 8 bytes only. * The setting value of endpoint FIFO number 0 can be set to the maximum packet size only and the rest data is all 0. * The maximum packet size of endpoint FIFO numbers 1 and 2 can be set to 64 only. * The maximum packet size of endpoint FIFO numbers 3 can be set to 8 only. * The maximum packet size of endpoint FIFO numbers 4 and 5 can be set in the range of 0 to 64.
Rev. 1.00 Oct. 01, 2007 Page 1552 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
* When the isochronous transfer is set, Alternate can be used in the range of 0 and 1 for the same endpoint. Be sure to allocate the Alternate to the same endpoint FIFO number. * Endpoint information can be set up to 10 in maximum. * Endpoint information of 10 pieces must be written. * All information of endpoints which are not used must be written as 0. A list of restrictions of settable transfer method, transfer direction, and maximum packet size is described in table 36.4. Table 36.4 Restrictions of Settable Values
Endpoint FIFO No. 0 1 2 3 4 5 Maximum Packet Size 8 bytes 64 bytes 64 bytes 8 bytes 0 to 64 bytes 0 to 64 bytes Transfer Method Control Bulk Bulk Interrupt Isochronous Isochronous Transfer Direction OUT IN IN OUT IN
* Example of Setting This is an example when endpoint 4 and 5 used for the isochronous transfer are allocated with Alternate value. Table 36.5 Example of Endpoint Configuration
EP No. 0 1 2 3 4 4 5 5 Conf. 1 1 1 1 1 1 1 1 1 Int. 0 0 0 1 1 2 2 3 3 Alt. 0 0 0 0 1 0 1 0 1 Transfer Method Control Bulk Bulk Interrupt Isochronous Isochronous Isochronous Isochronous Transfer Direction IN/OUT OUT IN IN OUT OUT IN IN Maximum Packet Size 8 bytes 64 bytes 64 bytes 8 bytes 0 bytes 64 bytes 0 bytes 64 bytes EP FIFO No. 0 1 2 3 4 4 5 5
Rev. 1.00 Oct. 01, 2007 Page 1553 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
Table 36.6 Example of Setting of Endpoint Configuration Information
N 0 1 2 3 4 5 6 7 8 9 EPIR[N]0 00 14 24 34 00 00 46 46 67 57 EPIR[N]1 00 20 28 38 00 00 10 50 18 58 EPIR[N]2 10 80 80 10 00 00 00 80 00 80 EPIR[N]3 00 00 00 00 00 00 00 00 00 00 EPIR[N]4 00 01 02 03 00 00 04 04 05 05
Config. 1
Int. 0
Alt. 0
EP No. 0 1 2 3
EP FIFO No. 0 1 2 3
Attribute Control BulkOut BulkIn InterruptIn
1
0 1
2
0 1
4 4 5 5
4
IsoOut
3
0 1
5
IsoIn
Figure 36.2 Example of Endpoint Configuration
Rev. 1.00 Oct. 01, 2007 Page 1554 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.39 Timer Register (TMRH/TMRL) TMRH/TMRL is a 16-bit timer which is operated with a peripheral clock . Measuring the SOF packet reception interval enables the SOF packet break to be detected. The timer is operated, stopped, and cleared according to the settings of the control register 1 (CTLR 1) TMRH/TMRL is handled as a 16-bit (TMR[15:0]) register in the USBF which consists of TMR[15:8] bits in TMRH and TMR[7:0] bits in TMRL. Although TMRH can be read directly, TMRL is read via an 8-bit temporary register. Therefore, the registers should be read in the order of TMRH and TMRL in byte units. TMRL cannot be read singly. * TMRH
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15
-- -- R 14
-- -- R 13
-- -- R 12
-- -- R 11
-- -- R 10
-- -- R 9
-- -- R 8
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
TMR[15:8] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 31 to 8
Bit Name
Initial value R/W Description Undefined R Reserved These bits are always read as undefined value. The write value should always be 0.
7 to 0
TMR[15:8]
0
R/W Upper Eight Bits of Count Value
Rev. 1.00 Oct. 01, 2007 Page 1555 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
* TMRL
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15
-- -- R 14
-- -- R 13
-- -- R 12
-- -- R 11
-- -- R 10
-- -- R 9
-- -- R 8
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
TMR[7:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 31 to 8
Bit Name
Initial value R/W Description Undefined R Reserved These bits are always read as undefined value. The write value should always be 0.
7 to 0
TMR[7:0]
0
R/W Lower Eight Bits of Count Value
Rev. 1.00 Oct. 01, 2007 Page 1556 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.3.40 Set Time Out Register (STOH/STOL) STOH/STOL specifies the time out value of the timer register. When the count value of the timer register reaches the specified time out value, the time out interrupt flag in the interrupt flag register 4 is set. STOH/STOL is handled as a 16-bit (STO[15:0]) register in the USBF which consists of STO[15:8] bits in STOH and STO[7:0] bits in STOL. Although STOH can be read directly STOL is read via an 8-bit temporary register. Therefore, the registers should be read in the order of STOH and STOL in byte units. STOL cannot be read singly. * STOH
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15
-- -- R 14
-- -- R 13
-- -- R 12
-- -- R 11
-- -- R 10
-- -- R 9
-- -- R 8
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
STO[15:8] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit
Bit Name
Initial Value Undefined
R/W R
Description Reserved These bits are always read as undefined value. The write value should always be 0.
31 to 8
7 to 0
STO[15:8]
0
R/W
Upper Eight Bits of Specified Time Out Value
Rev. 1.00 Oct. 01, 2007 Page 1557 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
* STOL
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- Initial value: R/W: Bit: -- R 15
-- -- R 14
-- -- R 13
-- -- R 12
-- -- R 11
-- -- R 10
-- -- R 9
-- -- R 8
-- -- R 7
-- -- R 6
-- -- R 5
-- -- R 4
-- -- R 3
-- -- R 2
-- -- R 1
-- -- R 0
STO[7:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit
Bit Name
Initial Value Undefined
R/W R
Description Reserved The read value is undefined. The write value should always be 0.
31 to 8
7 to 0
STO[7:0]
0
R/W
Lower Eight Bits of Specified Time Out Value
Rev. 1.00 Oct. 01, 2007 Page 1558 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.4
36.4.1
Operation
Cable Connection
Application
USB function
VSBHSC/PS = 1 Select USB transceiver
Cable disconnected USBF_VBUS pin = 0 V UDC core reset
Write 50-byte endpoint information to EPIR
Initial settings USB cable connection USB module interrupt setting
No
USB_PWREN = 1?
As soon as preparations are completed, enable D+ pull-up by USBF_UPLUP
Yes
IFR0/VBUSF = 1,VBUSMN= 1 USB bus connection or disconnection detection interrupt Interrupt request
Clear VBUS flag (IFR0/VBUSF)
UDC core reset release
Firmware preparations for start of USB communication
IFR0/CFDN = 1 Endpoint information load complete interrupt
Bus reset reception IFR0/BRST = 1 Bus reset interrupt
Interrupt request
Clear bus reset flag (IFR0/BRST)
Wait for setup command reception complete interrupt
Clear FIFOs
Wait for setup command reception complete interrupt
Figure 36.3 Cable Connection Operation
Rev. 1.00 Oct. 01, 2007 Page 1559 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
In applications that do not require USB cable connection to be detected, processing by the USB connection or disconnection detection interrupt is not necessary. Preparations should be made with the bus reset interrupt. Also, in applications that require connection detection regardless of D+ pull-up control, detection should be carried out using IRQ or a general input port. 36.4.2 Cable Disconnection
USB function Application
Cable connected USBF_VBUS pin = 1
USB cable disconnection
USBF_VBUS pin = 0 IFR0/VBUSF = 1, VBUSMN = 0 USB connection or disconnection detection interrupt UDC core reset
End
Figure 36.4 Cable Disconnection Operation In applications that require connection/disconnection detection regardless of D+ pull-up control, detection should be carried out using IRQ or a general input port.
Rev. 1.00 Oct. 01, 2007 Page 1560 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
* Setup Stage
USB function
SETUP token reception
Application
Receive 8-byte command data in EP0s
Command to be processed by application? Yes
No
Automatic processing by this module
Set setup command reception complete flag (IFR0/SETUP TS = 1)
Interrupt request
Clear SETUP TS flag (IFR0/SETUP TS = 0) Clear EP0i FIFO (FCLR/EP0iCLR = 1) Clear EP0o FIFO (FCLR/EP0oCLR = 1)
To data stage
Read 8-byte data from EP0s
Decode command data Determine data stage direction*1
Write 1 to EP0s read complete bit (TRG/EP0s RDFN = 1)
*2
To control-in data stage
To control-out data stage
Notes: 1 In the setup stage, the application analyzes command data from the host requiring processing by the application, and determines the subsequent processing (for example, data stage direction, etc.). 2 When the transfer direction is control-out, the EP0i transfer request interrupt required in the status stage should be enabled here. When the transfer direction is control-in, this interrupt is not required and should be disabled.
Figure 36.5 Setup Stage Operation
Rev. 1.00 Oct. 01, 2007 Page 1561 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
* Data Stage (Control-In)
USB function IN token reception Application From setup stage
1 written to TRG/EP0s RDFN? Yes Valid data in EP0i FIFO? Yes Data transmission to host ACK Set EP0i transmission complete flag (IFR0/EP0i TS = 1)
No NAK
Write data to EP0i data register (EPDR0i)
No NAK
Write 1 to EP0i packet enable bit (TRG/EP0i PKTE = 1)
Interrupt request
Clear EP0i transmission complete flag (IFR0/EP0i TS = 0) Write data to EP0i data register (EPDR0i) Write 1 to EP0i packet enable bit (TRG/EP0i PKTE = 1)
Figure 36.6 Data Stage (Control-In) Operation The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is intransfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be sent, this data is written to the FIFO after the data written first has been sent to the host (IFR0/EP0i TS = 1). The end of the data stage is identified when the host transmits an OUT token and the status stage is entered. Note: If the size of the data transmitted by the function is smaller than the data size requested by the host, the function indicates the end of the data stage by returning to the host a packet shorter than the maximum packet size. If the size of the data transmitted by the function is an integral multiple of the maximum packet size, the function indicates the end of the data stage by transmitting a zero-length packet.
Rev. 1.00 Oct. 01, 2007 Page 1562 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
* Data Stage (Control-Out)
USB function
OUT token reception
Application
1 written to TRG/EP0s RDFN?
Yes
No
NAK
Data reception from host
ACK
Set EP0o reception complete flag (IFR0/EP0o TS = 1)
Interrupt request
Clear EP0o reception complete flag (IFR0/EP0o TS = 0)
Read data from EP0o receive data size register (EPSZ0o)
OUT token reception
1 written to TRG/EP0o RDFN?
Yes
No
NAK
Read data from EP0o data register (EPDR0o)
Write 1 to EP0o read complete bit (TRG/EP0o RDFN = 1)
Figure 36.7 Data Stage (Control-Out) Operation The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is outtransfer, the application waits for data from the host, and after data is received (IFR0/EP0o TS = 1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit, empties the receive FIFO, and waits for reception of the next data. The end of the data stage is identified when the host transmits an IN token and the status stage is entered.
Rev. 1.00 Oct. 01, 2007 Page 1563 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
* Status Stage (Control-In)
USB function
OUT token reception Application
0-byte reception from host
ACK
Set EP0o reception complete flag (IFR0/EP0o TS = 1)
Interrupt request
Clear EP0o reception complete flag (IFR0/EP0o TS = 0)
End of control transfer
Write 1 to EP0o read complete bit (TRG/EP0o RDFN = 1)
End of control transfer
Figure 36.8 Status Stage (Control-In) Operation The control-in status stage starts with an OUT token from the host. The application receives 0byte data from the host, and ends control transfer.
Rev. 1.00 Oct. 01, 2007 Page 1564 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
* Status Stage (Control-Out)
USB function
IN token reception Application
Valid data in EP0i FIFO? Yes 0-byte transmission to host ACK Set EP0i transmission complete flag (IFR0/EP0i TS = 1)
No
NAK
Interrupt request
Clear EP0i transfer request flag (IFR0/EP0i TR = 0)
Write 1 to EP0i packet enable bit (TRG/EP0i PKTE = 1)
Interrupt request
Clear EP0i transmission complete flag (IFR0/EP0i TS = 0)
End of control transfer
End of control transfer
Figure 36.9 Status Stage (Control-Out) Operation The control-out status stage starts with an IN token from the host. When an IN-token is received at the start of the status stage, there is not yet any data in the EP0i FIFO, and so an EP0i transfer request interrupt is generated. The application recognizes from this interrupt that the status stage has started. Next, in order to transmit 0-byte data to the host, 1 is written to the EP0i packet enable bit but no data is written to the EP0i FIFO. As a result, the next IN token causes 0-byte data to be transmitted to the host, and control transfer ends. After the application has finished all processing relating to the data stage, 1 should be written to the EP0i packet enable bit.
Rev. 1.00 Oct. 01, 2007 Page 1565 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.4.3
EP1 Bulk-Out Transfer (Dual FIFOs)
USB function
OUT token reception
Application
Space in EP1 FIFO? Yes
No
NAK
Data reception from host
ACK
Set EP1 FIFO full status (IFR0/EP1 FULL = 1)
Interrupt request
Read EP1 receive data size register (EPSZ1)
Read data from EP1 data register (EPDR1)
Write 1 to EP1 read complete bit (TRG/EP1 RDFN = 1)
Both EP1 FIFOs empty? Yes
No
Interrupt request
Clear EP1 FIFO full status (IFR0/EP1 FULL = 0)
Figure 36.10 EP1 Bulk-Out Transfer Operation EP1 has two 64-byte FIFOs, but the user can perform data reception and receive data reads without being aware of this dual-FIFO configuration. When one FIFO is full after reception is completed, the IFR0/EP1 FULL bit is set. After the first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and so the next packet can be received immediately. When both FIFOs are full, NACK is returned to the host automatically. When reading of the receive data is completed following data reception, 1 is written to the TRG/EP1 RDFN bit. This operation empties the FIFO that has just been read, and makes it ready to receive the next packet.
Rev. 1.00 Oct. 01, 2007 Page 1566 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.4.4
EP2 Bulk-In Transfer (Dual FIFOs)
USB function IN token reception Application
Valid data in EP2 FIFO? Yes Data transmission to host ACK
No NAK
Interrupt request
Clear EP2 transfer request flag (IFR0/EP2 TR = 0)
Enable EP2 FIFO empty interrupt (IER0/EP2 EMPTY = 1)
Space in EP2 FIFO? No
Yes
Set EP2 empty status (IFR0/EP2 EMPTY = 1)
Interrupt request
IFR0/EP2 EMPTY interrupt
Clear EP2 empty status (IFR0/EP2 EMPTY = 0)
Write one packet of data to EP2 data register (EPDR2)
Write 1 to EP2 packet enable bit (TRG/EP2 PKTE = 1)
Figure 36.11 EP2 Bulk-In Transfer Operation EP2 has two 64-byte FIFOs, but the user can perform data transmission and transmit data writes without being aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2/PKTE at one time after consecutively writing 128 bytes of data. EP2/PKTE must be performed for each 64byte write. When performing bulk-in transfer, as there is no valid data in the FIFOs on reception of the first IN token, an IFR0/EP2 TR interrupt is requested. With this interrupt, 1 is written to the IER0/EP2 EMPTY bit, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs are empty, and so an EP2 FIFO empty interrupt is generated immediately.
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Section 36 USB Function Controller (USBF)
The data to be transmitted is written to the data register using this interrupt. After the first transmit data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to the other FIFO immediately. When both FIFOs are full, EP2 EMPTY is cleared to 0. If at least one FIFO is empty, IFR0/EP2 EMPTY is set to 1. When ACK is returned from the host after data transmission is completed, the FIFO used in the data transmission becomes empty. If the other FIFO contains valid transmit data at this time, transmission can be continued. When transmission of all data has been completed, write 0 to IER0/EP2 EMPTY and disable interrupt requests.
Rev. 1.00 Oct. 01, 2007 Page 1568 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.4.5
EP3 Interrupt-In Transfer
USB function Application
Is there data for transmission to host? IN token reception Yes Write data to EP3 data register (EPDR3) Valid data in EP3 FIFO? Yes Data transmission to host ACK Set EP3 transmission complete flag (IFR0/EP3 TS = 1) Interrupt request Clear EP3 transmission complete flag (IFR1/EP3 TS = 0) No NAK Write 1 to EP3 packet enable bit (TRG/EP3 PKTE = 1)
No
Is there data for transmission to host? Yes Write data to EP3 data register (EPDR3) Write 1 to EP3 packet enable bit (TRG/EP3 PKTE = 1)
No
Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an operation flow in which, if there is data to be transferred, the EP3 DE bit in the USB data status register is referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Figure 36.12 EP3 Interrupt-In Transfer Operation
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Section 36 USB Function Controller (USBF)
36.5
EP4 Isochronous-Out Transfer
USB function Firmware
Clear SOF packet detection flag (IFR2/SOF = 0)
SOF reception
INTN (SOF)
FIFO buffer switch over
Read time stamp register H, L(TSRH,TSRL)
No
FIFO A side
Time stamps match?
To figure 36.14
A
Out-token reception
Yes
FIFO B side
Data reception from host
Read EP4 flag (IFR3/EP4 TS, EP4 TF)
No errorin receive data?
No
Read EP4 receive data size register (EPSZ4)
Yes
Set EP4 normal reception flag to 1 (IFR3/EP4 TS = 1)
Set EP4 abnormal reception flag to 1 (IFR3/EP4 TF = 1)
Read data from EP4 data register (EPDR4)
SOF reception
INTN (SOF)
Clear SOF packet detection flag (IFR2/SOF = 0)
FIFO buffer switch over
Read time stamp register H, L(TSRH,TSRL)
No
Time stamps match? To figure 36.14
A
FIFO B side
Out-token reception
Yes
FIFO A side
Data reception from host
Read EP4 flag (IFR3/EP4 TS, EP4 TF) Read EP4 receive data size register (EPSZ4)
Set EP4 abnormal reception flag to 1 (IFR3/EP4 TF = 1)
No errorin receive data?
No
Yes
Set EP4 normal reception flag to 1 (IFR3/EP4 TS = 1)
Read data from EP4 data register (EPDR4)
Figure 36.13 EP4 Isochronous-Out Transfer Operation (SOF is Normal)
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Section 36 USB Function Controller (USBF)
USB function
Firmware Clear time out flag (IFR4/TMOUT = 0)
SOF is broken
INTN (Time out)
Interrupt end
FIFO A side
FIFO B side
Out-token reception
Data transmitted from host is broken
SOF reception
INTN (SOF)
Clear SOF packet detection flag (IFR2/SOF = 0)
FIFO buffer switch over
From figure 36.13
Read time stamp register H, L (TSRH,TSRL)
A
FIFO B side
Time stamps do not match
Out-token reception Interrupt end
Data reception from host FIFO A side No error in receive data?
No
Yes
Set EP4 normal reception flag to 1 (IFR3/EP4 TS = 1)
Set EP4 abnormal reception flag to 1 (IFR3/EP4 TF = 1)
Figure 36.14 EP4 Isochronous-Out Transfer Operation (SOF is Broken)
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Section 36 USB Function Controller (USBF)
Figure 36.13 shows the normal operation of the USB function and firmware in isochronous-out transfer. EP4 has two up to 64-byte FIFOs, but the user can perform data transmission and read receive data without being aware of this dual-FIFO configuration. In isochronous transfer, transfer is occurred only once per one frame (1 ms). So, when SOF is received, the FIFO buffer is switched automatically with hardware. FIFO buffers are switched over by the SOF reception. Therefore, the FIFO buffer in which the USB function receives the data from the host and the FIFO buffer in which the firmware reads the receive data have different buffers, and a read and write of FIFO buffer are not competed. Accordingly, the data read by the firmware is the data received in one frame before. The buffers of FIFOs are switched over automatically by the SOF reception, so reading of data must be completed within the frame. The USB function receives data from the host after an out-token is received. If there is an error in the data, set the internal TF flag to 1. If there is no error in the data, set the internal TS flag to 1. In firmware, first, the processing routine of the isochronous transfer is called by SOF interrupt to check the time stamp. Then data is read from the FIFO buffer. The flag information (TS, TF) is read and decided if the data has an error. The flag information at this time represents the status of the currently readable FIFO buffer. SOF happens to be broken because of external cause during transmission from the host. In this case, an operation flow is different from that in figure 36.13. As an example, figure 36.14 shows the operation flow of a broken frame and a subsequent frame when SOF is broken once. When SOF is broken, the FIFO buffer is not switched in current frame, and a time out interrupt is occurred after time set by user has been elapsed. The USB function controller discards the data which has been transmitted to the frame from the host. The firmware detects the SOF break by the time out interrupt. In this case, the FIFO buffer connected to the CPU does not read data since data has already been read. When the SOF interrupt is occurred in the subsequent frame, the processing routine of the isochronous transfer is called and the time stamps are compared. The time stamps do not much since the SOF break occurred in the previous frame. Data is not read since the data in FIFO is not current one.
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Section 36 USB Function Controller (USBF)
36.6
EP5 Isochronous-In Transfer
USB function Firmware
INTN (SOF)
SOF reception
Clear SOF packet detection flag (IFR2/SOF = 0)
Data in FIFO B side has been transmitted?
Yes
No
Read time stamp register H, L (TSRH, TSRL)
To figure 36.16
Set EP5 transmit flag (IFR3/EP5 TR = 1)
Time stamps match?
No
B
FIFO buffer switch over FIFO A side
Yes
In-token reception
FIFO B side
Valid data in EP5 FIFO?
Yes
No
Set EP5 transmit request flag (IFR3/EP5 TR = 1)
Write one packet of data to EP5 data register (EPDR5)
0-byte data transmission
Data transmission to host
Clear SOF packet detection flag (IFR2/SOF = 0)
SOF reception
INTN (SOF)
Data in FIFO A side has been transmitted?
Yes
No
Read time stamp register H, L (TSRH, TSRL) To figure 36.16
Set EP5 transmit flag (IFR3/EP5 TR = 1)
Time stamps match?
Yes
No
B
FIFO buffer switch over
In-token reception
FIFO B side
FIFO A side
Valid data in EP5 FIFO?
No
Set EP5 transmit request flag (IFR3/EP5 TR = 1)
Write one packet of data to EP5 data register (EPDR5)
Yes
0-byte data transmission
Data transmission to host
Figure 36.15 EP5 Isochronous-In Transfer Operation (SOF is Normal)
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Section 36 USB Function Controller (USBF)
USB function
Firmware
INTN (Time out)
SOF reception
Clear time out flag (IFR4/TMOUT = 0)
In-token reception
FIFO A side
FIFO B side
No valid data in EP5 FIFO
Set EP5 transmit request flag (IFR3/EP5 TR = 1)
Write 1 to EP5 CPU clear (FCLR1/EP5CCLR)
0-byte data transmission
0-byte data transmission to host
SOF reception
INTN (FIFO)
Clear SOF packet detection flag (IFR2/SOF = 0)
Read time stamp register H, L (TSRH, TSRL)
From figure 36.15
B
FIFO buffer switch over
Time stamps do not match
FIFO A side
In-token reception
FIFO B side
No valid data in EP5 FIFO
Set EP5 transmit request flag (IFR3/EP5 TR = 1)
Write one packet of data to EP5 data register (EPDR5)
0-byte data transmission
0-byte data transmission to host
Figure 36.16 EP5 Isochronous-In Transfer Operation (SOF in Broken)
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Section 36 USB Function Controller (USBF)
Figure 36.15 shows the normal operation of the USB function and firmware in isochronous-in transfer. EP5 has two up to 64-byte FIFOs, but the user can perform data transmission and write transmit data without being aware of this dual-FIFO configuration. In isochronous transfer, transfer is occurred only once per one frame (1 ms). So, when SOF is received, the FIFO buffer is switched automatically with hardware. FIFO buffers are switched over by the SOF reception. Therefore, the FIFO buffer in which the USB function transmits the data and the FIFO buffer in which the firmware writes the transmit data have different buffers, and a read and write of FIFO buffer are not competed. Accordingly, the data written by the firmware is the data transmitted in one frame after. The buffers of FIFOs are switched over automatically by the SOF reception, so writing of data must be completed within the frame. The USB function transmits data to the host, and the internal TR flag is set to 1, when data to be transmitted to the host exists in FIFO after an in-token is received. If there is no data in the FIFO buffer, set the internal TR flag to 1 and transmit 0-byte data to the host. In firmware, first, the processing routine of the isochronous transfer is called by SOF interrupt to check the time stamp. Then one packet data is written to FIFO. This written data is transmitted to the host in the next frame. SOF happens to be broken because of external cause during transmission from the host. In this case, an operation flow is different from that in figure 36.15. As an example, figure 36.16 shows the operation flow of a broken frame and a subsequent frame when SOF is broken once. When SOF is broken, the FIFO buffer is not switched in corresponding frame, and a time out interrupt is occurred after time set by user has been elapsed. The firmware detects the SOF break by the time out interrupt. In this case, the FIFO buffer connected to the CPU has the data to be transmitted in the current frame. If this data is transmitted in the next frame, the data which is not current one is transmitted. Therefore, the firmware writes the EP5 CPU clear (FCLR1/EP5 CCLR) to 1. When the SOF interrupt is occurred in the subsequent frame, the processing routine of the isochronous transfer is called and the time stamps are compared. The time stamps do not much since the SOF break occurred in the previous frame. One packet of data is written by the firmware according to the transmitted time stamp. In the frame in which the SOF is broken, the FIFO buffer is not switched and there in no data to be transmitted to the host. Therefore, USB function controller transmits 0-byte data to the host. Since the data to be transmitted is cleared by firmware, 0-byte data is transmitted to the host.
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Section 36 USB Function Controller (USBF)
36.7
Processing of USB Standard Commands and Class/Vendor Commands
Processing of Commands Transmitted by Control Transfer
36.7.1
A command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. Whether command decoding is required on the application side is indicated in table 36.7 below. Table 36.7 Command Decoding on Application Side
Decoding not Necessary on Application Side Clear feature Get configuration Get interface Get status Set address Set configuration Set feature Set interface Decoding Necessary on Application Side Get descriptor Class/Vendor command Synch frame Set descriptor
If decoding is not necessary on the application side, command decoding and data stage and status stage processing are performed automatically. No processing is necessary by the user. An interrupt is not generated in this case. If decoding is necessary on the application side, this module stores the command in the EP0s FIFO. After normal reception is completed, the IFR0/SETUP TS flag is set and an interrupt request is generated. In the interrupt routine, 8 bytes of data must be read from the EP0s data register (EPDR0S) and decoded by firmware. The necessary data stage and status stage processing should then be carried out according to the result of the decoding operation.
Rev. 1.00 Oct. 01, 2007 Page 1576 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.8
36.8.1
Stall Operations
Overview
This section describes stall operations in this module. There are two cases in which the USB function controller stall function is used: * When the application forcibly stalls an endpoint for some reason * When a stall is performed automatically within the USB function controller due to a USB specification violation The USB function controller has internal status bits that hold the status (stall or non-stall) of each endpoint. When a transaction is sent from the host, the module references these internal status bits and determines whether to return a stall to the host. These bits cannot be cleared by the application; they must be cleared with a Clear Feature command from the host. However, the internal status bit to EP0 is automatically cleared only when the setup command is received. 36.8.2 Forcible Stall by Application
The application uses the EPSTL register to issue a stall request for the USB function controller. When the application wishes to stall a specific endpoint, it sets the corresponding bit in EPSTL (11 in figure 36.17). The internal status bits are not changed at this time. When a transaction is sent from the host for the endpoint for which the EPSTL bit was set, the USB function controller references the internal status bit, and if this is not set, references the corresponding bit in EPSTL (1-2 in figure 36.17). If the corresponding bit in USBEPSTL is set, the USB function controller sets the internal status bit and returns a stall handshake to the host (1-3 in figure 36.17). In this time, if the CTLR/ASCE bit is set to 1, the corresponding bit in EPSTL is automatically cleared to 0 and a stall handshake is returned to the host (1-4 in figure 36.17). If the corresponding bit in EPSTL is not set, the internal status bit is not changed and the transaction is accepted. Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to the EPSTL register. Even after a bit is cleared by the Clear Feature command (3-1 in figure 36.17), the USB function controller continues to return a stall handshake while the bit in EPSTL is set, since the internal status bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figure 36.17). To clear a stall, therefore, it is necessary for the corresponding bit in EPSTL to be cleared automatically when a stall is returned from the USB controller while the CTLR/ASCE bit is set to 1, or to be cleared by the application, and also for the internal status bit to be cleared with a Clear Feature command (2-1, 2-2, and 2-3 in figure 36.17).
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Section 36 USB Function Controller (USBF)
(1) Transition from normal operation to stall (1-1)
USB
Internal status bit 0 EPnSTL 01 1. 1 written to EPnSTL by application
(1-2) Reference
Transaction request
Internal status bit 0
EPnSTL 1
1. IN/OUT token received from host 2. EPnSTL referenced
(1-3) Stall
STALL handshake
(1-4)
EPnSTL Internal status bit 1 01 To (2-1) or (3-1)
Stall Internal status bit 01 EPnSTL 1
1. 2. 3. 4.
0 set in CTLR/ASCE 1 set in EPnSTL Internal status bit set to 1 Transmission of STALL handshake
STALL handshake
To 2 of (2-1)
1. 1 set in CTLR/ASCE 2. 1 set in EPnSTL 3. EPnSTL cleared to 0 automatically 4. Internal status bit set to 1 5. Transmission of STALL handshake
(2) When Clear Feature is sent after EPSTL is cleared (2-1)
Transaction request
Internal status bit 1 EPnSTL 10 1. EPnSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. EPnSTL not referenced 5. Internal status bit not changed
(2-2)
STALL handshake
Internal status bit 1
EPnSTL 0
1. Transmission of STALL handshake
(2-3)
Clear Feature command
Internal status bit 10
EPnSTL 0
1. Internal status bit cleared to 0
Normal status restored
(3) When Clear Feature is sent before EPSTL is cleared to 0 (3-1) 1. Internal status bit cleared to 0 2. EPnSTL not changed
Clear Feature command
Internal status bit 10 To (1-2)
EPnSTL 1
Note: The CTLR/ASCE bit should be set to 1 before the EPnSTL bit (each stall bit) in EPSTL is set to 1.
Figure 36.17 Forcible Stall by Application
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Section 36 USB Function Controller (USBF)
36.8.3
Automatic Stall by USB Function Controller
When a stall setting is made with the Set Feature command, or in the event of a USB specification violation, the USB function controller automatically sets the internal status bit for the relevant endpoint without regard to the corresponding bit in EPSTL, and returns a stall handshake (1-1 in figure 36.18). Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to the corresponding bit in EPSTL. After a bit is cleared by the Clear Feature command, the corresponding bit in EPSTL is referenced (3-1 in figure 36.18). The USB function controller continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 36.18). To clear a stall, therefore, the internal status bit must be cleared with a Clear Feature command (3-1 in figure 36.18). In this time, if set by the application, the corresponding bit in EPSTL should also be cleared (2-1 in figure 36.18).
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Section 36 USB Function Controller (USBF)
(1) Transition from normal operation to stall (1-1) STALL handshake Internal status bit 01 To (2-1) or (3-1) EPnSTL 0 1. In case of USB specification violation, etc., USB function module stalls endpoint automatically
(2) When transaction is performed when internal status bit is set, and Clear Feature is sent (2-1) Transaction request Internal status bit 1 EPnSTL 0 1. EPnSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. EPnSTL not referenced 5. Internal status bit not changed 1. Transmission of STALL handshake
(2-2) STALL handshake Internal status bit 1 EPnSTL 0
Stall status maintained (3) When Clear Feature is sent before transaction is performed (3-1) Clear Feature command Internal status bit 10 EPnSTL 0 1. Internal status bit cleared to 0 2. EPnSTL not changed
Normal status restored
Figure 36.18 Automatic Stall by USB Function Controller
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Section 36 USB Function Controller (USBF)
36.9
36.9.1
Examples of External Circuit
Example of the Connection between USB Function Controller
Figures 36.19 shows an example connection of USB function controller. When using the USB function controller, the signals must be input to the cable connection monitor pin USBF_VBUS. The USBF_VBUS pin is multiplexed with the USB_PWREN pin. According to the status of the USBF_VBUS pin, the USB function controller recognizes whether the cable is connected/disconnected. Also, pin D+ must be pulled up in order to notify the USB host/hub that the connection is established. The sample circuit in figure 36.19 uses the USBF_UPLUP pin for pull-up control.
This LSI USB_PWREN/USBF_UPLUP IC allowing voltage application when system power is off IC2 IC1 USBF_VBUS USBP USBM 3.3V IC allowing voltage application when system power is off D+ 22 1.5k USB connector 5V
USB function
VBUS
D-
22
GND
Figure 36.19 Example of Transceiver Connection for USB function Controller
Rev. 1.00 Oct. 01, 2007 Page 1581 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.10
Usage Notes
36.10.1 Setup Data Reception The following points should be noted on the EP0s data register (EPDR0s) in which reception of 8byte setup data is performed. 1. Since the setup command must be received in the USB, writing from the USB bus side is prior to reading from the CPU side. While the CPU reads data after completion of reception and reception of the next setup command is started, reading from the CPU side is forcibly invalid. Therefore a value to be read after starting reception is undefined. 2. EPDR0s must be read in 8-byte units. If reading is suspended while it is in progress, data received in the next setup cannot be read successfully. 36.10.2 FIFO Clear When the USB cable is disconnected during communication, data which is receiving or transmitting may remain in the FIFO. Therefore the FIFO must be cleared immediately after connecting the USB cable again. Note that the FIFO in which data is receiving from the host or transmitting to the host must not be cleared. 36.10.3 Overreading/Overwriting of Data Register The following points should be noted when the data register of the USBF is read from or written to. Receive Data Register: The receive data register must not read data which is more than valid receive data bytes. That is, data which is more than bytes indicated in the receive data size register must not be read. In case of the receive data register which has the dual FIFO buffer, the maximum number of data which can be read in a single time is maximum packet size. Write 1 to TRG after data in the current valid buffer is read. This writing switches the FIFO buffer. Then, the new number of bytes is reflected in the receive data size and the next data can be read. Transmit Data Register: The transmit data register must not write data which is more than maximum packet size. In case of the transmit data register which has the dual FIFO buffer, the maximum number of data which can be written in a single time is maximum packet size. Write 1 to TRG/PKTE after data is written. This writing switches the FIFO buffer. Then, the next data can be written to another buffer. Therefore data must not be written in both buffers in a single time.
Rev. 1.00 Oct. 01, 2007 Page 1582 of 1956 REJ09B0256-0100
Section 36 USB Function Controller (USBF)
36.10.4 Assigning EP0 Interrupt Sources The EP0 interrupt sources assigned to IFR0 (bits 0, 1, and 2) must be assigned to the same interrupt pins by ISR0. The other interrupt sources have no restrictions. 36.10.5 FIFO Clear when DMA Transfer is Set When the DMA transfer is enabled in endpoint 1, the data register cannot be cleared. Cancel the DMA transfer before clearing the data register. 36.10.6 Note on Using TR Interrupt The bulk-in transfer has a transfer request interrupt (TR interrupt). The following points should be noted when using a TR interrupt. When the IN token is sent from the USB host and there is no data in the corresponding EP FIFO, the TR interrupt flag is set. However, the TR interrupt is generated continuously at the timing as shown in figure 36.20. In this case, note that erroneous operation should not occur. Note: When the IN token is received and there is no data in the corresponding EP FIFO, an NAK is determined. However, the TR interrupt flag is set after an NAK handshake is transmitted. Therefore when the next IN token is received before TRG/PKTE is written, the TR interrupt flag is set again.
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Section 36 USB Function Controller (USBF)
CPU
TR interrupt routine
TR interrupt routine
TR flag clearing
Transmit data writing
TRG/ PKTE
Host
IN token
IN token
IN token
NAK determination
USB
NAK determination NAK TR flag setting (TR flag is set again)
Data transmission ACK
NAK TR flag setting
Figure 36.20 Set Timing of TR Interrupt Flag
Rev. 1.00 Oct. 01, 2007 Page 1584 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Section 37 LCD Controller (LCDC)
A unified memory architecture is adopted for the LCD controller (LCDC) so that the image data for display is stored in system memory. The LCDC module reads data from system memory, uses the palette memory to determine the colors, then puts the display on the LCD panel. It is possible to connect the LCDC to the LCD module* other than microcomputer bus interface types and NTSC/PAL types and those that apply the LVDS interface. Note: * LCD module can be connected to the LVDS interface by using the LSI with LVDS conversion LSI.
37.1
Features
The LCDC has the following features. * Panel interface Serial interface method Supports data formats for STN/dual-STN/TFT panels (8/12/16/18-bit bus width)*1 * Supports 4/8/15/16-bpp (bits per pixel) color modes * Supports 1/2/4/6-bpp grayscale modes * Supports LCD-panel sizes from 16 x 1 to 1024 x 1024*2 * 24-bit color palette memory (16 of the 24 bits are valid; R:5/G:6/B:5) * STN/DSTN panels are prone to flicker and shadowing. The controller applies 65536-color control by 24-bit space-modulation FRC with 8-bit RGB values for reduced flicker. * Dedicated display memory is unnecessary using part of the DDR_SDRAM (area 3) as the VRAM to store display data of the LCDC. * The display is stable because of the large 2.4-kbyte line buffer * Supports the inversion of the output signal to suit the LCD panel's signal polarity * Supports the selection of data formats (the endian setting for bytes, backed pixel method) by register settings * An interrupt can be generated at the user specified position (controlling the timing of VRAM update start prevents flicker) * A hardware-rotation mode is included to support the use of landscape-format LCD panels as portrait-format LCD panels (the horizontal width of the panel before rotation must be within 320 pixels (see table 37.6.)
Rev. 1.00 Oct. 01, 2007 Page 1585 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Notes: 1. When connecting the LCDC to a TFT panel with an unwired 18-bit bus, the lower bit lines should be connected to GND or to the lowest bit from which data is output. 2. For details, see section 37.4.1, LCD Module Sizes which can be Displayed in this LCDC. Figure 37.1 shows a block diagram of LCDC.
LCD_CLK Bck Pck0
Clock generator DOTCLK Normal output pin group LCD_CL1 LCD_CL2 LCD_FLM LCD_D15 to 0 LCD_DON LCD_VCPWC LCD_VEPWC LCD_M_DISP Mirror output output group LCDM_CL1 LCDM_CL2 LCDM_FLM LCDM_D15 to 0 LCDM_DON LCDM_VCPWC LCDM_VEPWC LCDM_M_DISP
Bus interface
Register
LCDC
Peripheral bus 0
Pallet RAM 4 bytes x 256 entries Bus interface
Power control
Line buffer 2.4 Kbytes
DDRIF
DDR I/O
DDR-SDRAM (VRAM)
Figure 37.1 LCDC Block Diagram
Rev. 1.00 Oct. 01, 2007 Page 1586 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.2
Input/Output Pins
Table 37.1 summarizes the LCDC's pin configuration. The LCDC output pins are divided in two groups: normal output group and mirror output group. The input/output operations of pins in two groups are always the same. The pin select register of the PFC is used to select the LCDC pins. As pins in two groups have different input/output timing, mixed use of pins in two groups is not allowed. Table 37.1 Pin Configuration
Pin Normal Output LCD_D15 to 0 LCD_DON LCD_CL1 LCD_CL2 LCD_M_DISP LCD_FLM LCD_VCPWC LCD_VEPWC Mirror Output LCDM_D15 to 0 LCDM_DON LCDM_CL1 LCDM_CL2 LCDM_M_DISP LCDM_FLM LCDM_VCPWC LCDM_VEPWC LCD_CLK* I/O Output Output Output Output Output Output Output Output Input Function Data for LCD panel Display-on signal (DON) Shift-clock 1 (STN/DSTN)/horizontal sync signal (HSYNC) (TFT) Shift-clock 2 (STN/DSTN)/dot clock (DOTCLK) (TFT) LCD current-alternating signal/DISP signal First line marker/vertical sync signal (VSYNC) (TFT) LCD-module power control (VCC) LCD-module power control (VEE) LCD clock-source input
Note: Check the LCD module specifications carefully in section 37.5, Clock and LCD Data Signal Examples, before deciding on the wiring specifications for the LCD module. * Only this pin is available as the LCD_CLK pin in the LCDC module.
Rev. 1.00 Oct. 01, 2007 Page 1587 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3
Register Configuration
Table 37.2 Register Configuration
Register Name Abbreviation R/W Area P4 Address* H'FFE8 03FC Area 7 Address* H'1FE8 03FC Access Size
Palette data register 00 to FF LCDC input clock register LCDC module type register LCDC data format register LCDC scan mode register LCDC data fetch start address register for upper display panel LCDC data fetch start address register for lower display panel
LDPR00 to LDPRFF LDICKR LDMTR LDDFR LDSMR LDSARU LDSARL
R/W H'FFE8 0000 to H'1FE8 0000 to 32 R/W H'FFE8 0400 R/W H'FFE8 0402 R/W H'FFE8 0404 R/W H'FFE8 0406 R/W H'FFE8 0408 H'1FE8 0400 H'1FE8 0402 H'1FE8 0404 H'1FE8 0406 H'1FE8 0408 16 16 16 16 32
R/W H'FFE8 040C H'1FE8 040C 32 R/W H'FFE8 0410 R/W H'FFE8 0412 R/W H'FFE8 0414 R/W H'FFE8 0416 R/W H'FFE8 0418 H'1FE8 0410 H'1FE8 0412 H'1FE8 0414 H'1FE8 0416 H'1FE8 0418 16 16 16 16 16 16
LCDC fetch data line address offset LDLAOR register for display panel LCDC palette control register LCDC horizontal character number register LCDC horizontal synchronization signal register LCDC vertical displayed line number register LCDC vertical total line number register LCDC vertical synchronization signal register LCDC AC modulation signal toggle line number register LCDC interrupt control register LCDC power management mode register LCDC power supply sequence period register LCDC control register LDPALCR LDHCNR LDHSYNR LDVDLNR LDVTLNR LDVSYNR LDACLNR LDINTR LDPMMR LDPSPR LDCNTR
R/W H'FFE8 041A H'1FE8 041A
R/W H'FFE8 041C H'1FE8 041C 16 R/W H'FFE8 041E H'1FE8 041E R/W H'FFE8 0420 R/W H'FFE8 0424 R/W H'FFE8 0426 R/W H'FFE8 0428 H'1FE8 0420 H'1FE8 0424 H'1FE8 0426 H'1FE8 0428 16 16 16 16 16
Rev. 1.00 Oct. 01, 2007 Page 1588 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Register Name
Abbreviation
R/W
Area P4 Address*
Area 7 Address*
Access Size
LCDC user specified interrupt control register LCDC user specified interrupt line number register LCDC memory access interval number register Note: *
LDUINTR
R/W H'FFE8 0434
H'1FE8 0434 H'1FE8 0436 H'1FE8 0440
16 16 16
LDUINTLNR R/W H'FFE8 0436 LDLIRNR R/W H'FFE8 0440
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
Table 37.3 Register State in Each Operating Mode
Register Name Power-On Abbreviation Reset Manual Reset Sleep Standby
Palette data register 00 to FF LCDC input clock register LCDC module type register LCDC data format register LCDC scan mode register LCDC data fetch start address register for upper display panel LCDC data fetch start address register for lower display panel LCDC fetch data line address offset register for display panel LCDC palette control register LCDC horizontal character number register
LDPR00 to LDPRFF LDICKR LDMTR LDDFR LDSMR LDSARU LDSARL LDLAOR LDPALCR LDHCNR
Undefined H'1101 H'0109 H'000C H'0000
Undefined H'1101 H'0109 H'000C H'0000
Retained Retained Retained Retained Retained
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
H'0C000000 H'0C000000 Retained H'0C000000 H'0C000000 Retained
H'0280 H'0000 H'4F52 H'0050 H'01DF H'01DF
H'0280 H'0000 H'4F52 H'0050 H'01DF H'01DF
Retained Retained Retained Retained Retained Retained
LCDC horizontal synchronization LDHSYNR signal register LCDC vertical displayed line number register LCDC vertical total line number register LDVDLNR LDVTLNR
Rev. 1.00 Oct. 01, 2007 Page 1589 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Register Name
Power-On Abbreviation Reset
Manual Reset
Sleep
Standby
LCDC vertical synchronization signal register LCDC AC modulation signal toggle line number register LCDC interrupt control register
LDVSYNR LDACLNR LDINTR
H'01DF H'000C H'0000 H'0010 H'F60F H'0000 H'0000
H'01DF H'000C H'0000 H'0010 H'F60F H'0000 H'0000 H'004F H'0000
Retained Retained Retained Retained Retained Retained Retained Retained Retained
Retained Retained Retained Retained Retained Retained Retained Retained Retained
LCDC power management mode LDPMMR register LCDC power supply sequence period register LCDC control register LCDC user specified interrupt control register LCDC user specified interrupt line number register LCDC memory access interval number register LDPSPR LDCNTR LDUINTR
LDUINTLNR H'004F LDLIRNR H'0000
Rev. 1.00 Oct. 01, 2007 Page 1590 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.1
LCDC Input Clock Register (LDICKR)
This LCDC can select bus clock, the peripheral clock, or the external clock as its operation clock source. The selected clock source can be divided using an internal divider into a clock of 1/1 to 1/32 and be used as the LCDC operating clock (DOTCLK). The clock output from the LCDC is used to generate the synchronous clock output (LCD_CL2) for the LCD panel from the operating clock selected in this register. For a TFT panel, LCD_CL2 = DOTCLK, and for an STN or DSTN panel, LCD_CL2 = a clock with a frequency of (DOTCLK/data bus width of output to LCD panel). The LDICKR must be set so that the clock input to the LCDC is 66 MHz or less regardless of the LCD_CL2.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICKSEL[1:0]
DCDR[5:0]
Initial value: R/W:
0 R
0 R
0 R/W
1 R/W
0 R
0 R
0 R
1 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
Bit 15, 14
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13, 12
ICKSEL[1:0]
00
R/W
Input Clock Select Set the clock source for DOTCLK. 00: Setting prohibited 01: Peripheral clock is selected 10: External clock is selected 11: Setting prohibited
11 to 9
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
1
R
Reserved This bit is always read as 1. The write value should always be 1.
7, 6
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
5 to 0
DCDR[5:0]
000001
R/W
Clock Division Ratio Set the input clock division ratio. For details on the setting, refer to table 37.4.
Rev. 1.00 Oct. 01, 2007 Page 1591 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Table 37.4 I/O Clock Frequency and Clock Division Ratio
Clock Division Ratio 1/1 1/2 1/3 1/4 1/6 1/8 1/12 1/16 1/24 1/32 I/O Clock Frequency (MHz) 50.000 50.000 25.000 16.667 12.500 8.333 6.250 4.167 3.125 2.083 1.563 60.000 60.000 30.000 20.000 15.000 10.000 7.500 5.000 3.750 2.500 1.875 66.000 66.000 33.000 22.000 16.500 11.000 8.250 5.500 4.125 2.750 2.063
DCDR[5:0] 000001 000010 000011 000100 000110 001000 001100 010000 011000 100000
Note: Any setting other than above is handled as a clock division ratio of 1/1 (initial value).
Rev. 1.00 Oct. 01, 2007 Page 1592 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.2
LCDC Module Type Register (LDMTR)
LDMTR sets the control signals output from this LCDC and the polarity of the data signals, according to the polarity of the signals for the LCD module connected to the LCDC.
Bit:
15
FLM POL
14
CL1 POL
13
DISP POL
12
DPOL
11
10
9
8
7
6
5
4
3
2
1
0
MCNT CL1CNT CL2CNT
MIFTYP[5:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R
0 R/W
0 R/W
1 R/W
0 R
0 R
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
1 R/W
Bit 15
Bit Name FLMPOL
Initial Value 0
R/W R/W
Description FLM (Vertical Sync Signal) Polarity Select Selects the polarity of the LCD_FLM (vertical sync signal, first line marker) for the LCD module. 0: LCD_FLM pulse is high active 1: LCD_FLM pulse is low active
14
CL1POL
0
R/W
CL1 (Horizontal Sync Signal) Polarity Select Selects the polarity of the LCD_CL1 (horizontal sync signal) for the LCD module. 0: LCD_CL1 pulse is high active 1: LCD_CL1 pulse is low active
13
DISPPOL
0
R/W
DISP (Display Enable) Polarity Select Selects the polarity of the LCD_M_DISP (display enable) for the LCD module. 0: LCD_M_DISP is high active 1: LCD_M_DISP is low active
Rev. 1.00 Oct. 01, 2007 Page 1593 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Bit 12
Bit Name DPOL
Initial Value 0
R/W R/W
Description Display Data Polarity Select Selects the polarity of the LCD_D (display data) for the LCD module. This bit supports inversion of the LCD module. 0: LCD_D is high active, transparent-type LCD panel 1: LCD_D is low active, reflective-type LCD panel
11
0
R
Reserved This bit is always read as 0. The write value should always be 0.
10
MCNT
0
R/W
M Signal Control Sets whether or not to output the LCD's currentalternating signal of the LCD module. 0: M (AC line modulation) signal is output 1: M signal is not output
9
CL1CNT
0
R/W
CL1 (Horizontal Sync Signal) Control Sets whether or not to enable CL1 output during the vertical retrace period. 0: CL1 is output during vertical retrace period 1: CL1 is not output during vertical retrace period
8
CL2CNT
1
R/W
CL2 (Dot Clock of LCD Module) Control Sets whether or not to enable CL2 output during the vertical and horizontal retrace period. 0: CL2 is output during vertical and horizontal retrace period 1: CL2 is not output during vertical and horizontal retrace period
7, 6
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1594 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Bit 5 to 0
Bit Name MIFTYP [5:0]
Initial Value 001001
R/W R/W
Description Module Interface Type Select Set the LCD panel type and data bus width to be output to the LCD panel. There are three LCD panel types: STN, DSTN, and TFT. There are four data bus widths for output to the LCD panel: 4, 8, 12, and 16 bits. When the required data bus width for a TFT panel is 16 bits or more, connect the LCDC and LCD panel according to the data bus size of the LCD panel. Unlike in a TFT panel, in an STN or DSTN panel, the data bus width setting does not have a 1:1 correspondence with the number of display colors and display resolution, e.g., an 8-bit data bus can be used for 16 bpp, and a 12-bit data bus can be used for 4 bpp. This is because the number of display colors in an STN or DSTN panel is determined by how data is placed on the bus, and not by the number of bits. For data specifications for an STN or DSTN panel, see the specifications of the LCD panel used. The output data bus width should be set according to the mechanical interface specifications of the LCD panel. If an STN or DSTN panel is selected, display control is performed using a 24-bit space-modulation FRC consisting of the 8-bit R, G, and B included in the LCDC, regardless of the color and gradation settings. Accordingly, the color and gradation specified by DSPCOLOR is selected from 16 million colors in an STN or DSTN panel. If a palette is used, the color specified in the palette is displayed. 000000: STN monochrome 4-bit data bus module 000001: STN monochrome 8-bit data bus module 001000: STN color 4-bit data bus module 001001: STN color 8-bit data bus module 001010: STN color 12-bit data bus module 001011: STN color 16-bit data bus module 010001: DSTN monochrome 8-bit data bus module 010011: DSTN monochrome 16-bit data bus module 011001: DSTN color 8-bit data bus module 011010: DSTN color 12-bit data bus module 011011: DSTN color 16-bit data bus module 101011: TFT color 16-bit data bus module Settings other than above: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1595 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.3
LCDC Data Format Register (LDDFR)
LDDFR sets the bit alignment for pixel data in one byte and selects the data type and number of colors used for display so as to match the display driver software specifications.
Bit:
15
14
13
12
11
10
9
8
PABD
7
6
5
4
3
2
1
0
DSPCOLOR[6:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R
0 R/W
0 R/W
0 R/W
1 R/W
1 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 9
8
PABD
0
R/W
Byte Data Pixel Alignment Sets the pixel data alignment type in one byte of data. The contents of aligned data per pixel are the same regardless of this bit's setting. For example, data H'05 should be expressed as B'0101 which is the normal style handled by a MOV instruction of the this CPU, and should not be selected between B'0101 and B'1010. 0: Big endian for byte data 1: Little endian for byte data
7
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1596 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Bit 6 to 0
Bit Name DSPCOLOR [6:0]
Initial Value R/W 0001100 R/W
Description Display Color Select Set the number of display colors for the display (0 is written to upper bits of 4 to 6 bpp). For display colors to which the description (via palette) is added below, the color set by the color palette is actually selected by the display data and displayed. The number of colors that can be selected in rotation mode is restricted by the display resolution. For details, see table 37.5. 0000000: Monochrome, 2 grayscales, 1 bpp (via palette) 0000001: Monochrome, 4 grayscales, 2 bpp (via palette) 0000010: Monochrome, 16 grayscales, 4 bpp (via palette) 0000100: Monochrome, 64 grayscales, 6 bpp (via palette) 0001010: Color, 16 colors, 4 bpp (via palette) 0001100: Color, 256 colors, 8 bpp (via palette) 0011101: Color, 32K colors (RGB: 555), 15 bpp 0101101: Color, 64K colors (RGB: 565), 16 bpp Settings other than above: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1597 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.4
LCDC Scan Mode Register (LDSMR)
LDSMR selects whether or not to enable the hardware rotation function that is used to rotate the LCD panel, and sets the burst length for the VRAM (synchronous DRAM in area 3) used for display.
Bit:
15
14
13
ROT
12
11
10
9
8
AU[1:0]
7
6
5
4
3
2
1
0
Initial value: R/W:
0 R
0 R
0 R/W
0 R
0 R
0 R
0 R/W
0 R/W
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 15, 14
Bit Name Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13
ROT
0
R/W
Rotation Module Select Selects whether or not to rotate the display by hardware. Note that the following restrictions are applied to rotation. * * * An STN or TFT panel must be used. A DSTN panel is not allowed. The maximum horizontal (internal scan direction of the LCD panel) width of the LCD panel is 320. Set a binary exponential that exceeds the display size in LDLAOR. (For example, 256 must be selected when a 320 x 240 panel is rotated to be used as a 240 x 320 panel and the horizontal width of the image is 240 bytes.)
0: Not rotated 1: Rotated 90 degrees rightwards (left side of image is displayed on the upper side of the LCD module) 12 to 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1598 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Bit 9, 8
Bit Name AU[1:0]
Initial Value 00
R/W R/W
Description Access Unit Select Select access unit of VRAM. This bit is enabled when ROT = 1 (rotate the display). When ROT = 0, 16-burst memory read operation is carried out whatever the AU setting is. 00: 4-burst 01: 8-burst 10: 16-burst 11: 32-burst Notes: 1. Above burst lengths are used for 32-bit bus. For 16-bit bus, the burst lengths are twice the lengths of 32-bit bus. 2. When displaying a rotated image, the burst length is limited depending on the number of column address bits and bus width of connected SDRAM. For details, see table 37.5.
7 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
37.3.5
LCDC Start Address Register for Upper Display Data Fetch (LDSARU)
LDSARU sets the start address from which data is fetched by the LCDC for display of the LCDC panel. When a DSTN panel is used, this register specifies the fetch start address for the upper side of the panel.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SAU[25:16]
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
1 R
1 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SAU[15:4]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R
0 R
0 R
Rev. 1.00 Oct. 01, 2007 Page 1599 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 28
27, 26
All 1
R
Reserved These bits are always read as 1. The write value should always be 1.
25 to 4
SAU[25:4] All 0
R/W
Start Address for Upper Display Data Fetch The start address for data fetch of the display data must be set within the synchronous DRAM area of area 3.
3 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Notes: 1. The minimum alignment unit of LDSARU is 512 bytes when the hardware rotation function is not used. Write 0 to the lower nine bits. When using the hardware rotation function, set the LDSARU value so that the upper-left address of the image is aligned with the 512-byte boundary. 2. When the hardware rotation function is used (ROT = 1), set the upper-left address of the image which can be calculated from the display image size in this register. The equation below shows how to calculate the LDSARU value when the image size is 240 x 340 and LDLAOR = 256. The LDSARU value is obtained not from the panel size but from the memory size of the image to be displayed. Note that LDLAOR must be a binary exponential at least as large as the horizontal width of the image. Calculate backwards using the LDSARU value (LDSARU - 256 (LDLAOR value) x (320 - 1)) to ensure that the upper-left address of the image is aligned with the 512-byte boundary. LDSARU = (upper-left address of image) + 256 (LDLAOR value) x 319 (line)
Rev. 1.00 Oct. 01, 2007 Page 1600 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.6
LCDC Start Address Register for Lower Display Data Fetch (LDSARL)
When a DSTN panel is used, LDSARL specifies the fetch start address for the lower side of the panel.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SAL[25:16]
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
1 R
1 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SAL[15:4]
0 Initial value: R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R
0 R
0 R
Bit
Bit Name Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 28
27, 26
All 1
R
Reserved These bits are always read as 1. The write value should always be 1.
25 to 4
SAL[25:4] All 0
R/W
Start Address for Lower Panel Display Data Fetch The start address for data fetch of the display data must be set within the synchronous DRAM area of area 3. STN and TFT: Cannot be used DSTN: Start address for fetching display data corresponding to the lower panel
3 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1601 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.7
LCDC Line Address Offset Register for Display Data Fetch (LDLAOR)
LDLAOR sets the address width of the Y-coordinates increment used for LCDC to read the image recognized by the graphics driver. This register specifies how many bytes the address from which data is to be read should be moved when the Y coordinates have been incremented by 1. This register does not have to be equal to the horizontal width of the LCD panel. When the memory address of a point (X, Y) in the two-dimensional image is calculated by Ax + By+ C, this register becomes equal to B in this equation.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAO[15:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15 to 0
Bit Name Initial Value LAO [15:0] H'0280
R/W R/W
Description Line Address Offset The minimum alignment unit of LDLAOR is 16 bytes. Because the LCDC handles these values as 16-byte data, the values written to the lower four bits of the register are always treated as 0. The lower four bits of the register are always read as 0. The initial values (x resolution = 640) will continuously and accurately place the VGA (640 x 480 dots) display data without skipping an address between lines. For details, see table 37.5. A binary exponential at least as large as the horizontal width of the image is recommended for the LDLAOR value, taking into consideration the software operation speed. When the hardware rotation function is used, the LDLAOR value should be a binary exponential (in this example, 256) at least as large as the horizontal width of the image (after rotation, it becomes 240 in a 240 x 320 panel) instead of the horizontal width of the LCD panel (320 in a 320 x 240 panel).
Rev. 1.00 Oct. 01, 2007 Page 1602 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.8
LCDC Palette Control Register (LDPALCR)
LDPALCR selects whether the CPU or LCDC accesses the palette memory. When the palette memory is being used for display operation, display mode should be selected. When the palette memory is being written to, color-palette setting mode should be selected.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
PALS
3
2
1
0
PALEN
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
Bit 15 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits always read as 0. The write value should always be 0.
4
PALS
0
R
Palette State Indicates the access right state of the palette. 0: Normal display mode: LCDC uses the palette 1: Color-palette setting mode: The host (CPU) uses the palette
3 to 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PALEN
0
R/W
Palette Read/Write Enable Requests the access right to the palette. 0: Request for transition to normal display mode 1: Request for transition to color palette setting mode
Rev. 1.00 Oct. 01, 2007 Page 1603 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.9
Palette Data Registers 00 to FF (LDPR00 to LDPRFF)
LDPR registers are for accessing palette data directly allocated (4 bytes x 256 addresses) to the memory space. To access the palette memory, access the corresponding register among this register group (LDPR00 to LDPRFF). Each palette register is a 32-bit register including three 8-bit areas for R, G, and B. For details on the color palette specifications, see section 37.4.3, Color Palette Specification.
Bit:
31
30

29

28

27

26

25

24

23
22
21
20
19
18
17
16
PALDnn[23:16]
Initial value: R/W: Bit:
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PALDnn[15:0]
Initial value: R/W: R/W

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 23 to 0
Bit Name
Initial Value R/W R R/W
Description Reserved Palette Data Bits 18 to 16, 9, 8, and 2 to 0 are reserved within each RGB palette and cannot be set. However, these bits can be extended according to the upper bits.
31 to 24
PALDnn[23:0]
Note: nn = H'00 to H'FF
Rev. 1.00 Oct. 01, 2007 Page 1604 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.10 LCDC Horizontal Character Number Register (LDHCNR) LDHCNR specifies the LCD module's horizontal size (in the scan direction) and the entire scan width including the horizontal retrace period.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HDCN[7:0]
HTCN[7:0]
Initial value: 0 R/W: R/W
1 R/W
0 R/W
0 R/W
1 R/W
1 R/W
1 R/W
1 R/W
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
0 R/W
1 R/W
0 R/W
Bit
Bit Name Initial Value R/W 01001111 R/W
Description Horizontal Display Character Number Set the number of horizontal display characters (unit: character = 8 dots). Specify to the value of (the number of display characters) -1. Example: For a LCD module with a width of 640 pixels. HDCN = (640/8) -1 = 79 = H'4F
15 to 0 HDCN [7:0]
7 to 0
HTCN [7:0]
01010010
R/W
Horizontal Total Character Number Set the number of total horizontal characters (unit: character = 8 dots). Specify to the value of (the number of total characters) 1. However, the minimum horizontal retrace period is three characters (24 dots). Example: For a LCD module with a width of 640 pixels. HTCN = [(640/8)-1] +3 = 82 = H'52 In this case, the number of total horizontal dots is 664 dots and the horizontal retrace period is 24 dots.
Notes: 1. The values set in HDCN and HTCN must satisfy the relationship of HTCN HDCN. Also, the total number of characters of HTCN must be an even number. (The set value will be an odd number, as it is one less than the actual number.) 2. Set HDCN according to the display resolution as follows: 1 bpp: (multiplex of 16) - 1 [1 line is multiplex of 128 pixel] 2 bpp: (multiplex of 8) - 1 [1 line is multiplex of 64 pixel] 4 bpp: (multiplex of 4) - 1 [1 line is multiplex of 32 pixel] 6 bpp/8 bpp: (multiplex of 2) - 1 [1 line is multiplex of 16 pixel]
Rev. 1.00 Oct. 01, 2007 Page 1605 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) LDHSYNR specifies the timing of the generation of the horizontal (scan direction) sync signals for the LCD module.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HSYNW[3:0]
HSYNP[7:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R
0 R
0 R
0 R
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15 to 12
Bit Name HSYNW [3:0]
Initial Value R/W 0000 R/W
Description Horizontal Sync Signal Width Set the width of the horizontal sync signals (CL1 and Hsync) (unit: character = 8 dots). Specify to the value of (the number of horizontal sync signal width) -1. Example: For a horizontal sync signal width of 8 dots. HSYNW = (8 dots/8 dots/character) -1 = 0 = H'0
11 to 8
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
7 to 0
HSYNP [7:0]
01010000
R/W
Horizontal Sync Signal Output Position Set the output position of the horizontal sync signals (unit: character = 8 dots). Specify to the value of (the number of horizontal sync signal output position) -1. Example: For a LCD module with a width of 640 pixels. HSYNP = [(640/8) +1] -1 = 80 = H'50 In this case, the horizontal sync signal is active from the 648th through the 655th dot.
Note: The following conditions must be satisfied: HTCN HSYNP+HSYNW+1 HSYNP HDCN+1
Rev. 1.00 Oct. 01, 2007 Page 1606 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) LDVDLNR specifies the LCD module's vertical size (for both scan direction and vertical direction). For a DSTN panel, specify an even number at least as large as the LCD panel's vertical size regardless of the size of the upper and lower panels, e.g. 480 for a 640 x 480 panel.
Bit:
15
14
13
12
11
10
9
8
7
6
5
VDLN[10:0]
4
3
2
1
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
1 R/W
1 R/W
1 R/W
0 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 11
10 to 0
VDLN[10:0]
00111011111 R/W
Vertical Display Line Number Set the number of vertical display lines (unit: line). Specify to the value of (the number of display line) -1. Example: For an 480-line LCD module VDLN = 480-1 = 479 = H'1DF
Rev. 1.00 Oct. 01, 2007 Page 1607 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.13 LCDC Vertical Total Line Number Register (LDVTLNR) LDVTLNR specifies the LCD panel's entire vertical size including the vertical retrace period.
Bit:
15
14
13
12
11
10
9
8
7
6
5
VTLN[10:0]
4
3
2
1
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
1 R/W
1 R/W
1 R/W
0 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 11
10 to 0
VTLN[10:0]
00111011111 R/W
Vertical Total Line Number Set the total number of vertical display lines (unit: line). Specify to the value of (the number of total line) -1. The minimum for the total number of vertical lines is 2 lines. The following conditions must be satisfied: VTLN>=VDLN, VTLN>=1. Example: For an 480-line LCD module and a vertical period of 0 lines. VTLN = (480+0) -1 = 479 = H'1DF
Rev. 1.00 Oct. 01, 2007 Page 1608 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) LDVSYNR specifies the vertical (scan direction and vertical direction) sync signal timing of the LCD module.
Bit:
15
14
13
12
11
10
9
8
7
6
5
VSYNP[10:0]
4
3
2
1
0
VSYNW[3:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R
0 R/W
0 R/W
1 R/W
1 R/W
1 R/W
0 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit
Bit Name
Initial Value 0000
R/W R/W
Description Vertical Sync Signal Width Set the width of the vertical sync signals (FLM and Vsync) (unit: line). Specify to the value of (the vertical sync signal width) -1. Example: For a vertical sync signal width of 1 line. VSYNW = (1-1) = 0 = H'0
15 to 12 VSYNW[3:0]
11
0
R
Reserved This bit is always read as 0. The write value should always be 0.
10 to 0
VSYNP[10:0] 00111011111 R/W
Vertical Sync Signal Output Position Set the output position of the vertical sync signals (FLM and Vsync) (unit: line). Specify to the value of (the number of vertical sync signal output position) -2. DSTN should be set to an odd number value. It is handled as (setting value+1)/2. Example: For an 480-line LCD module and a vertical retrace period of 0 lines (in other words, VTLN=479 and the vertical sync signal is active for the first line): * Single display VSYNP = [(1-1)+VTLN]mod(VTLN+1) = [(1-1)+479]mod(479+1) = 479mod480 = 479 =H'1DF Dual displays VSYNP = [(1-1)x2+VTLN]mod(VTLN+1) = [(1-1)x2+479]mod(479+1) = 479mod480 = 479 =H'1DF
*
Rev. 1.00 Oct. 01, 2007 Page 1609 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) LDACLNR specifies the timing to toggle the AC modulation signal (LCD current-alternating signal) of the LCD module.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
ACLN[4:0]
1
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
1 R/W
1 R/W
0 R/W
0 R/W
Bit 15 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
4 to 0
ACLN[4:0]
01100
R/W
AC Line Number Set the number of lines where the LCD currentalternating signal of the LCD module is toggled (unit: line). Specify to the value of (the number of toggle line) 1. Example: For toggling every 13 lines. ACLN = 13-1 = 12= H'0C
Note: When the total line number of the LCD panel is even, set an even number so that toggling is performed at an odd line.
Rev. 1.00 Oct. 01, 2007 Page 1610 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.16 LCDC Interrupt Control Register (LDINTR) LDINTR specifies where to control the Vsync interrupt of the LCD module. See also section 37.3.20, LCDC User Specified Interrupt Control Register (LDUINTR) and section 37.3.21, LCDC User Specified Interrupt Line Number Register (LDUINTLNR) for interrupts. Note that operations by this register setting and LCDC user specified interrupt control register (LDUINTR) setting are independent.
Bit:
15
MINT EN
14
FINT EN
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VSINT VEINT MINTS FINTS VSINTS VEINTS EN EN
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 15
Bit Name MINTEN
Initial Value 0
R/W R/W
Description Memory Access Interrupt Enable Enables or disables an interrupt generation at the start point of each vertical retrace line period for VRAM access by LCDC. 0: Disables an interrupt generation at the start point of each vertical retrace line period for VRAM access 1: Enables an interrupt generation at the start point of each vertical retrace line period for VRAM access
14
FINTEN
0
R/W
Frame End Interrupt Enable Enables or disables the generation of an interrupt after the last pixel of a frame is output to LDC panel. 0: Disables an interrupt generation when the last pixel of the frame is output 1: Enables an interrupt generation when the last pixel of the frame is output
13
VSINTEN
0
R/W
Vsync Starting Point Interrupt Enable Enables or disables the generation of an interrupt at the start point of LCDC's Vsync. 0: Interrupt at the start point of the Vsync is disabled 1: Interrupt at the start point of the Vsync is enabled
Rev. 1.00 Oct. 01, 2007 Page 1611 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Bit 12
Bit Name VEINTEN
Initial Value 0
R/W R/W
Description Vsync Ending Point Interrupt Enable Enables or disables the generation of an interrupt at the end point of LCDC's Vsync. 0: Interrupt at the end point of the Vsync signal is disabled 1: Interrupt at the end point of the Vsync signal is enabled
11
MINTS
0
R/W
Memory Access Interrupt State Indicates the memory access interrupt handling state. This bit indicates 1 when the LCDC memory access interrupt is generated (set state). During the memory access interrupt handling routine, this bit should be cleared by writing 0. 0: LCDC did not generate a memory access interrupt or has been informed that the generated memory access interrupt has completed 1: LCDC has generated a memory access end interrupt and not yet been informed that the generated memory access interrupt has completed
10
FINTS
0
R/W
Flame End Interrupt State Indicates the flame end interrupt handling state. This bit indicates 1 at the time when the LCDC flame end interrupt is generated (set state). During the flame end interrupt handling routine, this bit should be cleared by writing 0. 0: LCDC did not generate a flame end interrupt or has been informed that the generated flame end interrupt has completed 1: LCDC has generated a flame end interrupt and not yet been informed that the generated flame end interrupt has completed
Rev. 1.00 Oct. 01, 2007 Page 1612 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Bit 9
Bit Name VSINTS
Initial Value 0
R/W R/W
Description Vsync Start Interrupt State Indicates the LCDC's Vsync start interrupt handling state. This bit is set to 1 at the time a Vsync start interrupt is generated. During the Vsync start interrupt handling routine, this bit should be cleared by writing 0 to it. 0: LCDC did not generate a Vsync start interrupt or has been informed that the generated Vsync start interrupt has completed 1: LCDC has generated a Vsync start interrupt and has not yet been informed that the generated Vsync start interrupt has completed
8
VEINTS
0
R/W
Vsync End Interrupt State Indicates the LCDC's Vsync end interrupt handling state. This bit is set to 1 at the time a Vsync end interrupt is generated. During the Vsync end interrupt handling routine, this bit should be cleared by writing 0. 0: LCDC did not generate a Vsync end interrupt or has been informed that the generated Vsync end interrupt has completed 1: LCDC has generated a Vsync end interrupt and has not yet been informed that the generated Vsync interrupt has completed
7 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1613 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.17 LCDC Power Management Mode Register (LDPMMR) LDPMMR controls the power supply circuit that provides power to the LCD module. The usage of two types of power-supply control pins, LCD_VCPWC and LCD_VEPWC, and turning on or off the power supply function are selected.
Bit:
15
14
13
12
11
10
9
8
7
6
VCPE
5
VEPE
4
DONE
3
2
1
0
ONC[3:0]
OFFD[3:0]
LPS[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R/W
0 R/W
1 R/W
0 R
0 R
0 R
0 R
Bit
Bit Name
Initial Value 0000
R/W R/W
Description LCDC Power-On Sequence Period Set the period from LCD_VEPWC assertion to LCD_DON assertion in the power-on sequence of the LCD module in frame units. Specify to the value of (the period) -1. This period is the (c) period in figures 37.4 to 37.7, Power-Supply Control Sequence and States of the LCD Module. For details on setting this register, see table 37.6, Available Power-Supply ControlSequence Periods at Typical Frame Rates. (The setting method is common for ONA, ONB, OFFD, OFFE, and OFFF.)
15 to 12 ONC[3:0]
11 to 8
OFFD[3:0]
0000
R/W
LCDC Power-Off Sequence Period Set the period from LCD_DON negation to LCD_VEPWC negation in the power-off sequence of the LCD module in frame units. Specify to the value of (the period) -1. This period is the (d) period in figures 37.4 to 37.7, Power-Supply Control Sequence and States of the LCD Module.
7
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1614 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Bit 6
Bit Name VCPE
Initial Value 0
R/W R/W
Description LCD_VCPWC Pin Enable Sets whether or not to enable a power-supply control sequence using the LCD_VCPWC pin. 0: Disabled: LCD_VCPWC pin is masked and fixed low 1: Enabled: LCD_VCPWC pin output is asserted and negated according to the power-on or poweroff sequence
5
VEPE
0
R/W
LCD_VEPWC Pin Enable Sets whether or not to enable a power-supply control sequence using the LCD_VEPWC pin. 0: Disabled: LCD_VEPWC pin is masked and fixed low 1: Enabled: LCD_VEPWC pin output is asserted and negated according to the power-on or poweroff sequence
4
DONE
1
R/W
LCD_DON Pin Enable Sets whether or not to enable a power-supply control sequence using the LCD_DON pin. 0: Disabled: LCD_DON pin is masked and fixed low 1: Enabled: LCD_DON pin output is asserted and negated according to the power-on or power-off sequence
3, 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
LPS[1:0]
00
R
LCD Module Power-Supply Input State Indicates the power-supply input state of the LCD module when using the power-supply control function. 0: LCD module power off 1: LCD module power on
Rev. 1.00 Oct. 01, 2007 Page 1615 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR) LDPSPR controls the power supply circuit that provides power to the LCD module. The timing to start outputting the timing signals to the LCD_VEPWC and LCD_VCPWC pins is specified.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ONA[3:0]
ONB[3:0]
OFFE[3:0]
OFFF[3:0]
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
0 R/W
1 R/W
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit
Bit Name
Initial Value 1111
R/W R/W
Description LCDC Power-On Sequence Period Set the period from LCD_VCPWC assertion to starting output of the display data (LCD_D) and timing signals (LCD_FLM, LCD_CL1, LCD_CL2, and LCD_M_DISP) in the power-on sequence of the LCD module in frame units. Specify to the value of (the period)-1. This period is the (a) period in figures 37.4 to 37.7, Power-Supply Control Sequence and States of the LCD Module.
15 to 12 ONA[3:0]
11 to 8
ONB[3:0]
0110
R/W
LCDC Power-On Sequence Period Set the period from starting output of the display data (LCD_D) and timing signals (LCD_FLM, LCD_CL1, LCD_CL2, and LCD_M_DISP) to the LCD_VEPWC assertion in the power-on sequence of the LCD module in frame units. Specify to the value of (the period)-1. This period is the (b) period in figures 37.4 to 37.7, Power-Supply Control Sequence and States of the LCD Module.
Rev. 1.00 Oct. 01, 2007 Page 1616 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Bit 7 to 4
Bit Name OFFE[3:0]
Initial Value 0000
R/W R/W
Description LCDC Power-Off Sequence Period Set the period from LCD_VEPWC negation to stopping output of the display data (LCD_D) and timing signals (LCD_FLM, LCD_CL1, LCD_CL2, and LCD_M_DISP) in the power-off sequence of the LCD module in frame units. Specify to the value of (the period)-1. This period is the (e) period in figures 37.4 to 37.7, Power-Supply Control Sequence and States of the LCD Module.
3 to 0
OFFF[3:0]
1111
R/W
LCDC Power-Off Sequence Period Set the period from stopping output of the display data (LCD_D) and timing signals (LCD_FLM, LCD_CL1, LCD_CL2, and LCD_M_DISP) to LCD_VCPWC negation to in the power-off sequence of the LCD module in frame units. Specify to the value of (the period)-1. This period is the (f) period in figures 37.4 to 37.7, Power-Supply Control Sequence and States of the LCD Module.
Rev. 1.00 Oct. 01, 2007 Page 1617 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.19 LCDC Control Register (LDCNTR) LDCNTR specifies start and stop of display by the LCDC. When 1s are written to the DON2 bit and the DON bit, the LCDC starts display. Turn on the LCD module following the sequence set in the LDPMMR and LDCNTR. The sequence ends when the LPS[1:0] value changes from B'00 to B'11. Do not make any action to the DON bit until the sequence ends. When 0 is written to the DON bit, the LCDC stops display. Turn off the LCD module following the sequence set in the LDPMMR and LDCNTR. The sequence ends when the LPS[1:0] value changes from B'11 to B'00. Do not make any action to the DON bit until the sequence ends.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
DON2
3
2
1
0
DON
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R
0 R
0 R
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 5
4
DON2
0
R/W
Display On 2 Specifies the start of the LCDC display operation. 0: LCDC is being operated or stopped 1: LCDC starts operation When this bit is read, always read as 0. Write 1 to this bit only when starting display. If a value other than 0 is written when starting display, the operation is not guaranteed. When 1 is written to, it resumes automatically to 0. Accordingly, this bit does not need to be cleared by writing 0.
3 to 1
All 0
R
Reserved. These bits are always read as 0. The write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1618 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Bit 0
Bit Name DON
Initial Value 0
R/W R/W
Description Display On Specifies the start and stop of the LCDC display operation. The control sequence state can be checked by referencing the LPS[1:0] of LDPMMR. 0: Display-off mode: LCDC is stopped 1: Display-on mode: LCDC operates
Notes: 1. Write H'0011 to LDCNTR when starting display and H'0000 when completing display. Data other than H'0011 and H'0000 must not be written to. 2. Setting bit DON2 to 1 makes the contents of the palette RAM undefined. Before writing to the palette RAM, set bit DON2 to 1.
37.3.20 LCDC User Specified Interrupt Control Register (LDUINTR) LDUINTR sets whether the user specified interrupt is generated, and indicates its processing state. This interrupt is generated at the time when image data which is set by the line number register (LDUINTLNR) in LCDC is read from VRAM. This LCDC issues the interrupts (LCDCI): user specified interrupt by this register, memory access interrupt by the LCDC interrupt control register (LDINTR), and OR of Vsync interrupt output. This register and LCDC interrupt control register (LDINTR) settings affect the interrupt operation independently.
Bit:
15
14
13
12
11
10
9
8
UINTEN
7
6
5
4
3
2
1
0
UINTS
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 9
8
UINTEN
0
R/W
User Specified Interrupt Enable Sets whether generate an LCDC user specified interrupt. 0: LCDC user specified interrupt is not generated 1: LCDC user specified interrupt is generated
Rev. 1.00 Oct. 01, 2007 Page 1619 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Bit 7 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved. These bits are always read as 0. The write value should always be 0.
0
UINTS
0
R/W
User Specified Interrupt State This bit is set to 1 at the time an LCDC user specified interrupt is generated (set state). During the user specified interrupt handling routine, this bit should be cleared by writing 0 to it. 0: LCDC did not generate a user specified interrupt or has been informed that the generated user specified interrupt has completed 1: LCDC has generated a user specified interrupt and has not yet been notified that the generated user specified interrupt has completed
Note:
Interrupt processing flow: 1. Interrupt signal is input 2. LDINTR is read 3. If MINTS, FINTS, VSINTS, or VEINTS is 1, a generated interrupt is memory access interrupt, flame end interrupt, Vsync rising edge interrupt, or Vsync falling edge interrupt. Processing for each interrupt is performed. 4. If MINTS, FINTS, VSINTS, or VEINTS is 0, a generated interrupt is not memory access interrupt, flame end interrupt, Vsync rising edge interrupt, or Vsync falling edge interrupt. 5. UINTS is read. 6. If UINTS is 1, a generated interrupt is a user specified interrupt. Process for user specified interrupt is carried out. 7. If UINTS is 0, a generated interrupt is not a user specified interrupt. Other processing is performed.
Rev. 1.00 Oct. 01, 2007 Page 1620 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.21 LCDC User Specified Interrupt Line Number Register (LDUINTLNR) LDUINTLNR sets the point where the user specified interrupt is generated. Setting is done in horizontal line units.
Bit:
15
14
13
12
11
10
9
8
7
6
5
UINTLN[10:0]
4
3
2
1
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 11
10 to 0 UINTLN [10:0]
00001001111 R/W
User Specified Interrupt Generation Line Number Specifies the line in which the user specified interrupt is generated (line units). Set (the number of lines in which interrupts are generated) -1 Example: Generate the user specified interrupt in the 80th line. UINTLN = 160/2 - 1 = 79 = H'04F
Notes: 1. When using the LCD module with STN/TFT display, the setting value of this register should be equal to lower than the vertical display line number (VDLN) in LDVDLNR. 2. When using the LCD module with DSTN display, the setting value of this register should be equal to or lower than half the vertical display line number (VDLN) in LDVDLNR. The user specified interrupt is generated at the point when the LCDC read the specified piece of image data in lower display from VRAM.
Rev. 1.00 Oct. 01, 2007 Page 1621 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.3.22 LCDC Memory Access Interval Number Register (LDLIRNR) LDLIRNR controls the bus cycle interval when the LCDC reads VRAM. When LDLIRNR is set to a value other than H'00, the LCDC does not access VRAM until clock count of the DDRSDRAM matches the value set in LDLIRNR. When LDLIRNR is set to H'00 (initial value), the LCDC accesses VRAM one clock after the LCDC accessed VRAM.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LIRN[7:0]
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 8
7 to 0
LIRN[7:0]
All 0
R/W
VRAM Read Bus Cycle Interval Specifies the number of the DDR-SDRAM clock cycles which can be performed during burst cycles to read VRAM by LCDC. H'00: one clock cycle H'01: one clock cycle H'02: two clock cycles : H'FE: 254 clock cycles H'FF: 255 clock cycles
Rev. 1.00 Oct. 01, 2007 Page 1622 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.4
37.4.1
Operation
LCD Module Sizes which can be Displayed in this LCDC
This LCDC is capable of controlling displays with up to 1024 x 1024 dots and 16 bpp (bits per pixel). The image data for display is stored in VRAM, which is shared with the CPU. This LCDC should read the data from VRAM before display. This LSI has a maximum 32-burst memory read operation and a 2.4-Kbyte line buffer, so although a complete breakdown of the display is unlikely, there may be some problems with the display depending on the combination. A recommended size at the frame rate of 60 Hz is 320 x 240 dots in 16 bpp or 640 x 480 dots in 8 bpp. As a rough standard, the bus occupation ratio shown below should not exceed 40%.
Overhead coefficient x Total number of display pixels ((HDCN + 1) x 8 x (VDLN + 1)) x Frame rate (Hz) x Number of colors (bpp) Bus occupation ratio (%) =
CLKOUT (Hz) x Bus width (bit)
x 100
The overhead coefficient becomes 1.375 when the CL2.5 DDR-SDRAM is connected to a 32-bit data bus.
Rev. 1.00 Oct. 01, 2007 Page 1623 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Figure 37.2 shows the valid display and the retrace period.
Hsync Signal
H Total Time
Hsync Time
Right Border
Back Porch
H AddressableVideo
Front Porch
Left Border
Vsync Time Back Porch Top Border V Addressable Video Bottom Border
Front Porch
Active Video =Top/Left Border + Addressable Video + Bottom/Right Border Total H Blank = Hsync Time + Back Porch + Front Porch Total V Blank = Vsync Time + Back Porch + Front Porch HTCN = H Total Time HDCN = H Addressable Video HSYNP = H Addressable Video + Right Border + Front Porch HSYNW = Hsync Time VTLN = V Total Time CDLN = V Addressable Video VSYNP = V Addressable Video + Bottom Border + Front porch VSYNW = Vsync Time
V Total Time
Figure 37.2 Valid Display and the Retrace Period
Rev. 1.00 Oct. 01, 2007 Page 1624 of 1956 REJ09B0256-0100
Vsync Signal
Section 37 LCD Controller (LCDC)
37.4.2
Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (SDRAM)
This LCDC is capable of displaying a landscape-format image on a LCD module by rotating a portrait format image for display by 90 degrees. Only the numbers of colors for each resolution are supported as shown in table 37.5. The size of the SDRAM (the number of column address bits) and its burst length are limited to read the SDRAM continuously. The number of colors for display, SDRAM column addresses, and LCDC burst length are shown table 37.5. A monochromatic LCD module is necessary for the display of images in the above monochromatic formats. A color LCD module is necessary for the display of images in the above color formats. Table 37.5 Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (32-bit SDRAM)
Image for Display in Memory (X-Resolution x YResolution) LCD Module (X-Resolution x Number of Colors for Y-Resolution) Display Number of Column Address Bits of Burst Length of SDRAM LCDC (LDSMR*)
240 x 320
320 x 240
Monochrome 4 bpp (packed)
9 bits 10 bits
Not more than 16 bursts Not more than 8 bursts Not more than 16 bursts Not more than 8 bursts Not more than 16 bursts Not more than 8 bursts Not more than 16 bursts
9 bits 4 bpp (unpacked) 10 bits 6 bpp 9 bits 10 bits Color 8 bpp 9 bits 10 bits
Rev. 1.00 Oct. 01, 2007 Page 1625 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Image for Display in Memory (X-Resolution x YResolution)
LCD Module (X-Resolution x Number of Colors for Y-Resolution) Display
Number of Column Address Bits of Burst Length of SDRAM LCDC (LDSMR*)
240 x 320
320 x 240
16 bpp
9 bits 10 bits
4 bursts Not more than 8 bursts Not more than 8 bursts Not more than 16 bursts 4 bursts Not more than 8 bursts Not more than 16 bursts Not more than 16 bursts Not more than 16 bursts Not more than 16 bursts Not more than 8 bursts Not more than 16 bursts
234 x 320
320 x 234
Monochrome 6 bpp
9 bits 10 bits
Color
16 bpp
9 bits 10 bits
80 x 160
160 x 80
Monochrome 2 bpp
9 bits 10 bits
4 bpp (packed)
9 bits 10 bits
4 bpp 9 bits (unpacked) 10 bits 6 bpp 9 bits 10 bits Color 4 bpp (packed) 9 bits 10 bits
9 bits 4 bpp (unpacked) 10 bits 8 bpp 9 bits 10 bits 16 bpp 9 bits 10 bits
Rev. 1.00 Oct. 01, 2007 Page 1626 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Image for Display in Memory (X-Resolution x YResolution)
LCD Module (X-Resolution x Number of Colors for Y-Resolution) Display
Number of Column Address Bits of Burst Length of SDRAM LCDC (LDSMR*)
64 x 128
128 x 64
Monochrome 1 bpp
9 bits 10 bits

2 bpp
9 bits 10 bits
4 bpp (packed)
9 bits 10 bits
4 bpp 9 bits (unpacked) 10 bits 6 bpp 9 bits 10 bits Color 4 bpp (packed) 4 bpp 9 bits 10 bits 9 bits
(unpacked) 10 bits 8 bpp Note: * 9 bits 10 bits
Specify the data of the number of line specified as burst length can be stored in address of SDRAM same as that of ROM.
Rev. 1.00 Oct. 01, 2007 Page 1627 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.4.3 (1)
Color Palette Specification
Color Palette Register
This LCDC has a color palette which outputs 24 bits of data per entry and is able to simultaneously hold 256 entries. The color palette thus allows the simultaneous display of 256 colors chosen from among 16-M colors. The procedure below may be used to set up color palettes at any time. 1. The PALEN bit in the LDPALCR is 0 (initial value); normal display operation 2. Access LDPALCR and set the PALEN bit to 1; enter color-palette setting mode after three cycles of peripheral clock. 3. Access LDPALCR and confirm that the PALS bit is 1. 4. Access LDPR00 to LDPRFF and write the required values to the PALD00 to PALDFF bits. 5. Access LDPALCR and clear the PALEN bit to 0; return to normal display mode after a cycle of peripheral clock. A 0 is output on the LCDC display data output (LCD_D) while the PALS bit in LDPALCR is set to 1.
31 23 15 7 0 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Color Monochrome
M7 M6 M5 M4 M3 M2 M1 M0
Figure 37.3 Color-Palette Data Format PALDnn color and gradation data should be set as above. For a color display, PALDnn[23:16], PALDnn[15:8], and PALDnn[7:0] respectively hold the R, G, and B data. Although the bits PALDnn[18:16], PALDnn[9:8], and PALDnn[2:0] exist, no memory is associated with these bits. PALDnn[18:16], PALDnn[9:8], and PALDnn[2:0] are thus not available for storing palette data. The numbers of valid bits are thus R: 5, G: 6, and B: 5. A 24bit (R: 8 bits, G: 8 bits, and B: 8 bits) data should, however, be written to the palette-data registers. When the values for PALDnn[23:19], PALDnn[15:10], or PALDnn[7:3] are not 0, 1 or 0 should be written to PALDnn[18:16], PALDnn[9:8], or PALDnn[2:0], respectively. When the values of PALDnn[23:19], PALDnn[15:10], or PALDnn[7:3] are 0, 0s should be written to PALDnn[18:16], PALDnn[9:8], or PALDnn[2:0], respectively. Then 24 bits are extended. Grayscale data for a monochromatic display should be set in PALDnn[7:3]. PALDnn[23:8] are all "don't care". When the value in PALDnn[7:3] is not 0, 1s should be written to PALDnn[2:0].
Rev. 1.00 Oct. 01, 2007 Page 1628 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
When the value in PALDnn[7:3] is 0, 0s should be written to PALDnn[2:0]. Then 8 bits are extended. 37.4.4 Data Format
1. Packed 1bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
MSB LSB 76 5 4 3 2 1 0 [Bit] P00 P01 P02 P03 P04 P05 P06 P07 (Byte0) (Byte1) P08 ... P10 P11 P12 P13 P14 P15 P16 P17 P18 ... Display Memory Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ...
Display Pn: Put 1-bit data
Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ...
... ...
LAO: Line Address Offset --Unused bits should be 0
2. Packed 2bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... MSB 76 P00 P04 54 P01 P05 ... P11 P15 ... 32 P02 P06 LSB 1 0 [Bit] P03 (Byte0) P07 (Byte1)
Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display
Pn=Pn[1:0]: Put 2-bit data
... ...
P10 P14
P12 P16
P13 P17
Display Memory
LAO: Line Address Offset --Unused bits should be 0
3. Packed 4bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... MSB 76 5 P00 P02 P04 4 3 21 P01 P03 P05 LSB 0 [Bit] (Byte0) (Byte1) (Byte2)
Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display
Pn=Pn[3:0]: Put 4-bit data
... ...
... P10 P12 P14 ... Display Memory P11 P13 P15
LAO: Line Address Offset --Unused bits should be 0
Rev. 1.00 Oct. 01, 2007 Page 1629 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
4. Packed 1bpp (Pixel Alignment in Byte is Little Endian)
Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... MSB LSB 76 5 4 3 2 1 0 [Bit] P07 P06 P05 P04 P03 P02 P01 P00 (Byte0) P08 (Byte1) ... P17 P16 P15 P14 P13 P12 P11 P10 P18 ... Display Memory Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display
Pn: Put 1-bit data
... ...
LAO: Line Address Offset --Unused bits should be 0
5. Packed 2bpp (Pixel Alignment in Byte is Little Endian)
Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... MSB 7 6 P03 P07 54 P02 P06 ... P12 P16 ... 32 P01 P05 LSB 1 0 [Bit] P00 (Byte0) P04 (Byte1)
Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display
Pn = Pn[1:0]: Put 2-bit data
... ...
P13 P17
P11 P15
P10 P14
Display Memory
LAO: Line Address Offset --Unused bits should be 0
6. Packed 4bpp (Pixel Alignment in Byte is Little Endian)
Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... MSB 7 65 P01 P03 P05 4 3 21 P00 P02 P04 LSB 0 [Bit] (Byte0) (Byte1) (Byte2)
Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display
Pn = Pn[3:0]: Put 4-bit data
... ...
... P11 P13 P15 ... Display Memory P10 P12 P14
LAO: Line Address Offset --Unused bits should be 0
Rev. 1.00 Oct. 01, 2007 Page 1630 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
7. Unpacked 4bpp [Windows CE Recommended Format]
Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... MSB 7 6 5 4 3 21 P00 P01 P02 LSB 0 [Bit] (Byte0) (Byte1) (Byte2) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display Pn = Pn[3:0]: Put 4-bit data ... ...
... P10 P11 P12 ... Display Memory
LAO: Line Address Offset --Unused bits should be 0
8. Unpacked 5bpp [Windows CE Recommended Format]
Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... MSB 7 6 5 4 3 2 P00 P01 P02 1 LSB 0 [Bit] (Byte0) (Byte1) (Byte2) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display Pn = Pn[4:0]: Put 5-bit data ... ...
... P10 P11 P12 ... Display Memory
LAO: Line Address Offset --Unused bits should be 0
9. Unpacked 6bpp [Windows CE Recommended Format]
Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... MSB 7 6 5 4 3 2 P00 P01 P02 1 LSB 0 [Bit] (Byte0) (Byte1) (Byte2) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display Pn = Pn[5:0]: Put 6-bit data ... ...
... P10 P11 P12 ... Display Memory
LAO: Line Address Offset --Unused bits should be 0
Rev. 1.00 Oct. 01, 2007 Page 1631 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
10. Packed 8bpp [Windows CE Recommended Format]
Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... MSB 76 5 43 P00 P01 P02 ... P10 P11 P12 ... Display Memory
Pn = Pn[7:0]: Put 8-bit data
2
1
LSB 0 [Bit] (Byte0) (Byte1) (Byte2)
Top Left Pixel P00P01 P02 P03 P04 P05 P06 P07 P10P11 P12 P13 P14 P15 P16 P17 ... ... Display
... ...
LAO: Line Address Offset --Unused bits should be 0
11. Unpacked color 15bpp (RGB 555) [Windows CE Recommended Format]
Address +00 +02 +04 +06 ... +LAO+00 +LAO+02 +LAO+04 +LAO+06 ... MSB 15 14 13 12 11 10 P00R P01R P02R 9 876 P00G P01G P02G ... P10R P11R P12R P10G P11G P12G ... Display Memory P10B P11B P12B 5 4 321 P00B P01B P02B
Top Left Pixel LSB 0 [Bit] P00P01 P02 P03 P04 P05 P06 P07 (Word0) P10P11 P12 P13 P14 P15 P16 P17 ... (Word2) (Word4) Display ... ...
Pr = (PrR, PrG, PrB). Pr 15-bit data PrR = PrR[4.0]. Pr 5-bit RED data PrG = PrG[4.0]. Pr 5-bit GREEN data PrB = PrB[4.0]. Pr 5-bit BLUE data LAO: Line Address Offset --Unused bits should be 0
12. Packed color 16bpp (RGB 565) [Windows CE Recommended Format]
Address +00 +02 +04 +06 ... +LAO+00 +LAO+02 +LAO+04 +LAO+06 ... MSB 15 14 13 12 11 10 P00R P01R P02R 9 87 P00G P01G P02G ... P10R P11R P12R P10G P11G P12G ... Display Memory P10B P11B P12B 6 5 4 321 P00B P01B P02B
Top Left Pixel LSB 0 [Bit] P00P01 P02 P03 P04 P05 P06 P07 (Word0) P10P11 P12 P13 P14 P15 P16 P17 ... (Word2) Display (Word4) ... ...
Pr = (PrR, PrG, PrB). Pr 16-bit data PrR = PrR[4.0]. Pr 5-bit RED data PrG = PrG[5.0]. Pr 6-bit GREEN data PrB = PrB[4.0]. Pr 5-bit BLUE data LAO: Line Address Offset --Unused bits should be 0
Rev. 1.00 Oct. 01, 2007 Page 1632 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
37.4.5
Setting the Display Resolution
The display resolution is set up in LDHCNR, LDHSYNR, LDVDLNR, LDVTLNR, and LDVSYNR. The LCD current-alternating period for an STN or DSTN display is set by using the LDACLNR. The initial values in these registers are typical settings for VGA (640 x 480 dots) on an STN or DSTN display. The clock to be used is set with the LDICKR. The LCD module frame rate is determined by the display interval + retrace line interval (non-display interval) for one screen set in a size related register and the frequency of the clock used. This LCDC has a Vsync interrupt function so that it is possible to issue an interrupt at the beginning of each vertical retrace line period (to be exact, at the beginning of the line after the last line of the display). This function is set up by using the LDINTR. 37.4.6 Power-Supply Control Sequence
An LCD module normally requires a specific sequence for processing to do with the cutoff of the input power supply. Settings in LDPMMR, LDPSPR, and LDCNTR, in conjunction with the LCD power-supply control pins (LCD_VCPWC, LCD_VEPWC, and LCD_DON), are used to provide processing of power-supply control sequences that suits the requirements of the LCD module. Figures 37.4 to 37.7 are timing charts that show outlines of power-supply control sequences and table 37.6 is a summary of available power-supply control sequence periods. Figures 37.4 to 37.7 show operations of the normal output pins (LCD_***). The mirror pins (LCDM_***) have the same timing as the normal output pins.
Rev. 1.00 Oct. 01, 2007 Page 1633 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
(1) STN, DSTN Power-Supply Control
(in) DON register
Start power supply
(out) LCD_VCPWC pin (out) Display data, timing signal
Start power cutoff
VCPE = ON
Undefined
Arbitrary
Undefined
(out) LCD_VEPWC pin (out) LCD_DON pin Register control sequence (out) LPS register
VEPE = ON
DONE = ON
(a) 0 frame
(c) (b) 1 frame 1 frame
(d) 1 frame
(e) 1 frame
(f) 0 frame
00b LCD module stopped
00b, 11b
11b LCD module active
00b, 11b
00b LCD module stopped
Figure 37.4 Power-Supply Control Sequence and States of the LCD Module
(2) Power-Supply Control for LCD Panels other than STN or DSTN (in) DON register
Start power supply
(out) LCD_VCPWC pin (out) Display data, timing signal (out) LCD_VEPWC pin (out) LCD_DON pin
Start power cutoff
(Internal signal) VCPE = OFF
Undefined
Arbitrary (Internal signal)
Undefined
VEPE = OFF
DONE = ON
Register control sequence (out) LPS register
(a) 0 frame (b) 0 frame 00b
LCD module stopped
(c) 1 frame
(d) 1 frame
(f) 0 frame (e) 0 frame
00b, 11b
11b
LCD module active
00b, 11b
00b
LCD module stopped
Figure 37.5 Power-Supply Control Sequence and States of the LCD Module
Rev. 1.00 Oct. 01, 2007 Page 1634 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
(3) Power-Supply Control for TFT Panels (in) DON register Start power supply (out) LCD_VCPWC pin (out) Display data, timing signal Undefined Arbitrary Undefined Start power cutoff VCPE = ON
(out) LCD_VEPWC pin (Internal signal) (out) LCD_DON pin (a) 1 frame (f) 1 frame
VEPE = ON
DONE = OFF
Register control sequence (out) LPS register 00b LCD module stopped
(b) 6 frame
(c) 0 frame 11b
(d) 0 frame
(e) 1 frame
00b, 11b
00b, 11b
00b LCD module stopped
LCD module active
Figure 37.6 Power-Supply Control Sequence and States of the LCD Module
(4) Power Supply Control for LCD panels other than TFT
(in) DON register
Start power supply
(out) LCD_VCPWC pin (out) Display data, timing signal (out) LCD_VEPWC pin
(Internal signal) Start power cutoff VCPE = OFF
Undefined
Arbitrary (Internal signal)
Undefined
VEPE = OFF (Internal signal)
(out) LCD_DON pin Register control sequence
DONE = OFF
(a) 0 frame (b) 0 frame (c) 0 frame 00b
LCD module stopped
(f) 0 frame (e) 0 frame (d) 0 frame 11b
LCD module active
(out) LPS register
00b
LCD module stopped
Figure 37.7 Power-Supply Control Sequence and States of the LCD Module
Rev. 1.00 Oct. 01, 2007 Page 1635 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Table 37.6 Available Power-Supply Control-Sequence Periods at Typical Frame Rates
ONX, OFFX Register Value H'F H'0 H'1 H'2 H'3 H'4 H'5 H'6 H'7 H'8 H'9 H'A H'B H'C H'D H'E Frame Rate 120 Hz (-1+1)/120 = 0.00 (ms) (0+1)/120 = 8.33 (ms) (1+1)/120 = 16.67 (ms) (2+1)/120 = 25.00 (ms) (3+1)/120 = 33.33 (ms) (4+1)/120 = 41.67 (ms) (5+1)/120 = 50.00 (ms) (6+1)/120 = 58.33 (ms) (7+1)/120 = 66.67 (ms) (8+1)/120 = 75.00 (ms) (9+1)/120 = 83.33 (ms) (10+1)/120 = 91.67 (ms) (11+1)/120 = 100.00 (ms) (12+1)/120 = 108.33 (ms) (13+1)/120 = 116.67 (ms) (14+1)/120 = 125.00 (ms) 60 Hz (-1+1)/60 = 0.00 (ms) (0+1)/60 = 16.67 (ms) (1+1)/60 = 33.33 (ms) (2+1)/60 = 50.00 (ms) (3+1)/60 = 66.67 (ms) (4+1)/60 = 83.33 (ms) (5+1)/60 = 100.00 (ms) (6+1)/60 = 116.67 (ms) (7+1)/60 = 133.33 (ms) (8+1)/60 = 150.00 (ms) (9+1)/60 = 166.67 (ms) (10+1)/60 = 183.33 (ms) (11+1)/60 = 200.00 (ms) (12+1)/60 = 216.67 (ms) (13+1)/60 = 233.33 (ms) (14+1)/60 = 250.00 (ms)
ONA, ONB, ONC, OFFD, OFFE, and OFFF are used to set the power-supply control-sequence periods, in units of frames, from 0 to 15. 1 is subtracted from each register. H'0 to H'E settings select from 1 to15 frames. The setting H'F selects 0 frames. Actual sequence periods depend on the register values and the frame frequency of the display. The following table gives power-supply control-sequence periods for display frame frequencies used by typical LCD modules. * When ONB is set to H'6 and display's frame frequency is 120 Hz The display's frame frequency is 120 Hz. 1 frame period is thus 8.33 (ms) = 1/120 (sec). The power-supply input sequence period is 7 frames because ONB setting is subtracted by 1. As a result, the sequence period is 58.33 (ms) = 8.33 (ms) x 7.
Rev. 1.00 Oct. 01, 2007 Page 1636 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
Table 37.7 LCDC Operating Modes
Mode Display on (LCDC active) Register setting: DON = 1 Function Fixed resolution, the format of the data for display is determined by the number of colors, and timing signals are output to the LCD module. Register access is enabled. Fixed resolution, the format of the data for display is determined by the number of colors, and timing signals are not output to the LCD module.
Display off (LCDC stopped)
Register setting: DON = 0
Table 37.8 LCD Module Power-Supply States (STN, DSTN module)
Power Supply for Logic LCD_VCPWC Display Data, Timing Signal LCD_CL2, LCD_CL1, LCD_FLM, LCD_M_DISP, LCD_D Supply Supply Supply Power Supply for High-Voltage Systems DON Signal LCD_VEPWC LCD_DON
State Control Pin
Operating State (Transitional State)
Supply Supply Supply Supply
Supply Supply
Supply
Stopped State
Rev. 1.00 Oct. 01, 2007 Page 1637 of 1956 REJ09B0256-0100
Section 37 LCD Controller (LCDC)
(TFT module)
State Control Pin Power Supply for Logic LCD_VCPWC Display Data, Timing Signal LCD_CL2, LCD_CL1, LCD_FLM, LCD_M_DISP, LCD_D Supply Supply Power Supply for HighVoltage Systems LCD_VEPWC
Operating State (Transitional State)
Supply Supply Supply
Supply
Stopped State
The table above shows the states of the power supply, display data, and timing signals for the typical LCD module in its active and stopped states. Some of the supply voltages described may not be necessary, because some modules internally generate the power supply required for highvoltage systems from the logic-level power-supply voltage. Notes on display-off mode (LCDC stopped): If LCD module power-supply control-sequence processing is in use by the LCDC or the supply of power is cut off while the LCDC is in its display-on mode, normal operation is not guaranteed. In the worst case, the connected LCD module may be damaged. 37.4.7 Operation for Hardware Rotation
Operation in hardware-rotation mode is described below. Hardware-rotation mode can be thought of as using a landscape-format LCD panel instead of a portrait-format LCD panel by placing the landscape-format LCD panel as if it were a portrait-format panel. Whether the panel is intended for use in landscape or portrait format is thus no problem. The panel must, however, be within 320 pixels wide. When making settings for hardware rotation, the following five differences from the setting for no hardware rotation must be noted. (The following example is for a display at 8 bpp. At 16 bpp, the amount of memory per dot will be doubled. The image size and register values used for rotation will thus be different.) 1. The image data must be prepared for display in the rotated panel. (If 240 x 320 pixels will be required after rotation, 240 x 320 pixel image data must be prepared.) 2. The register settings for the address of the image data must be changed (LDSARU and LDLAOR).
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Section 37 LCD Controller (LCDC)
3. LDLAOR should be power of 2 (when the horizontal width after rotation is 240 pixels, LDLAOR should be set to 256). 4. Graphics software should be set up for the number 3 setting. 5. LDSARU should be changed to represent the address of the data for the lower-left pixel of the image rather than of the data for the upper-left pixel of the image.
1) Normal mode
LDSARU (start point) Picture image
LDSARU + LDLAOR - 1
Picture image
Scanning starts from LDSARU. Scanning is done from small address to large address of X coordination.
LDSARU + LDLAOR x LDVDLNR - 1(end point)
Start point LCD panel
Picture image
End point
Figure 37.8 Operation for Hardware Rotation (Normal Mode) For example, the registers have been set up for the display of image data in landscape format (320 x 240), which starts from LDSARU = 0x0c001000, on a 320 x 240 LCD panel. The graphics driver software is complete. Some changes are required to apply hardware rotation and use the panel as a 240 x 320 display. If LDLAOR is 512, the graphics driver software uses this power of 2 as the offset for the calculation of the addresses of Y coordinates in the image data. Before setting ROT to 1, the image data must be redrawn to suit the 240 x 320 LCD panel. LDLAOR will then be 256 because the size has changed and the graphics driver software must be altered accordingly. The point that corresponds to LDSARU moves from the upper left to the lower left of the display, so LDSARU should be changed to 0x0c001000 + 256 * 319.
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Section 37 LCD Controller (LCDC)
Note: Hardware rotation allows the use of an LCD panel that has been rotated by 90 degrees. The settings in relation to the LCD panel should match the settings for the LCD panel before rotation. Rotation is possible regardless of the drawing processing carried out by the graphics driver software. However, the sizes in the image data and address offset values which are managed by the graphics driver software must be altered.
2) Rotation mode
LDSARU - LDLAOR x (HDCN x 8 - 2) - 1(end point) Picture image
Scanning starts from LDSARU. Scanning is done from large address to small address of Y coordination.
LDSARU (start point)
Start point LCD panel
End point
Figure 37.9 Operation for Hardware Rotation (Rotation Mode)
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Section 37 LCD Controller (LCDC)
37.5
Clock and LCD Data Signal Examples
The following timing charts show timing of the normal output pins (LCD_***). The mirror pins (LCDM_***) have the same timing as the normal output pins.
1) STN monochrome 4-bit data bus module
DOTCLK LCD_CL2 LCD_D3 LCD_D2 LCD_D1 LCD_D0 LCD_D4 to 15 Low B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
Figure 37.10 Clock and LCD Data Signal Example
2) STN monochrome 8-bit data bus module
DOTCLK LCD_CL2
LCD_D7 LCD_D6 LCD_D5 LCD_D4
B0 B1 B2 B3 B4 B5 B6 B7
B8 B9 B10 B11
B12 B13 B14
B15
LCD_D3 LCD_D2 LCD_D1 LCD_D0
LCD_D8 to 15
Low
Figure 37.11 Clock and LCD Data Signal Example (STN Monochrome 8-Bit Data Bus Module)
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Section 37 LCD Controller (LCDC)
3) STN color 4-bit data bus module
DOTCLK LCD_CL2
LCD_D3 LCD_D2 LCD_D1 LCD_D0 R0 G0 B0 R1 G1 B1 R2
G2 B2 R3 G3
B3 R4 G4 B4
R5 G5 B5 R6
G6 B6 R7 G7
B7 R8 G8 B8
R9 G9 B9 R10
G10 B10 R11 G11
B11
R12 G13 G12 B13 B12 R14
R13 G14
B14 R15 G15
B15
LCD_D4 to 15
Low
Figure 37.12 Clock and LCD Data Signal Example (STN Color 4-Bit Data Bus Module)
4) STN color 8-bit data bus module
DOTCLK LCD_CL2
LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0 R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7
B7 R8 G8 B8 R9 G9
B9 B10 R11 G11 B11 R12 G12 B12 R13 G13 B13 R14 G14 B14 R15 G15 B15
R10
G10
LCD_D8 to 15
Low
Figure 37.13 Clock and LCD Data Signal Example (STN Color 8-Bit Data Bus Module)
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Section 37 LCD Controller (LCDC)
5) STN color 12-bit data bus module
DOTCLK LCD_CL2 LCD_D11 LCD_D10 LCD_D9 LCD_D8 LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0 LCD_D12 to 15 Low R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 B10 R11 G11 B11 R12 G12 B12 R13 G13 B13 R14 G14 B14 R15 G15 B15
Figure 37.14 Clock and LCD Data Signal Example (STN Color 12-Bit Data Bus Module)
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Section 37 LCD Controller (LCDC)
6) STN color 16-bit data bus module
DOTCLK LCD_CL2
LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D9 LCD_D8
R0 G0 B0 R1 G1
B1
G5 B5 R6 G6 B6 R7 G7
B7 R8 G8 B8 R9 G9
B9
B10 R11 G11 B11 R12 G12 B12 R13 G13 B13 R14 G14 B14 R15 G15 B15
R2
G2
B2 R3 G3 B3 R4 G4 B4 R5
LCD_D7 LCD_D6 LCD_D5 LCD_D4
LCD_D3 LCD_D2 LCD_D1 LCD_D0
R10
G10
Figure 37.15 Clock and LCD Data Signal Example (STN Color 16-Bit Data Bus Module)
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Section 37 LCD Controller (LCDC)
7) DSTN monochrome 8-bit data bus module
DOTCLK LCD_CL2 LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0 UB0 UB1 UB2 UB3 LB0 LB1 LB2 LB3 UB4 UB5 UB6 UB7 LB4 LB5 LB6 LB7
LCD_DATA8 to 15 Low
Figure 37.16 Clock and LCD Data Signal Example (DSTN Monochrome 8-Bit Data Bus Module)
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Section 37 LCD Controller (LCDC)
8) DSTN monochrome 16-bit data bus module DOTCLK LCD_CL2
LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D9 LCD_D8 LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0 UB0 UB1 UB2 UB3 UB4 UB5 UB6 UB7 LB0 LB1 LB2 LB3 LB4 LB5 LB6 LB7
Figure 37.17 Clock and LCD Data Signal Example (DSTN Monochrome 16-Bit Data Bus Module)
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Section 37 LCD Controller (LCDC)
9) DSTN color 8-bit data bus module
DOTCLK LCD_CL2
LCD_D7 LCD_D6 LCD_D5 LCD_D4
UR0 UG0 UB0 UR1
LR0 LG0 LB0 LR1
UG1
UB1
UB2 UR3 UG3 UB3
LB2 LR3 LG3 LB3
UR4 UG4 UB4 UR5
LR4 LG4 LB4 LR5
UG5 UB5 UR6 UG6
LG5 LB5 LR6 LG6
UB6 UR7 UG7
UB7 LB6 LR7 LG7 LB7
UR2 UG2
LG1 LB1 LR2 LG2
LCD_D3 LCD_D2 LCD_D1 LCD_D0
LCD_D8 to 15
Low
Figure 37.18 Clock and LCD Data Signal Example (DSTN Color 8-Bit Data Bus Module)
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Section 37 LCD Controller (LCDC)
10) DSTN color 12-bit data bbus module DOTCLK LCD_CL2 LCD_D11 LCD_D10 LCD_D9 LCD_D8 LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0 UR0 UG0 UB0 UR1 UG1 UB1 LR0 LG0 LB0 LR1 LG1 LB1 UR2 UG2 UB2 UR3 UG3 UB3 LR2 LG2 LB2 LR3 LG3 LB3 UR4 UG4 UB4 UR5 UG5 UB5 LR4 LG4 LB4 LR5 LG5 LB5 UR6 UG6 UB6 UR7 UG7 UB7 LR6 LG6 LB6 LR7 LG7 LB7
LCD_D12 to 15
Low
Figure 37.19 Clock and LCD Data Signal Example (DSTN Color 12-Bit Data Bus Module)
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Section 37 LCD Controller (LCDC)
11) DSTN color 16-bit data bus module DOTCLK LCD_CL2
LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D9 LCD_D8
UR0 UG0 UB0 UR1 UG1
UB1
UB2 UR3 UG3 UB3 UR4 UG4 UB4 UR5
LB2 LR3 LG3 LB3 LR4 LG4 LB4 LR5
UG5 UB5 UR6 UG6 UB6 UR7 UG7
UB7 LG5 LB5 LR6 LG6 LB6 LR7 LG7 LB7
UR2
UG2
LR0 LG0 LB0 LR1 LG1 LB1 LR2 LG2
LCD_D7 LCD_D6 LCD_D5 LCD_D4
LCD_D3 LCD_D2 LCD_D1 LCD_D0
Figure 37.20 Clock and LCD Data Signal Example (DSTN Color 16-Bit Data Bus Module)
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Section 37 LCD Controller (LCDC)
12) TFT color 16-bit data bus module
DOTCLK LCD_CL2
LCD_D15 LCD_D14 R05 R04 R03 R02 R01 G05 G04 G03 G02 G01 G00 R15 R14 R13 R12 R11 G15 G14 G13 G12 G11 G10 B15 B14 B13 B12 B11 R25 R24 R23 R22 R21 G25 G24 G23 G22 G21 G20 B25 B24 B23 B22 B21 R35 R34 R33 R32 R31 G35 G34 G33 G32 G31 G30 B35 B34 B33 B32 B31
LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D9 LCD_D8 LCD_D7
LCD_D6 LCD_D5 LCD_D4 LCD_D3
B05
B04
LCD_D2 LCD_D1 LCD_D0
B03 B02 B01
Figure 37.21 Clock and LCD Data Signal Example (TFT Color 16-Bit Data Bus Module)
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Section 37 LCD Controller (LCDC)
13) 8-bit interface color 640 x 840 STN-LCD Horizontal wave DOTCLK LCD_CL2 LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0 LCD_D8 to 15 LCD_CL1 One horizontal display time (640 x DCLK) Horizontal synchronization position Horizontal retrace time Horizontal synchronization width R0 B2 G0 R3 B0 G3 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 G637 B637 R638 G638 B638 R639 G639 B639 R0 G0 B0 R1 G1 B1 R2 G2
R1 B3 G1 R4 B1 G4
R2 B4 G2 R5 Low
One horizontal time ( ex. 640 + 8 x 3 (:3 characters) = 664 DCLK) No vertical retrace LCD_CL2 LCD_CL1 LCD_D LCD_FLM 1st line data One horizontal time One vertical retrace LCD_CL2 LCD_CL1 LCD_D LCD_FLM 1st line data One horizontal time One frame time (481 x CL1) 2nd line data 480th line data Vertical retrace time (One horizontal time) 1st line data 2nd line data Valid Valid Valid Valid Valid 2nd line data 480th line data 1st line data 2nd line data Valid Valid Valid Valid Valid Valid
One frame time (480 x CL1)
Next frame time (480 x CL1)
Next frame time (480 x CL1)
Figure 37.22 Clock and LCD Data Signal Example (8-Bit Interface Color 640 x 480)
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Section 37 LCD Controller (LCDC)
14) 16-bit I/F color 640 x 480 TFT-LCD Horizontal wave DOTCLK LCD_CL2
LCD_D0 LCD_D1 LCD_D2 LCD_D3 LCD_D4 LCD_D5 LCD_D6 LCD_D7
LCD_D8 LCD_D9 LCD_D10 LCD_D11
LCD_D12 LCD_D13
LCD_D14 LCD_D15
8DCLK
8DCLK
8DCLK
B0, 3 B1, 3 B0, 4 B1, 4 B0, 5 B1, 5 B0, 6 B1, 6 B0, 7 B1, 7 G0, 2 G1, 2 G0, 3 G1, 3 G0, 4 G1, 4 G0, 5 G1, 5 G0, 6 G1, 6 G0, 7 G1, 7 R0, 3 R1, 3 R0, 4 R1, 4 R0, 5 R1, 5 R0, 6 R1, 6 R0, 7 R1, 7
B639,3 B639,4 B639,5 B639,6 B639,7 G639,2 G639,3 G639,4 G639,5 G639,6 G639,7 R639,3 R639,4 R639,5 R639,6
R639,7
B0, 3 B0, 4 B0, 5 B0, 6 B0, 7 G0, 2 G0, 3 G0, 4 G0, 5 G0, 6 G0, 7 R0, 3 R0, 4 R0, 5 R0, 6
R0, 7
LCD_CL1
LCD_M_DISP
One horizontal display time (640 x DCLK) Horizontal synchronization position
Horizontal retrace time
Horizontal synchronization width
One horizontal time ( ex. 640 + 8 x 3 (:3 characters) = 664 DCLK)
No vertical retrace
LCD_CL2
LCD_CL1
LCD_D
LCD_M_DISP
Valid Valid Valid
Valid
Valid
Valid
LCD_FLM
1st line data
2nd line data
480th line data
1st line data
2nd line data
One horizontal time
One frame time (480 x CL1)
Next frame time (480 x CL1)
Figure 37.23 Clock and LCD Data Signal Example (16-Bit Interface Color 640 x 480)
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Section 37 LCD Controller (LCDC)
37.6
37.6.1
Usage Notes
Procedure for Halting Access to Display Data Storage VRAM (DDR-SDRAM in Area 3)
Follow the procedure below to halt access to VRAM for storing display data (DDR-SDRAM in area 3). Procedure for Halting Access to Display Data Storage VRAM: 1. 2. 3. 4. Confirm that the LPS1 and LPS0 bits in LDPMMR are currently set to 1. Clear the DON bit in LDCNTR to 0 (display-off mode). Confirm that the LPS1 and LPS0 bits in LDPMMR have changed to 0. Wait for the display time for a single frame to elapse.
This halting procedure is required before selecting self-refreshing for the display data storage VRAM (DDR-SDRAM in area 3) or making a transition to standby mode or module standby mode. 37.6.2 Notes on Using NMI Interrupt
If the NMIFL bit in the NMIFCR register is set to 1 by an NMI interrupt while the LCDC is used, the LCDC cannot access the VRAM that is used for the display data storage (DDR_SDRAM in area 3). As the LCDC continues to output data stored in the lime buffer to the LCD panel data pin, the LCD display will be stopped if the line buffer becomes empty. Accordingly, NMI interrupts should be disabled and he NMIFL bit should be cleared to 0 before the line buffer becomes empty.
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Section 37 LCD Controller (LCDC)
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Section 38 A/D Converter
Section 38 A/D Converter
This LSI includes a 10-bit successive-approximation A/D converter allowing selection of up to four analog input channels.
38.1
Features
A/D converter features are listed below. * 10-bit resolution * Four input channels * High-speed conversion Conversion time: maximum 8.5 s per channel (Pck0 = 33 MHz operation) * Three conversion modes Single mode: A/D conversion on one channel Multi mode: A/D conversion on one to four channels Scan mode: Continuous A/D conversion on one to four channels * Four 16-bit data registers * Sample-and-hold function * A/D interrupt requested at the end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.
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Section 38 A/D Converter
Figure 38.1 shows a block diagram of the A/D converter.
Peripheral data bus
AVcc
Successive approximation register
ADDRD
AVss
10-bit D/A
AN0
AN1
AN2
AN3
+
ADDRC
ADDRA
ADDRB
ADCSR
Pck0/4 Pck0/8
Analog multiplexer
-
Control circuit
Comparator
Sample-andhold circuit
Frequency devider
Bus interface
Internal data bus
Pck0/16
Pck0/32
Peripheral Clock (Pck0)
ADI interrupt signal
A/D converter [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D
Figure 38.1 Block Diagram of A/D Converter
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Section 38 A/D Converter
38.2
Input Pins
Table 38.1 summarizes the A/D converter's input pins. AVcc and AVss are the power supply inputs for the analog circuits in the A/D converter. AVcc also functions as the A/D converter reference voltage pin. Table 38.1 Pin Configuration
Pin Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Abbreviation AVcc AVss AN0 AN1 AN2 AN3 I/O Input Input Input Input Input Input Function Analog power supply Analog ground and reference voltage for A/D conversion Analog inputs
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Section 38 A/D Converter
38.3
Register Descriptions
Table 38.2 shows the ADC register configuration. Table 38.3 shows the register state in each operating mode. Table 38.2 Register Configuration
Register Name A/D data register A A/D data register B A/D data register C A/D data register D A/D control/status register Note: * Abbreviation R/W ADDRA ADDRB ADDRC ADDRD ADCSR R R R R R/W Area P4 Address* H'FFEA 0000 H'FFEA 0002 H'FFEA 0004 H'FFEA 0006 H'FFEA 0010 Area 7 Address* H'1FEA 0000 H'1FEA 0002 H'1FEA 0004 H'1FEA 0006 H'1FEA 0010 Access Size 16 16 16 16 16
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
Table 38.3 Register State in Each Operating Mode
Register Name A/D data register A A/D data register B A/D data register C A/D data register D A/D control/status register Power-On Abbreviation Reset ADDRA ADDRB ADDRC ADDRD ADCSR H'0000 H'0000 H'0000 H'0000 H'0000 Manual Reset H'0000 H'0000 H'0000 H'0000 H'0000 Sleep Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained
38.3.1
A/D Data Registers A to D (ADDRA to ADDRD)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte (bits 15 to 6) of the A/D data register. Bits 5 to 0 of an A/D data register are always read as 0. Table 38.4 indicates the pairings of analog input channels and A/D data registers.
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Section 38 A/D Converter
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Bit: 15 14 13 12 11 10
AD[9:0]
9
8
7
6
5 --
4 -- 0 R
3 -- 0 R
2 -- 0 R
1 -- 0 R
0 -- 0 R
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 15 to 6 5 to 0
Bit Name AD[9:0]
Initial Value R/W 0 All 0 R R
Description Bit data (10 bits) Reserved These bits are always read as 0. The write value should always be 0.
Table 38.4 Analog Input Channels and A/D Data Registers
Analog Input Channel AN0 AN1 AN2 AN3 A/D Data Register ADDRA ADDRB ADDRC ADDRD
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Section 38 A/D Converter
38.3.2
A/D Control/Status Registers (ADCSR)
ADCSR is a 16-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'0080 by a reset and in standby mode.
Bit: 15
ADF
14
ADIE
13
ADST
12 -- 0 R
11 -- 0 R
10 -- 0 R
9 -- 0 R
8 -- 0 R
7
6
5
4
3 -- 0 R
2
1
CH[2:0]
0
CKS[1:0]
MDS[1:0]
Initial value: 0 0 R/W: R/(W)* R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Note: * Only 0 can be written to clear the flag.
Bit 15
Bit Name ADF
Initial Value R/W 0
Description Indicates the end of A/D conversion. [Clearing conditions] (1) Cleared by reading ADF while ADF = 1, then writing 0 to ADF [Setting conditions] Single mode: A/D conversion ends Multi mode: A/D conversion has cycled through the selected channels (A/D conversion cycles through the selected channels) Scan mode: A/D conversion has cycled through the selected channels (A/D conversion is continuously repeated for the selected channels) Note: When clearing the ADST bit to 0 to stop A/D conversion in scan mode or in multi mode (ADF = 0), after clearing the ADST bit to 0, read the ADST bit in ADCSR and confirm that it is 0. Then, after at least the time for A/D conversion on one channel has elapsed, set the ADST bit to 1 again. Note that the A/D conversion time differs according to the A/D conversion clock division ratio.
R/(W)* A/D End Flag
14
ADIE
0
R/W
A/D Interrupt Enable Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Set the ADIE bit while A/D conversion is not being made. 0: A/D end interrupt request (ADI) is disabled 1: A/D end interrupt request (ADI) is enabled
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Section 38 A/D Converter
Bit 13
Bit Name ADST
Initial Value R/W 0 R/W
Description A/D Start Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. 0: A/D conversion is stopped 1: Single mode: A/D conversion starts. This bit is cleared to 0 automatically when conversion on the specified channel ends. Even when the ADST bit is cleared to 0 (by software), A/D conversion does not stop (0 cannot be written to this bit during A/D conversion). Multi mode: A/D conversion starts. This bit is cleared to 0 automatically when conversion on the specified channels has been performed for one cycle. When the ADST bit is cleared to 0 (by software), A/D conversion stops when the currently executed channel ends. Scan mode: A/D conversion starts. A/D conversion continues until the ADST bit is cleared to 0 by software, a reset, or a transition to standby mode.
12 to 8
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 38 A/D Converter
Bit 7, 6
Bit Name Initial Value CKS[1:0] 01
R/W R/W
Description Clock Select Selects the A/D conversion clock divition ratio. 00: Pck0/4 01: Pck0/8 10: Pck0/16 11: Pck0/32
5, 4
MDS[1:0]
00
R/W
conversion mode select Selects single mode, multi mode, or scan mode. 00: Single mode 01: Reserved (setting prohibited) 10: Multi mode 11: Scan mode
3
0
R
Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
CH[2:0]
000
R/W
Channel Select These bits and the MDS bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Single mode Multi mode or scan mode 000: AN0 001: AN1 010: AN2 011: AN3 AN0 AN0, AN1 AN0 to AN2 AN0 to AN3
100: Reserved (setting prohibited) 101: Reserved (setting prohibited) 110: Reserved (setting prohibited) 111: Reserved (setting prohibited) Note: * Only 0 can be written to clear the flag.
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Section 38 A/D Converter
38.4
Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has three operating modes: single mode, multi mode, and scan mode. 38.4.1 Single Mode (MDS1 = 0, MDS0 = 0)
Single mode should be selected when A/D conversion on only one channel is required. A/D conversion starts when the ADST bit (bit 13) of the A/D control/status register (ADCSR) is set to 1 by software. The ADST bit holds 1 during A/D conversion and is automatically cleared to 0 when A/D conversion ends. When A/D conversion ends, the ADF bit (bit 15) of ADCSR is set to 1. If the ADIE bit (bit 14) in ADCSR is also set to 1, an A/D conversion end interrupt (ADI) is requested at this time. Writing 0 to the ADF bit after reading ADF = 1 clears the ADF bit. When setting the A/D control/status register (ADCSR) or switching the analog input channel during A/D conversion, first clear the ADST bit to 0 to halt A/D conversion in order to avoid malfunction. After the change has been made, setting the ADST bit to 1 resumes A/D conversion. Typical operations when channel 1 (AN1) is selected in single mode are described below. Figure 38.2 shows a timing diagram for this example. 1. Select single mode as the operating mode (MDS[1:0] = 00), AN1 as the input channel (CH[2:0] = 001), and enable A/D interrupt requests (ADIE = 1). Then start A/D conversion (ADST = 1). 2. When A/D conversion is completed, the A/D conversion result is transferred into ADDRB. At the same time, the ADF bit is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt request is generated. 4. The A/D interrupt processing routine starts. 5. The A/D interrupt processing routine reads and processes the A/D conversion result (ADDRB). 6. After reading ADF = 1, write 0 in the ADF bit. 7. Execution of the A/D interrupt processing routine ends. After this, when the ADST bit is set to 1, A/D conversion starts and steps 2 to 7 are repeated.
Rev. 1.00 Oct. 01, 2007 Page 1663 of 1956 REJ09B0256-0100
Section 38 A/D Converter
Set* ADST Clear* ADF
Set*
Clear*
ADI Interrupt occurs Channel 0(AN0) Idle
Channel 1(AN1)
Idle
A/D conversion (1)
Idle
A/D conversion (2)
Idle
Channel 2(AN2)
Idle
Channel 3(AN3)
Idle
ADDRA Read result ADDRB A/D conversion result (1) Read result A/D conversion result (2)
ADDRC ADDRD Note: * Vertical arrows () indicate instruction execution by software.
Figure 38.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 38.4.2 Multi Mode (MDS[1:0] = 10)
In multi mode, analog inputs for the specified channels (one or more) are converted once each. A/D conversion starts with the first channel (AN0) when the ADST bit (bit 13) of the A/D control/status register (ADCSR) is set to 1 by software. When multiple channels are selected, A/D conversion for the second channel (AN1) starts immediately after A/D conversion for the first channel ends. A/D conversion on the specified channels is performed for one cycle. The conversion results are transferred for storage to the ADDR that corresponds to the channel. When setting the A/D control/status register (ADCSR) or switching the analog input channel during A/D conversion, first clear the ADST bit to 0 to halt A/D conversion in order to avoid malfunction. After the change has been made, setting the ADST bit to 1 selects the first channel and A/D conversion is resumed.
Rev. 1.00 Oct. 01, 2007 Page 1664 of 1956 REJ09B0256-0100
Section 38 A/D Converter
Typical operations when three channels (AN0 to AN2) are selected in multi mode are described below. Figure 38.3 shows a timing diagram for this example. 1. Select multi mode as the operating mode (MDS[1:0] = 10) and AN0 to AN2 as the analog input channels (CH[2:0] = 010). Then start A/D conversion (ADST = 1). 2. A/D conversion of the first channel (AN0) starts. When A/D conversion ends, the result is transferred into ADDRA. Next, the second channel (AN1) is selected automatically and A/D conversion starts. 3. A/D conversion proceeds in the same way up to the third channel (AN2). 4. When A/D conversion of all selected channels (AN0 to AN2) is completed, the ADF bit is set to 1, the ADST bit is cleared to 0, and A/D conversion stops. If the ADIE bit is set to 1 at this time, an ADI interrupt is generated after A/D conversion ends.
A/D conversion execution Set* ADST Clear* ADF Clear*
ADI Interrupt occurs Channel 0(AN0) Idle A/D conversion (1) Idle
Channel 1(AN1)
Idle
A/D conversion (2)
Idle
Channel 2(AN2)
Idle
A/D conversion (3)
Idle
Channel 3(AN3)
Idle
ADDRA
A/D conversion rusult (1)
ADDRB
A/D conversion rusult (2)
ADDRC ADDRD Note: * Vertical arrows () indicate instruction execution by software.
A/D conversion rusult (3)
Figure 38.3 Example of A/D Converter Operation (Multi Mode, Three Channels AN0 to AN2 Selected)
Rev. 1.00 Oct. 01, 2007 Page 1665 of 1956 REJ09B0256-0100
Section 38 A/D Converter
38.4.3
Scan Mode (MDS1 = 1, MDS0 = 1)
In scan mode, A/D conversion is continuously repeated for the selected channels until the ADST bit (bit 13) is cleared to 0. The A/D conversion results are transferred for storage to the ADDR that corresponds to the channel. This mode is suitable for systems that continuously monitor analog inputs to multiple channels (or a single channel). A/D conversion starts with the first channel (AN0) when the ADST bit of the A/D control/status register (ADCSR) is set to 1 by software. When multiple channels are selected, after A/D conversion for channel n ends, A/D conversion for channel (n + 1) starts immediately. A/D conversion is continuously repeated for the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage to the ADDR that corresponds to the channel. When setting the A/D control/status register (ADCSR) or switching the analog input channel during A/D conversion, first clear the ADST bit to 0 to halt A/D conversion in order to avoid malfunction. After the change has been made, setting the ADST bit to 1 selects the first channel and A/D conversion is resumed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described below. Figure 38.4 shows a timing diagram for this example. 1. Select scan mode as the operating mode (MDS[1:0] = 11) and AN0 to AN2 as the input channels (CH[2:0] = 010). Then start A/D conversion (ADST = 1). 2. A/D conversion of the first channel (AN0) starts. When A/D conversion ends, the result is transferred into ADDRA. Next, the second channel (AN1) is selected automatically and A/D conversion starts. 3. A/D conversion proceeds in the same way up to the third channel (AN2). 4. When A/D conversion of all selected channels (AN0 to AN2) is completed, the ADF bit is set to 1, the first channel (AN0) is selected again, and A/D conversion is consecutively performed. (In multi mode, A/D conversion ends when the selected channels have been cycled through. However, in scan mode, after the selected channels have been cycled through, A/D conversion starts again from the first channel and is consecutively repeated.) If the ADIE bit is set to 1 at this time, an ADI interrupt is generated after A/D conversion ends. 5. While the ADST bit is set to 1, steps 2 to 4 above are repeated. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0).
Rev. 1.00 Oct. 01, 2007 Page 1666 of 1956 REJ09B0256-0100
Section 38 A/D Converter
Consecutive A/D conversion execution
Set* ADST
Clear*
Clear ADF
ADI Interrupt occurs Channel 0(AN0) Idle A/D conversion (1) Idle A/D conversion (4) Idle
Channel 1(AN1)
Idle
A/D conversion (2)
Idle
A/D conversion (5)
Idle
Channel 2(AN2)
Idle
A/D conversion (3)
Idle
Channel 3(AN3)
Idle
ADDRA
A/D conversion result (1)
A/D conversion result (4)
ADDRB
A/D conversion result (2)
A/D conversion result (5)
ADDRC ADDRD Note: * Vertical arrows () indicate instruction execution by software.
A/D conversion result (3)
Figure 38.4 Example of A/D Converter Operation (Scan Mode, Three Channels AN0 to AN2 Selected)
Rev. 1.00 Oct. 01, 2007 Page 1667 of 1956 REJ09B0256-0100
Section 38 A/D Converter
38.4.4
A/D Conversion Time
Table 38.5 indicates the A/D conversion time. Table 38.5 A/D Conversion Time
Pck0/4 Conversion Time Type A/D conversion time for the first conversion (single mode)* A/D conversion time for the second and subsequent conversions (multi mode or scan mode) Min 136 -- Max 139 128 Min 268 -- Pck0/8 Max 275 256 Pck0/16 Min 532 -- Max 547 512 Pck0/32 Min 1060 -- Max 1091 1024
Notes: Values in the table are the numbers of states (one state is one peripheral clock (IO-Bus) Pck0 cycle). * Period starting from when the ADST bit is set to 1 and until data is stored in the register.
38.5
Interrupts
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. The ADI interrupt request is enabled/disabled by specifying the ADIE bit in ADCSR.
Rev. 1.00 Oct. 01, 2007 Page 1668 of 1956 REJ09B0256-0100
Section 38 A/D Converter
38.6
Definitions of A/D Conversion Accuracy
The A/D converter compares an input for an analog channel to its analog reference voltage and converts it into 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors: 1. Offset error (figure 38.5 (1)) Deviation between actual A/D conversion characteristics and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) 0000000000 (000 in figure 38.5) to 0000000001 (001 in figure 38.5) 2. Full-scale error (figure 38.5 (2)) Deviation between actual A/D conversion characteristics and ideal A/D conversion characteristics when the digital output value changes from 1111111110 (110 in figure 38.5) to the maximum 1111111111 (111 in figure 38.5). 3. Quantization error (figure 38.5 (3)) Intrinsic error of the A/D converter and is expressed as 1/2 LSB. 4. Nonlinearity error (figure 38.5 (4)) Deviation between actual A/D conversion characteristics and ideal A/D conversion characteristics between zero voltage and full-scale voltage. Note that it does not include offset, full-scale, and quantization errors.
Rev. 1.00 Oct. 01, 2007 Page 1669 of 1956 REJ09B0256-0100
Section 38 A/D Converter
(2) Full-scale error Digital output Ideal A/D conversion characteristic Digital output Ideal A/D conversion characteristic
111 110 101 100 011 010 010 001 000 0 1/8 2/8
(4) Nonlinearity error (3) Quantization error
3/8
4/8
5/8
6/8
7/8
FS
Analog input voltage (1) Offset error
FS
Analog input voltage
FS: Full-scale voltage
Figure 38.5 Definitions of A/D Conversion Accuracy
Rev. 1.00 Oct. 01, 2007 Page 1670 of 1956 REJ09B0256-0100
Section 38 A/D Converter
38.7
Usage Notes
When using the A/D converter, note the points listed below. 38.7.1 1. Setting Analog Input Voltage
Analog input voltage range During A/D conversion, the voltages input to the analog input pins ANn should be in the range AVss ANn AVcc (n = 0 to 3). AVcc and AVss input voltages The AVcc and AVss input voltages should be as follows: AVcc = 3.3 V 0.3 V and AVss = Vss. (AVcc = Analog power supply, AVss = Analog ground, Vss = Internal digital power supply) Processing of Analog Input Pins
2.
38.7.2
To prevent damage from abnormal voltage such as voltage surges at the analog input pins (AN0 to AN3), connect a protection circuit like the one shown in figure 38.6. The circuit shown also includes a CR filter to suppress noise. This circuit is shown as an example; the circuit constants should be determined according to actual application conditions.
AVcc
100
AN0 to AN3 *
0.1 F
AVss This LSI
Note: * Bypass capacitor connected to AVcc
10 F
0.01 F
Figure 38.6 Example of Analog Input Pin Protection Circuit
Rev. 1.00 Oct. 01, 2007 Page 1671 of 1956 REJ09B0256-0100
Section 38 A/D Converter
38.7.3
Pck0 Clock and Clock Division Ratio Settings
Four types of frequency divided clocks can be used as the clock for A/D conversion. Since the internal circuit configuration affects the limits of the interface between the analog and digital sections, be sure to see table 38.6 when setting the Pck0 clock and clock division ratio. Table 38.6 Relationship between Clock Division Ratio and Usable Pck0 Clock Frequency
Clock Division Ratio Pck0/4 Pck0/8 Pck0/16 Pck0/32 Pck0 Clock 18 MHz or lower 34 MHz or lower 67 MHz or lower 67 MHz or lower
38.7.4
A/D Conversion Stop
In multi mode or scan mode, A/D conversion does not stop as soon as the setting to halt A/D conversion has been made. A/D conversion stops as soon as A/D conversion of the data in the relevant channel has finished.
Rev. 1.00 Oct. 01, 2007 Page 1672 of 1956 REJ09B0256-0100
Section 39 D/A Converter (DAC)
Section 39 D/A Converter (DAC)
This LSI incorporates a two-channel D/A converter (DAC) with the following features.
39.1
* * * *
Features
8-bit resolution Two output channels Conversion time: Max. 10 s (when load capacitance is 20 pF) Output voltage: 0 V to AVcc (analog power supply)
Figure 28.1 shows the block diagram for the DAC.
DA0 DA1 Analog I/O buffer
DAO0 DAO1
DACR
Control circuit
Module data bus
8-bit D/A converter
DADR1
Bus interface
AVcc AVss
DADR0
Peripheral data bus
Peripheral clock (Pck0) [Legend] DACR: DADR0: DADR1: AVcc: AVss: D/A control register D/A data register 0 D/A data register 1 Analog power supply Analog ground DAO0: Analog output 0 DAO1: Analog output 1 D/A converter circuit
Figure 39.1 Block Diagram of D/A Converter
Rev. 1.00 Oct. 01, 2007 Page 1673 of 1956 REJ09B0256-0100
Section 39 D/A Converter (DAC)
39.2
Input/Output Pins
Table 39.1 summarizes the input/output pins used by the D/A converter. Table 39.1 Pin Configuration
Pin Name AVcc AVss DA0 DA1 I/O Output Output Function Analog block power supply and D/A conversion reference voltage Analog block ground Channel 0 analog output Channel 1 analog output
39.3
Register Descriptions
Table 39.2 shows the ADC register configuration. Table 39.3 shows the register state in each operating mode. Table 39.2 Register Configuration
Register Name D/A data register 0 D/A data register 1 D/A control register Note: * Abbreviation R/W DADR0 DADR1 DACR R/W R/W R/W Area P4 Address* H'FFEA 8000 H'FFEA 8002 H'FFEA 8004 Area 7 Address* H'1FEA 8000 H'1FEA 8002 H'1FEA 8004 Access Size 8 8 8
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
Table 39.3 Register State in Each Operating Mode
Register Name D/A data register 0 D/A data register 1 D/A control register Power-On Abbreviation Reset DADR0 DADR1 ADCR H'00 H'00 H'3F Manual Reset H'00 H'00 H'3F Sleep Retained Retained Retained Standby Retained Retained Retained
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Section 39 D/A Converter (DAC)
39.3.1
D/A Data Registers 0 and 1 (DADR0, DADR1)
DADR0 and DADR1 are 8-bit readable/writable registers that store data for D/A conversion. When the D/A output enable bits (DAOE1, DAOE0) of the DA control register (DACR) are set to 1, the contents of the D/A data register are converted and output to analog output pins (DA0, DA1). The D/A data register is initialized to H'00 at reset. Note that the D/A data register is not initialized upon entering the software standby, module standby, or hardware standby mode.
Bit:
7
--
6
-- 0 R/W
5
-- 0 R/W
4
-- 0 R/W
3
-- 0 R/W
2
-- 0 R/W
1
-- 0 R/W
0 -- 0 R/W
Initial value: 0 R/W: R/W
Bit 7 to 0
Bit Name
Initial Value H'00
R/W R/W
Description 8-bit registers that store data for D/A conversion.
Rev. 1.00 Oct. 01, 2007 Page 1675 of 1956 REJ09B0256-0100
Section 39 D/A Converter (DAC)
39.3.2
D/A Control Register (DACR)
The DACR register is an 8-bit readable/writable register that controls D/A converter operation. The DACR is initialized to H'3F at reset. Note that the DACR is not initialized in software standby, module standby, or hardware standby mode.
Bit:
7
6
5
-- 1 R
4
-- 1 R
3
-- 1 R
2
-- 1 R
1
-- 1 R
0
-- 1 R
DAOE1 DAOE0
Initial value: 0 R/W: R/W
0 R/W
Bit 7
Initial Bit Name Value DAOE1 0
R/W R/W
Description Controls D/A conversion for channel 1 and analog output. 0: D/A conversion for channel 1 and analog output (DA1) are disabled 1: D/A conversion for channel 1 and analog output (DA1) are enabled
6
DAOE0
0
R/W
Controls D/A conversion for channel 0 and analog output. 0: D/A conversion for channel 0 and analog output (DA0) are disabled 1: D/A conversion for channel 0 and analog output (DA0) are enabled
5 to 0
All 1
R
Reserved These bits are always read as 1. The write value should always be 1. If 0 is written to these bits, correct operation cannot be guaranteed.
Rev. 1.00 Oct. 01, 2007 Page 1676 of 1956 REJ09B0256-0100
Section 39 D/A Converter (DAC)
39.4
Operation
The D/A converter incorporates two D/A channels that can operate individually. The D/A converter executes D/A conversion while analog output is enabled by the D/A control register (DACR). If the D/A data registers (DADR0 and DADR1) are modified, the D/A converter immediately initiates the new data conversion. When the DAOE1 and DAOE0 bits in the DACR register are set to 1, D/A conversion results are output. An example of D/A conversion for channel 0 is shown below. The operation timing is shown in figure 39.2. 1. Write conversion data to DADR0. 2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. The results are output after the conversion has ended. The output value will be (DADR0 contents/256) x AVcc. The conversion results are output continuously until DADR0 is modified or the DAOE0 bit is cleared to 0. 3. When D/A data register 0 (DMDR0) is modified, the conversion starts again. The results are output after the conversion has ended. 4. When the DAOE0 bit is cleared to 0, analog output is disabled (high-impedance state).
DADR0 DACR write cycle write cycle DADR0 write cycle DACR write cycle
Pck0
Address bus
DADR0
Conversion data (1)
Conversion data (2)
DAOE0 Conversion result (2) tDCONV
DA0 High impedance state [Legend] tDCONV: D/A conversion time
tDCONV
Conversion result (1)
Figure 39.2 D/A Converter Operation Example
Rev. 1.00 Oct. 01, 2007 Page 1677 of 1956 REJ09B0256-0100
Section 39 D/A Converter (DAC)
39.5
Usage Notes
The input voltages AVcc and AVss of the analog power supply should be as follows: AVcc = 3.3 0.3 V AVss = Vss
Rev. 1.00 Oct. 01, 2007 Page 1678 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Section 40 General Purpose I/O (GPIO)
40.1 Features
This LSI has 16 general ports (A to P), which provide 118 input/output pins in total. Each of the general port pins is multiplexed with the pins of peripheral modules, and its function is selected as either a General Purpose I/O (GPIO) pin or a peripheral module pin. The GPIO has the following features. * Each port pin is a multiplexed pin, for which the port control register can set the pin function and MOS pull-up control individually. * Each port has a data register that stores data for its pins. * GPIO interrupts are supported. Table 40.1 lists the multiplexed pins controlled by the GPIO registers. Each port pin is pulled up in the initial state. When using peripheral modules, the relevant pins should be released from the pulled up state for use.
Rev. 1.00 Oct. 01, 2007 Page 1679 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Table 40.1 Multiplexed Pins Controlled by Port Control Registers
Other Port Function Function 1 (Related (Related Port module) module) Other Function 2 (Related module) Other Function 3 (Related module) Other Function 4 (Related module) Other Function 5 (Related module)
GPIO Interrupt
A
PTA6 Input/output (Port) PTA5 Input/output (Port) PTA4 Input/output (Port) PTA3 Input/output (Port) PTA2 Input/output (Port) PTA1 Input/output (Port) PTA0 Input/output (Port)
AD1 TRI (PCIC) AD12 TRI (PCIC) AD13 TRI (PCIC) AD15 TRI (PCIC) LOCK STRI (PCIC) DEVSEL STRI (PCIC) PAR TRI (PCIC) AD6 TRI (PCIC) CBE0 TRI (PCIC) AD14 TRI (PCIC) CBE1 TRI (PCIC)
MMC_VDDON Output (MMC)

SCIF1_RTS Input/output (SCIF1) SCIF1_CTS Input/output (SCIF1) SCIF1_TXD Output (SCIF1)

SCIF1_RXD Input (SCIF1) SCIF1_SCK Input/output (SCIF1)

B
PTB7 Input/output (Port) PTB6 Input/output (Port) PTB5 Input/output (Port) PTB4 Input/output (Port)
LCDM_D2 Output (LCDCM) LCDM_D3 Output (LCDCM)
PINT15 Input (INT) PINT14 Input (INT)

LCDM_M_DISP PINT13 Input Output (LCDCM) (INT)
LCDM_D8 Output (LCDCM)
PINT12 Input (INT)
Rev. 1.00 Oct. 01, 2007 Page 1680 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Other Port Function Function 1 (Related (Related Port module) module)
Other Function 2 (Related module)
Other Function 3 (Related module)
Other Function 4 (Related module)
Other Function 5 (Related module)
GPIO Interrupt
B
PTB3 Input/output (Port) PTB2 Input/output (Port) PTB1 Input/output (Port) PTB0 Input/output (Port)
AD9 TRI (PCIC) AD11 TRI (PCIC) SERR O/D (PCIC) PERR STRI (PCIC) AD3 TRI (PCIC) AD5 TRI (PCIC) AD0 TRI (PCIC) AD7 TRI (PCIC) AD8 TRI (PCIC) AD2 TRI (PCIC) AD4 TRI (PCIC) AD10 TRI (PCIC)
LCDM_D6 Output (LCDCM) LCDM_D7 Output (LCDCM) LCDM_D9 Output (LCDCM) LCDM_D10 Output (LCDCM)
PINT11 Input (INT) PINT10 Input (INT) PINT9 Input (INT) PINT8 Input (INT)

C
PTC7 Input/output (Port) PTC6 Input/output (Port) PTC5 Input/output (Port) PTC4 Input/output (Port) PTC3 Input/output (Port) PTC2 Input/output (Port) PTC1 Input/output (Port) PTC0 Input/output (Port)
MMC_CLK Output (MMC)
LCDM_CL1 Output (LCDCM) LCDM_FLM Output (LCDCM) LCDM_CL2 Output (LCDCM) LCDM_D4 Output (LCDCM) LCDM_D0 Output (LCDCM) LCDM_D1 Output (LCDCM) LCDM_D5 Output (LCDCM)
MMC_CD Input (MMC)
MMC_CMD Input/output (MMC)

MMC_ODMOD Output (MMC)

MMC_DAT Input/output (MMC)
Rev. 1.00 Oct. 01, 2007 Page 1681 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Other Port Function Function 1 (Related (Related Port module) module)
Other Function 2 (Related module)
Other Function 3 (Related module)
Other Function 4 (Related module)
Other Function 5 (Related module)
GPIO Interrupt
D
PTD7 Output (Port) PTD6 Input/output (Port) PTD5 Input/output (Port) PTD4 Input/output (Port) PTD3 Input/output (Port) PTD2 Input/output (Port) PTD1 Input/output (Port) PTD0 Input/output (Port)
PCIRESET PCC_RESET GET1_ETXD7 Output (PCIC) Output (PCC) Output (GMII1) REQ2 Input (PCIC) AD18 TRI (PCIC) STOP STRI (PCIC) PCIFRAME STRI (PCIC) TRDY STRI (PCIC) CBE2 TRI (PCIC) IRDY STRI (PCIC) AD29 TRI (PCIC) PCC_BVD1 Input (PCC) PCC_CD2 Input (PCC) PCC_CD1 Input (PCC) PCC_BVD2 Input (PCC) PCC_RDY Input (PCC) PCC_VS2 Input (PCC) PCC_VS1 Input (PCC) SCIF2_TXD Output (SCIF2)
GET1_ETXD5 SSI1_SCK Output (GMII1) Input/output
LCDM_VEPWC Output (LCDCM) LCDM_VCPWC Output (LCDCM)
(SSI1)
GET1_ERXD6 SSI1_SDATA LCDM_D14 Input/output Output Input (GMII1)
(SSI1) SIOF0_MCLK SSI1_WS Input (SIOF0) Input/output (SSI1) SIOF0_SCK Input/output (SIOF0)
(LCDCM) LCDM_DON Output (LCDCM)
HAC_RES LCDM_D12 Output (HAC) Output (LCDCM)
SIOF0_RXD HAC_SYNC LCDM_D11 Input (SIOF0) Output (HAC) Output (LCDCM) SIOF0_TXD Output (SIOF0)
SIOF0_SYNC Input/output (SIOF0)
HAC_SD_OU LCDM_D15 T Output Output (HAC) (LCDCM) HAC_SD_IN Input (HAC) SSI0_SCK Input/output (SSI0) LCDM_D13 Output (LCDCM)
E
PTE5 Input/output (Port) PTE4 Input/output (Port) PTE3 Input/output (Port) PTE2 Input/output (Port)
GET1_ GTX-CLK Output (GMII1)
AD22 TRI (PCIC) AD20 TRI (PCIC) AD16 TRI (PCIC)
SCIF2_RXD GET1_ERXD4 SSI0_SDATA Input (SCIF2) Input (GMII1) Input/output (SSI0) SCIF2_SCK Input/output (SCIF2) PCC_IOIS16 Input (PCC)
GET1_ERXD5 SSI0_WS Input/output Input (GMII1)
(SSI0)
GET1_ERXD7 TEND2 Output Input (GMII1)
(DMAC2)
Rev. 1.00 Oct. 01, 2007 Page 1682 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Other Port Function Function 1 (Related (Related Port module) module)
Other Function 2 (Related module)
Other Function 3 (Related module)
Other Function 4 (Related module)
Other Function 5 (Related module)
GPIO Interrupt
E
PTE1 Input/output (Port) PTE0 Input/output (Port)
PCICLK Input (PCIC) INTA O/D (PCIC) CBE3 TRI (PCIC) AD31 TRI (PCIC) REQ0/ REQOUT TRI (PCIC)
GET1_ETXD4 DACK2 Output (GMII1) Output
(DMAC2)
PCC_DRV Output (PCC) GET1_ETXD6 DREQ2 Output (GMII1) Input
(DMAC2)
ET1_TX-CLK Input (MII1)
F
PTF3 Input/output (Port) PTF2 Input/output (Port) PTF1 Input/output (Port) PTF0 Input/output (Port)
SIM_RST Output (SIM)
ET1_MDIO Input/output (MII1) ET1_MDC Output (MII1)
TEND3 Output (DMAC3) DACK3 Output (DMAC3)
SIM_CLK Output (SIM)
GNT0/GNTIN SIM_D TRI (PCIC) Input/output
(SIM)
ET1_ETXD3 Output (MII1)
DREQ3 Input (DMAC3)
G
PTG7 Input/output (Port) PTG6 Input/output (Port) PTG5 Input/output (Port) PTG4 Input/output (Port) PTG3 Input/output (Port) PTG2 Input/output (Port)
AD28 TRI (PCIC) AD26 TRI (PCIC) GNT3 TRI (PCIC) AD30 TRI (PCIC) REQ3 Input (PCIC) REQ1 Input (PCIC)
ET1_TX-EN Output (MII1) ET1_TX-ER Output (MII1)

ET1_RX-CLK Input (MII1) ET1_LINKST A Input (MII1) ET1_ETXD2 Output (MII1) ET1_ETXD1 Output (MII1)

Rev. 1.00 Oct. 01, 2007 Page 1683 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Other Port Function Function 1 (Related (Related Port module) module)
Other Function 2 (Related module)
Other Function 3 (Related module)
Other Function 4 (Related module)
Other Function 5 (Related module)
GPIO Interrupt
G
PTG1 Input/output (Port) PTG0 Input/output (Port)
GNT2 TRI (PCIC) GNT1 TRI (PCIC) AD17 TRI (PCIC) AD27 TRI (PCIC)
ET1_ETXD0 Output (MII1) ET1_WOL Output (MII1) ET1_RX-DV Input (MII1) ET1_CRS Input (MII1)

H
PTH7 Input/output (Port) PTH6 Input/output (Port) PTH5 Input/output (Port) PTH4 Input/output (Port) PTH3 Input/output (Port) PTH2 Input/output (Port) PTH1 Input/output (Port) PTH0 Input/output (Port)
TPU_TO3 Output (TPU) TPU_TO2 Output (TPU)
RMII1M_TXD_ EN Output (RMII1M) RMII1M_TXD0 Output (RMII1M) RMII1M_RXD0 Input (RMII1M) RMII1M_RXD1 Input (RMII1M) RMII1M_TXD1 Output (RMII1M)
AD23 TRI (PCIC) AD19 TRI (PCIC) AD21 TRI (PCIC) AD24 TRI (PCIC) IDSEL Input (PCIC) AD25 TRI (PCIC) IRQ3/IRL3 Input (INT) IRQ2/IRL2 Input (INT)
TPU_TO1 Output (TPU) TPU_TO0 Output (TPU) TPU_TI2B Input (TPU) TPU_TI2A Input (TPU) TPU_TI3B Input (TPU) TPU_TI3A Input (TPU) ST0M_D7I Input (STIF0M) ST0M_D6I Input (STIF0M)
ET1_ERXD1 Input (MII1) ET1_ERXD3 Input (MII1) ET1_ERXD2 Input (MII1) ET1_ERXD0 Input (MII1)

ET1_RXER RMII1M_CRS_ Input (MII1) DV
Input (RMII1M)
ET1_COL Input (MII1) IIC1_SDA Input/output (IIC1) IIC1_SCL Input/output (IIC1)
RMII1M_RX_ ER Input (RMII1M)
I
PTI7 Input (Port) PTI6 Input (Port)

Rev. 1.00 Oct. 01, 2007 Page 1684 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Other Port Function Function 1 (Related (Related Port module) module)
Other Function 2 (Related module)
Other Function 3 (Related module)
Other Function 4 (Related module)
Other Function 5 (Related module)
GPIO Interrupt
I
PTI5 Input/output (Port) PTI4 Input/output (Port) PTI3 Input (Port) PTI2 Input (Port)
MD10* ST1_VALID Input (EXCPU) Input/output
1
(STIF1) MD8* Input (CPG)
1
LCD_D1 Output (LCDC)
ST1_START Input/output (STIF1)
ET1_PHY-INT RMII0M0_ MDC Input (ETC1)
Output (RMII0M0)
USB_PWREN/ USBF_UPLUP Output (USBH/F)
ST0M_VALIDI IIC0_SDA Input (STIF0M) Input/output
(IIC0)
ST0M_STARTI IIC0_SCL Input (STIF0M) Input/output
SIOF1_MCLK USB_CLK Input (SIOF1) Input (USBH/F) SIOF1_RXD USB_ Input (SIOF1) OVERCRT/
USBF_VBUS Input (USBH/F)
(IIC0) PTI1 Input/output (Port) PTI0 Input/output (Port) J PTJ7 Input/output (Port) PTJ6 Input/output (Port) PTJ5 Input/output (Port) PTJ4 Input/output (Port) PTJ3 Input/output (Port) STATUS1 Output (-) STATUS0 Output (-) ST1_REQ Input/output (STIF1) ST1_CLK/ ST1_STRB Input/output (STIF1) ST0M_D5I Input (STIF0M) ST0M_D4I Input (STIF0M) ST0M_D3I Input (STIF0M) ST0M_D2I Input (STIF0M) ST0M_D1I Input (STIF0M) RMII0_MDIO Input/output (RMII0) RMII0_MDC Output (RMII0) IRQOUT Output (INT) ET0_CRS Input (MII0) ET0_ERXD3 Input (MII0) ET0_ERXD2 Input (MII0) ET0_ERXD1 Input (MII0)

INTB Input (PCIC)
RMII1_TXD0 Output (RMII1)
LCD_D0 Output (LCDC)
RMII1_TXD_ LCD_FLM Output EN Output (RMII1) (LCDC)
RMII1_RXD0 Input (RMII1) RMII1_RXD1 Input (RMII1)
RMII1_CRS_ DV Input (RMII1)
LCD_DON Output (LCDC) LCD_CL2 Output (LCDC) LCD_CL1 Output (LCDC)

Rev. 1.00 Oct. 01, 2007 Page 1685 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Other Port Function Function 1 (Related (Related Port module) module)
Other Function 2 (Related module)
Other Function 3 (Related module)
Other Function 4 (Related module)
Other Function 5 (Related module)
GPIO Interrupt
J
PTJ2 Input/output (Port) PTJ1 Input/output (Port) PTJ0 Input/output (Port)
ST0M_D0I Input (STIF0M)
ET0_ERXD0 Input (MII0)
RMII1_TXD1 Output (RMII1)
LCD_M_DISP Output (LCDC)
ST0M_CLKIO/ ST0M_STRBI Input/output (STIF0M)
RMII1_RX_ER LCD_CLK Input (LCDC) Input (RMII1)
ST0M_REQO GET0_GTX_ REF50CK Output CLK Input (RMII0/1) (STIF0M) Output (GMII0) ST1_D7 Input/output (STIF1) ST1_D6 Input/output (STIF1) ST1_D5 Input/output (STIF1) ST1_D4 Input/output (STIF1) ST1_D3 Input/output (STIF1) ST1_D2 Input/output (STIF1) ST1_D1 Input/output (STIF1) ST1_D0 Input/output (STIF1)
GET0_ERXD7 SIOF2_MCLK Input (GMII0) Input (SIOF2)
K
PTK7 Input/output (Port) PTK6 Input/output (Port) PTK5 Input/output (Port) PTK4 Input/output (Port) PTK3 Input/output (Port) PTK2 Input/output (Port) PTK1 Input/output (Port) PTK0 Input/output (Port)
LCD_VCPWC Output (LCDC) LCD_VEPWC Output (LCDC)
GET0_ERXD6 SIOF2_SCK Input (GMII0) Input/output (SIOF2) GET0_ERXD5 SIOF2_RXD Input (GMII0) Input (SIOF2)
LCD_D7 Output (LCDC)
GET0_ERXD4 SIOF2_TXD LCD_D6 Input (GMII0) Output (SIOF2) Output
(LCDC)
GET0_ETXD7 SIOF2_SYNC Output (GMII0) Input/output (SIOF2) GET0_ETXD6 SIOF1_SCK Output (GMII0) Input/output (SIOF1)
LCD_D5 Output (LCDC) LCD_D4 Output (LCDC)

GET0_ETXD5 SIOF1_TXD LCD_D3 Output (GMII0) Output (SIOF1) Output
(LCDC)
GET0_ETXD4 SIOF1_SYNC Output (GMII0) Input/output (SIOF1)
LCD_D2 Output (LCDC) LCD_D15 Output (LCDC)
L
PTL7 Input/output (Port)
D23/EX_AD23 ST0_VALID Input/output Input/output 2 (STIF0) (LBSC* / EXCPU)
ET0_TX-EN Output (MII0)
TEND1 Output (DMAC1)
Rev. 1.00 Oct. 01, 2007 Page 1686 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Other Port Function Other Function 1 Function 2 (Related (Related (Related module) Port module) module)
Other Function 3 (Related module)
Other Function 4 (Related module)
Other Function 5 (Related module)
GPIO Interrupt
L
PTL6 Input/output (Port) PTL5 Input/output (Port) PTL4 Input/output (Port) PTL3 Input/output (Port) PTL2 Input/output (Port) PTL1 Input/output (Port) PTL0 Input/output (Port)
D22/EX_AD22 ST0_START Input/output Input/output 2 (LBSC* /EXCPU) (STIF0) D21/EX_AD21 ST0_CLK/ ST0_STRB Input/output 2 (LBSC* /EXCPU) Input/output
ET0_ETXD2 Output (MII0) ET0_ETXD1 Output (MII0)
DACK1 Output (DMAC1) DREQ1 Input (DMAC1)
LCD_D14 Output (LCDC) LCD_D13 Output (LCDC)
(STIF0)
D20/EX_AD20 ST0_REQ Input/output Input/output 2 (LBSC* /EXCPU) (STIF0) D19/EX_AD19 IRQ7/IRL7 Input (INT) Input/output 2 (LBSC* /EXCPU) D18/EX_AD18 IRQ6/IRL6 Input (INT) Input/output 2 (LBSC* /EXCPU) D17/EX_AD17 IRQ5/IRL5 Input (INT) Input/output 2 (LBSC* /EXCPU) D16/EX_AD16 IRQ4/IRL4 Input (INT) Input/output 2 (LBSC* /EXCPU) D31/EX_AD31 ST0_D7 Input/output Input/output 2 (LBSC* /EXCPU) (STIF0) D30/EX_AD30 ST0_D6 Input/output Input/output 2 (LBSC* /EXCPU) (STIF0) D29/EX_AD29 ST0_D5 Input/output Input/output 2 (LBSC* /EXCPU) (STIF0)
ET0_ETXD0 Output (MII0) ET0_MDIO Input/output (MII0) ET0_ETXD3 Output (MII0) ET0_MDC Output (MII0) ET0_COL Input (MII0) ET0_RX-DV Input (MII0)
INTD LCD_D12 Input (PCIC) Output (LCDC) INTC LCD_D11 Input (PCIC) Output (LCDC) TEND0 Output (DMAC0) DACK0 Output (DMAC0) DREQ0 Input (DMAC0) LCD_D10 Output (LCDC) LCD_D9 Output (LCDC) LCD_D8 Output (LCDC)

M
PTM7 Input/output (Port) PTM6 Input/output (Port) PTM5 Input/output (Port) PTM4 Input/output (Port) PTM3 Input/output (Port)
RMII0_TXD0 Output (RMII0)
PINT7 Input (INT) PINT6 Input (INT) PINT5 Input (INT) PINT4 Input (INT) PINT3 Input (INT)
ET0_RX-CLK RMII0_TXD1 Input (MII0) Output
(RMII0)
ET0_RX-ER Input (MII0)
RMII0_TXD_ EN Output (RMII0)
D28/EX_AD28 ST0_D4 Input/output Input/output 2 (LBSC* /EXCPU) (STIF0) D27/EX_AD27 ST0_D3 Input/output Input/output 2 (LBSC* /EXCPU) (STIF0)
ET0_PHY-INT RMII0_RXD0 Input (ETC0) Input (RMII0) ET0_LINKSTA RMII0_RXD1 Input (MII0) Input (RMII0)
Rev. 1.00 Oct. 01, 2007 Page 1687 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Other Port Function Other Function 2 (Related Function 1 (Related (Related module) module) Port module)
Other Function 3 (Related module)
Other Function 4 (Related module)
Other Function 5 (Related module)
GPIO Interrupt
M
PTM2 Input/output (Port) PTM1 Input/output (Port) PTM0 Input/output (Port)
D26/EX_AD26 Input/output 2 (LBSC* /EXCPU) D25/EX_AD25 Input/output 2 (LBSC* /EXCPU) D24/EX_AD24 Input/output 2 (LBSC* /EXCPU)
ST0_D2 Input/output (STIF0) ST0_D1 Input/output (STIF0) ST0_D0 Input/output (STIF0)
ET0_WOL RMII0_CRS_ Output (MII0) DV
Input (RMII0) ET0_TX-CLK Input (MII0) RMII0_RX_ ER Input (RMII0)
PINT2 Input (INT) PINT1 Input (INT)
ET0_TX-ER Output (MII0)
RMII0M0_ PINT0 MDIO Input Input/output (INT) (RMII0M0)
N
PTN5 Input/output (Port) PTN4 Input/output (Port) PTN3 Input/output (Port) PTN2 Input/output (Port) PTN1 Input/output (Port) PTN0 Input/output (Port)
NMI Input (INT) SCIF0_RTS Input/output (SCIF0) SCIF0_CTS Input/output (SCIF0) SCIF0_TXD Output (SCIF0) SCIF0_RXD Input (SCIF0) SCIF0_SCK Input/output (SCIF0) IRQ1/IRL1 Input (INT) IRQ0/IRL0 Input (INT)
MD2* Input (CPG) MD4* Input (LBSC) MD1* Input (CPG) MD3* Input (LBSC) MD0* Input (CPG) TEND1M Output (DMAC1M) DACK1M Output (DMAC1M)
1 1 1 1
1

O
PTO7 Input/output (Port) PTO6 Input/output (Port)
SSI3_SCK Input/output (SSI3)
MD6* Input (PCIC)
1
1
MD5* Input (LBSC)
Rev. 1.00 Oct. 01, 2007 Page 1688 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Other Port Function Function 1 (Related (Related Port module) module)
Other Function 2 (Related module)
Other Function 3 (Related module)
Other Function 4 (Related module)
Other Function 5 (Related module)
GPIO Interrupt
O
PTO5 Input/output (Port) PTO4 Input/output (Port) PTO3 Input/output (Port) PTO2 Input/output (Port) PTO1 Input/output (Port) PTO0 Input/output (Port)
AUDCK DREQ1M Output (AUD) Input (DMAC1M) AUDATA3 EX_INT Output (AUD) Output (EXCPU) AUDATA2 RMII0M1_ Output (AUD) MDIO Input/output (RMII0M1) AUDATA1 RMII0M1_ Output (AUD) MDC Output (RMII0M1) AUDATA0 RMII1_MDIO Output (AUD) Input/output
(RMII1)
SSI3_SDATA Input/output (SSI3) SSI3_WS Input/output (SSI3) SSI2_SCK Input/output (SSI2)

SSI2_SDATA Input/output (SSI2)
AUDSYNC RMII1_MDC SSI2_WS Output (AUD) Output (RMII1) Input/output (SSI2)
[Legend]
Note:
1. 2. 3. 4.
TRI: Tri-state STRI: Sustained tri-state O/D: Open drain Hatched areas in the table indicate the pin functions that are ready for use immediately after a reset. When using on-chip modules. select functions for the relevant pins before initializing each module. MD0 to MD6, MD8, and MD10 are valid only during power-on reset. When 32-bit is selected as the data bus width by the LBSC, select this pin function.
Rev. 1.00 Oct. 01, 2007 Page 1689 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2
Register Descriptions
Table 40.2 shows the GPIO register configuration. Table 40.3 shows the register states in each operating mode. Table 40.2 Register Configuration (1)
Register Name Port A control register Port B control register Port C control register Port D control register Port E control register Port F control register Port G control register Port H control register Port I control register Port J control register Port K control register Port L control register Port M control register Port N control register Port O control register Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Port H data register Port I data register Port J data register Abbreviation R/W PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR PICR PJCR PKCR PLCR PMCR PNCR POCR PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PIDR PJDR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Area P4 Address*1 H'FFEF 0000 H'FFEF 0002 H'FFEF 0004 H'FFEF 0006 H'FFEF 0008 H'FFEF 000A H'FFEF 000C H'FFEF 000E H'FFEF 0010 H'FFEF 0012 H'FFEF 0014 H'FFEF 0016 H'FFEF 0018 H'FFEF 001A H'FFEF 001C H'FFEF 0020 H'FFEF 0022 H'FFEF 0024 H'FFEF 0026 H'FFEF 0028 H'FFEF 002A H'FFEF 002C H'FFEF 002E H'FFEF 0030 H'FFEF 0032 Area 7 Address*1 H'1FEF 0000 H'1FEF 0002 H'1FEF 0004 H'1FEF 0006 H'1FEF 0008 H'1FEF 000A H'1FEF 000C H'1FEF 000E H'1FEF 0010 H'1FEF 0012 H'1FEF 0014 H'1FEF 0016 H'1FEF 0018 H'1FEF 001A H'1FEF 001C H'1FEF 0020 H'1FEF 0022 H'1FEF 0024 H'1FEF 0026 H'1FEF 0028 H'1FEF 002A H'1FEF 002C H'1FEF 002E H'1FEF 0030 H'1FEF 0032 Access Size*2 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8
Rev. 1.00 Oct. 01, 2007 Page 1690 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Register Name Port K data register Port L data register Port M data register Port N data register Port O data register Port I pull-up control register Port J pull-up control register Port K pull-up control register Port L pull-up control register Port M pull-up control register Port N pull-up control register Port O pull-up control register Input pin pull-up control register Pin select register 0 Pin select register 1 Pin select register 2 Pin select register 3 Pin select register 4
Abbreviation R/W PKDR PLDR PMDR PNDR PODR PIPUPR PJPUPR PKPUPR PLPUPR PMPUPR PNPUPR POPUPR PPUPR PSEL0 PSEL1 PSEL2 PSEL3 PSEL4 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Area P4 Address*1 H'FFEF 0034 H'FFEF 0036 H'FFEF 0038 H'FFEF 003A H'FFEF 003C H'FFEF 0050 H'FFEF 0052 H'FFEF 0054 H'FFEF 0056 H'FFEF 0058 H'FFEF 005A H'FFEF 005C H'FFEF 0060 H'FFEF 0070 H'FFEF 0072 H'FFEF 0074 H'FFEF 0076 H'FFEF 0078
Area 7 Address*1 H'1FEF 0034 H'1FEF 0036 H'1FEF 0038 H'1FEF 003A H'1FEF 003C H'1FEF 0050 H'1FEF 0052 H'1FEF 0054 H'1FEF 0056 H'1FEF 0058 H'1FEF 005A H'1FEF 005C H'1FEF 0060 H'1FEF 0070 H'1FEF 0072 H'1FEF 0074 H'1FEF 0076 H'1FEF 0078
Access Size*2 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16
Notes: 1. Area P4 address is the address when the P4 area of virtual address space is used. Area 7 address is the address when the register is accessed through area 7 of physical address space by using the TLB. 2. There are 16-bit access registers and 8-bit access registers. These registers should be read or written in their specified access size.
Rev. 1.00 Oct. 01, 2007 Page 1691 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Table 40.3 Register States in Each Operating Mode
Register Name Port A control register Port B control register Port C control register Port D control register Port E control register Port F control register Port G control register Port H control register Port I control register Port J control register Port K control register Port L control register Port M control register Port N control register Port O control register Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Port H data register Port I data register Port J data register Port K data register Port L data register Port M data register Port N data register Port O data register Abbrevia- Power-on Manual tion Reset Reset PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR PICR PJCR PKCR PLCR PMCR PNCR POCR PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PIDR PJDR PKDR PLDR PMDR PNDR PODR H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0AA0 H'FFFF H'FFFF H'0000 H'0000 H'02AA H'0FFF H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'xx H'xx H'xx H'00 H'00 H'xx H'xx Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 1692 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Register Name Port I pull-up control register Port J pull-up control register Port K pull-up control register Port L pull-up control register Port M pull-up control register Port N pull-up control register Port O pull-up control register Input pin pull-up control register Pin select register 0 Pin select register 1 Pin select register 2 Pin select register 3 Pin select register 4
Abbrevia- Power-on Manual tion Reset Reset PIPUPR PJPUPR PKPUPR PLPUPR PMPUPR PNPUPR POPUPR PPUPR PSEL0 PSEL1 PSEL2 PSEL3 PSEL4 H'FF H'FF H'FF H'FF H'FF H'FF H'FF H'FF H'0008 H'4888 H'0000 H'4444 H'0000 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
40.2.1
Port A Control Register (PACR)
PACR is a 16-bit readable/writable register that selects the pin function.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- Initial value: R/W: 0 R
-- 0 R
PA6MD[1:0]
PA5MD[1:0]
PA4MD[1:0]
PA3MD[1:0]
PA2MD[1:0]
PA1MD[1:0]
PA0MD[1:0]
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15, 14
Bit Name
Initial value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13, 12
PA6MD[1:0] 00
R/W
PTA6 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1693 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 11, 10
Bit Name
Initial value
R/W R/W
Description PTA5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PA5MD[1:0] 00
9, 8
PA4MD[1:0] 00
R/W
PTA4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
7, 6
PA3MD[1:0] 00
R/W
PTA3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
5, 4
PA2MD[1:0] 00
R/W
PTA2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
3, 2
PA1MD[1:0] 00
R/W
PTA1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
1, 0
PA0MD[1:0] 00
R/W
PTA0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1694 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.2
Port B Control Register (PBCR)
PBCR is a 16-bit readable/writable register that selects the pin function.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PB7MD[1:0]
PB6MD[1:0]
PB5MD[1:0]
PB4MD[1:0]
PB3MD[1:0]
PB2MD[1:0]
PB1MD[1:0]
PB0MD[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15, 14
Bit Name
Initial value
R/W R/W
Description PTB7 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PB7MD[1:0] 00
13, 12
PB6MD[1:0] 00
R/W
PTB6 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
11, 10
PB5MD[1:0] 00
R/W
PTB5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
9, 8
PB4MD[1:0] 00
R/W
PTB4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
7, 6
PB3MD[1:0] 00
R/W
PTB3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1695 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 5, 4
Bit Name
Initial value
R/W R/W
Description PTB2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PB2MD[1:0] 00
3, 2
PB1MD[1:0] 00
R/W
PTB1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
1, 0
PB0MD[1:0] 00
R/W
PTB0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
40.2.3
Port C Control Register (PCCR)
PCCR is a 16-bit readable/writable register that selects the pin function.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC7MD[1:0]
PC6MD[1:0]
PC5MD[1:0]
PC4MD[1:0]
PC3MD[1:0]
PC2MD[1:0]
PC1MD[1:0]
PC0MD[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15, 14
Bit Name
Initial value
R/W R/W
Description PTC7 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PC7MD[1:0] 00
Rev. 1.00 Oct. 01, 2007 Page 1696 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 13, 12
Bit Name
Initial value
R/W R/W
Description PTC6 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PC6MD[1:0] 00
11, 10
PC5MD[1:0] 00
R/W
PTC5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
9, 8
PC4MD[1:0] 00
R/W
PTC4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
7, 6
PC3MD[1:0] 00
R/W
PTC3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
5, 4
PC2MD[1:0] 00
R/W
PTC2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
3, 2
PC1MD[1:0] 00
R/W
PTC1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1697 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 1, 0
Bit Name
Initial value
R/W R/W
Description PTC0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PC0MD[1:0] 00
40.2.4
Port D Control Register (PDCR)
PDCR is a 16-bit readable/writable register that selects the pin function.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD7MD[1:0]
PD6MD[1:0]
PD5MD[1:0]
PD4MD[1:0]
PD3MD[1:0]
PD2MD[1:0]
PD1MD[1:0]
PD0MD[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15, 14
Bit Name
Initial value
R/W R/W
Description PTD7 Mode 00: Other function 01: Port output 10: Setting prohibited 11: Setting prohibited
PD7MD[1:0] 00
13, 12
PD6MD[1:0] 00
R/W
PTD6 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
11, 10
PD5MD[1:0] 00
R/W
PTD5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1698 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 9, 8
Bit Name
Initial value
R/W R/W
Description PTD4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PD4MD[1:0] 00
7, 6
PD3MD[1:0] 00
R/W
PTD3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
5, 4
PD2MD[1:0] 00
R/W
PTD2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
3, 2
PD1MD[1:0] 00
R/W
PTD1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
1, 0
PD0MD[1:0] 00
R/W
PTD0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1699 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.5
Port E Control Register (PECR)
PECR is a 16-bit readable/writable register that selects the pin function.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- Initial value: R/W: 0 R
-- 0 R
-- 0 R
-- 0 R
PE5MD[1:0]
PE4MD[1:0]
PE3MD[1:0]
PE2MD[1:0]
PE1MD[1:0]
PE0MD[1:0]
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15, 12
Bit Name
Initial value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
11, 10
PE5MD[1:0] 00
R/W
PTE5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
9, 8
PE4MD[1:0] 00
R/W
PTE4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
7, 6
PE3MD[1:0] 00 0
R/W
PTE3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
5, 4
PE2MD[1:0] 00
R/W
PTE2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1700 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 3, 2
Bit Name
Initial value
R/W R/W
Description PTE1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PE1MD[1:0] 00
1, 0
PE0MD[1:0] 00
R/W
PTE0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
40.2.6
Port F Control Register (PFCR)
PFCR is a 16-bit readable/writable register that selects the pin function.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- Initial value: R/W: 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
PF3MD[1:0]
PF2MD[1:0]
PF1MD[1:0]
PF0MD[1:0]
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15 to 8
Bit Name
Initial value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
7, 6
PF3MD[1:0] 00
R/W
PTF3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1701 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 5, 4
Bit Name
Initial value
R/W R/W
Description PTF2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PF2MD[1:0] 00
3, 2
PF1MD[1:0] 00
R/W
PTF1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
1, 0
PF0MD[1:0] 00
R/W
PTF0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1702 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.7
Port G Control Register (PGCR)
PGCR is a 16-bit readable/writable register that selects the pin function.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PG7MD[1:0]
PG6MD[1:0]
PG5MD[1:0]
PG4MD[1:0]
PG3MD[1:0]
PG2MD[1:0]
PG1MD[1:0]
PG0MD[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15, 14
Bit Name
Initial value
R/W R/W
Description PTG7 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PG7MD[1:0] 00
13, 12
PG6MD[1:0] 00
R/W
PTG6 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
11, 10
PG5MD[1:0] 00
R/W
PTG5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
9, 8
PG4MD[1:0] 00
R/W
PTG4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1703 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 7, 6
Bit Name
Initial value
R/W R/W
Description PTG3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PG3MD[1:0] 00
5, 4
PG2MD[1:0] 00
R/W
PTG2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
3, 2
PG1MD[1:0] 00
R/W
PTG1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
1, 0
PG0MD[1:0] 00
R/W
PTG0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1704 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.8
Port H Control Register (PHCR)
PHCR is a 16-bit readable/writable register that selects the pin function.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PH7MD[1:0]
PH6MD[1:0]
PH5MD[1:0]
PH4MD[1:0]
PH3MD[1:0]
PH2MD[1:0]
PH1MD[1:0]
PH0MD[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15,14
Bit Name
Initial value
R/W R/W
Description PH7 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PH7MD[1:0] 00
13, 12
PH6MD[1:0] 00
R/W
PH6 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
11, 10
PH5MD[1:0] 00
R/W
PH5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
9, 8
PH4MD[1:0] 00
R/W
PTH4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1705 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 7, 6
Bit Name
Initial value
R/W R/W
Description PTH3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PH3MD[1:0] 00
5, 4
PH2MD[1:0] 00
R/W
PTH2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
3, 2
PH1MD[1:0] 00
R/W
PTH1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
1, 0
PH0MD[1:0] 00
R/W
PTH0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1706 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.9
Port I Control Register (PICR)
PICR is a 16-bit readable/writable register that selects the pin function and MOS input pull-up control.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PI7MD[1:0]
PI6MD[1:0]
PI5MD[1:0]
PI4MD[1:0]
PI3MD[1:0]
PI2MD[1:0]
PI1MD[1:0]
PI0MD[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15, 14
Bit Name PI7MD[1:0]
Initial value 00
R/W R/W
Description PTI7 Mode 00: Other function 01: Setting prohibited 10: Port input 11: Setting prohibited
13, 12
PI6MD[1:0]
00
R/W
PTI6 Mode 00: Other function 01: Setting prohibited 10: Port input 11: Setting prohibited
11, 10
PI5MD[1:0]
10
R/W
PTI5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
9, 8
PI4MD[1:0]
10
R/W
PTI4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1707 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 7, 6
Bit Name PI3MD[1:0]
Initial value 10
R/W R/W
Description PTI3 Mode 00: Other function 01: Setting prohibited 10: Port input 11: Setting prohibited
5, 4
PI2MD[1:0]
10
R/W
PTI2 Mode 00: Other function 01: Setting prohibited 10: Port input 11: Setting prohibited
3, 2
PI1MD[1:0]
00
R/W
PTI1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
1, 0
PI0MD[1:0]
00
R/W
PTI0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
Rev. 1.00 Oct. 01, 2007 Page 1708 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.10 Port J Control Register (PJCR) PJCR is a 16-bit readable/writable register that selects the pin function and MOS input pull-up control.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PJ7MD[1:0]
PJ6MD[1:0]
PJ5MD[1:0]
PJ4MD[1:0]
PJ3MD[1:0]
PJ2MD[1:0]
PJ1MD[1:0]
PJ0MD[1:0]
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 15, 14
Bit Name
Initial value
R/W R/W
Description PTJ7 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
PJ7MD[1:0] 11
13, 12
PJ6MD[1:0] 11
R/W
PTJ6 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
11, 10
PJ5MD[1:0] 11
R/W
PTJ5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
9, 8
PJ4MD[1:0] 11
R/W
PTJ4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
Rev. 1.00 Oct. 01, 2007 Page 1709 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 7, 6
Bit Name
Initial value
R/W R/W
Description PTJ3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
PJ3MD[1:0] 11
5, 4
PJ2MD[1:0] 11
R/W
PTJ2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
3, 2
PJ1MD[1:0] 11
R/W
PTJ1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
1, 0
PJ0MD[1:0] 11
R/W
PTJ0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
Rev. 1.00 Oct. 01, 2007 Page 1710 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.11 Port K Control Register (PKCR) PKCR is a 16-bit readable/writable register that selects the pin function and MOS input pull-up control.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PK7MD[1:0]
PK6MD[1:0]
PK5MD[1:0]
PK4MD[1:0]
PK3MD[1:0]
PK2MD[1:0]
PK1MD[1:0]
PK0MD[1:0]
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 15, 14
Bit Name
Initial value
R/W R/W
Description PTK7 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
PK7MD[1:0] 11
13, 12
PK6MD[1:0] 11
R/W
PTK6 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
11, 10
PK5MD[1:0] 11
R/W
PTK5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
9, 8
PK4MD[1:0] 11
R/W
PTK4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
Rev. 1.00 Oct. 01, 2007 Page 1711 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 7, 6
Bit Name
Initial value
R/W R/W
Description PTK3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
PK3MD[1:0] 11
5, 4
PK2MD[1:0] 11
R/W
PTK2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
3, 2
PK1MD[1:0] 11
R/W
PTK1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
1, 0
PK0MD[1:0] 11
R/W
PTK0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
Rev. 1.00 Oct. 01, 2007 Page 1712 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.12 Port L Control Register (PLCR) PLCR is a 16-bit readable/writable register that selects the pin function and MOS input pull-up control.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PL7MD[1:0]
PL6MD[1:0]
PL5MD[1:0]
PL4MD[1:0]
PL3MD[1:0]
PL2MD[1:0]
PL1MD[1:0]
PL0MD[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15, 14
Bit Name
Initial value
R/W R/W
Description PTL7 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
PL7MD[1:0] 00
13, 12
PL6MD[1:0] 00
R/W
PTL6 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
11, 10
PL5MD[1:0] 00
R/W
PTL5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
9, 8
PL4MD[1:0] 00
R/W
PTL4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
Rev. 1.00 Oct. 01, 2007 Page 1713 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 7, 6
Bit Name
Initial value
R/W R/W
Description PTL3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
PL3MD[1:0] 00
5, 4
PL2MD[1:0] 00
R/W
PTL2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
3, 2
PL1MD[1:0] 00
R/W
PTL1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
1, 0
PL0MD[1:0] 00
R/W
PTL0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
Rev. 1.00 Oct. 01, 2007 Page 1714 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.13 Port M Control Register (PMCR) PMCR is a 16-bit readable/writable register that selects the pin function and MOS input pull-up control.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PM7MD[1:0]
PM6MD[1:0]
PM5MD[1:0]
PM4MD[1:0]
PM3MD[1:0]
PM2MD[1:0]
PM1MD[1:0]
PM0MD[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15, 14
Bit Name
Initial value
R/W R/W
Description PTM7 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
PM7MD[1:0] 00
13, 12
PM6MD[1:0] 00
R/W
PTM6 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
11, 10
PM5MD[1:0] 00
R/W
PTM5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
9, 8
PM4MD[1:0] 00
R/W
PTM4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
Rev. 1.00 Oct. 01, 2007 Page 1715 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 7, 6
Bit Name
Initial value
R/W R/W
Description PTM3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
PM3MD[1:0] 00
5, 4
PM2MD[1:0] 00
R/W
PTM2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
3, 2
PM1MD[1:0] 00
R/W
PTM1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
1, 0
PM0MD[1:0] 00
R/W
PTM0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
Rev. 1.00 Oct. 01, 2007 Page 1716 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.14 Port N Control Register (PNCR) PNCR is a 16-bit readable/writable register that selects the pin function and MOS input pull-up control.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- Initial value: R/W: 0 R
-- 0 R
-- 0 R
-- 0 R
PN5MD[1:0]
PN4MD[1:0]
PN3MD[1:0]
PN2MD[1:0]
PN1MD[1:0]
PN0MD[1:0]
0 R/W
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
Bit 15, 12
Bit Name
Initial value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
11, 10
PN5MD[1:0] 00
R/W
PTN5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
9, 8
PN4MD[1:0] 10
R/W
PTN4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
7, 6
PN3MD[1:0] 10
R/W
PTN3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1717 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 5, 4
Bit Name
Initial value
R/W R/W
Description PTN2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PN2MD[1:0] 10
3, 2
PN1MD[1:0] 10
R/W
PTN1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
1, 0
PN0MD[1:0] 10
R/W
PTN0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1718 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.15 Port O Control Register (POCR) POCR is a 16-bit readable/writable register that selects the pin function and MOS input pull-up control.
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PO7MD[1:0]
PO6MD[1:0]
PO5MD[1:0]
PO4MD[1:0]
PO3MD[1:0]
PO2MD[1:0]
PO1MD[1:0]
PO0MD[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 15, 14
Bit Name
Initial value
R/W R/W
Description PTO7 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
PO7MD[1:0] 00
13, 12
PO6MD[1:0] 00
R/W
PTO6 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Setting prohibited
11, 10
PO5MD[1:0] 11
R/W
PTO5 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
9, 8
PO4MD[1:0] 11
R/W
PTO4 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
Rev. 1.00 Oct. 01, 2007 Page 1719 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 7, 6
Bit Name
Initial value
R/W R/W
Description PTO3 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
PO3MD[1:0] 11
5, 4
PO2MD[1:0] 11
R/W
PTO2 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
3, 2
PO1MD[1:0] 11
R/W
PTO1 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
1, 0
PO0MD[1:0] 11
R/W
PTO0 Mode 00: Other function 01: Port output 10: Port input (MOS pull-up: Off) 11: Port input (MOS pull-up: On)
Rev. 1.00 Oct. 01, 2007 Page 1720 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.16 Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores port A data.
Bit: 7 -- Initial value: R/W: 0 R 6 5 4 3 2 1 0
PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name
Initial value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
6 5 4 3 2 1 0
PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT
0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W
Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Rev. 1.00 Oct. 01, 2007 Page 1721 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.17 Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores port B data.
Bit: 7 6 5 4 3 2 1 0
PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Rev. 1.00 Oct. 01, 2007 Page 1722 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.18 Port C Data Register (PCDR) PCDR is an 8-bit readable/writable register that stores port C data.
Bit: 7 6 5 4 3 2 1 0
PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Rev. 1.00 Oct. 01, 2007 Page 1723 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.19 Port D Data Register (PDDR) PDDR is an 8-bit readable/writable register that stores port D data.
Bit: 7 6 5 4 3 2 1 0
PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Rev. 1.00 Oct. 01, 2007 Page 1724 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.20 Port E Data Register (PEDR) PEDR is an 8-bit readable/writable register that stores port E data.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 4 3 2 1 0
PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name
Initial value All0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT
0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Rev. 1.00 Oct. 01, 2007 Page 1725 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.21 Port F Data Register (PFDR) PFDR is an 8-bit readable/writable register that stores port F data.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 2 1 0
PF3DT PF2DT PF1DT PF0DT
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 to 4
Bit Name
Initial value All0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
3 2 1 0
PF3DT PF2DT PF1DT PF0DT
0 0 0 0
R/W R/W R/W R/W
Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Rev. 1.00 Oct. 01, 2007 Page 1726 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.22 Port G Data Register (PGDR) PGDR is an 8-bit readable/writable register that stores port G data.
Bit: 7 6 5 4 3 2 1 0
PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Rev. 1.00 Oct. 01, 2007 Page 1727 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.23 Port H Data Register (PHDR) PHDR is an 8-bit readable/writable register that stores port H data.
Bit: 7 6 5 4 3 2 1 0
PH7DT PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PH7DT PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Rev. 1.00 Oct. 01, 2007 Page 1728 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.24 Port I Data Register (PIDR) PIDR is an 8-bit readable/writable register that stores port I data.
Bit: 7 6 5
PI5DT
4
PI4DT
3
PI3DT
2
PI2DT
1
PI1DT
0
PI0DT
PI7DT PI6DT
Initial value: R/W:
0 R
0 R
Pin state Pin state Pin state Pin state
R/W
R/W
R
R
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PI7DT PI6DT PI5DT PI4DT PI3DT PI2DT PI1DT PI0DT
Initial value 0 0
R/W R R
Description Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Pin state R/W Pin state R/W Pin state R Pin state R 0 0 R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 1729 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.25 Port J Data Register (PJDR) PJDR is an 8-bit readable/writable register that stores port J data.
Bit: 7 6 5 4 3 2 1 0
PJ7DT PJ6DT PJ5DT PJ4DT PJ3DT PJ2DT PJ1DT PJ0DT
Initial value: Pin state Pin state Pin state Pin state Pin state Pin state Pin state Pin state R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PJ7DT PJ6DT PJ5DT PJ4DT PJ3DT PJ2DT PJ1DT PJ0DT
Initial value
R/W
Description Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Pin state R/W Pin state R/W Pin state R/W Pin state R/W Pin state R/W Pin state R/W Pin state R/W Pin state R/W
Rev. 1.00 Oct. 01, 2007 Page 1730 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.26 Port K Data Register (PKDR) PKDR is an 8-bit readable/writable register that stores port K data.
Bit: 7 6 5 4 3 2 1 0
PK7DT PK6DT PK5DT PK4DT PK3DT PK2DT PK1DT PK0DT
Initial value: Pin state Pin state Pin state Pin state Pin state Pin state Pin state Pin state R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PK7DT PK6DT PK5DT PK4DT PK3DT PK2DT PK1DT PK0DT
Initial value
R/W
Description Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Pin state R/W Pin state R/W Pin state R/W Pin state R/W Pin state R/W Pin state R/W Pin state R/W Pin state R/W
Rev. 1.00 Oct. 01, 2007 Page 1731 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.27 Port L Data Register (PLDR) PLDR is an 8-bit readable/writable register that stores port L data.
Bit: 7 6 5 4 3 2 1 0
PL7DT PL6DT PL5DT PL4DT PL3DT PL2DT PL1DT PL0DT
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PL7DT PL6DT PL5DT PL4DT PL3DT PL2DT PL1DT PL0DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Rev. 1.00 Oct. 01, 2007 Page 1732 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.28 Port M Data Register (PMDR) PMDR is an 8-bit readable/writable register that stores port M data.
Bit: 7 6 5 4 3 2 1 0
PM7DT PM6DT PM5DT PM4DT PM3DT PM2DT PM1DT PM0DT
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PM7DT PM6DT PM5DT PM4DT PM3DT PM2DT PM1DT PM0DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Rev. 1.00 Oct. 01, 2007 Page 1733 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.29 Port N Data Register (PNDR) PNDR is an 8-bit readable/writable register that stores port N data.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 4 3 2 1 0
PN5DT PN4DT PN3DT PN2DT PN1DT PN0DT
0 R/W
Pin state Pin state Pin state Pin state Pin state
R/W
R/W
R/W
R/W
R/W
Bit 7 6 5 4 3 2 1 0
Bit Name
Initial value All0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
PN5DT PN4DT PN3DT PN2DT PN1DT PN0DT
0
R/W
Pin state R/W Pin state R/W Pin state R/W Pin state R/W Pin state R/W
Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Rev. 1.00 Oct. 01, 2007 Page 1734 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.30 Port O Data Register (PODR) PODR is an 8-bit readable/writable register that stores port O data.
Bit: 7 6 5 4 3 2 1 0
PO7DT PO6DT PO5DT PO4DT PO3DT PO2DT PO1DT PO0DT
Initial value: 0 R/W: R/W
0 R/W
Pin state Pin state Pin state Pin state Pin state Pin state
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PO7DT PO6DT PO5DT PO4DT PO3DT PO2DT PO1DT PO0DT
Initial value 0 0
R/W R/W R/W
Description Each of these bits stores output data for the corresponding pin that is used as a general output port. If the port is read, the value of the corresponding bit in this register will be read for a pin configured as a general output port, while the state of the corresponding pin will be read for a pin configured as a general input port.
Pin state R/W Pin state R/W Pin state R/W Pin state R/W Pin state R/W Pin state R/W
Rev. 1.00 Oct. 01, 2007 Page 1735 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.31 Port I Pull-Up Control Register (PIPUPR) PIPUPR is an 8-bit readable/writable register. Each bit of this register corresponds to PTI7 to PTI0, and when the pins of Port I are used by "other function", pull-up control is performed for the individual pins. The settings in this register are invalid for the pins specified to function as port pins by PICR.
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 -- 1 R 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 0
PI1PUPR PI0PUPR
1 R/W
1 R/W
Bit 7 to 2
Bit Name --
Initial value All 1
R/W R
Description Reserved These bits are always read as 1, and the write value should always be 1.
1
PI1PUPR
1
R/W
Controls pull-up of the PTI1 pin 0: PTI1 pin pull-up off 1: PTI1 pin pull-up on
0
PI0PUPR
1
R/W
Controls pull-up of the PTI0 pin 0: PTI0 pin pull-up off 1: PTI0 pin pull-up on
Rev. 1.00 Oct. 01, 2007 Page 1736 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.32 Port J Pull-Up Control Register (PJPUPR) PJPUPR is an 8-bit readable/writable register. Each bit of this register corresponds to PTJ7 to PTJ0, and when the pins of Port J are used by "other function", pull-up control is performed for the individual pins. The settings in this register are invalid for the pins specified to function as port pins by PJCR.
Bit: 7 6 5 4 3 2 1 0
PJ7PUPR PJ6PUPR PJ5PUPR PJ4PUPR PJ3PUPR PJ2PUPR PJ1PUPR PJ0PUPR
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 7
Bit Name PJ7PUPR
Initial value 1
R/W R/W
Description Controls pull-up of the PTJ7 pin 0: PTJ7 pin pull-up off 1: PTJ7 pin pull-up on
6
PJ6PUPR
1
R/W
Controls pull-up of the PTJ6 pin 0: PTJ6 pin pull-up off 1: PTJ6 pin pull-up on
5
PJ5PUPR
1
R/W
Controls pull-up of the PTJ5 pin 0: PTJ5 pin pull-up off 1: PTJ5 pin pull-up on
4
PJ4PUPR
1
R/W
Controls pull-up of the PTJ4 pin 0: PTJ4 pin pull-up off 1: PTJ4 pin pull-up on
3
PJ3PUPR
1
R/W
Controls pull-up of the PTJ3 pin 0: PTJ3 pin pull-up off 1: PTJ3 pin pull-up on
2
PJ2PUPR
1
R/W
Controls pull-up of the PTJ2 pin 0: PTJ2 pin pull-up off 1: PTJ2 pin pull-up on
1
PJ1PUPR
1
R/W
Controls pull-up of the PTJ1 pin 0: PTJ1 pin pull-up off 1: PTJ1 pin pull-up on
Rev. 1.00 Oct. 01, 2007 Page 1737 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 0
Bit Name PJ0PUPR
Initial value 1
R/W R/W
Description Controls pull-up of the PTJ0 pin 0: PTJ0 pin pull-up off 1: PTJ0 pin pull-up on
40.2.33 Port K Pull-Up Control Register (PKPUPR) PKPUPR is an 8-bit readable/writable register. Each bit of this register corresponds to PTK7 to PTK0, and when the pins of Port K are used by "other function", pull-up control is performed for the individual pins. The settings in this register are invalid for the pins specified to function as port pins by PKCR.
Bit: 7 6 5 4 3 2 1 0
PK7PUPR PK6PUPR PK5PUPR PK4PUPR PK3PUPR PK2PUPR PK1PUPR PK0PUPR
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 7
Bit Name PK7PUPR
Initial value 1
R/W R/W
Description Controls pull-up of the PTK7 pin 0: PTK7 pin pull-up off 1: PTK7 pin pull-up on
6
PK6PUPR
1
R/W
Controls pull-up of the PTK6 pin 0: PTK6 pin pull-up off 1: PTK6 pin pull-up on
5
PK5PUPR
1
R/W
Controls pull-up of the PTK5 pin 0: PTK5 pin pull-up off 1: PTK5 pin pull-up on
4
PK4PUPR
1
R/W
Controls pull-up of the PTK4 pin 0: PTK4 pin pull-up off 1: PTK4 pin pull-up on
3
PK3PUPR
1
R/W
Controls pull-up of the PTK3 pin 0: PTK3 pin pull-up off 1: PTK3 pin pull-up on
Rev. 1.00 Oct. 01, 2007 Page 1738 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 2
Bit Name PK2PUPR
Initial value 1
R/W R/W
Description Controls pull-up of the PTK2 pin 0: PTK2 pin pull-up off 1: PTK2 pin pull-up on
1
PK1PUPR
1
R/W
Controls pull-up of the PTK1 pin 0: PTK1 pin pull-up off 1: PTK1 pin pull-up on
0
PK0PUPR
1
R/W
Controls pull-up of the PTK0 pin 0: PTK0 pin pull-up off 1: PTK0 pin pull-up on
40.2.34 Port L Pull-Up Control Register (PLPUPR) PLPUPR is an 8-bit readable/writable register. Each bit of this register corresponds to PTL7 to PTL0, and when the pins of Port L are used by "other function", pull-up control is performed for the individual pins. The settings in this register are invalid for the pins specified to function as port pins by PLCR.
Bit: 7 6 5 4 3 2 1 0
PL7PUPR PL6PUPR PL5PUPR PL4PUPR PL3PUPR PL2PUPR PL1PUPR PL0PUPR
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 7
Bit Name PL7PUPR
Initial value 1
R/W R/W
Description Controls pull-up of the PTL7 pin 0: PTL7 pin pull-up off 1: PTL7 pin pull-up on
6
PL6PUPR
1
R/W
Controls pull-up of the PTL6 pin 0: PTL6 pin pull-up off 1: PTL6 pin pull-up on
5
PL5PUPR
1
R/W
Controls pull-up of the PTL5 pin 0: PTL5 pin pull-up off 1: PTL5 pin pull-up on
Rev. 1.00 Oct. 01, 2007 Page 1739 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 4
Bit Name PL4PUPR
Initial value 1
R/W R/W
Description Controls pull-up of the PTL4 pin 0: PTL4 pin pull-up off 1: PTL4 pin pull-up on
3
PL3PUPR
1
R/W
Controls pull-up of the PTL3 pin 0: PTL3 pin pull-up off 1: PTL3 pin pull-up on
2
PL2PUPR
1
R/W
Controls pull-up of the PTL2 pin 0: PTL2 pin pull-up off 1: PTL2 pin pull-up on
1
PL1PUPR
1
R/W
Controls pull-up of the PTL1 pin 0: PTL1 pin pull-up off 1: PTL1 pin pull-up on
0
PL0PUPR
1
R/W
Controls pull-up of the PTL0 pin 0: PTL0 pin pull-up off 1: PTL0 pin pull-up on
40.2.35 Port M Pull-Up Control Register (PMPUPR) PMPUPR is an 8-bit readable/writable register. Each bit of this register corresponds to PTM7 to PTM0, and when the pins of Port M are used by "other function", pull-up control is performed for the individual pins. The settings in this register are invalid for the pins specified to function as port pins by PMCR.
Bit: 7 6 5 4 3 2 1 0
PM7PUPR PM6PUPR PM5PUPR PM4PUPR PM3PUPR PM2PUPR PM1PUPR PM0PUPR
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Rev. 1.00 Oct. 01, 2007 Page 1740 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 7
Bit Name PM7PUPR
Initial value 1
R/W R/W
Description Controls pull-up of the PTM7 pin 0: PTM7 pin pull-up off 1: PTM7 pin pull-up on
6
PM6PUPR
1
R/W
Controls pull-up of the PTM6 pin 0: PTM6 pin pull-up off 1: PTM6 pin pull-up on
5
PM5PUPR
1
R/W
Controls pull-up of the PTM5 pin 0: PTM5 pin pull-up off 1: PTM5 pin pull-up on
4
PM4PUPR
1
R/W
Controls pull-up of the PTM4 pin 0: PTM4 pin pull-up off 1: PTM4 pin pull-up on
3
PM3PUPR
1
R/W
Controls pull-up of the PTM3 pin 0: PTM3 pin pull-up off 1: PTM3 pin pull-up on
2
PM2PUPR
1
R/W
Controls pull-up of the PTM2 pin 0: PTM2 pin pull-up off 1: PTM2 pin pull-up on
1
PM1PUPR
1
R/W
Controls pull-up of the PTM1 pin 0: PTM1 pin pull-up off 1: PTM1 pin pull-up on
0
PM0PUPR
1
R/W
Controls pull-up of the PTM0 pin 0: PTM0 pin pull-up off 1: PTM0 pin pull-up on
Rev. 1.00 Oct. 01, 2007 Page 1741 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.36 Port N Pull-Up Control Register (PNPUPR) PNPUPR is an 8-bit readable/writable register. Each bit of this register corresponds to PTN7 to PTN0, and when the pins of Port N are used by "other function", pull-up control is performed for the individual pins. The settings in this register are invalid for the pins specified to function as port pins by PNCR.
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5
PN5PUPR
4 -- 1 R
3 -- 1 R
2 -- 1 R
1 -- 1 R
0 -- 1 R
1 R/W
Bit 7 6 5
Bit Name --
Initial value All 1
R/W R
Description Reserved These bits are always read as 1, and the write value should always be 1.
PN5PUPR
1
R/W
Controls pull-up of the PTN5 pin 0: PTN5 pin pull-up off 1: PTN5 pin pull-up on
4 to 0
--
All 1
R
Reserved These bits are always read as 1, and the write value should always be 1.
Rev. 1.00 Oct. 01, 2007 Page 1742 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.37 Port O Pull-Up Control Register (POPUPR) POPUPR is an 8-bit readable/writable register. Each bit of this register corresponds to PTO7 to PTO0, and when the pins of Port O are used by "other function", pull-up control is performed for the individual pins. The settings in this register are invalid for the pins specified to function as port pins by POCR.
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 4 3 2 1 0
PO5PUPRPO4PUPRPO3PUPRPO2PUPRPO1PUPRPO0PUPR
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 7 6 5
Bit Name --
Initial value All 1
R/W R
Description Reserved These bits are always read as 1, and the write value should always be 1.
PO5PUPR
1
R/W
Controls pull-up of the PTO5 pin 0: PTO5 pin pull-up off 1: PTO5 pin pull-up on
4
PO4PUPR
1
R/W
Controls pull-up of the PTO4 pin 0: PTO4 pin pull-up off 1: PTO4 pin pull-up on
3
PO3PUPR
1
R/W
Controls pull-up of the PTO3 pin 0: PTO3 pin pull-up off 1: PTO3 pin pull-up on
2
PO2PUPR
1
R/W
Controls pull-up of the PTO2 pin 0: PTO2 pin pull-up off 1: PTO2 pin pull-up on
1
PO1PUPR
1
R/W
Controls pull-up of the PTO1 pin 0: PTO1 pin pull-up off 1: PTO1 pin pull-up on
0
PO0PUPR
1
R/W
Controls pull-up of the PTO0 pin 0: PTO0 pin pull-up off 1: PTO0 pin pull-up on
Rev. 1.00 Oct. 01, 2007 Page 1743 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.38 Input-Pin Pull-Up Control Register (PPUPR) PPUPR is an 8-bit readable/writable register that individually controls the pull-up for the pin connected to each bit.
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 -- 1 R 4 -- 1 R 3 -- 1 R 2 1 0
IOIS16UP BREQPUP RDYPUP
1 R
1 R/W
1 R/W
Bit 7 to 3
Bit Name --
Initial value All 1
R/W R
Description Reserved These bits are always read as 1, and the write value should always be 1.
2
IOIS16UP
1
R/W
Controls pull-up of the IOIS16 pin 0: IOIS16 pin pull-up off 1: IOIS16 pin pull-up on
1
BREQPUP
1
R/W
Controls pull-up of the BREQ pin 0: BREQ pin pull-up off 1: BREQ pin pull-up on
0
RDYPUP
1
R/W
Controls pull-up of the RDY/PCC_WAIT pin 0: RDY/PCC_WAIT pin pull-up off 1: RDY/PCC_WAIT pin pull-up on
Rev. 1.00 Oct. 01, 2007 Page 1744 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.39 Pin Select Register 0 (PSEL0) PSEL0 is a 16-bit readable/writable register that selects the functions of the Port A (PTA), Port B (PTB), and Port C (PTC) pins multiplexed with "other function". When using the pins with "other function" assigned, set PSEL0 and then set the corresponding port control register to select "other function".
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2
PTSEL0[4:0]
1
0
-- Initial value: R/W: 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R
-- 0 R 0 R/W 1 R/W
0 R/W
0 R/W
0 R/W
Bit 15 to 5
Bit Name --
Initial value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0. These bits select the functions of Port A (PTA), Port B (PTB), and Port C (PTC).
Bit setting Selected function PTB PCIC* MMC LCDCM PTC PCIC* MMC LCDCM PTSEL0[4:0] PTA 01xxx 00001 10xxx Other than above PCIC* SCIF1 SCIF1
4 to 0
PTSEL0 [4:0]
01000
R/W
Setting prohibited
[Legend] x: Don't care Note: * When clearing interrupt mask of the interrupt controller (INTC) with the PCIC function selected, make sure to select the PCIC function with this register in advance.
Rev. 1.00 Oct. 01, 2007 Page 1745 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.40 Pin Select Register 1 (PSEL1) PSEL1 is a 16-bit readable/writable register that selects the functions of the Port D (PTD), Port E (PTE), Port F (PTF), Port G (PTG), and Port H (PTH) pins multiplexed with "other function". When using the pins with "other function" assigned, set PSEL1 and then set the corresponding port control register to select "other function".
Bit:
15 14 13
PTSEL1[14:12]
12
11
10
9
8
7
6
5
4
3
2
1
0
-- Initial value: R/W: 0 R
PTSEL1[11:8]
PTSEL1[7:4]
PTSEL1[3:0]
1 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
Bit 15
Bit Name --
Initial value 0
R/W R
Description Reserved This bit is always read as 0, and the write value should always be 0. These bits select the function of Port H (PTH).
Bit setting Selected function PTSEL1[14:12] PTH 1xx 01x 001 000 PCIC* MII1 RMII1M TPU
14 to 12 PTSEL1 [14:12]
100
R/W
[Legend] x: Don't care Note: * When clearing interrupt mask of the interrupt controller (INTC) with the PCIC function selected, make sure to select the PCIC function with this register in advance.
Rev. 1.00 Oct. 01, 2007 Page 1746 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 11 to 8
Bit Name PTSEL1 [11:8]
Initial value 1000
R/W R/W
Description These bits select the functions of Port F (PTF) and Port G (PTG).
Bit setting Selected function PTG PCIC* MII1 PTSEL1[11:8] PTF 1xxx 01xx 0011 0010 Other than above PCIC* MII1 SIM DMAC3
Setting prohibited
[Legend] x: Don't care Note: * When clearing interrupt mask of the interrupt controller (INTC) with the PCIC function selected, make sure to select the PCIC function with this register in advance. 7 to 4 PTSEL1 [7:4] 1000 R/W These bits select the functions of Port E (PTE).
Bit setting Selected function PTSEL1[7:4] PTE 1xxx 0000 0010 0011 0100 0101 Other than above PCIC* GMII1 DMAC2 DMAC2 PCC PCC SCIF2 SSI0 SCIF2 SSI0
Setting prohibited
[Legend] x: Don't care Note: * When clearing interrupt mask of the interrupt controller (INTC) with the PCIC function selected, make sure to select the PCIC function with this register in advance.
Rev. 1.00 Oct. 01, 2007 Page 1747 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 3 to 0
Bit Name PTSEL1 [3:0]
Initial value 1000
R/W R/W
Description These bits select the functions of Port D (PTD).
Bit setting Selected function PTSEL1[3:0] PTD 1xxx 0000 0001 0010 0100 0101 Other than above PCIC* GMII1 LCDCM PCC HAC HAC SSI1 GMII1 SIOF0
Setting prohibited
[Legend] x: Don't care Note: * When clearing interrupt mask of the interrupt controller (INTC) with the PCIC function selected, make sure to select the PCIC function with this register in advance.
Rev. 1.00 Oct. 01, 2007 Page 1748 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.41 Pin Select Register 2 (PSEL2) PSEL2 is a 16-bit readable/writable register that selects the functions of the Port I (PTI), Port J (PTJ), and Port K (PTK) pins multiplexed with "other function". When using the pins with "other function" assigned, set PSEL2 and then set the corresponding port control register to select "other function".
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- Initial value: R/W: 0 R
PTSEL2[14:12]
PTSEL2[11:8]
PTSEL2[7:6]
PTSEL2[5:4]
PTSEL2[3:2]
PTSEL2[1:0]
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15
Bit Name --
Initial value 0
R/W R
Description Reserved This bit is always read as 0, and the write value should always be 0. These bits select the functions of Port K (PTK).
Bit setting PTSEL2[14:12] 000 001 010 100 Other than above Selected function PTK LCDC GMII0 SIOF1 STIF1 SIOF2
14 to 12 PTSEL2 [14:12]
All 0
R/W
Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 1749 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 11 to 8
Bit Name PTSEL2 [11:8]
Initial value All 0
R/W R/W
Description These bits select the functions of Port J (PTJ7 to PTJ1).
Bit setting Selected function PTSEL2 [11:8] 0000 0010 0011 0110 1000 PTJ1 LCDC LCDC LCDC RMII1 PTJ7 to PTJ2 LCDC MII0 MII0 RMII1 PCIC* INT
STIF0M STIF0M
Other than Setting prohibited above
Note:
*
When clearing interrupt mask of the interrupt controller (INTC) with the PCIC function selected, make sure to select the PCIC function with this register in advance.
7 6
PTSEL2 [7:6]
All 0
R/W
These bits select the functions of Port J (PTJ0).
Bit setting PTSEL2[7:6] 00 01 10 Selected function PTJ0 REF50CK GMII0 STIF0M
Other than above Setting prohibited
5 4
PTSEL2 [5:4]
All 0
R/W
These bits select the functions of Port I (PTI5, PTI4).
Bit setting PTSEL2[5:4] 00 01 10 11 Selected function PTI5, PTI4 LCDC LCDC LCDC STIF1 USBH/F ETC1 RMII0M0
Rev. 1.00 Oct. 01, 2007 Page 1750 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 3 2
Bit Name PTSEL2 [3:2]
Initial value All 0
R/W R/W
Description These bits select the functions of Port I (PTI3, PTI2).
Bit setting PTSEL2[3:2] 00 01 10 11 Selected function PTI3, PTI2 USB STIF0M SIOF1 IIC0
1 0
PTSEL2 [1:0]
All 0
R/W
These bits select the functions of Port I (PTI1, PTI0).
Bit setting PTSEL2[1:0] 00 01 1x Selected function PTI1, PTI0 SYS STIF1 RMII0
[Legend] x: Don't care
Rev. 1.00 Oct. 01, 2007 Page 1751 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.42 Pin Select Register 3 (PSEL3) PSEL3 is a 16-bit readable/writable register that selects the functions of the Port L (PTL), and Port M (PTM) pins multiplexed with "other function". When using the pins with "other function" assigned, set PSEL3 and then set the corresponding port control register to select "other function".
Bit:
15 14 13 12 11 10 9
PTSEL3[10:8]
8
7
6
5
PTSEL3[6:4]
4
3
2
1
PTSEL3[2:0]
0
-- Initial value: R/W: 0 R
PTSEL3[14:12]
-- 0 R
-- 0 R
-- 0 R
1 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
Bit 15
Bit Name --
Initial value 0
R/W R
Description Reserved This bit is always read as 0, and the write value should always be 0. These bits select the functions of Port L (PTL7 to PTL4) and Port M (PTM7 to PTM1).
Bit setting Selected function PTM7 to PTM1 LBSC* / EXCPU RMII0 MII0
2
1
14 to 12 PTSEL3 [14:12]
100
R/W
PTSEL3[14:12] PTL7 to PTL4 1xx 000 001 010 011 LBSC* / EXCPU LCDC MII0 DMAC1 STIF0
1
PCIC*
RMII0 STIF0
[Legend] x: Don't care Notes: 1. When 32-bit is selected as the data bus width in the LBSC, select this pin function. 2. When clearing interrupt mask of the interrupt controller (INTC) with the PCIC function selected, make sure to select the PCIC function with this register in advance. 11 -- 0 R Reserved This bit is always read as 0, and the write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1752 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 10 to 8
Bit Name PTSEL3 [10:8]
Initial value 100
R/W R/W
Description These bits select the function of Port M (PTM0).
Bit setting PTSEL3[10:8] 1xx 000 001 011 Selected function PTM0 LBSC*/EXCPU STIF0 RMII0M0 MII0
[Legend] x: Don't care Note: * When 32-bit is selected as the data bus width in the LBSC, select this pin function. 7 -- 0 R Reserved This bit is always read as 0, and the write value should always be 0. These bits select the function of Port L (PTL3).
Bit setting PTSEL3[6:4] 1xx 000 001 010 011 Selected function PTL3 LBSC* /EXCPU LCDC PCIC* IRQ7 MII0
2
1
6 to 4
PTSEL3 [6:4]
100
R/W
[Legend] x: Don't care Notes: 1. When 32-bit is selected as the data bus width in the LBSC, select this pin function. 2. When clearing interrupt mask of the interrupt controller (INTC) with the PCIC function selected, make sure to select the PCIC function with this register in advance. 3 -- 0 R Reserved This bit is always read as 0, and the write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1753 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 2 to 0
Bit Name PTSEL3 [2:0]
Initial value 100
R/W R/W
Description These bits select the functions of Port L (PTL2 to PTL0).
Bit setting PTSEL3[2:0] 1xx 000 001 010 011 Selected function PTL2 to PTL0 LBSC*/EXCPU LCDC DMAC0 INT MII0
[Legend] x: Don't care Note: * When 32-bit is selected as the data bus width in the LBSC, select this pin function.
Rev. 1.00 Oct. 01, 2007 Page 1754 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.2.43 Pin Select Register 4 (PSEL4) PSEL4 is a 16-bit readable/writable register that selects the functions of the Port I (PTI) and Port O (PTO) pins multiplexed with "other function", and also selects the function of the IOIS16/TCLK pin and the REF125CK/HAC_BITCLK pin. When using the pins with "other function" assigned, set PSEL4 and then set the corresponding port control register to select "other function".
Bit:
15 14 13 12 11
PTSEL4B
10
9
8
PTSEL48
7
6
PTSEL46
5
4
3
2
1
0
PTSEL4F PTSEL4E PTSEL4D
-- 0 R
PTSEL4[10:9]
-- 0 R
PTSEL4[5:4]
PTSEL4[3:2]
PTSEL4[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15
Bit Name PTSEL4F
Initial value 0
R/W R/W
Description Selects the function of the IOIS16/TCLK pin. 0: IOIS16 function is selected 1: TCLK function is selected When the IOIS16 function is selected, this bit should be set to the initial value. Do not select the IOIS16 function after the TCLK function is selected.
14
PTSEL4E
0
R/W
Selects the function of the REF125CK/HAC_BITCLK pin. 0: REF125CK function is selected 1: HAC_BITCLK function is selected Selects the pin for DREQ1 0: Input from PTL5 is used as DREQ1 1: Input from PTO5 is used as DREQ1
13
PTSEL4D
0
R/W
12
0
R
Reserved This bit is always read as 0, and the write value should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1755 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 11
Bit Name PTSEL4B
Initial value 0
R/W R/W
Description Selects the pins for ST0_D0 to ST0_D07, ST0_START, ST0_VALID, and ST0_CLK. 0: Inputs from PTL5 to PTL7 and PTM0 to PTM7 are used as ST0_D0 to ST0_D07, ST0_START, ST0_VALID, and ST0_CLK, respectively 1: Inputs from PTJ1 to PTJ7, PTI2, PTI3, PTI6, and PTI7 are used as ST0_D0 to ST0_D07, ST0_START, ST0_VALID, and ST0_CLK, respectively These bits select the pin for MDIO0. 00: Input from PTL3 is used as ET0_ MDIO (only PTL3 can be used when using GMII0 and MII0) 01: Input from PTI1 is used as RMII0_ MDIO 10: Input from PTM0 is used as RMII0_ MDIO 11: Input from PTO3 is used as RMII0_ MDIO Selects the pin for MDIO1. 0: Input from PTF2 is used as ET1_ MDIO (only PTF2 can be used when using GMII1 and MII1) 1: Input from PTO1 is used as ET1_ MDIO Reserved This bit is always read as 0, and the write value should always be 0. Selects the pins for RMII1_RX_ER, RMII1_CRS_DV, RMII1_RXD1, and RMII1_RXD0. 0: Inputs from PTJ1 and PTJ3 to PTJ5 are used as RMII1_RX_ER, RMII1_CRS_DV, RMII1_RXD1, and RMII1_RXD0, respectively 1: Inputs from PTH0, PTH1, PTH3, and PTH4 are used as RMII1_RX_ER, RMII1_CRS_DV, RMII1_RXD1, and RMII1_RXD0, respectively
10, 9
PTSEL4 [10:9]
All 0
R/W
8
PTSEL48
0
R/W
7
0
R
6
PTSEL46
0
R/W
Rev. 1.00 Oct. 01, 2007 Page 1756 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
Bit 5 4
Bit Name PTSEL4 [5:4]
Initial value 00
R/W R/W
Description These bits select the functions of Port I (PTI7 and PTI6).
Bit setting PTSEL4[5:4] 00 01 11 Selected function PTI7, PTI6 INT IIC1 STIF0M
Other than above Setting prohibited
3 2
PTSEL4 [3:2]
00
R/W
These bits select the function of Port O (PTO3 to PTO0).
Bit setting PTSEL4[3:2] 00 01 1x Selected function PTO3 to PTO0 AUD SSI2
RMII0M1 RMII1M
[Legend] x: Don't care 1 0 PTSEL4 [1:0] 00 R/W These bits select the function of Port O (PTO7 to PTO4).
Bit setting Selected function PTSEL4 [1:0] 00 01 1x PTO7 to PTO4 AUD DMAC1M SSI3 INT EXCPU
[Legend] x: Don't care
Rev. 1.00 Oct. 01, 2007 Page 1757 of 1956 REJ09B0256-0100
Section 40 General Purpose I/O (GPIO)
40.3
Usage Examples
Example procedures for configuring general-purpose input/output ports (GPIO) are shown below. 40.3.1 Port Output Function
To set up a pin for the port output function, write B'01 to the corresponding two bits in the port control register (PACR to PPCR). This allows the data of the corresponding bit in the port data register (PADR to PPDR) to be output from that pin. Note that settings in the pull-up control register (PAPUPR to PPPUPR) and pin select register (PSEL0 to PSEL4) are invalid for the pins configured for the port output function. 40.3.2 Port Input Function
To set up a pin for the port input function, write B'10 (when not using MOS pull-up) or B'11 (when using MOS pull-up) to the corresponding two bits in the port control register (PACR to PPCR). This allows the value of that pin to be read from the corresponding bit in the port data register (PADR to PPDR). Note that settings in the pull-up control register (PAPUPR to PPPUPR) and pin select register (PSEL0 to PSEL4) are invalid for the pins configured for the port output function. 40.3.3 Peripheral Module Function
To set up a pin for use by peripheral modules, first set the pin select register (PSEL0 to PSEL4) to select the module that uses that pin. Then, if the pin is to be used as an input or input/output pin, set the pull-up control register (PAPUPR to PPPUPR) to create the MOS pull-up setting: to the corresponding bit, write 0 when not using the MOS pull-up or write 1 when using the MOS pull-up. For a pin used for output, the MOS pull-up is always turned off for any setting of the pull-up control register. Finally, write B'00 to the corresponding two bits in the port control register (PACR to PPCR).
Rev. 1.00 Oct. 01, 2007 Page 1758 of 1956 REJ09B0256-0100
Section 41 User Break Controller (UBC)
Section 41 User Break Controller (UBC)
The user break controller (UBC) provides versatile functions to facilitate program debugging. These functions help to ease creation of a self-monitor/debugger, which allows easy program debugging using this LSI alone, without using the in-circuit emulator. Various break conditions can be set in the UBC: instruction fetch or read/write access of an operand, operand size, data contents, address value, and program stop timing for instruction fetch.
41.1
Features
1. The following break conditions can be set. Break channels: Two (channels 0 and 1) User break conditions can be set independently for channels 0 and 1, and can also be set as a single sequential condition for the two channels, that is, a sequential break. (Sequential break involves two cases such that the channel 0 break condition is satisfied in a certain bus cycle and then the channel 1 break condition is satisfied in a different bus cycle, and vice versa.) * Address When 40 bits containing ASID and 32-bit address are compared with the specified value, all the ASID bits can be compared or masked. 32-bit address can be masked bit by bit, allowing the user to mask the address in desired page sizes such as lower 12 bits (4-Kbyte page) and lower 10 bits (1-Kbyte page). * Data 32 bits can be masked only for channel 1. * Bus cycle The program can break either for instruction fetch (PC break) or operand access. * Read or write access * Operand sizes Byte, word, longword, and quadword are supported. 2. The user-designated exception handling routine for the user break condition can be executed. 3. Pre-instruction-execution or post-instruction-execution can be selected as the PC break timing. 4. A maximum of 212 - 1 repetition counts can be specified as the break condition (available only for channel 1).
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Section 41 User Break Controller (UBC)
Figure 41.1 shows the UBC block diagram.
SDB SAB
ASID
Access control
Internal bus Access comparator ASID comparator Address comparator Channel 0 operation control
CAR0 CAMR0 CRR0
CBR0
Access comparator ASID comparator Address comparator
CBR1
CAR1 CAMR1 CDR1 CDMR1 CETR1 CRR1
Data comparator Channel 1 operation control
CCMFR
Control
CBCR
User break is requested. [Legend]
CBR0: CRR0: CAR0: CAMR0: CBR1: CRR1: CAR1:
Match condition setting register 0 Match operation setting register 0 Match address setting register 0 Match address mask setting register 0 Match condition setting register 1 Match operation setting register 1 Match address setting register 1
CAMR1: Match address mask setting register 1 CDR1: Match data setting register 1 CDMR1: Match data mask setting register 1 CETR1: Execution count break register CCMFR: Channel match flag register CBCR: Break control register Operand address bus SAB: Operand data bus SDB:
Figure 41.1 Block Diagram of UBC
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Section 41 User Break Controller (UBC)
41.2
Register Descriptions
The UBC has the following registers. Table 41.1 Register Configuration
Name Match condition setting register 0 Match operation setting register 0 Match address setting register 0 Abbreviation CBR0 CRR0 CAR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P4 Address* H'FF200000 H'FF200004 H'FF200008 H'FF20000C H'FF200020 H'FF200024 H'FF200028 H'FF20002C H'FF200030 H'FF200034 H'FF200038 H'FF200600 H'FF200620 Area 7 Address* H'1F200000 H'1F200004 H'1F200008 H'1F20000C H'1F200020 H'1F200024 H'1F200028 H'1F20002C H'1F200030 H'1F200034 H'1F200038 H'1F200600 H'1F200620 Access Size 32 32 32 32 32 32 32 32 32 32 32 32 32
Match address mask setting CAMR0 register 0 Match condition setting register 1 Match operation setting register 1 Match address setting register 1 CBR1 CRR1 CAR1
Match address mask setting CAMR1 register 1 Match data setting register 1 CDR1 Match data mask setting register 1 Execution count break register 1 Channel match flag register Break control register Note: * CDMR1 CETR1 CCMFR CBCR
P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB.
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Section 41 User Break Controller (UBC)
Table 41.2 Register Status in Each Processing State
Register Name Match condition setting register 0 Match operation setting register 0 Match address setting register 0 Match address mask setting register 0 Match condition setting register 1 Match operation setting register 1 Match address setting register 1 Match address mask setting register 1 Match data setting register 1 Match data mask setting register 1 Execution count break register 1 Channel match flag register Break control register Abbreviation CBR0 CRR0 CAR0 CAMR0 CBR1 CRR1 CAR1 CAMR1 CDR1 CDMR1 CETR1 CCMFR CBCR Power-on Reset H'20000000 H'00002000 Undefined Undefined H'20000000 H'00002000 Undefined Undefined Undefined Undefined Undefined H'00000000 H'00000000 Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
The access size must be the same as the control register size. If the size is different, the register is not written to if attempted, and reading the register returns the undefined value. A desired break may not occur between the time when the instruction for rewriting the control register is executed and the time when the written value is actually reflected on the register. In order to confirm the exact timing when the control register is updated, read the data which has been written most recently. The subsequent instructions are valid for the most recently written register value.
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Section 41 User Break Controller (UBC)
41.2.1
Match Condition Setting Registers 0 and 1 (CBR0 and CBR1)
CBR0 and CBR1 are readable/writable 32-bit registers which specify the break conditions for channels 0 and 1, respectively. The following break conditions can be set in the CBR0 and CBR1: (1) whether or not to include the match flag in the conditions, (2) whether or not to include the ASID, and the ASID value when included, (3) whether or not to include the data value, (4) operand size, (5) whether or not to include the execution count, (6) bus type, (7) instruction fetch cycle or operand access cycle, and (8) read or write access cycle. * CBR0
Bit : Initial value : R/W: Bit : Initial value : R/W:
31
MFE 0 R/W 15
0 R
30
AIE 0 R/W 14
0 R/W
29
1 R/W 13 SZ
0 R/W
28
0 R/W 12
0 R/W
27
MFI 0 R/W 11
0 R
26
0 R/W 10
0 R
25
0 R/W 9
0 R
24
0 R/W 8
0 R
23
0 R/W 7 CD
0 R/W
22
0 R/W 6
0 R/W
21
0 R/W 5 ID
0 R/W
20
AIV 0 R/W 4
0 R/W
19
0 R/W 3
0 R
18
0 R/W 2 RW
0 R/W
17
0 R/W 1
0 R/W
16 0 R/W
0 CE 0 R/W
Bit 31
Bit Name MFE
Initial Value 0
R/W R/W
Description Match Flag Enable Specifies whether or not to include the match flag value specified by the MFI bit of this register in the match conditions. When the specified match flag value is 1, the condition is determined to be satisfied. 0: The match flag is not included in the match conditions; thus, not checked. 1: The match flag is included in the match conditions.
30
AIE
0
R/W
ASID Enable Specifies whether or not to include the ASID specified by the AIV bit of this register in the match conditions. 0: The ASID is not included in the match conditions; thus, not checked. 1: The ASID is included in the match conditions.
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Section 41 User Break Controller (UBC)
Bit 29 to 24
Bit Name MFI
Initial Value 100000
R/W R/W
Description Match Flag Specify Specifies the match flag to be included in the match conditions. 000000: MF0 bit of the CCMFR register 000001: MF1 bit of the CCMFR register Others: Reserved (setting prohibited) Note: The initial value is the reserved value, but when 1 is written into CBR0[0], MFI must be set to 000000 or 000001. And note that the channel 0 is not hit when MFE bit of this register is 1 and MFI bits are 000000 in the condition of CCRMF.MF0 = 0.
23 to 16
AIV
All 0
R/W
ASID Specify Specifies the ASID value to be included in the match conditions.
15
--
0
R
Reserved For read/write in this bit, refer to General Precautions on Handling of Product.
14 to 12
SZ
All 0
R/W
Operand Size Select Specifies the operand size to be included in the match conditions. This bit is valid only when the operand access cycle is specified as a match condition. 000: The operand size is not included in the match conditions; thus, not checked (any operand size specifies the match condition).*1 001: Byte access 010: Word access 011: Longword access 100: Quadword access*
2
Others: Reserved (setting prohibited) 11 to 8 -- All 0 R Reserved For read/write in this bit, refer to General Precautions on Handling of Product.
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Section 41 User Break Controller (UBC)
Bit 7, 6
Bit Name CD
Initial Value All 0
R/W R/W
Description Bus Select Specifies the bus to be included in the match conditions. This bit is valid only when the operand access cycle is specified as a match condition. 00: Operand bus for operand access Others: Reserved (setting prohibited)
5, 4
ID
All 0
R/W
Instruction Fetch/Operand Access Select Specifies the instruction fetch cycle or operand access cycle as the match condition. 00: Instruction fetch cycle or operand access cycle 01: Instruction fetch cycle 10: Operand access cycle 11: Instruction fetch cycle or operand access cycle
3
--
0
R
Reserved For read/write in this bit, refer to General Precautions on Handling of Product.
2, 1
RW
All 0
R/W
Bus Command Select Specifies the read/write cycle as the match condition. This bit is valid only when the operand access cycle is specified as a match condition. 00: Read cycle or write cycle 01: Read cycle 10: Write cycle 11: Read cycle or write cycle
0
CE
0
R/W
Channel Enable Validates/invalidates the channel. If this bit is 0, all the other bits of this register are invalid. 0: Invalidates the channel. 1: Validates the channel.
Notes: 1. If the data value is included in the match conditions, be sure to specify the operand size. 2. If the quadword access is specified and the data value is included in the match conditions, the upper and lower 32 bits of 64-bit data are each compared with the contents of both the match data setting register and the match data mask setting register.
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Section 41 User Break Controller (UBC)
* CBR1
Bit :
31
MFE
30
AIE 0 R/W 14
0 R/W
29
1 R/W 13 SZ 0 R/W
28
0 R/W 12
27
MFI 0 R/W 11
26
0 R/W 10
0 R
25
0 R/W 9
0 R
24
0 R/W 8
0 R
23
0 R/W 7 CD
0 R/W
22
0 R/W 6
0 R/W
21
0 R/W 5 ID
0 R/W
20
AIV 0 R/W 4
0 R/W
19
0 R/W 3
0 R
18
0 R/W 2 RW
0 R/W
17
0 R/W 1
0 R/W
16 0 R/W
0
Initial value : 0 R/W: R/W Bit :
15
DBE Initial value : 0 R/W: R/W
ETBE 0 0 R/W R/W
CE 0 R/W
Bit 31
Bit Name MFE
Initial Value 0
R/W R/W
Description Match Flag Enable Specifies whether or not to include the match flag value specified by the MFI bit of this register in the match conditions. When the specified match flag value is 1, the condition is determined to be satisfied. 0: The match flag is not included in the match conditions; thus, not checked. 1: The match flag is included in the match conditions.
30
AIE
0
R/W
ASID Enable Specifies whether or not to include the ASID specified by the AIV bit of this register in the match conditions. 0: The ASID is not included in the match conditions; thus, not checked. 1: The ASID is included in the match conditions.
29 to 24
MFI
100000
R/W
Match Flag Specify Specifies the match flag to be included in the match conditions. 000000: The MF0 bit of the CCMFR register 000001: The MF1 bit of the CCMFR register Others: Reserved (setting prohibited) Note: The initial value is the reserved value, but when 1 is written into CBR1[0], MFI must be set to 000000 or 000001. And note that the channel 1 is not hit when MFE bit of this register is 1 and MFI bits are 000001 in the condition of CCRMF.MF1 = 0.
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Section 41 User Break Controller (UBC)
Bit 23 to 16
Bit Name AIV
Initial Value All 0
R/W R/W
Description ASID Specify Specifies the ASID value to be included in the match conditions.
15
DBE
0
R/W
Data Value Enable*3 Specifies whether or not to include the data value in the match condition. This bit is valid only when the operand access cycle is specified as a match condition. 0: The data value is not included in the match conditions; thus, not checked. 1: The data value is included in the match conditions.
14 to 12
SZ
All 0
R/W
Operand Size Select Specifies the operand size to be included in the match conditions. This bit is valid only when the operand access cycle is specified as a match condition. 000: The operand size is not included in the match condition; thus, not checked (any operand size 1 specifies the match condition). * 001: Byte access 010: Word access 011: Longword access 100: Quadword access*
2
Others: Reserved (setting prohibited) 11 ETBE 0 R/W Execution Count Value Enable Specifies whether or not to include the execution count value in the match conditions. If this bit is 1 and the match condition satisfaction count matches the value specified by the CETR1 register, the operation specified by the CRR1 register is performed. 0: The execution count value is not included in the match conditions; thus, not checked. 1: The execution count value is included in the match conditions. 10 to 8 -- All 0 R Reserved For read/write in this bit, refer to General Precautions on Handling of Product.
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Section 41 User Break Controller (UBC)
Bit 7, 6
Bit Name CD
Initial Value All 0
R/W R/W
Description Bus Select Specifies the bus to be included in the match conditions. This bit is valid only when the operand access cycle is specified as a match condition. 00: Operand bus for operand access Others: Reserved (setting prohibited)
5, 4
ID
All 0
R/W
Instruction Fetch/Operand Access Select Specifies the instruction fetch cycle or operand access cycle as the match condition. 00: Instruction fetch cycle or operand access cycle 01: Instruction fetch cycle 10: Operand access cycle 11: Instruction fetch cycle or operand access cycle
3
--
0
R
Reserved For read/write in this bit, refer to General Precautions on Handling of Product.
2, 1
RW
All 0
R/W
Bus Command Select Specifies the read/write cycle as the match condition. This bit is valid only when the operand access cycle is specified as a match condition. 00: Read cycle or write cycle 01: Read cycle 10: Write cycle 11: Read cycle or write cycle
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Section 41 User Break Controller (UBC)
Bit 0
Bit Name CE
Initial Value 0
R/W R/W
Description Channel Enable Validates/invalidates the channel. If this bit is 0, all the other bits in this register are invalid. 0: Invalidates the channel. 1: Validates the channel.
Notes: 1. If the data value is included in the match conditions, be sure to specify the operand size. 2. If the quadword access is specified and the data value is included in the match conditions, the upper and lower 32 bits of 64-bit data are each compared with the contents of both the match data setting register and the match data mask setting register. 3. The OCBI instruction is handled as longword write access without the data value, and the PREF, OCBP, and OCBWB instructions are handled as longword read access without the data value. Therefore, do not include the data value in the match conditions for these instructions.
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Section 41 User Break Controller (UBC)
41.2.2
Match Operation Setting Registers 0 and 1 (CRR0 and CRR1)
CRR0 and CRR1 are readable/writable 32-bit registers which specify the operation to be executed when channels 0 and 1 satisfy the match condition, respectively. The following operations can be set in the CRR0 and CRR1 registers: (1) breaking at a desired timing for the instruction fetch cycle and (2) requesting a break. * CRR0
Bit : Initial value : R/W: Bit : Initial value : R/W:
31
0 R 15
0 R
30
0 R 14
0 R
29
0 R 13
1 R
28
0 R 12
0 R
27
0 R 11
0 R
26
0 R 10
0 R
25
0 R 9
0 R
24
0 R 8
0 R
23
0 R 7
0 R
22
0 R 6
0 R
21
0 R 5
0 R
20
0 R 4
0 R
19
0 R 3
0 R
18
0 R 2
0 R
17
0 R 1 PCB 0 R/W
16 0 R
0
BIE 0 R/W
Bit 31 to 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved For read/write in this bit, refer to General Precautions on Handling of Product.
13
--
1
R
Reserved This bit is always read as 1. The write value should always be 1.
12 to 2
--
All 0
R
Reserved For read/write in this bit, refer to General Precautions on Handling of Product.
1
PCB
0
R/W
PC Break Select Specifies either before or after instruction execution as the break timing for the instruction fetch cycle. This bit is invalid for breaks other than the ones for the instruction fetch cycle. 0: Sets the PC break before instruction execution. 1: Sets the PC break after instruction execution.
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Section 41 User Break Controller (UBC)
Bit 0
Bit Name BIE
Initial Value 0
R/W R/W
Description Break Enable Specifies whether or not to request a break when the match condition is satisfied for the channel. 0: Does not request a break. 1: Requests a break.
* CRR1
Bit : Initial value : R/W: Bit : Initial value : R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 1 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 PCB 0 R/W 16 0 R 0 BIE 0 R/W
Bit 31 to 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved For read/write in this bit, refer to General Precautions on Handling of Product.
13
--
1
R
Reserved This bit is always read as 1. The write value should always be 1.
12 to 2
--
All 0
R
Reserved For read/write in this bit, refer to General Precautions on Handling of Product.
1
PCB
0
R/W
PC Break Select Specifies either before or after instruction execution as the break timing for the instruction fetch cycle. This bit is invalid for breaks other than ones for the instruction fetch cycle. 0: Sets the PC break before instruction execution. 1: Sets the PC break after instruction execution.
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Section 41 User Break Controller (UBC)
Bit 0
Bit Name BIE
Initial Value 0
R/W R/W
Description Break Enable Specifies whether or not to request a break when the match condition is satisfied for the channel. 0: Does not request a break. 1: Requests a break.
41.2.3
Match Address Setting Registers 0 and 1 (CAR0 and CAR1)
CAR0 and CAR1 are readable/writable 32-bit registers specifying the virtual address to be included in the break conditions for channels 0 and 1, respectively. * CAR0
Bit : Initial value : R/W: Bit : Initial value : R/W: 31 30 29 28 27 26 25 24 CA R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 CA R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 23 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name CA
Initial Value Undefined
R/W R/W
Description Compare Address Specifies the address to be included in the break conditions. When the operand bus has been specified using the CBR0 register, specify the SAB address in CA[31:0].
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Section 41 User Break Controller (UBC)
* CAR1
Bit : Initial value : R/W: Bit : Initial value : R/W: 31 30 29 28 27 26 25 24 CA R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 CA R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 23 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name CA
Initial Value Undefined
R/W R/W
Description Compare Address Specifies the address to be included in the break conditions. When the operand bus has been specified using the CBR1 register, specify the SAB address in CA[31:0].
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Section 41 User Break Controller (UBC)
41.2.4
Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)
CMAR0 and CMAR1 are readable/writable 32-bit registers which specify the bits to be masked among the address bits specified by using the match address setting register of the corresponding channel. (Set the bits to be masked to 1.) * CAMR0
Bit : Initial value : R/W: Bit : Initial value : R/W: 31 30 29 28 27 26 25 24 23 CAM R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 CAM R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name CAM
Initial Value Undefined
R/W R/W
Description Compare Address Mask Specifies the bits to be masked among the address bits which are specified using the CAR0 register. (Set the bits to be masked to 1.) 0: Address bits CA[n] are included in the break condition. 1: Address bits CA[n] are masked and not included in the break condition. [n] = any values from 31 to 0
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Section 41 User Break Controller (UBC)
* CAMR1
Bit : Initial value : R/W: Bit : Initial value : R/W: 31 30 29 28 27 26 25 24 23 CAM R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 CAM R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name CAM
Initial Value Undefined
R/W R/W
Description Compare Address Mask Specifies the bits to be masked among the address bits which are specified using the CAR1 register. (Set the bits to be masked to 1.) 0: Address bits CA[n] are included in the break condition. 1: Address bits CA[n] are masked and not included in the break condition. [n] = any values from 31 to 0
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Section 41 User Break Controller (UBC)
41.2.5
Match Data Setting Register 1 (CDR1)
CDR1 is a readable/writable 32-bit register which specifies the data value to be included in the break conditions for channel 1.
Bit : Initial value : R/W: Bit : Initial value : R/W: 31 30 29 28 27 26 25 24 CD R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 CD R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 23 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name CD
Initial Value Undefined
R/W R/W
Description Compare Data Value Specifies the data value to be included in the break conditions. When the operand bus has been specified using the CBR1 register, specify the SDB data value in CD[31:0].
Table 41.3 Settings for Match Data Setting Register
Bus and Size Selected Using CBR1 CD[31:24] Operand bus (byte) Operand bus (word) Don't care Don't care CD[23:16] Don't care Don't care CD[15:8] Don't care SDB15 to SDB8 CD[7:0] SDB7 to SDB0 SDB7 to SDB0 SDB7 to SDB0
Operand bus (longword) SDB31 to SDB24 SDB23 to SDB16 SDB15 to SDB8
Notes: 1. If the data value is included in the match conditions, be sure to specify the operand size. 2. The OCBI instruction is handled as longword write access without the data value, and the PREF, OCBP, and OCBWB instructions are handled as longword read access without the data value. Therefore, do not include the data value in the match conditions for these instructions. 3. If the quadword access is specified and the data value is included in the match conditions, the upper and lower 32 bits of 64-bit data are each compared with the contents of both the match data setting register and match data mask setting register.
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Section 41 User Break Controller (UBC)
41.2.6
Match Data Mask Setting Register 1 (CDMR1)
CDMR1 is a readable/writable 32-bit register which specifies the bits to be masked among the data value bits specified using the match data setting register. (Set the bits to be masked to 1.)
Bit : Initial value : R/W: Bit : Initial value : R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDM R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 CDM R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0
Bit 31 to 0
Bit Name CDM
Initial Value Undefined
R/W R/W
Description Compare Data Value Mask Specifies the bits to be masked among the data value bits specified using the CDR1 register. (Set the bits to be masked to 1.) 0: Data value bits CD[n] are included in the break condition. 1: Data value bits CD[n] are masked and not included in the break condition. [n] = any values from 31 to 0
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Section 41 User Break Controller (UBC)
41.2.7
Execution Count Break Register 1 (CETR1)
CETR1 is a readable/writable 32-bit register which specifies the number of the channel hits before a break occurs. A maximum value of 212 - 1 can be specified. When the execution count value is included in the match conditions by using the match condition setting register, the value of this register is decremented by one every time the channel is hit. When the channel is hit after the register value reaches H'001, a break occurs.
Bit : Initial value : R/W: Bit : Initial value : R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 26 0 R 10 25 0 R 9 24 0 R 8 23 0 R 7 22 0 R 6 CET R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
Bit
Initial Bit Name Value All 0
R/W R
Description Reserved For read/write in this bit, refer to General Precautions on Handling of Product.
31 to 12 --
11 to 0
CET
Undefined R/W
Execution Count Specifies the execution count to be included in the break conditions.
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Section 41 User Break Controller (UBC)
41.2.8
Channel Match Flag Register (CCMFR)
CCMFR is a readable/writable 32-bit register which indicates whether or not the match conditions have been satisfied for each channel. When a channel match condition has been satisfied, the corresponding flag bit is set to 1. To clear the flags, write the data containing value 0 for the bits to be cleared and value 1 for the other bits to this register. (The logical AND between the value which has been written and the current register value is actually written to the register.) Sequential operation using multiple channels is available by using these match flags.
Bit : Initial value : R/W: Bit : Initial value : R/W:
31
0 R 15
0 R
30
0 R 14
0 R
29
0 R 13
0 R
28
0 R 12
0 R
27
0 R 11
0 R
26
0 R 10
0 R
25
0 R 9
0 R
24
0 R 8
0 R
23
0 R 7
0 R
22
0 R 6
0 R
21
0 R 5
0 R
20
0 R 4
0 R
19
0 R 3
0 R
18
0 R 2
0 R
17
0 R 1 MF1 0 R/W
16 0 R
0
MF0 0 R/W
Bit 31 to 2
Bit Name --
Initial Value All 0
R/W R
Description Reserved For read/write in this bit, refer to General Precautions on Handling of Product.
1
MF1
0
R/W
Channel 1 Condition Match Flag This flag is set to 1 when the channel 1 match condition has been satisfied. To clear the flag, write 0 to this bit. 0: Channel 1 match condition has not been satisfied. 1: Channel 1 match condition has been satisfied.
0
MF0
0
R/W
Channel 0 Condition Match Flag This flag is set to 1 when the channel 0 match condition has been satisfied. To clear the flag, write 0 to this bit. 0: Channel 0 match condition has not been satisfied. 1: Channel 0 match condition has been satisfied.
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Section 41 User Break Controller (UBC)
41.2.9
Break Control Register (CBCR)
CBCR is a readable/writable 32-bit register which specifies whether or not to use the user break debugging support function. For details on the user break debugging support function, refer to section 41.4, User Break Debugging Support Function.
Bit : Initial value : R/W: Bit : Initial value : R/W:
31
0 R 15
0 R
30
0 R 14
0 R
29
0 R 13
0 R
28
0 R 12
0 R
27
0 R 11
0 R
26
0 R 10
0 R
25
0 R 9
0 R
24
0 R 8
0 R
23
0 R 7
0 R
22
0 R 6
0 R
21
0 R 5
0 R
20
0 R 4
0 R
19
0 R 3
0 R
18
0 R 2
0 R
17
0 R 1
0 R
16 0 R
0
UBDE 0 R/W
Bit 31 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved For read/write in this bit, refer to General Precautions on Handling of Product.
0
UBDE
0
R/W
User Break Debugging Support Function Enable Specifies whether or not to use the user break debugging support function. 0: Does not use the user break debugging support function. 1: Uses the user break debugging support function.
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Section 41 User Break Controller (UBC)
41.3
41.3.1
Operation Description
Definition of Words Related to Accesses
"Instruction fetch" refers to an access in which an instruction is fetched. For example, fetching the instruction located at the branch destination after executing a branch instruction is an instruction access. "Operand access" refers to any memory access accompanying execution of an instruction. For example, accessing an address (PC + disp x 2 + 4) in the instruction MOV.W@(disp,PC),Rn is an operand access. "Data" is used in contrast to "address". All types of operand access are classified into read or write access. Special care must be taken in using the following instructions. * PREF, OCBP, and OCBWB: Instructions for a read access * MOVCA.L and OCBI: Instructions for a write access * TAS.B: Instruction for a single read access or a single write access The operand access accompanying the PREF, OCBP, OCBWB, and OCBI instructions is access without the data value; therefore, do not include the data value in the match conditions for these instructions. The operand size should be defined for all types of operand access. Available operand sizes are byte, word, longword, and quadword. For operand access accompanying the PREF, OCBP, OCBWB, MOVCA.L, and OCBI instructions, the operand size is defined as longword.
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Section 41 User Break Controller (UBC)
41.3.2
User Break Operation Sequence
The following describes the sequence from when the break condition is set until the user break exception handling is initiated. 1. Specify the operand size, bus, instruction fetch/operand access, and read/write as the match conditions using the match condition setting register (CBR0 or CBR1). Specify the break address using the match address setting register (CAR0 or CAR1), and specify the address mask condition using the match address mask setting register (CAMR0 or CAMR1). To include the ASID in the match conditions, set the AIE bit in the match condition setting register and specify the ASID value by the AIV bit in the same register. To include the data value in the match conditions, set the DBE bit in the match condition setting register; specify the break data using the match data setting register (CDR1); and specify the data mask condition using the match data mask setting register (CDMR1). To include the execution count in the match conditions, set the ETBE bit of the match condition setting register; and specify the execution count using the execution count break register (CETR1). To use the sequential break, set the MFE bit of the match condition setting register; and specify the number of the first channel using the MFI bit. 2. Specify whether or not to request a break when the match condition is satisfied and the break timing when the match condition is satisfied as a result of fetching the instruction using the match operation setting register (CRR0 or CRR1). After having set all the bits in the match condition setting register except the CE bit and the other necessary registers, set the CE bit and read the match condition setting register again. This ensures that the set values in the control registers are valid for the subsequent instructions immediately after reading the register. Setting the CE bit of the match condition setting register in the initial state after reset via the control registers may cause an undesired break. 3. When the match condition has been satisfied, the corresponding condition match flag (MF1 or MF0) in the channel match flag register (CCMFR) is set. A break is also requested to the CPU according to the set values in the match operation setting register (CRR0 or CRR1). The CPU operates differently according to the BL bit value of the SR register: when the BL bit is 0, the CPU accepts the break request and executes the specified exception handling; and when the BL bit is 1, the CPU does not execute the exception handling. 4. The match flags (MF1 and MF0) can be used to confirm whether or not the corresponding match condition has been satisfied. Although the flag is set when the condition is satisfied, it is not cleared automatically; therefore, write 0 to the flag bit by issuing a memory store instruction to the channel match flag register (CCMFR) in order to use the flag again. 5. Breaks may occur virtually at the same time for channels 0 and 1. In this case, only one break request is sent to the CPU; however, the two condition match flags corresponding to these breaks may be set.
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Section 41 User Break Controller (UBC)
6. While the BL bit in the SR register is 1, no break requests are accepted. However, whether or not the condition has been satisfied is determined. When the condition is determined to be satisfied, the corresponding condition match flag is set. 7. If the sequential break conditions are set, the condition match flag is set every time the match conditions are satisfied for each channel. When the conditions have been satisfied for the first channel in the sequence but not for the second channel in the sequence, clear the condition match flag for the first channel in the sequence in order to release the first channel in the sequence from the match state.
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Section 41 User Break Controller (UBC)
41.3.3
Instruction Fetch Cycle Break
1. If the instruction fetch cycle is set in the match condition setting register (CBR0 or CBR1), the instruction fetch cycle is handled as a match condition. To request a break upon satisfying the match condition, set the BIE bit in the match operation setting register (CRR0 or CRR1) of the corresponding channel. Either before or after executing the instruction can be selected as the break timing according to the PCB bit value. If the instruction fetch cycle is specified as a match condition, be sure to clear the LSB to 0 in the match address setting register (CAR0 or CAR1); otherwise, no break occurs. 2. If pre-instruction-execution break is specified for the instruction fetch cycle, the break is requested when the instruction is fetched and determined to be executed. Therefore, this function cannot be used for the instructions which are fetched through overrun (i.e., the instructions fetched during branching or making transition to the interrupt routine but not executed). For priorities of pre-instruction-execution break and the other exceptions, refer to section 5, Exception Handling. If pre-instruction-execution break is specified for the delayed slot of the delayed branch instruction, the break is requested before the delayed branch instruction is executed. However, do not specify pre-instruction-execution break for the delayed slot of the RTE instruction. 3. If post-instruction-execution break is specified for the instruction fetch cycle, the break is requested after the instruction which satisfied the match condition has been executed and before the next instruction is executed. Similar to pre-instruction-execution break, this function cannot be used for the instructions which are fetched through overrun. For priorities of post-instruction-execution break and the other exceptions, refer to section 5, Exception Handling. If post-instruction-execution break is specified for the delayed branch instruction and its delayed slot, the break does not occur until the first instruction at the branch destination. 4. If the instruction fetch cycle is specified as the channel 1 match condition, the DBE bit of match condition setting register CBR1 becomes invalid, the settings of match data setting register CDR1 and match data mask setting register CDMR1 are ignored. Therefore, the data value cannot be specified for the instruction fetch cycle break.
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Section 41 User Break Controller (UBC)
41.3.4
Operand Access Cycle Break
1. Table 41.4 shows the relation between the operand sizes specified using the match condition setting register (CBR0 or CBR1) and the address bits to be compared for the operand access cycle break. Table 41.4 Relation between Operand Sizes and Address Bits to be Compared
Selected Operand Size Quadword Longword Word Byte Operand size is not included in the match conditions Address Bits to be Compared Address bits A31 to A3 Address bits A31 to A2 Address bits A31 to A1 Address bits A31 to A0 Address bits A31 to A3 for quadword access Address bits A31 to A2 for longword access Address bits A31 to A1 for word access Address bits A31 to A0 for byte access
The above table means that if address H'00001003 is set in the match address setting register (CAR0 or CAR1), for example, the match condition is satisfied for the following access cycles (assuming that all the other conditions are satisfied): Longword access to address H'00001000 Word access to address H'00001002 Byte access to address H'00001003 2. When the data value is included in the channel 1 match conditions: If the data value is included in the match conditions, be sure to select the quadword, longword, word, or byte as the operand size using the operand size select bit (SZ) of the match condition setting register (CBR1), and also set the match data setting register (CDR1) and the match data mask setting register (CDMR1). With these settings, the match condition is satisfied when both of the address and data conditions are satisfied. The data value and mask control for byte access, word access, and longword access should be set in bits 7 to 0, 15 to 0, and 31 to 0 in the bits CDR1 and CDMR1, respectively. For quadword access, 64-bit data is divided into the upper and lower 32-bit data units, and each unit is independently compared with the specified condition. When either the upper or lower 32-bit data unit satisfies the match condition, the match condition for the 64-bit data is determined to be satisfied.
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Section 41 User Break Controller (UBC)
3. The operand access accompanying the PREF, OCBP, OCBWB, and OCBI instructions are access without the data value; therefore, if the data value is included in the match conditions for these instructions, the match conditions will never be satisfied. 4. If the operand bus is selected, a break occurs after executing the instruction which has satisfied the conditions and immediately before executing the next instruction. However, if the data value is included in the match conditions, a break may occur after executing several instructions after the instruction which has satisfied the conditions; therefore, it is impossible to identify the instruction causing the break. If such a break has occurred for the delayed branch instruction or its delayed slot, the break does not occur until the first instruction at the branch destination. However, do not specify the operand break for the delayed slot of the RTE instruction. And if the data value is included in the match conditions, it is not allowed to set the break for the preceding the RTE instruction by one to six instructions.
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Section 41 User Break Controller (UBC)
41.3.5
Sequential Break
1. Sequential break conditions can be specified by setting the MFE and MFI bits in the match condition setting registers (CBR0 and CBR1). (Sequential break involves two cases such that channel 0 break condition is satisfied then channel 1 break condition is satisfied, and vice versa.) To use the sequential break function, clear the MFE bit of the match condition setting register and the BIE bit of the match operation setting register of the first channel in the sequence, and set the MFE bit and specify the number of the second channel in the sequence using the MFI bit in the match condition setting register of the second channel in the sequence. If the sequential break condition is set, the condition match flag is set every time the match condition is satisfied for each channel. When the condition has been satisfied for the first channel in the sequence but not for the second channel in the sequence, clear the condition match flag for the first channel in the sequence in order to release the first channel in the sequence from the match state. 2. For channel 1, the execution count break condition can also be included in the sequential break conditions. 3. If the match conditions for the first and second channels in the sequence are satisfied within a significantly short time, sequential operation may not be guaranteed in some cases, as shown below. * When the Match Condition is Satisfied at the Instruction Fetch Cycle for Both the First and Second Channels in the Sequence:
Instruction B is 0 instruction after instruction A Equivalent to setting the same addresses; do not use this setting.
Instruction B is one instruction after instruction A Sequential operation is not guaranteed. Instruction B is two or more instructions after instruction A Sequential operation is guaranteed.
* When the match condition is satisfied at the instruction fetch cycle for the first channel in the sequence whereas the match condition is satisfied at the operand access cycle for the second channel in the sequence:
Instruction B is 0 or one instruction after instruction A Instruction B is two or more instructions after instruction A Sequential operation is not guaranteed. Sequential operation is guaranteed.
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Section 41 User Break Controller (UBC)
* When the match condition is satisfied at the operand access cycle for the first channel in the sequence whereas the match condition is satisfied at the instruction fetch cycle for the second channel in the sequence:
Instruction B is 0 to five instructions after instruction A Instruction B is six or more instructions after instruction A Sequential operation is not guaranteed. Sequential operation is guaranteed.
* When the match condition is satisfied at the operand access cycle for both the first and second channels in the sequence:
Instruction B is 0 to five instructions after instruction A Instruction B is six or more instructions after instruction A Sequential operation is not guaranteed. Sequential operation is guaranteed.
41.3.6
Program Counter Value to be Saved
When a break has occurred, the address of the instruction to be executed when the program restarts is saved in the SPC then the exception handling state is initiated. A unique instruction causing a break can be identified unless the data value is included in the match conditions. 1. When the instruction fetch cycle (before instruction execution) is specified as the match condition: The address of the instruction which has satisfied the match conditions is saved in the SPC. The instruction which has satisfied the match conditions is not executed, but a break occurs instead. However, if the match conditions are satisfied for the delayed slot instruction, the address of the delayed branch instruction is saved in the SPC. 2. When the instruction fetch cycle (after instruction execution) is specified as the match condition: The address of the instruction immediately after the instruction which has satisfied the match conditions is saved in the SPC. The instruction which has satisfied the match conditions is executed, then a break occurs before the next instruction. If the match conditions are satisfied for the delayed branch instruction or its delayed slot, these instructions are executed and the address of the branch destination is saved in the SPC.
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Section 41 User Break Controller (UBC)
3. When the operand access (address only) is specified as the match condition: The address of the instruction immediately after the instruction which has satisfied the break conditions is saved in the SPC. The instruction which has satisfied the match conditions are executed, then a break occurs before the next instruction. However, if the conditions are satisfied for the delayed slot, the address of the branch destination is saved in the SPC. 4. When the operand access (address and data) is specified as the match condition: If the data value is added to the match conditions, the instruction which has satisfied the match conditions is executed. A user break occurs before executing an instruction that is one through six instructions after the instruction which has satisfied the match conditions. The address of the instruction is saved in the SPC; thus, it is impossible to identify exactly where a break will occur. If the conditions are satisfied for the delayed slot instruction, the address of the branch destination is saved in the SPC. If a branch instruction follows the instruction which has satisfied the match conditions, a break may occur after the delayed instruction and delayed slot are executed. In this case, the address of the branch destination is also saved in the SPC.
41.4
User Break Debugging Support Function
By using the user break debugging support function, the branch destination address can be modified when the CPU accepts the user break request. Specifically, setting the UBDE bit of break control register CBCR to 1 allows branching to the address indicated by DBR instead of branching to the address indicated by the [VBR + offset]. Figure 41.2 shows the flowchart of the user break debugging support function.
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Section 41 User Break Controller (UBC)
Exception/interrupt is generated
Hardware operations
SPC PC SSR SR SR.BL B'1 SR.MD B'1 SR.RB B'1 Exception Trap
Exception/interrupt/trap? Interrupt
EXPEVT Exception code
INTEVT Interrupt code
EXPEVT H'160 TRA TRAPA (imm)
SGR R15
No Yes
Reset exception? No
Yes
(CBCR.UBDE == 1) && (user break)?
PC DBR
PC VBR + vector offset
PC H'A000 0000
Debugging program R15 SGR (STC instruction)
Exception handling routine
Execute RTE instruction PC SPC SR SSR
Exception operation ends
Figure 41.2 Flowchart of User Break Debugging Support Function
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Section 41 User Break Controller (UBC)
41.5
(1)
User Break Examples
Match Conditions are Specified for an Instruction Fetch Cycle
* Example 1-1 Register settings: CBR0 = H'00000013 / CRR0 = H'00002003 / CAR0 = H'00000404 / CAMR0 = H'00000000 / CBR1 = H'00000013 / CRR1 = H'00002001 / CAR1 = H'00008010 / CAMR1 = H'00000006 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 = H'00000000 / CBCR = H'00000000 Specified conditions: Independent for channels 0 and 1 Channel 0 Address: H'00000404 / Address mask: H'00000000 Bus cycle: Instruction fetch (after executing the instruction) ASID is not included in the conditions. Channel 1: Address: H'00008010 / Address mask: H'00000006 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Instruction fetch (before executing instruction) ASID, data values, and execution count are not included in the conditions. With the above settings, the user break occurs after executing the instruction at address H'00000404 or before executing the instruction at address H'00008010 to H'00008016. * Example 1-2 Register settings: CBR0 = H'40800013 / CRR0 = H'00002000 / CAR0 = H'00037226 / CAMR0 = H'00000000 / CBR1 = H'C0700013 / CRR1 = H'00002001 / CAR1 = H'0003722E / CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 = H'00000000 / CBCR = H'00000000 Specified conditions: Channel 0 Channel1 sequential mode Channel 0 Address: H'00037226 / Address mask: H'00000000 / ASID: H'80 Bus cycle: Instruction fetch (before executing the instruction) Channel 1 Address: H'0003722E / Address mask: H'00000000 / ASID: H'70 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Instruction fetch (before executing the instruction) Data values and execution count are not included in the conditions.
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Section 41 User Break Controller (UBC)
With the above settings, the user break occurs after executing the instruction at address H'00037226 where ASID is H'80 before executing the instruction at address H'0003722E where ASID is H'70. * Example 1-3 Register settings: CBR0 = H'00000013 / CRR0 = H'00002001 / CAR0 = H'00027128 / CAMR0 = H'00000000 / CBR1 = H'00000013 / CRR1 = H'00002001 / CAR1 = H'00031415 / CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 = H'00000000 / CBCR = H'00000000 Specified conditions: Independent for channels 0 and 1 Channel 0 Address: H'00027128 / Address mask: H'00000000 Bus cycle: Instruction fetch (before executing the instruction) ASID is not included in the conditions. Channel 1 Address: H'00031415 / Address mask: H'00000000 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Instruction fetch (before executing the instruction) ASID, data values, and execution count are not included in the conditions. With the above settings, the user break occurs for channel 0 before executing the instruction at address H'00027128. No user break occurs for channel 1 since the instruction fetch is executed only at even addresses. * Example 1-4 Register settings: CBR0 = H'40800013 / CRR0 = H'00002000 / CAR0 = H'00037226 / CAMR0 = H'00000000 / CBR1 = H'C0700013 / CRR1 = H'00002001 / CAR1 = H'0003722E / CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 = H00000000 / CBCR = H'00000000 Specified conditions: Channel 0 Channel 1 sequential mode Channel 0 Address: H'00037226 / Address mask: H'00000000 / ASID: H'80 Bus cycle: Instruction fetch (before executing the instruction) Channel 1 Address: H'0003722E / Address mask: H'00000000 / ASID: H'70 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Instruction fetch (before executing the instruction) Data values and execution count are not included in the conditions.
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Section 41 User Break Controller (UBC)
With the above settings, the user break occurs after executing the instruction at address H'00037226 where ASID is H'80 and before executing the instruction at address H'0003722E where ASID is H'70. * Example 1-5 Register settings: CBR0 = H'00000013 / CRR0 = H'00002001 / CAR0 = H'00000500 / CAMR0 = H'00000000 / CBR1 = H'00000813 / CRR1 = H'00002001 / CAR1 = H'00001000 / CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 = H'00000005 / CBCR = H'00000000 Specified conditions: Independent for channels 0 and 1 Channel 0 Address: H'00000500 / Address mask: H'00000000 Bus cycle: Instruction fetch (before executing the instruction) ASID is not included in the conditions. Channel 1 Address: H'00001000 / Address mask: H'00000000 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000005 Bus cycle: Instruction fetch (before executing the instruction) Execution count: 5 ASID and data values are not included in the conditions. With the above settings, the user break occurs for channel 0 before executing the instruction at address H'00000500. The user break occurs for channel 1 after executing the instruction at address H'00001000 four times; before executing the instruction five times. * Example 1-6 Register settings: CBR0 = H'40800013 / CRR0 = H'00002003 / CAR0 = H'00008404 / CAMR0 = H'00000FFF / CBR1 = H'40700013 / CRR1 = H'00002001 / CAR1 = H'00008010 / CAMR1 = H'00000006 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 = H'00000000 / CBCR = H'00000000 Specified conditions: Independent for channels 0 and 1 Channel 0 Address: H'00008404 / Address mask: H'00000FFF / ASID: H'80 Bus cycle: Instruction fetch (after executing the instruction) Channel 1 Address: H'00008010 / Address mask: H'00000006 / ASID: H'70 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Instruction fetch (before executing the instruction)
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Section 41 User Break Controller (UBC)
Data values and execution count are not included in the conditions. With the above settings, the user break occurs after executing the instruction at address H'00008000 to H'00008FFE where ASID is H'80 or before executing the instruction at address H'00008010 to H'00008016 where ASID is H'70. (2) Match Conditions are Specified for an Operand Access Cycle
* Example 2-1 Register settings: CBR0 = H'40800023 / CRR0 = H'00002001 / CAR0 = H'00123456 / CAMR0 = H'00000000 / CBR1 = H'4070A025 / CRR1 = H'00002001 / CAR1 = H'000ABCDE / CAMR1 = H'000000FF / CDR1 = H'0000A512 / CDMR1 = H'00000000 / CETR1 = H'00000000 / CBCR = H'00000000 Specified conditions: Independent for channels 0 and 1 Channel 0 Address: H'00123456 / Address mask: H'00000000 / ASID: H'80 Bus cycle: Operand bus, operand access, and read (operand size is not included in the conditions.) Channel 1 Address: H'000ABCDE / Address mask: H'000000FF / ASID: H'70 Data: H'0000A512 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Operand bus, operand access, write, and word size Execution count is not included in the conditions. With these settings, the user break occurs for channel 0 for the following accesses: longword read access to address H'000123454, word read access to address H'000123456, byte read access to address H'000123456 where ASID is H'80. The user break occurs for channel 1 when word H'A512 is written to address H'000ABC00 to H'000ABCFE where ASID is H'70.
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Section 41 User Break Controller (UBC)
41.6
Usage Notes
1. A desired break may not occur between the time when the instruction for rewriting the UBC register is executed and the time when the written value is actually reflected on the register. After the UBC register is updated, execute one of the following three methods. A. Read the updated UBC register, and execute a branch using the RTE instruction. (It is not necessary that a branch using the RTE instruction is next to a reading UBC register.) B. Execute the ICBI instruction for any address (including non-cacheable area). (It is not necessary that the ICBI instruction is next to a reading UBC register.) C. Set 0(initial value) to IRMCR.R1 before updating the UBC register and update with following sequence. a. Write the UBC register. b. Read the UBC register which is updated at 1. c. Write the value which is read at 2 to the UBC register. Note: When two or more UBC registers are updated, executing these methods at each updating the UBC registers is not necessary. At only last updating the UBC register, execute one of these methods. 2. The PCB bit of the CRR0 and CRR1 registers is valid only when the instruction fetch is specified as the match condition. 3. If the sequential break conditions are set, the sequential break conditions are satisfied when the conditions for the first and second channels in the sequence are satisfied in this order. Therefore, if the conditions are set so that the conditions for channels 0 and 1 should be satisfied simultaneously for the same bus cycle, the sequential break conditions will not be satisfied, causing no break. 4. For the SLEEP instruction, do not allow the post-instruction-execution break where the instruction fetch cycle is the match condition. For the instructions preceding the SLEEP instruction by one to five instructions, do not allow the break where the operand access is the match condition. 5. If the user break and other exceptions occur for the same instruction, they are determined according to the specified priority. For the priority, refer to section 5, Exception Handling. If the exception having the higher priority occurs, the user break does not occur. The pre-instruction-execution break is accepted prior to any other exception.
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Section 41 User Break Controller (UBC)
If the post-instruction-execution break and data access break have occurred simultaneously with the re-execution type exception (including the pre-instruction-execution break) having a higher priority, only the re-execution type exception is accepted, and no condition match flags are set. When the exception handling has finished thus clearing the exception source, and when the same instruction has been executed again, the break occurs setting the corresponding flag. If the post-instruction-execution break or operand access break has occurred simultaneously with the completion-type exception (TRAPA) having a higher priority, then no user break occurs; however, the condition match flag is set. 6. When conditions have been satisfied simultaneously and independently for channels 0 and 1, resulting in identical SPC values for both of the breaks, the user break occurs only once. However, the condition match flags are set for both channels. For example, Instruction at address 110 (post-instruction-execution break for instruction fetch for channel 0) SPC = 112, CCMFR.MF0 = 1 Instruction at address 112 (pre-instruction-execution break for instruction fetch for channel 1) SPC = 112, CCMFR.MF1 = 1 7. It is not allowed to set the pre-instruction-execution break or the operand break in the delayed slot instruction of the RTE instruction. And if the data value is included in the match conditions of the operand break, do not set the break for the preceding the RTE instruction by one to six instructions. 8. If the re-execution type exception and the post-instruction-execution break are in conflict for the instruction requiring two or more execution states, then the re-execution type exception occurs. Here, the CCMFR.MF0 (or CCMFR.MF1) bit may or may not be set to 1 when the break conditions have been satisfied.
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Section 42 User Debugging Interface (H-UDI)
Section 42 User Debugging Interface (H-UDI)
The H-UDI is a serial interface which conforms to the JTAG (IEEE 1149.4: IEEE Standard Test Access Port and Boundary-Scan Architecture) standard. The H-UDI is also used for emulator connection.
42.1
Features
The H-UDI is a serial interface which conforms to the JTAG standard. The H-UDI is also used for emulator connection. When using an emulator, H-UDI functions should not be used. Refer to the appropriate emulator users manual for the method of connecting the emulator. The H-UDI has six pins: TCK, TMS, TDI, TDO, TRST, and ASEBRK/BRKACK. The pin functions except ASEBRK/BRKACK and serial communications protocol conform to the JTAG standard. This LSI has additional six pins for emulator connection: (AUDSYNC, AUDCK, and AUDATA3 to AUDATA0). These six pins for emulator are multiplexed with on-chip modules. And the H-UDI has one chip-mode setting pin: (MPMD). The H-UDI has two TAP controller blocks; one is for the boundary-scan test and another is H-UDI function except the boundary-scan test. The H-UDI initial state is for the boundary scan after power-on or TRST asserted. It is necessary to set H-UDI switchover command to use the H-UDI function. And the CPU cannot access the boundary scan TAP controller. Figure 42.1 shows a block diagram of the H-UDI. The H-UDI has the TAP (Test Access Port) controller and four registers (SDBPR, SDBSR, SDIR, and SDINT). SDBPR supports the JTAG bypass mode, SDBSR supports the JTAG boundary scan mode, SDIR is used for commands, and SDINT is used for H-UDI interrupts. SDIR is directly accessed from the TDI and TDO pins. The TAP controller, control registers and boundary scan TAP controller are initialized by driving the TRST pin low or by applying the TCK signal for five or more clock cycles with the TMS pin set to 1. This initialization sequence is independent of the reset pin for this LSI. Other circuits are initialized by a normal reset.
Rev. 1.00 Oct. 01, 2007 Page 1797 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Interrupt/reset etc ASEBRK/BRKACK Break controller
Boundary-scan TAP controller
SDBSR SDBPR
TCK TMS TRST
Pin multiplexer
TAP controller
Decoder
TDI
SDIR
TDO
SDINT
[Legend] SDBPR: SDBSR: SDINT: SDIR:
Bypass register Boundary scan register Interrupt source register Instruction register
Figure 42.1 H-UDI Block Diagram
Rev. 1.00 Oct. 01, 2007 Page 1798 of 1956 REJ09B0256-0100
Peripheral bus
Shift register
Section 42 User Debugging Interface (H-UDI)
42.2
Input/Output Pins
Table 42.1 shows the pin configuration for the H-UDI. Table 42.1 Pin Configuration
Pin Name TCK Function Clock I/O Input Description
Functions as the serial clock input pin stipulated in the JTAG standard. Data input to the H-UDI via the TDI pin or data Output via the TDO pin is performed in synchronization with this signal. Mode Select Input Changing this signal in synchronization with the TCK signal determines the significance of data input via the TDI pin. Its protocol conforms to the JTAG standard (IEEE standard 1149.1).
When Not in Use Open*1
TMS
Mode
Input
Open*1
TRST*2
Reset
Input
Fixed to ground or This signal is received asynchronously with a TCK signal. Asserting this signal resets the JTAG interface connected to the PRESET circuit. When a power is supplied, the TRST pin pin*3 should be asserted for a given period regardless of
H-UDI Reset Input whether or not the JTAG function is used, which differs from the JTAG standard.
TDI
Data input
Input
Data Input Data is sent to the H-UDI by changing this signal in synchronization with the TCK signal.
Open*1
TDO
Data output Output Data Output
Data is read from the H-UDI in synchronization with the TCK signal.
Open
ASEBRK/ BRKACK
Emulator
I/O
Pins for an emulator
Open*1 Open
AUDSYNC, Emulator AUDCK, AUDATA3 to AUDATA0 MPMD Chip-mode
Output Pins for an emulator
Input
Selects the operation mode of this LSI, whether emulation support mode (Low level) or LSI operation mode (High level).
Open
Notes: 1. This pin is pulled up in this LSI. When using interrupts or resets via the H-UDI or emulator, the use of external pull-up resistors will not cause any problem. 2. When using interrupts or resets via the H-UDI or emulator, the TRST pin should be designed so that it can be controlled independently and can be controlled to retain low level while the PRESET pin is asserted at a power-on reset.
Rev. 1.00 Oct. 01, 2007 Page 1799 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
3. This pin should be connected to ground, the PRESET, or another pin which operates in the same manner as the PRESET pin. However, when connected to a ground pin, the following problem occurs. Since the TRST pin is pulled up within this LSI, a weak current flows when the pin is externally connected to ground pin. The value of the current is determined by a resistance of the pull-up MOS for the port pin. Although this current does not affect the operation of this LSI, it consumes unnecessary power.
The TCK clock or the CPG of this LSI should be set to ensure that the frequency of the TCK clock is less than the peripheral-clock frequency of this LSI.
42.3
Boundary Scan TAP Controllers (IDCODE, EXTEST, SAMPLE/PRELOAD, and BYPASS)
The H-UDI contains two separate TAP controllers: one for controlling the boundary-scan function and another for controlling the H-UDI reset and interrupt functions. Assertion of TRST, for example at power-on reset, activates the boundary-scan TAP controller and enables the boundaryscan function prescribed in the JTAG standards. Executing a switchover command to the H-UDI allows usage of the H-UDI reset and H-UDI interrupts. This LSI, however, has the following limitations: * Clock-related pins (EXTAL, XTAL, EXTAL2, and XTAL2) are out of the scope of the boundary-scan test. * Reset-related pins (PRESET, MRESET) are out of the scope of the boundary-scan test. * H-UDI-related pins (TCK, TDI, TDO, TMS, TRST and MPMD) are out of the scope of the boundary-scan test. * DDRIF-related pins are out of the scope of the boundary-scan test * XRTCTBI, USBP, USBM, DA0, DA1, and AN0 to AN3 pins are out of the scope of the boundary-scan test * During the boundary scan (IDCODE, EXTEST, SAMPLE/PRELOAD, BYPASS, and H-UDI switchover command), the maximum TCK signal frequency is 2 MHz. * The external controller has 8-bit access to the boundary-scan TAP controller via the H-UDI. Note: During the boundary scan, the PRESET pin should be fixed high-level. Table 42.2 shows the commands supported by the boundary-scan TAP controller.
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Section 42 User Debugging Interface (H-UDI)
Table 42.2 Commands Supported by Boundary-Scan TAP Controller
Bit 7 0 1 0 0 0 Bit 6 1 1 0 1 0 Bit 5 0 1 0 0 0 Bit 4 1 1 0 0 0 Bit 3 0 1 0 0 1 Bit 2 1 1 0 0 0 Bit 1 0 1 0 0 0 Bit 0 1 1 0 0 0 Description IDCODE BYPASS EXTEST SAMPLE/PRELOAD H-UDI (switchover command) Setting prohibited
Other than above
TRST is asserted
H-UDI select command is input to boundary-scan TAP controller
H-UDI is used
TRST is asserted
TCK
External pins
TMS TRST TDI
H-UDI select command (B'00001000) (when Shift-IR state > 8 cycles, input of last 8 cycles is valid)
0
0
0
1
0
0
0
0
Boundary-scan TAP controller
Capture-IR
Test-Logic -Reset
Update-IR
Select-DR
Test-Logic -Reset Test-Logic -Reset
Run-Test -Idle
Select-IR
Status
Shift-IR
Run-Test-Idle
Switchover is determined at falling of first tck cycle after the boundary-scan TAP controller has entered the Run-Test/Idle state
H-UDI selection
Capture-IR
Select-DR
Test-Logic -Reset
Select-IR
Status
Run-Test-Idle
Shift-IR ---
Figure 42.2 Sequence for switching from Boundary-Scan TAP Controller to H-UDI
Rev. 1.00 Oct. 01, 2007 Page 1801 of 1956 REJ09B0256-0100
Run-Test -Idle
H-UDI
Run-Test -Idle
Exit1-IR
Section 42 User Debugging Interface (H-UDI)
42.4
Register Descriptions
The H-UDI has the following registers. Table 42.3 Register Configuration (1)
CPU Side Register Name Abbrev. R/W Area P4 1 Address* Area 7 Address*
1
Size
Initial 2 Value*
Instruction register Interrupt source register Boundary scan register Bypass register
SDIR SDINT SDBSR SDBPR
R R/W
H'FC11 0000 H'FC11 0018
H'1C11 0000 H'1C11 0018
16 16
H'0EFF H'0000
Notes: 1. The area P4 address is an address when accessing through area P4 in a virtual address space. The area 7 address is an address when accessing through area 7 in a physical space using the TLB. 2. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller initializes to these values.
Table 42.4 Register Configuration (2)
H-UDI Side Register Name Abbrev. R/W Size Initial Value*
1
Instruction register Interrupt source register Boundary scan register Bypass register Note:
SDIR SDINT SDBSR SDBPR
R/W W*3 R/W
32 32 1
H'FFFF FFFD (fixed value*2) H'0000 0000 Undefined
1. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller initializes to these values. 2. When reading via the H-UDI, the value is always H'FFFF FFFD. 3. Only 1 can be written to the LSB by the H-UDI interrupt command.
Table 42.5 Register Status in Each Processing State
Register Name Abbrev. Power-On Reset Manual Reset Sleep Standby
Instruction register
SDIR
H'0EFF H'0000
Retained Retained
Retained Retained
Retained Retained
Interrupt source register SDINT
Rev. 1.00 Oct. 01, 2007 Page 1802 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
42.4.1
Instruction Register (SDIR)
SDIR is a 16-bit read-only register that can be read from the CPU. Commands are set via the serial input (TDI). SDIR is initialized by TRST or in the Test-Logic-Reset state and can be written by the H-UDI irrespective of the CPU mode. Operation is not guaranteed when a reserved command is set to this register.
Bit: Initial value: R/W: 15 14 13 12
TI
11
10
9
8
7
6
5
4
3
2
1
0 1 R
0 R
0 R
0 R
0 R
1 R
1 R
1 R
0 R
1 R
1 R
1 R
1 R
1 R
1 R
1 R
Bit 15 to 8
Bit Name TI
Initial Value R/W 0000 1110 R
Description Test Instruction Bits 7 to 0 0110 xxxx : 0111 xxxx : 101x xxxx : 0000 1110: H-UDI reset negate H-UDI reset assert H-UDI interrupt Initial state
Other than above: Setting prohibited Note: Though H-UDI reset asserted, CPG, watchdog/reset and part of RTC registers are not initialized. 7 to 0 All 1 R Reserved These bits are always read as 1.
Rev. 1.00 Oct. 01, 2007 Page 1803 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
42.4.2
Interrupt Source Register (SDINT)
SDINT is a 16-bit register that can be read from or written to by the CPU. Specifying an H-UDI interrupt command in SDIR via H-UDI pin (Update-IR) sets the INTREQ bit to 1. While an HUDI interrupt command is set in SDIR, SDINT which is connected between the TDI and TDO pins can be read as a 32-bit register. In this case, the upper 16 bits will be 0 and the lower 16 bits represent the SDINT value. Only 0 can be written to the INTREQ bit by the CPU. While this bit is set to 1, an interrupt request will continue to be generated. This bit, therefore, should be cleared by the interrupt handling routine. It is initialized by TRST or in the Test-Logic-Reset state.
Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
INTREQ
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
Bit 15 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved For reading from or writing to this bit, see General Precautions on Handling of Product. Interrupt Request Indicates whether or not an interrupt by an H-UDI interrupt command has occurred. Clearing this bit to 0 by the CPU cancels an interrupt request. When writing 1 to this bit, the previous value is maintained.
0
INTREQ
0
R/W
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Section 42 User Debugging Interface (H-UDI)
42.4.3
Bypass Register (SDBPR)
SDBPR is a one-bit register that supports the J-TAG bypass mode. When the BYPASS command is set to the boundary scan TAP controller, the TDI and TDO are connected by way of SDBPR. This register cannot be accessed from the CPU regardless of the LSI mode. Though this register is not initialized by a power-on reset and the TRST pin asserted, initialized to 0 in the Capture-DR state. 42.4.4 Boundary Scan Register (SDBSR)
SDBSR is a shift register, located on the PAD, for controlling the input/Output pins, which supports the boundary scan mode of the JTAG standard. Using the EXTEST and SAMPLE/PRELOAD commands, a boundary-scan test complying with the JTAG standards (IEEE1149.1) can be carried out. This register cannot be accessed from the CPU regardless of the LSI mode. This register is not initialized by a power-on reset and the TRST pin asserted.
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Section 42 User Debugging Interface (H-UDI)
Table 42.6 SDBSR Configuration
Number Pin Name From TDI 517 516 515 514 513 512 511 510 509 508 507 506 505 504 503 502 501 500 499 498 497 496 495 494 493 492 491 490 489 BACK BACK BACK BREQ BREQ BREQ IOIS16/TMU_TCLK IOIS16/TMU_TCLK IOIS16/TMU_TCLK CE2A CE2A CE2A CE2B CE2B CE2B A25/EX_SIZE2 A25/EX_SIZE2 A25/EX_SIZE2 A24/EX_SIZE1 A24/EX_SIZE1 A24/EX_SIZE1 A23/EX_SIZE0 A23/EX_SIZE0 A23/EX_SIZE0 A22 A22 A22 A21 A21 OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL I/O*
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Section 42 User Debugging Interface (H-UDI)
Number 488 487 486 485 484 483 482 481 480 479 478 477 476 475 474 473 472 471 470 469 468 467 466 465 464 463 462 461 460 459 458 457
Pin Name A21 A20 A20 A20 A15 A15 A15 A14 A14 A14 A19 A19 A19 A18 A18 A18 A13 A13 A13 A12 A12 A12 A17 A17 A17 A16 A16 A16 A7 A7 A7 A6
I/O* INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT
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Section 42 User Debugging Interface (H-UDI)
Number 456 455 454 453 452 451 450 449 448 447 446 445 444 443 442 441 440 439 438 437 436 435 434 433 432 431 430 429 428 427 426 425
Pin Name A6 A6 A11 A11 A11 A10 A10 A10 A5 A5 A5 A4 A4 A4 A9 A9 A9 A8 A8 A8 A3 A3 A3 A2 A2 A2 A1 A1 A1 A0 A0 A0
I/O* CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT
Rev. 1.00 Oct. 01, 2007 Page 1808 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 424 423 422 421 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 405 404 403 402 401 400 399 398 397 396 395 394 393
Pin Name RD/FRAME/EX_FRAME RD/FRAME/EX_FRAME RD/FRAME/EX_FRAME WE0/PCC_REG WE0/PCC_REG WE0/PCC_REG D1/EX_AD1 D1/EX_AD1 D1/EX_AD1 D0/EX_AD0 D0/EX_AD0 D0/EX_AD0 WE1/WE WE1/WE WE1/WE CLKOUT CLKOUT D3/EX_AD3 D3/EX_AD3 D3/EX_AD3 D2/EX_AD2 D2/EX_AD2 D2/EX_AD2 D9/EX_AD9 D9/EX_AD9 D9/EX_AD9 D8/EX_AD8 D8/EX_AD8 D8/EX_AD8 D5/EX_AD5 D5/EX_AD5 D5/EX_AD5
I/O* OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT CONTROL OUTPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT
Rev. 1.00 Oct. 01, 2007 Page 1809 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 392 391 390 389 388 387 386 385 384 383 382 381 380 379 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 363 362 361
Pin Name D4/EX_AD4 D4/EX_AD4 D4/EX_AD4 D11/EX_AD11 D11/EX_AD11 D11/EX_AD11 D10/EX_AD10 D10/EX_AD10 D10/EX_AD10 D7/EX_AD7 D7/EX_AD7 D7/EX_AD7 D6/EX_AD6 D6/EX_AD6 D6/EX_AD6 D13/EX_AD13 D13/EX_AD13 D13/EX_AD13 D12/EX_AD12 D12/EX_AD12 D12/EX_AD12 PTL0/D16/EX_AD16/IRQ4/IRL4/ET0_COL/DREQ0/LCD_D8 PTL0/D16/EX_AD16/IRQ4/IRL4/ET0_COL/DREQ0/LCD_D8 PTL0/D16/EX_AD16/IRQ4/IRL4/ET0_COL/DREQ0/LCD_D8 PTL1/D17/EX_AD17/IRQ5/IRL5/ET0_MDC/DACK0/LCD_D9 PTL1/D17/EX_AD17/IRQ5/IRL5/ET0_MDC/DACK0/LCD_D9 PTL1/D17/EX_AD17/IRQ5/IRL5/ET0_MDC/DACK0/LCD_D9 D15/EX_AD15 D15/EX_AD15 D15/EX_AD15 D14/EX_AD14 D14/EX_AD14
I/O* OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
Rev. 1.00 Oct. 01, 2007 Page 1810 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 360 359 358 357 356 355 354 353 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329
Pin Name D14/EX_AD14 PTL3/D19/EX_AD19/IRQ7/IRL7/ET0_MDIO/INTC/LCD_D11 PTL3/D19/EX_AD19/IRQ7/IRL7/ET0_MDIO/INTC/LCD_D11 PTL3/D19/EX_AD19/IRQ7/IRL7/ET0_MDIO/INTC/LCD_D11 PTL2/D18/EX_AD18/IRQ6/IRL6/ET0_ETXD3/TEND0/LCD_D10 PTL2/D18/EX_AD18/IRQ6/IRL6/ET0_ETXD3/TEND0/LCD_D10 PTL2/D18/EX_AD18/IRQ6/IRL6/ET0_ETXD3/TEND0/LCD_D10 WE3/IOWR WE3/IOWR WE3/IOWR WE2/IORD WE2/IORD WE2/IORD PTK1/ST1_D1/GET0_ETXD5/SIOF1_TXD/LCD_D3 PTK1/ST1_D1/GET0_ETXD5/SIOF1_TXD/LCD_D3 PTK1/ST1_D1/GET0_ETXD5/SIOF1_TXD/LCD_D3 PTK0/ST1_D0/GET0_ETXD4/SIOF1_SYNC/LCD_D2 PTK0/ST1_D0/GET0_ETXD4/SIOF1_SYNC/LCD_D2 PTK0/ST1_D0/GET0_ETXD4/SIOF1_SYNC/LCD_D2 PTL4/D20/EX_AD20/ST0_REQ/ET0_ETXD0/INTD/LCD_D12 PTL4/D20/EX_AD20/ST0_REQ/ET0_ETXD0/INTD/LCD_D12 PTL4/D20/EX_AD20/ST0_REQ/ET0_ETXD0/INTD/LCD_D12 PTJ0/ST0M_REQO/GET0_GTX-CLK/REF50CK PTJ0/ST0M_REQO/GET0_GTX-CLK/REF50CK PTJ0/ST0M_REQO/GET0_GTX-CLK/REF50CK PTK3/ST1_D3/GET0_ETXD7/SIOF2_SYNC/LCD_D5 PTK3/ST1_D3/GET0_ETXD7/SIOF2_SYNC/LCD_D5 PTK3/ST1_D3/GET0_ETXD7/SIOF2_SYNC/LCD_D5 PTK2/ST1_D2/GET0_ETXD6/SIOF1_SCK/LCD_D4 PTK2/ST1_D2/GET0_ETXD6/SIOF1_SCK/LCD_D4 PTK2/ST1_D2/GET0_ETXD6/SIOF1_SCK/LCD_D4 PTL6/D22/EX_AD22/ST0_START/ET0_ETXD2/DACK1/LCD_D14
I/O* INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT
Rev. 1.00 Oct. 01, 2007 Page 1811 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300
Pin Name PTL6/D22/EX_AD22/ST0_START/ET0_ETXD2/DACK1/LCD_D14 PTL6/D22/EX_AD22/ST0_START/ET0_ETXD2/DACK1/LCD_D14
I/O* CONTROL INPUT
PTL5/D21/EX_AD21/ST0_CLK/ST0_STRB/ET0_ETXD1/DREQ1/LC D_D13 OUTPUT PTL5/D21/EX_AD21/ST0_CLK/ST0_STRB/ET0_ETXD1/DREQ1/LC D_D13 CONTROL PTL5/D21/EX_AD21/ST0_CLK/ST0_STRB/ET0_ETXD1/DREQ1/LC D_D13 INPUT RDWR/EX_RDWR RDWR/EX_RDWR RDWR/EX_RDWR PTM0/D24/EX_AD24/ST0_D0/ET0_TX-ER/PINT0/RMII0M0_MDIO PTM0/D24/EX_AD24/ST0_D0/ET0_TX-ER/PINT0/RMII0M0_MDIO PTM0/D24/EX_AD24/ST0_D0/ET0_TX-ER/PINT0/RMII0M0_MDIO PTL7/D23/EX_AD23/ST0_VALID/ET0_TX-EN/TEND1/LCD_D15 PTL7/D23/EX_AD23/ST0_VALID/ET0_TX-EN/TEND1/LCD_D15 PTL7/D23/EX_AD23/ST0_VALID/ET0_TX-EN/TEND1/LCD_D15 BS/EX_BS BS/EX_BS BS/EX_BS PTM2/D26/EX_AD26/ST0_D2/ET0_WOL/RMII0_CRS_DV/PINT2 PTM2/D26/EX_AD26/ST0_D2/ET0_WOL/RMII0_CRS_DV/PINT2 PTM2/D26/EX_AD26/ST0_D2/ET0_WOL/RMII0_CRS_DV/PINT2 PTM1/D25/EX_AD25/ST0_D1/ET0_TX-CLK/RMII0_RX_ER/PINT1 PTM1/D25/EX_AD25/ST0_D1/ET0_TX-CLK/RMII0_RX_ER/PINT1 PTM1/D25/EX_AD25/ST0_D1/ET0_TX-CLK/RMII0_RX_ER/PINT1 REF125CK/SSI_CLK/HAC_BITCLK REF125CK/SSI_CLK/HAC_BITCLK REF125CK/SSI_CLK/HAC_BITCLK PTM3/D27/EX_AD27/ST0_D3/ET0_LINKSTA/RMII0_RXD1/PINT3 PTM3/D27/EX_AD27/ST0_D3/ET0_LINKSTA/RMII0_RXD1/PINT3 PTM3/D27/EX_AD27/ST0_D3/ET0_LINKSTA/RMII0_RXD1/PINT3 OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT
Rev. 1.00 Oct. 01, 2007 Page 1812 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268
Pin Name CS0 CS0 CS0 PTM5/D29/EX_AD29/ST0_D5/ET0_RX-ER/RMII0_TXD_EN/PINT5 PTM5/D29/EX_AD29/ST0_D5/ET0_RX-ER/RMII0_TXD_EN/PINT5 PTM5/D29/EX_AD29/ST0_D5/ET0_RX-ER/RMII0_TXD_EN/PINT5 PTM4/D28/EX_AD28/ST0_D4/ET0_PHY-INT/RMII0_RXD0/PINT4 PTM4/D28/EX_AD28/ST0_D4/ET0_PHY-INT/RMII0_RXD0/PINT4 PTM4/D28/EX_AD28/ST0_D4/ET0_PHY-INT/RMII0_RXD0/PINT4 PTM7/D31/EX_AD31/ST0_D7/ET0_RX-DV/RMII0_TXD0/PINT7 PTM7/D31/EX_AD31/ST0_D7/ET0_RX-DV/RMII0_TXD0/PINT7 PTM7/D31/EX_AD31/ST0_D7/ET0_RX-DV/RMII0_TXD0/PINT7 PTM6/D30/EX_AD30/ST0_D6/ET0_RX-CLK/RMII0_TXD1/PINT6 PTM6/D30/EX_AD30/ST0_D6/ET0_RX-CLK/RMII0_TXD1/PINT6 PTM6/D30/EX_AD30/ST0_D6/ET0_RX-CLK/RMII0_TXD1/PINT6 CS1/EX_CS0 CS1/EX_CS0 CS1/EX_CS0 CS2/EX_CS1 CS2/EX_CS1 CS2/EX_CS1 CS5/CE1A CS5/CE1A CS5/CE1A CS4 CS4 CS4 CS6/CE1B CS6/CE1B CS6/CE1B RDY/EX_RDY/PCC_WAIT RDY/EX_RDY/PCC_WAIT
I/O* OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Section 42 User Debugging Interface (H-UDI)
Number 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238
Pin Name RDY/EX_RDY/PCC_WAIT PTJ1/ST0M_CLKIO/ST0M_STRBI/RMII1_RX_ER/LCD_CLK PTJ1/ST0M_CLKIO/ST0M_STRBI/RMII1_RX_ER/LCD_CLK PTJ1/ST0M_CLKIO/ST0M_STRBI/RMII1_RX_ER/LCD_CLK PTJ2/ST0M_D0I/ET0_ERXD0/RMII1_TXD1/LCD_M_DISP PTJ2/ST0M_D0I/ET0_ERXD0/RMII1_TXD1/LCD_M_DISP PTJ2/ST0M_D0I/ET0_ERXD0/RMII1_TXD1/LCD_M_DISP PTJ3/ST0M_D1I/ET0_ERXD1/RMII1_CRS_DV/LCD_CL1 PTJ3/ST0M_D1I/ET0_ERXD1/RMII1_CRS_DV/LCD_CL1 PTJ3/ST0M_D1I/ET0_ERXD1/RMII1_CRS_DV/LCD_CL1 PTJ4/ST0M_D2I/ET0_ERXD2/RMII1_RXD1/LCD_CL2 PTJ4/ST0M_D2I/ET0_ERXD2/RMII1_RXD1/LCD_CL2 PTJ4/ST0M_D2I/ET0_ERXD2/RMII1_RXD1/LCD_CL2 PTJ5/ST0M_D3I/ET0_ERXD3/RMII1_RXD0/LCD_DON PTJ5/ST0M_D3I/ET0_ERXD3/RMII1_RXD0/LCD_DON PTJ5/ST0M_D3I/ET0_ERXD3/RMII1_RXD0/LCD_DON PTJ6/ST0M_D4I/ET0_CRS/RMII1_TXD_EN/LCD_FLM PTJ6/ST0M_D4I/ET0_CRS/RMII1_TXD_EN/LCD_FLM PTJ6/ST0M_D4I/ET0_CRS/RMII1_TXD_EN/LCD_FLM PTJ7/INTB/ST0M_D5I/IRQOUT/RMII1_TXD0/LCD_D0 PTJ7/INTB/ST0M_D5I/IRQOUT/RMII1_TXD0/LCD_D0 PTJ7/INTB/ST0M_D5I/IRQOUT/RMII1_TXD0/LCD_D0 PTI6/IRQ2/IRL2/ST0M_D6I/IIC1_SCL PTI6/IRQ2/IRL2/ST0M_D6I/IIC1_SCL PTI7/IRQ3/IRL3/ST0M_D7I/IIC1_SDA PTI7/IRQ3/IRL3/ST0M_D7I/IIC1_SDA PTI4/MD8/ST1_START/ET1_PHYINT/RMII0M0_MDC/USB_PWREN/USBF_UPLUP PTI4/MD8/ST1_START/ET1_PHYINT/RMII0M0_MDC/USB_PWREN/USBF_UPLUP PTI4/MD8/ST1_START/ET1_PHYINT/RMII0M0_MDC/USB_PWREN/USBF_UPLUP PTI5/MD10/ST1_VALID/LCD_D1
I/O* INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT CONTROL INPUT OUTPUT
Rev. 1.00 Oct. 01, 2007 Page 1814 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208
Pin Name PTI5/MD10/ST1_VALID/LCD_D1 PTI5/MD10/ST1_VALID/LCD_D1 PTK4/ST1_D4/GET0_ERXD4/SIOF2_TXD/LCD_D6 PTK4/ST1_D4/GET0_ERXD4/SIOF2_TXD/LCD_D6 PTK4/ST1_D4/GET0_ERXD4/SIOF2_TXD/LCD_D6 PTK5/ST1_D5/GET0_ERXD5/SIOF2_RXD/LCD_D7 PTK5/ST1_D5/GET0_ERXD5/SIOF2_RXD/LCD_D7 PTK5/ST1_D5/GET0_ERXD5/SIOF2_RXD/LCD_D7 PTK6/ST1_D6/GET0_ERXD6/SIOF2_SCK/LCD_VEPWC PTK6/ST1_D6/GET0_ERXD6/SIOF2_SCK/LCD_VEPWC PTK6/ST1_D6/GET0_ERXD6/SIOF2_SCK/LCD_VEPWC PTK7/ST1_D7/GET0_ERXD7/SIOF2_MCLK/LCD_VCPWC PTK7/ST1_D7/GET0_ERXD7/SIOF2_MCLK/LCD_VCPWC PTK7/ST1_D7/GET0_ERXD7/SIOF2_MCLK/LCD_VCPWC PTI0/STATUS0/ST1_CLK/ST1_STRB/RMII0_MDC PTI0/STATUS0/ST1_CLK/ST1_STRB/RMII0_MDC PTI0/STATUS0/ST1_CLK/ST1_STRB/RMII0_MDC PTI1/STATUS1/ST1_REQ/RMII0_MDIO PTI1/STATUS1/ST1_REQ/RMII0_MDIO PTI1/STATUS1/ST1_REQ/RMII0_MDIO PTI2/ST0M_STARTI/IIC0_SCL/SIOF1_RXD/USB_OVRCRT /USBF_VBUS PTI2/ST0M_STARTI/IIC0_SCL/SIOF1_RXD/USB_OVRCRT /USBF_VBUS PTI3/ST0M_VALIDI/IIC0_SDA/SIOF1_MCLK/USB_CLK PTI3/ST0M_VALIDI/IIC0_SDA/SIOF1_MCLK/USB_CLK PTF0/GNT0/GNTIN/SIM_D/ET1_ETXD3/DREQ3 PTF0/GNT0/GNTIN/SIM_D/ET1_ETXD3/DREQ3 PTF0/GNT0/GNTIN/SIM_D/ET1_ETXD3/DREQ3 PTG3/REQ3/ET1_ETXD2 PTG3/REQ3/ET1_ETXD2 PTG3/REQ3/ET1_ETXD2
I/O* CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT
Rev. 1.00 Oct. 01, 2007 Page 1815 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179
Pin Name PTG2/REQ1/ET1_ETXD1 PTG2/REQ1/ET1_ETXD1 PTG2/REQ1/ET1_ETXD1 PTG1/GNT2/ET1_ETXD0 PTG1/GNT2/ET1_ETXD0 PTG1/GNT2/ET1_ETXD0 PTD7/PCIRESET/PCC_RESET/GET1_ETXD7/LCDM_VEPWC PTE0/INTA/PCC_DRV/GET1_ETXD6/DREQ2 PTE0/INTA/PCC_DRV/GET1_ETXD6/DREQ2 PTE0/INTA/PCC_DRV/GET1_ETXD6/DREQ2 PTD6/REQ2/PCC_BVD1/GET1_ETXD5/SSI1_SCK/ LCDM_VCPWC PTD6/REQ2/PCC_BVD1/GET1_ETXD5/SSI1_SCK/ LCDM_VCPWC PTD6/REQ2/PCC_BVD1/GET1_ETXD5/SSI1_SCK/ LCDM_VCPWC PTE1/PCICLK/GET1_ETXD4/DACK2 PTE1/PCICLK/GET1_ETXD4/DACK2 PTE1/PCICLK/GET1_ETXD4/DACK2 PTG4/AD30/ET1_LINKSTA PTG4/AD30/ET1_LINKSTA PTG4/AD30/ET1_LINKSTA PTG0/GNT1/ET1_WOL PTG0/GNT1/ET1_WOL PTG0/GNT1/ET1_WOL PTF2/AD31/SIM_RST/ET1_MDIO/TEND3 PTF2/AD31/SIM_RST/ET1_MDIO/TEND3 PTF2/AD31/SIM_RST/ET1_MDIO/TEND3 PTF1/REQ0/REQOUT/SIM_CLK/ET1_MDC/DACK3 PTF1/REQ0/REQOUT/SIM_CLK/ET1_MDC/DACK3 PTF1/REQ0/REQOUT/SIM_CLK/ET1_MDC/DACK3 PTG6/AD26/ET1_TX-ER
I/O* OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT
Rev. 1.00 Oct. 01, 2007 Page 1816 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148
Pin Name PTG6/AD26/ET1_TX-ER PTG6/AD26/ET1_TX-ER PTG7/AD28/ET1_TX-EN PTG7/AD28/ET1_TX-EN PTG7/AD28/ET1_TX-EN PTE5/AD29/SCIF2_TXD/GET1_GTX-CLK/SSI0_SCK PTE5/AD29/SCIF2_TXD/GET1_GTX-CLK/SSI0_SCK PTE5/AD29/SCIF2_TXD/GET1_GTX-CLK/SSI0_SCK PTH0/AD25/TPU_TI3A/ET1_COL/RMII1M_RX_ER PTH0/AD25/TPU_TI3A/ET1_COL/RMII1M_RX_ER PTH0/AD25/TPU_TI3A/ET1_COL/RMII1M_RX_ER PTH6/AD27/TPU_TO2/ET1_CRS/RMII1M_TXD_EN PTH6/AD27/TPU_TO2/ET1_CRS/RMII1M_TXD_EN PTH6/AD27/TPU_TO2/ET1_CRS/RMII1M_TXD_EN PTF3/CBE3/ET1_TX-CLK PTF3/CBE3/ET1_TX-CLK PTF3/CBE3/ET1_TX-CLK PTG5/GNT3/ET1_RX-CLK PTG5/GNT3/ET1_RX-CLK PTG5/GNT3/ET1_RX-CLK PTH2/AD24/TPU_TI2A/ET1_ERXD0/RMII1M_TXD1 PTH2/AD24/TPU_TI2A/ET1_ERXD0/RMII1M_TXD1 PTH2/AD24/TPU_TI2A/ET1_ERXD0/RMII1M_TXD1 PTH5/AD23/TPU_TO1/ET1_ERXD1/RMII1M_TXD0 PTH5/AD23/TPU_TO1/ET1_ERXD1/RMII1M_TXD0 PTH5/AD23/TPU_TO1/ET1_ERXD1/RMII1M_TXD0 PTH1/IDSEL/TPU_TI3B/ET1_RX-ER/RMII1M_CRS_DV PTH1/IDSEL/TPU_TI3B/ET1_RX-ER/RMII1M_CRS_DV PTH1/IDSEL/TPU_TI3B/ET1_RX-ER/RMII1M_CRS_DV PTH3/AD21/TPU_TI2B/ET1_ERXD2/RMII1M_RXD1 PTH3/AD21/TPU_TI2B/ET1_ERXD2/RMII1M_RXD1
I/O* CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
Rev. 1.00 Oct. 01, 2007 Page 1817 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
Pin Name PTH3/AD21/TPU_TI2B/ET1_ERXD2/RMII1M_RXD1 PTH4/AD19/TPU_TO0/ET1_ERXD3/RMII1M_RXD0 PTH4/AD19/TPU_TO0/ET1_ERXD3/RMII1M_RXD0 PTH4/AD19/TPU_TO0/ET1_ERXD3/RMII1M_RXD0 PTE4/AD22/SCIF2_RXD/GET1_ERXD4/SSI0_SDATA PTE4/AD22/SCIF2_RXD/GET1_ERXD4/SSI0_SDATA PTE4/AD22/SCIF2_RXD/GET1_ERXD4/SSI0_SDATA PTE3/AD20/SCIF2_SCK/GET1_ERXD5/SSI0_WS PTE3/AD20/SCIF2_SCK/GET1_ERXD5/SSI0_WS PTE3/AD20/SCIF2_SCK/GET1_ERXD5/SSI0_WS PTH7/AD17/TPU_TO3/ET1_RX-DV PTH7/AD17/TPU_TO3/ET1_RX-DV PTH7/AD17/TPU_TO3/ET1_RX-DV PTD1/CBE2/PCC_VS2/SIOF0_TXD/HAC_SD_OUT/LCDM_D15 PTD1/CBE2/PCC_VS2/SIOF0_TXD/HAC_SD_OUT/LCDM_D15 PTD1/CBE2/PCC_VS2/SIOF0_TXD/HAC_SD_OUT/LCDM_D15 PTD5/AD18/PCC_CD2/GET1_ERXD6/SSI1_SDATA/LCDM_D14 PTD5/AD18/PCC_CD2/GET1_ERXD6/SSI1_SDATA/LCDM_D14 PTD5/AD18/PCC_CD2/GET1_ERXD6/SSI1_SDATA/LCDM_D14 PTE2/AD16/PCC_IOIS16/GET1_ERXD7/TEND2 PTE2/AD16/PCC_IOIS16/GET1_ERXD7/TEND2 PTE2/AD16/PCC_IOIS16/GET1_ERXD7/TEND2 PTD0/IRDY/PCC_VS1/SIOF0_SYNC/HAC_SD_IN/LCDM_D13 PTD0/IRDY/PCC_VS1/SIOF0_SYNC/HAC_SD_IN/LCDM_D13 PTD0/IRDY/PCC_VS1/SIOF0_SYNC/HAC_SD_IN/LCDM_D13 PTA1/DEVSEL/SCIF1_RXD PTA1/DEVSEL/SCIF1_RXD PTA1/DEVSEL/SCIF1_RXD PTD3/PCIFRAME/PCC-BVD2/SIOFO_SCK/HAC_RES/LCDM_D12 PTD3/PCIFRAME/PCC-BVD2/SIOFO_SCK/HAC_RES/LCDM_D12 PTD3/PCIFRAME/PCC-BVD2/SIOFO_SCK/HAC_RES/LCDM_D12
I/O* INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT
Rev. 1.00 Oct. 01, 2007 Page 1818 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
Pin Name PTD2/TRDY/PCC_RDY/SIOF0_RXD/HAC_SYNC/LCDM_D11 PTD2/TRDY/PCC_RDY/SIOF0_RXD/HAC_SYNC/LCDM_D11 PTD2/TRDY/PCC_RDY/SIOF0_RXD/HAC_SYNC/LCDM_D11 PTA2/LOCK/SCIF1_TXD* PTA2/LOCK/SCIF1_TXD PTA2/LOCK/SCIF1_TXD PTB0/PERR/PINT8/LCDM_D10 PTB0/PERR/PINT8/LCDM_D10 PTB0/PERR/PINT8/LCDM_D10 PTD4/STOP/PCC_CD1/SIOF0_MCLK/SSI1_WS/LCDM_DON PTD4/STOP/PCC_CD1/SIOF0_MCLK/SSI1_WS/LCDM_DON PTD4/STOP/PCC_CD1/SIOF0_MCLK/SSI1_WS/LCDM_DON PTA0/PAR/SCIF1_SCK PTA0/PAR/SCIF1_SCK PTA0/PAR/SCIF1_SCK PTB1/SERR/PINT9/LCDM_D9 PTB1/SERR/PINT9/LCDM_D9 PTB1/SERR/PINT9/LCDM_D9 PTB4/CBE1/PINT12/LCDM_D8 PTB4/CBE1/PINT12/LCDM_D8 PTB4/CBE1/PINT12/LCDM_D8 PTA3/AD15/SCIF1_CTS PTA3/AD15/SCIF1_CTS PTA3/AD15/SCIF1_CTS PTA4/AD13/SCIF1_RTS PTA4/AD13/SCIF1_RTS PTA4/AD13/SCIF1_RTS PTB5/AD14/PINT13/LCDM_M_DISP PTB5/AD14/PINT13/LCDM_M_DISP PTB5/AD14/PINT13/LCDM_M_DISP PTA5/AD12 PTA5/AD12
I/O* OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
Rev. 1.00 Oct. 01, 2007 Page 1819 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
Pin Name PTA5/AD12 PTB2/AD11/PINT10/LCDM_D7 PTB2/AD11/PINT10/LCDM_D7 PTB2/AD11/PINT10/LCDM_D7 PTB3/AD9/PINT11/LCDM_D6 PTB3/AD9/PINT11/LCDM_D6 PTB3/AD9/PINT11/LCDM_D6 PTC0/AD10/MMC_DAT/LCDM_D5 PTC0/AD10/MMC_DAT/LCDM_D5 PTC0/AD10/MMC_DAT/LCDM_D5 PTC3/AD8/MMC_ODMOD/LCDM_D4 PTC3/AD8/MMC_ODMOD/LCDM_D4 PTC3/AD8/MMC_ODMOD/LCDM_D4 PTB6/CBE0/PINT14/LCDM_D3 PTB6/CBE0/PINT14/LCDM_D3 PTB6/CBE0/PINT14/LCDM_D3 PTB7/AD6/PINT15/LCDM_D2 PTB7/AD6/PINT15/LCDM_D2 PTB7/AD6/PINT15/LCDM_D2 PTC4/AD7/MMC_CMD/LCDM_CL2 PTC4/AD7/MMC_CMD/LCDM_CL2 PTC4/AD7/MMC_CMD/LCDM_CL2 PTC6/AD5/LCDM_CL1 PTC6/AD5/LCDM_CL1 PTC6/AD5/LCDM_CL1 PTC1/AD4/LCDM_D1 PTC1/AD4/LCDM_D1 PTC1/AD4/LCDM_D1 PTC2/AD2/LCDM_D0 PTC2/AD2/LCDM_D0 PTC2/AD2/LCDM_D0 PTC7/AD3/MMC_CLK
I/O* INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT
Rev. 1.00 Oct. 01, 2007 Page 1820 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Pin Name PTC7/AD3/MMC_CLK PTC7/AD3/MMC_CLK PTA6/AD1/MMC_VDDON PTA6/AD1/MMC_VDDON PTA6/AD1/MMC_VDDON PTC5/AD0/MMC_CD/LCDM_FLM PTC5/AD0/MMC_CD/LCDM_FLM PTC5/AD0/MMC_CD/LCDM_FLM PTN0/SCIF0_SCK/MD0 PTN0/SCIF0_SCK/MD0 PTN0/SCIF0_SCK/MD0 PTN1/SCIF0_RXD/MD3 PTN1/SCIF0_RXD/MD3 PTN1/SCIF0_RXD/MD3 PTN2/SCIF0_TXD/MD1 PTN2/SCIF0_TXD/MD1 PTN2/SCIF0_TXD/MD1 PTN3/SCIF0_CTS/MD4 PTN3/SCIF0_CTS/MD4 PTN3/SCIF0_CTS/MD4 PTN4/SCIF0_RTS/MD2 PTN4/SCIF0_RTS/MD2 PTN4/SCIF0_RTS/MD2 PTN5/NMI PTN5/NMI PTN5/NMI PTO6/IRQ0/IRL0/DACK1M/MD5 PTO6/IRQ0/IRL0/DACK1M/MD5 PTO6/IRQ0/IRL0/DACK1M/MD5 PTO7/IRQ1/IRL1/TEND1M/SSI3_SCK/MD6 PTO7/IRQ1/IRL1/TEND1M/SSI3_SCK/MD6 PTO7/IRQ1/IRL1/TEND1M/SSI3_SCK/MD6
I/O* CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT
Rev. 1.00 Oct. 01, 2007 Page 1821 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
Number 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: *
Pin Name PTO0/AUDSYNCS/RMII_MDC/SSI2_WS PTO0/AUDSYNCS/RMII_MDC/SSI2_WS PTO0/AUDSYNCS/RMII_MDC/SSI2_WS PTO1/AUDATA0/RMII_MDIO/SSI2_SDATA PTO1/AUDATA0/RMII_MDIO/SSI2_SDATA PTO1/AUDATA0/RMII_MDIO/SSI2_SDATA PTO2/AUDATA1/RMII0M1_MDC PTO2/AUDATA1/RMII0M1_MDC PTO2/AUDATA1/RMII0M1_MDC PTO3/AUDATA2/RMII0M1_MDIO/SSI2_SCK PTO3/AUDATA2/RMII0M1_MDIO/SSI2_SCK PTO3/AUDATA2/RMII0M1_MDIO/SSI2_SCK PTO4/AUDATA3/EX_INT/SSI3_WS PTO4/AUDATA3/EX_INT/SSI3_WS PTO4/AUDATA3/EX_INT/SSI3_WS PTO5/AUDCK/DREQ1M/SSI3_SDATA PTO5/AUDCK/DREQ1M/SSI3_SDATA PTO5/AUDCK/DREQ1M/SSI3_SDATA ASEBRK/BRKACK ASEBRK/BRKACK ASEBRK/BRKACK To TDO
I/O* OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT
Control is an active-high signal. When Control is driven high, the corresponding pin is driven according to the OUT value.
Rev. 1.00 Oct. 01, 2007 Page 1822 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
42.5
42.5.1
Operation
TAP Control
Figure 42.3 shows the internal states of the TAP controller. The state transitions basically conform to the JTAG standard. * State transitions occur according to the TMS value at the rising edge of the TCK signal. * The TDI value is sampled at the rising edge of the TCK signal and shifted at the falling edge of the TCK signal. * The TDO value is changed at the falling edge of the TCK signal. The TDO signal is in a Hi-Z state other than in the Shift-DR or Shift-IR state. * A transition to the Test-Logic-Reset by clearing TRST to 0 is performed asynchronously with the TCK signal.
1
Test -Logic-Reset 0 1 1 Select-DR-Scan 0 0 1 Capture-DR 0 Shift-DR 1 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 Exit1-IR 0 Pause-IR 1 0 0 1 Capture-IR 0 Shift-IR 1 1 0 Select-IR-Scan 1
0
Run-Test/Idle
Figure 42.3 TAP Controller State Transitions
Rev. 1.00 Oct. 01, 2007 Page 1823 of 1956 REJ09B0256-0100
Section 42 User Debugging Interface (H-UDI)
42.5.2
H-UDI Reset
A power-on reset is generated by the SDIR command. After the H-UDI reset assert command has been sent from the H-UDI pin, sending the H-UDI reset negate command resets the CPU (see figure 42.4). The required time between the H-UDI reset assert and H-UDI reset negate commands is the same as the time for holding the reset pin low in order to reset this LSI by a power-on reset.
H-UDI pin
H-UDI reset assert
H-UDI reset negate
Chip internal reset
CPU state
Normal
Reset
Reset handling
Figure 42.4 H-UDI Reset 42.5.3 H-UDI Interrupt
The H-UDI interrupt function generates an interrupt by setting the appropriate command in SDIR from the H-UDI. An H-UDI interrupt request signal is asserted when the INTREQ bit in SDINT is set to 1 by setting the appropriate command. Since the interrupt request signal is not negated until the INTREQ bit is cleared to 0 by software, it is not possible to lose the interrupt request. While an H-UDI interrupt command is set in SDIR, SDINT is connected between the TDI and TDO pins.
42.6
Usage Notes
Once an SDIR command is set, it will be changed only by an assertion of the TRST signal, making the TAP controller Test-Logic-Reset state, or writing other commands from the H-UDI. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when using an emulator.
Rev. 1.00 Oct. 01, 2007 Page 1824 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Section 43 Electrical Characteristics
43.1 Absolute Maximum Ratings
Table 43.1 Absolute Maximum Ratings*1, *2
Item I/O power supply voltage Symbol VDDQ VDD-RTC VCCQ-DDR Internal power supply voltage VDD VDD-PLL1/2/3 VDD-DLL1/2 Analog power supply voltage Input voltage AVcc Vin Vin-DDR Analog input voltage Operating temperature Storage temperature VAN Topr Tstg -0.3 to 4.6 -0.3 to VCCQ + 0.3*
3 3
Value -0.3 to 4.6 -0.3 to 2.8 -0.3 to 1.8
Unit V
V
V V
-0.3 to VDD-RTC + 0.3* -0.3 to AVcc + 0.3 -20 to 75 -55 to 125
-0.3 to VCCQ-DDR + 0.3*3 V C C
Notes: 1. The LSI may be permanently damaged if the maximum ratings are exceeded. 2. The LSI may be permanently damaged if any of the VSS pins are not connected to GND. 3. The upper limit of the input voltage must not exceed the power supply voltage.
Rev. 1.00 Oct. 01, 2007 Page 1825 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.2
43.2.1
Power-On and Power-Off Order
Power-On Order
There are no restrictions on the power-on order. After a single power supply is turned on, all other power supplies should be turned on within 10 ms. It is recommended that this time period is as short as possible. The system should be designed so that a system malfunction is not caused by the undefined states of pins and internal circuits. The internal circuit states are undefined until a low level is input to the RESETP pin after voltage is applied to all power supplies. While the internal circuit states are undefined, the state of each pin is also undefined. Accordingly, the system should be designed so that a system malfunction is not caused by such undefined state. 43.2.2 Power-Off Order
There are no restrictions on the power-off order. After a single power supply is turned off, all other power supplies should be turned off within 10 ms. It is recommended that this time period is as short as possible. The system should be designed so that a system malfunction is not caused by the undefined states of pins and internal circuits.
Rev. 1.00 Oct. 01, 2007 Page 1826 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Power-on timing A power supply that is turned off first: VCCQ, VDD-RTC*1, AVCC, VCCQ-DDR*2, VDD, VDD-PLL or VDD-DLL
tPWU
All power supplies other than the above
Power-off timing A power supply that is turned off first: VCCQ, VDD-RTC*1, AVCC, VCCQ-DDR*2, VDD, VDD-PLL or VDD-DLL
tPWD
All power supplies other than the above.
Notes: *1 A transition to the RTC power supply backup mode is excluded. *2 A transition to the DDR power supply backup mode is excluded.
Figure 43.1 Power-On and Power-Off Timing Table 43.2 Power-On and Power-Off Timing
Item Time lags among powering on (VCCQ, VDD-RTC, AVCC), (VCCQ-DDR), and (VDD, VDD-PLL1 to 3, VDD-DLL1 to 3) Time lags among powering off (VCCQ, VDD-RTC, AVCC), (VCCQ-DDR), and (VDD, VDD-PLL1 to 3, VDD-DLL1 to 3) Symbol tPWU tPWD Maximum time 10 10 Unit ms ms
Rev. 1.00 Oct. 01, 2007 Page 1827 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.2.3
Power-Off and Power-On Order in RTC Power-Supply Backup Mode (Hardware Standby)
To use RTC power supply backup mode, the RTC clock should be supplied. First bring the XRTCSTBI pin low, and then make sure that the STATUS0 and STATUS1 pins have been pulled high and low, respectively. After that, turn off the power supplies (VCCQ, AVCC), (VCCQ-DDR), and (VDD, VDD-PLL1 to 3, VDD-DLL1 to 3). The power supply VDDRTC should remain on, and the XRTCSTBI pin should remain low. Turn on the power supplies (VCCQ, AVCC), (VCCQ-DDR), and (VDD, VDD-PLL1 to 3, VDDDLL1 to 3) while the XRTCSTBI pin is low. After these power supplies become stable, bring the XRTCSTBI pin high and negate the PRESET pin to high level. 43.2.4 Power-Off and Power-On Order in DDR-SDRAM Power-Supply Backup Mode
To use DDR-SDRAM power-supply backup mode, the DDR-SDRAM should be placed in the self-refresh state. After the DDR-SDRAM is placed in the self-refresh state, bring the M-CKE pin low. Make sure that the SELFS bit in the MIM register is set to 1, and then bring the M_BKPRST pin low. After that, turn off the power supplies (VCCQ, AVCC, VDD-RTC) and (VDD, VDDPLL1 to 3, VDD-DLL1 to 3). The power supply VCCQ-DDR should remain on and the M_BKPRST pin should remain low. Turn on the power supplies (VCCQ, AVCC, VDD-RTC) and (VDD, VDD-PLL1 to 3, VDDDLL1 to 3) while the M_BKPRST pin is low. After these power supplies become stable, negate the M_BKPRST and PRESET pins to high level.
Rev. 1.00 Oct. 01, 2007 Page 1828 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.3
DC Characteristics
Table 43.3 DC Characteristics (1) [common] Condition: Ta = -20 to 75C
Item Power supply voltage Symbol VCCQ VDD-RTC Min. 3.0 3.0 Typ. Max. 3.3 3.3 2.5 1.25 3.6 3.6 2.7 1.35 Unit V V V V Test Conditions
VCCQ-DDR 2.3
VDD VDD-PLL1/2/3 VDD-DLL1/2 Analog power supply voltage AVCC
1.15
3.0
3.3
3.6
V
When not in use the same voltage as VCCQ
Reference voltage Current Normal operation dissipation
DDR-VREF IDD IDD-PLL IDD-DLL ICCQ IDD-RTC ICCQ-DDR
1.15 -- -- -- -- -- -- -- -- -- -- --
1.25 950 -- -- 200 -- -- -- -- -- -- -- --
1.35 1200 10 12 300 0.9 250 800 25 50 155 30 30 20
V mA mA mA mA mA mA mA mA A A mA VDD-RTC = 3.3V DDRck = 133MHz Ick = 266MHz Ick = 266MHz
Sleep mode
IDD ICCQ IDD-RTC ICCQ-DDR AICC
RTC backup mode DDR backup mode Analog power supply current A/D conversion period A/D and D/A conversion period Idle
--
--
Note: Note that a heat radiation countermeasure, such as a heat sinks, is required when the ambient temperature exceeds 60 degrees.
Rev. 1.00 Oct. 01, 2007 Page 1829 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Table 43.4 DC Characteristics (2-a) [Except of USB Transceiver and I2C Related Pins] Condition: Ta = -20 to 75C
Item Input voltage Input pin group* DDR pins
1
Symbol VIH
Min.
Typ. Max.
VCCQ + 0.3 VCCQ-DDR + 0.3
Unit Test Conditions V VCCQ = 3.0 to 3.6 V DDR-VREF = 1.15 to 1.35V VCCQ-DDR = 2.3 to 2.7V VCCQ = 3.0 to 3.6V
VCCQ x 0.9 --
DDR-VREF + 0.15
--
PCICLK Other PCI pins Other input pins Input pin group* DDR pins M_BKPRST PCICLK Other PCI pins Other input pins Input leak current DDR pins All input pins Output voltage PCI pins DDR pins Other output pins |L| |lin| VOH
1
VCCQ x 0.6 -- VCCQ x 0.5 --
VCCQ + 0.3 VCCQ + 0.3 VCCQ + 0.3 VCCQ x 0.1
2 VIL -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -- -- 2.4 1.84 2.4
-- -- -- -- -- -- -- -- -- -- -- --
V
VCCQ = 3.0 to 3.6 V
DDR-VREF - 0.18
VCCQ-DDR x 0.2 VCCQ x 0.2 VCCQ x 0.3 VCCQ x 0.2
DDR-VREF = 1.15 to 1.35V VCCQ-DDR = 2.3 to 2.7V
VCCQ = 3.0 to 3.6V
2 1 -- -- --
A
VIN = 0.5 to VCCQ-DDR - 0.5V VIN = 0.5 to VCCQ - 0.5V
V
VCCQ = 3.0 to 3.6V IOH = -4mA VCCQ-DDR = 2.3V IOH = -7.6mA VCCQ = 3.0 to 3.6V IOH = -2mA
Rev. 1.00 Oct. 01, 2007 Page 1830 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Item Output voltage PCI pins DDR pins
Symbol VOL
Min. -- --
Typ. Max. -- -- 0.55 0.54
Unit Test Conditions V
VCCQ = 3.0 to 3.6V IOL = 4mA VCCQ-DDR = 2.3 to 2.7 V IOL = 7.6mA VCCQ = 3.0 to 3.6V IOL = 2mA
Other output pins Pull-up resistance All pins Rpull CL
-- 20 -- --
-- 60 -- --
0.55 180 5 10 k pF
Pin DDR pins capacitance Other pins
Notes: 1. Input pin group: EXTAL, EXTAL2, PRESET, XRTCSTBI, MRESET, TRST, MD0 to MD6, MD8, MD10, MPMD, PTN0 to PTN5, PTO6, PTO7, PTI2 to PTI7, NMI, IRQ0 to IRQ7, IRL0 to IRL7, PINT0 to PINT15, DACK1M, SSI3_SCK, SSI_CLK, SIOF1_MCLK, SIOF1_RXD, SCIF0_SCK, SCIF0_RTS, SCIF0_RXD, SCIF0_CTS, ET1_PHY-INT, ST1_START, ST1_VALID, ST0M_VALIDI, ST0M_D7I, ST0M_D6I, REF125CK, HAC_BITCLK, USB_CLK, USB_OVRCRT/USBF_VBUS 2. The current dissipation values are for VIH min = VDDQ -0.5 V and VIL max = 0.5 V with all output pins unload.
Table 43.5 DC Characteristics (2-b) [I2C Related Pins] Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Item Power supply voltage Input high voltage Input low voltage Output low voltage Permissible output low current Symbol VCCQ VIH VIL VOL IOL Min. 3.0
VCCQ x 0.7
Typ. 3.3
Max. 3.6
VCCQ + 0.3 VCCQ x 0.3
Unit V V V V mA
Test Conditions
-0.3
0.4 10
IOL = 3 mA
Note: I2C related pins: IIC0_SCL, IIC1_SCL, IIC0_SDA, and IIC1_SDA pins (open-drain pins).
Rev. 1.00 Oct. 01, 2007 Page 1831 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Table 43.6 DC Characteristics (2-c) [USB Transceiver Related Pins] Condition:
Item Power supply voltage Differential input sensitivity Differential common mode range Single ended receiver threshold voltage Output high voltage Output low voltage Tray state leakage voltage
Ta = -20 to 75C
Symbol VCCQ VDI VCM VSE VOH VOL ILO Min. 3.0 0.2 0.8 0.8 2.5 -10 Typ. 3.3 Max. 3.6 2.5 2.0 VCCQ 0.3 10 Unit V V V V V V A 0V < VIN < 3.3V (DP) - (DM) Test Conditions
Note: Transceiver related pins: USBP, USBM.
Table 43.7 Permissible Output Currents Conditions:
Item Permissible output low current (per pin; DDR1 pins) Permissible output low current (per pin; PCI1 pins) Permissible output low current (per pin; other than DDR and PCI pins) Permissible output low current (total) Permissible output high current (per pin; DDR1 pins) Permissible output high current (per pin; PCI1 pins) Permissible output high current (per pin; other than DDR and PCI pins) Permissible output high current (total) |-IOH| IOL -IOH
VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol IOL Min. Typ. Max. 16 4 2 120 16 4 2 40 mA mA mA Unit mA
Note: To protect chip reliability, do not exceed the output current values in table 43.7.
Rev. 1.00 Oct. 01, 2007 Page 1832 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4
AC Characteristics
In principle, this LSI's input should be synchronous. Unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. Table 43.8 Maximum Operating Frequency Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Item Operating frequency CPU, FPU, cache, TLB DDR-SDRAM bus External bus PCI bus Peripheral modules 0 Peripheral modules 1 RTC oscillator Symbol f Min. 200 100 50 32 50 25 32 Typ. Max. 267 134 67 67 67 34 33 kHz Unit MHz
Rev. 1.00 Oct. 01, 2007 Page 1833 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.1
Clock and Control Signal Timing
Table 43.9 Clock and Control Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol PLL1 PLL2 operation fEX tEXcyc tEXL tEXH tEXr tEXf tOP tCLKOUTcyc tCLKOUTL1 tCLKOUTH1 tCLKOUTr tCLKOUTf tCLKOUTL2 tCLKOUTH2 tOSC1 Min. 25 30 3.5 3.5 50 15 3 3 3 3 30 30 0 0 0 20 200 10 20 Max. 33.4 40 4 4 67 20 3 3 3 Unit MHz ns ns ns ns ns MHz ns ns ns ns ns ns ns ms ms ns ns ms tcyc* s s ms tcyc*3 43.6 43.7 43.8
3
Item EXTAL clock input frequency*1
Figure
EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CLKOUT clock output*2 PLL1/PLL2 operation
43.2 43.2 43.2 43.2 43.2
CLKOUT clock output cycle time CLKOUT clock output low-level pulse width CLKOUT clock output high-level pulse width CLKOUT clock output rise time CLKOUT clock output fall time CLKOUT clock output low-level pulse width CLKOUT clock output high-level pulse width Power-on oscillation settling time
43.3 43.3 43.3 43.3 43.3 43.4 43.4 43.5 43.5 43.5 43.5 43.5 43.8
Power-on oscillation settling time/mode settling tOSCMD time MDn reset hold time TRST reset hold time Reset holding time PRESET pulse width Power-on RTC oscillation settling time PLL synchronization settling time tMDRH tTRSTRH tRESH tRESPW tRTC-OSC tPLL
Oscillation settling time on return from standby TSOC2 2 MRESET pulse width tRESMW
Rev. 1.00 Oct. 01, 2007 Page 1834 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Item MRESET setup time MRESET hold time
Symbol tRESMS tRESMH
Min. 23 2
Max.
Unit ns ns
Figure 43.8 43.8
Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34MHz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. The load capacitance connected to the CLKOUT pin should be a maximum of 50 pF. 3. tcyc shows 1 cycle time of a CLKOUT clock.
tEXcyc
tEXH
tEXL
EXTAL input
VIH 1/2VCCQ
VIH VIL tEXf VIL
VIH 1/2VCCQ
tEXr
Notes: When the clock is input from EXTAL pin
Figure 43.2 EXTAL Clock Input Timing
tCLKOUTcyc
tCLKOUTH1
tCLKOUTL1
CLKOUT
VOH 1/2VCCQ
VOH VOL tCLKOUTf VOL
VOH 1/2VCCQ
tCLKOUTr
Figure 43.3 CLKOUT Clock Output Timing (1)
Rev. 1.00 Oct. 01, 2007 Page 1835 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
tCLKOUTH2
tCLKOUTL2
CLKOUT
1.5V
1.5V
1.5V
Figure 43.4 CLKOUT Clock Output Timing (2)
Stable oscillation
Internal clock
VDD
VDD min tOSC1
tRESPW
PRESET
tOSCMD tMDRH
MDn
tTRSTRH TRST
BKPRST
STATUS0 STATUS1 tRESH
Stable oscillation
CLKOUT
Note: Oscillation settling time when on-chip resonator is used.
Figure 43.5 Power-On Oscillation Settling Time
Rev. 1.00 Oct. 01, 2007 Page 1836 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
EXTAL input
CLKOUT output
tPLL
Figure 43.6 PLL Synchronization Settling Time
Standby CLKOUT Internal clock tSOC2 Stable oscillation
NMI, IRQ7-IRQ0
Note:
Oscillation setting time when on-chip resonator is used.
Figure 43.7 Oscillation Settling Time on Return from Standby NMI or IRQ
CLKOUT
tRESMS
tRESMW
tRESMH
tRESMS
MRESET
Figure 43.8 Reset Input Timing
Rev. 1.00 Oct. 01, 2007 Page 1837 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.2
Control Signal Timing
Table 43.10 Control Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tBREQS tBREQH tBACKD tBOFF1 tBON1 tSTD Min. 6 3 1 Max. 13 13 13 20 Unit ns ns ns ns ns ns Figure 43.9 43.9 43.9 43.9 43.9 43.10
Item BREQ setup time BREQ hold time BACK delay time Bus three-state delay time Bus buffer on time STATUS0, STATUA1 delay time Note: tcyc : One CLK cycle time
CLKOUT
tBREQH tBREQS
tBREQH
tBREQS
BREQ
tBACKD
tBACKD
BACK
A[25:0], CSn, BS, RDWR, CE2A, CE2B, WEn, RD
tBOFF1
tBON1
Figure 43.9 Control Signal Timing
Rev. 1.00 Oct. 01, 2007 Page 1838 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Normal mode
Standby mode
Normal mode
CLKOUT tSTD STATUS0 STATUS1 tBOFF1
RD, RDWR, CSn, WEn, BS
tBON1
tBOFF1
A25-A0, D15-D0
tBON1
Figure 43.10 Pin Drive Timing in Standby Mode
Rev. 1.00 Oct. 01, 2007 Page 1839 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.3
Bus Timing
Table 43.11 Bus Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tAD tBSD tCSD tRWD tRSD tRDS tRDH tWEDF tWED1 Min. 1 1 1 1 1 6 2 1 Max. Unit Remarks Figure 13 13 13 13 13 13 13 ns ns ns ns ns ns ns ns ns 43.11 to 43.21, 43.26, 43.27 43.11 to 43.27 43.11 to 43.27 43.11 to 43.27 43.11 to 43.19, 43.26, 43.27 43.11 to 43.22, 43.24, 43.26, 43.27 43.11 to 43.22, 43.24, 43.26, 43.27 43.11 to 43.14, 43.19, 43.26, 43.27 43.11 to 43.14, 43.19, 43.22, 43.23, 43.26, 43.27 43.11 to 43.14, 43.19 to 43.25 43.12, 43.13, 43.16, 43.18 to 43.27 43.12, 43.13, 43.16, 43.18 to 43.27 MPX 43.22 to 43.25
Item Address delay time BS delay time CSn delay time RDWR delay time RD delay time Read data setup time Read data hold time WEn delay time (falling edge)* WEn delay time
Write data delay time RDY setup time RDY hold time FRAME delay time IOIS16 setup time IOIS16 hold time IOWR delay time (falling edge) IORD delay time Note: *
tWDD tRDYS tRDYH tFMD tIO16S tIO16H tIOWSDF tIORSD
1 6 2.5 1 6 2.5 1 1
13 13 13 13
ns ns ns ns ns ns ns ns
PCMCIA 43.20, 43.21 PCMCIA 43.20, 43.21 PCMCIA 43.20, 43.21 PCMCIA 43.20, 43.21
Delay time from the rising edge of CLKOUT
Rev. 1.00 Oct. 01, 2007 Page 1840 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
T1 CLKOUT
T2
tAD
A25-A0
tAD tCSD tRWD
tCSD
CSn
tRWD
RDWR
tRSD
RD D31-D0 (read)
tRSD
tRSD
tRDS tWED1 tWEDF tWDD tWEDF tWDD
tRDH
WEn
tWDD
D31-D0 (write)
tBSD
BS
tBSD
RDY
tDACD
DACK
tDACD
Figure 43.11 SRAM Bus Cycle: Basic Bus Cycle (No Wait)
Rev. 1.00 Oct. 01, 2007 Page 1841 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
T1 CLKOUT
Tw
T2
tAD
A25-A0
tAD
tCSD
CSn
tCSD
tRWD
RDWR
tRWD
tRSD
RD
tRSD
tRSD
D31-D0
tRDS tWED1
tRDH
(read)
tWEDF
tWEDF
WEn
tWDD
D31-D0
tWDD
tWDD
(write)
tBSD
BS
tBSD
tRDYS
RDY
tRDYH
tDACD
DACK
tDACD
Figure 43.12 SRAM Bus Cycle: Basic Bus Cycle (One Wait only by Software)
Rev. 1.00 Oct. 01, 2007 Page 1842 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
T1 CLKOUT
Tw
Twe
T2
tAD
A25-A0
tAD
tCSD
CSn
tCSD
tRWD
RDWR
tRWD
tRSD
RD
tRSD
tRSD
D31-D0 (read)
tRDS tWED1
tRDH
tWEDF
tWEDF
WEn
tWDD
D31-D0 (write)
tWDD
tWDD
tBSD
BS
tBSD
tRDYS
RDY
tRDYH tRDYS tRDYH tDACD
DACK
tDACD
Figure 43.13 SRAM Bus Cycle: Basic Bus Cycle (One Wait by Software + One Wait by RDY, RDY Signal is Synchronous Input)
Rev. 1.00 Oct. 01, 2007 Page 1843 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
TS1
CLKOUT
T1
T2
TH1
tAD
A25-A0
tAD
CSn
tCSD
tCSD
tRWD
RDWR
tRWD
tRSD
RD
tRSD
tRSD
D31-D0 (read)
tRDS
tWED1
tRDH
WEn
tWEDF
tWEDF
tWDD
D31-D0 (write)
tWDD
tWDD
tBSD
BS
tBSD
RDY
DACK
tDACD
tDACD
Figure 43.14 SRAM Bus Cycle: Basic Bus Cycle (No Wait, No Address Setup/Hold Time Insertion, RDS = 1, RDH = 0, WTS = 1, WTH = 1)
Rev. 1.00 Oct. 01, 2007 Page 1844 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
T1
TB2
TB1
TB2
TB1
TB2
TB1
T2
CLKOUT
tAD
tAD
A25-A5
tAD
A4-A0
tCSD
tCSD tRWD
CSn
tRWD
RDWR RD D31-D0 (read)
tRSD
tRSD
tRSD
tRDS
tRDH
tRDS
tRDH
tBSD
tBSD
BS RDY
tDACD tDACD
DACK
Figure 43.15 Burst ROM Bus Cycle (No Wait)
Rev. 1.00 Oct. 01, 2007 Page 1845 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
tRWD
tRDH
tAD
tRSD
tRDYH
Twb
tRDS
Twb
TB2
TB1
Twb
TB2
TB1
TB1
tAD
tRDH
tRDYS
TB2
Twe
tRDS
tRDYH
Tw
tRSD
tRDYS
tCSD
tRWD
CLKOUT
D31-D0 (read)
A25-A5
RDWR
A4-A0
tBSD
tAD
T1
tDACD
DACK
Figure 43.16 Burst ROM Bus Cycle (1st Data: One Wait by Software + One Wait by RDY; 2nd/3rd/4th Data: One Wait only by software)
Rev. 1.00 Oct. 01, 2007 Page 1846 of 1956 REJ09B0256-0100
RDY
CSn
RD
BS
tRDYS
tRDYH
tDACD
T2
tCSD
Section 43 Electrical Characteristics
tRWD
tCSD
tRSD
tAD
tRDH
TB1
TB2
TH1
TS1
TB1
TB2
TH1
TS1
TB1
TS1
tAD
TH1
TB2
tRSD
tRDS
tRDH
tRDS
T2
tBSD
T1
TS1
tAD
tRWD
tCSD
CLKOUT
D31-D0 (read)
A25-A5
RDWR
A4-A0
tBSD
tDACD
DACK RDY BS
CSn
Figure 43.17 Burst ROM Bus Cycle (No Wait, No Address Setup/Hold Time Insertion, RDS = 1, RDH = 0)
Rev. 1.00 Oct. 01, 2007 Page 1847 of 1956 REJ09B0256-0100
RD
tDACD
TH1
REJ09B0256-0100
Twe TB2 TB1 Twb Twbe
TB2
T1
Tw
TB1
Twb
Twb
Twbe
TB2
TB1
Twbe
T2
CLKOUT
tAD
tAD
tAD
A25-A5
Section 43 Electrical Characteristics
A4-A0
Rev. 1.00 Oct. 01, 2007 Page 1848 of 1956
tCSD
CSn
tCSD
RDWR
tRWD
tRWD
tRSD
tRSD
tRSD
RD
D31-D0 (read)
tRDS
tRDH
tBSD
tRDS
tBSD
tRDH
tBSD
tBSD
BS
tRDYS
tRDYH
tRDYH
tRDYS
tRDYH
tRDYS
RDY
tRDYS
tRDYH
tDACD
tDACD
Figure 43.18 Burst ROM Bus Cycle (One Wait by Software + One Wait by RDY)
DACK
Section 43 Electrical Characteristics
Tpcm1 CLKOUT
Tpcm2
Tpcm0
Tpcm1
Tpcm1w
Tpcm1w
Tpcm2
Tpcm2w
tAD
A25-A0
tAD tCSD tRWD
tAD tCSD tRWD
tAD tCSD tRWD
tCSD
CExx PCC_REG (WE0)
tRWD
RDWR
tRSD
RD D15-D0 (read)
tRSD tRDS
tRSD tRDH
tRSD
tRSD tRDS tRDH tWEDF
tRSD
tWED1
WE1
tWEDF tWDD
tWEDF tWDD
tWED1 tWDD tWDD tBSD tBSD
tWEDF
D15-D0 (write)
tWDD tBSD
tWDD
BS
tBSD
tRDYS
RDY
tRDYH tRDYS tRDYH tDACD
tDACD
DACK
tDACD
tDACD
(1) TED = 0, TEH = 0, No Wait
(2) TED = 1, TEH = 1, One Internal Wait + One External Wait
Figure 43.19 PCMCIA Memory Bus Cycle
Rev. 1.00 Oct. 01, 2007 Page 1849 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Tpci1 CLKOUT
Tpci2
Tpci0
Tpci1
Tpci1w
Tpci1w
Tpci2
Tpci2w
tAD
A25-A0
tAD tCSD tRWD
tAD tCSD tRWD
tAD tCSD tRWD
tCSD
CExx PCC_REG (WE0)
tRWD
RDWR
tIORSD tIORSD
IORD (WE2) D15-D0 (read)
tIORSD tRDH tIOWSDF tWDD
tIORSD tRDS tIOWSDF
tIORSD
tRDS tIOWSDF tIOWSDF
tRDH tIOWSDF tWDD
IOWR (WE3)
tWDD
D15-D0 (write)
tWDD
tWDD tBSD
tBSD
BS RDY
tBSD
tBSD tRDYS tRDYH tRDYS tRDYH tIO16H tDACD
tIO16S
IOIS16
tIO16H tDACD tDACD
tDACD
DACK
tIO16S
(1) TED = 0, TEH = 0, No Wait
(2) TED = 1, TEH = 1, One Internal Wait + One External Wait
Figure 43.20 PCMCIA I/O Bus Cycle
Rev. 1.00 Oct. 01, 2007 Page 1850 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Tpci0 CLKOUT
Tpci1
Tpci1w
Tpci2
Tpci2w
Tpci0
Tpci1
Tpci1w
Tpci2
Tpci2w
tAD
A25-A1
tAD
tAD
A0 CExx PCCREG (WE0)
tCSD
tCSD
tCSD
tRWD
RDWR
tRWD
tIORSD
tRDS
tIORSD
IORD (WE2) D15-D0 (read)
tIORSD
tRDH
tIOWSDF tIOWSDF
IOWR (WE3)
tIOWSDF
tIOWSDF
tIOWSDF
D15-D0 (write)
tWDD
tWDD
tWDD
tWDD
tWDD
tBSD
BS
tBSD
tRDYS tRDYH tRDYS tRDYH
RDY
IOIS16
tIO16S tIO16H
Figure 43.21 PCMCIA I/O Bus Cycle (TEDA/TEDB = 1, TEHA/TEHB = 1, IW/PCIW = 1, Dynamic Bus Sizing)
Rev. 1.00 Oct. 01, 2007 Page 1851 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Tm1 CLKOUT
Tmd1w
Tmd1
Tm0
Tmd1w
Tmd1w
Tmd1
tFMD
RD/FRAME
tFMD tWDD tRDS
D0
tFMD tRDH tWDD
A
tFMD tWDD tRDS
D0
tWDD
D31-D0 A
tRDH
tCSD
CSn
tCSD tRWD
tCSD tRWD
tCSD tRWD
tRWD
RDWR WE
tWED1 tRDYS tRDYH
tWED1
tWED1 tRDYS tRDYH tRDYS tRDYH
tWED1
RDY
tBSD
tBSD
tBSD
tBSD
BS
tDACD
DACK
tDACD
tDACD
tDACD
(1) 1st Data : One Internal Wait 1st data bus cycle information D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 1xx: Burst (32 bytes) D25-D0: Address
(2) 1st Data : One Internal Wait + One External Wait 1st data bus cycle information D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 1xx: Burst (32 bytes) D25-D0: Address
Figure 43.22 MPX Basic Bus Cycle: Read
Rev. 1.00 Oct. 01, 2007 Page 1852 of 1956 REJ09B0256-0100
Tm1
Tmd1
Tm1
Tmd1w
Tmd1
Tm1
Tmd1w
Tmd1we
Tmd1
CLKOUT
tFMD
tWDD
A
tFMD
tWDD
D0
A
tFMD
tFMD
tFMD
tWDD
D0
tFMD
tWDD
D0
A
RD/FRAME
tWDD
tWDD
tWDD
tWDD
tWDD
D31-D0
tCSD
tCSD
tCSD
tRWD
tRWD
tRWD
tCSD
tCSD
tCSD
tRWD
CSn
tRWD
tRWD
tWED1
RDWR
WE
tWED1
tWED1
tWED1
tWED1
tWED1
tRDYS
tRDYH
tRDYS
tRDYH
tBSD
tRDYS
tRDYH
tRDYH
RDY
tBSD
tBSD
tBSD
tBSD
tRDYS tBSD
BS
tDACD
tDACD
tDACD
tDACD
tDACD
tDACD
Figure 43.23 MPX Basic Bus Cycle: Write
(1) 1st Data : No Wait 1st data bus cycle information D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 1xx: Burst (32 bytes) D25-D0: Address (2) 1st Data : One Internal Wait 1st data bus cycle information D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 1xx: Burst (32 bytes) D25-D0: Address
DACK
(3) 1st Data : One Internal Wait + One External Wait 1st data bus cycle information D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 1xx: Burst (32 bytes) D25-D0: Address
Section 43 Electrical Characteristics
Rev. 1.00 Oct. 01, 2007 Page 1853 of 1956
REJ09B0256-0100
REJ09B0256-0100
Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 Tm1 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8we Tmd8
Tm1
Tmd1w
Tmd1
CLKOUT
RD/ FRAME
tFMD tRDH
D1 D2 D3 D4 D5 D6 D7 D8 A D1 D2
tFMD tWDD tWDD tRDS tRDH
D3
tFMD
tFMD
Section 43 Electrical Characteristics
tWDD tCSD tRWD tRWD tRDYS tBSD tDACD tDACD tBSD tRDYH tCSD
D31-D0
tWDD tRDS
A
D7
D8
tCSD
tCSD tRWD tRDYS tRDYH
Rev. 1.00 Oct. 01, 2007 Page 1854 of 1956
tDACD
(2) 1st Data : One Internal Wait, 2nd to 8th Data : No Internal Wait + External Wait Control 1st data bus cycle information
CSn
tRWD
RDWR
tRDYS
tRDYH
RDY
tBSD
tBSD
BS
tDACD
DACK
Figure 43.24 MPX Bus Cycle: Burst Read
D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 1xx: Burst (32 bytes) D25-D0: Address
(1) 1st Data : One Internal Wait, 2nd to 8th Data : No Internal Wait 1st data bus cycle information
D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 1xx: Burst (32 bytes) D25-D0: Address
Tm1
Tmd1
Tmd2
Tmd3
Tmd4
Tmd5
Tmd6
Tmd7
Tmd8
Tm1
Tmd1w
Tmd1
Tmd2w
Tmd2
Tmd3
Tmd7
Tmd8we
Tmd8
CLKOUT
RD/ FRAME
tFMD
tFMD
tFMD
tWDD
D3
tFMD
tWDD
D1
tWDD
D4
D5
tWDD
D6 D7
D8
A
tWDD
D2
D3
tWDD
D7 D8
D31-D0
A
D1
D2
tCSD
tRWD
tRDYS
tRDYH
tRWD
tCSD
tCSD
tCSD
tRWD
tRDYS
tRDYH
CSn
tRWD
RDWR
tRDYS
tBSD
tBSD
tRDYH
RDY
tBSD
tBSD
BS
tDACD
tDACD
tDACD
tDACD
DACK
(1) No Internal Wait
Figure 43.25 MPX Bus Cycle: Burst Write
D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 1xx: Burst (32 bytes) D25-D0: Address
1st data bus cycle information
(2) 1st Data : One Internal Wait, 2nd to 8th Data : No Internal Wait + External Wait Control 1st data bus cycle information
Section 43 Electrical Characteristics
D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 1xx: Burst (32 bytes) D25-D0: Address
Rev. 1.00 Oct. 01, 2007 Page 1855 of 1956
REJ09B0256-0100
T1
T2
T1
Tw
T2
T1
Tw
Twe
T2
REJ09B0256-0100
tAD
tAD
tAD
tAD
tAD
tAD
CLKOUT
A25-A0
tCSD
tCSD
tCSD
tRWD
tRSD
tRDS
tCSD
tRWD
tRSD
tRDH
tCSD
tRWD
tCSD
tRWD
Section 43 Electrical Characteristics
CSn
tRWD
tRSD
tRSD
tRSD
tRWD
tRSD
tRSD
RDWR
Rev. 1.00 Oct. 01, 2007 Page 1856 of 1956
tRSD
tRDS
tRSD
tRDH
RD
D31-D0 (read)
tRDS
tRDH
tWED1
tWEDF
tWED1
tBSD
tBSD
tWED1
tWEDF
tWED1
tWED1
tWEDF
tBSD
tWED1
WE
tBSD
tBSD
tBSD
BS
tRDYS
tRDYH
tDACD
tDACD
tRDYS
tRDYS
tRDYH
tRDYH tDACD
RDY
Figure 43.26 Byte Control SRAM Bus Cycle
tDACD
tDACD
tDACD
DACK
(1) Basic Read Cycle : No Wait
(2) Basic Read Cycle : One Internal Wait
(3) Basic Read Cycle : One Internal Wait + One External Wait
Section 43 Electrical Characteristics
TS1
T1
T2
TH1
CLKOUT
tAD
A25-A0
tAD
tCSD
CSn
tCSD
tRWD
RDWR
tRWD
tRSD
RD D31-D0 (read)
tRSD
tRDS
tRSD
tRDH
tWED1
tWEDF
tWED1
WE
tBSD
BS
tBSD
RDY
tDACD
DACK
tDACD
Figure 43.27 Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, No Address Setup/Hold Time Insertion, RDS = 1, RDH = 0)
Rev. 1.00 Oct. 01, 2007 Page 1857 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.4
DDRIF Signal Timing
Table 43.12 DDRIF Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tMCLK tMCLKH tMCLKL tADCTLS Min. 10 7.5 M_CLK output high-level pulse width M_CLK output low-level pulse width Address and command signal setup time to M_CLK rising edge 0.45 0.45 1.5 1.2 1.5 1.2 -0.8 M_DQSn-to-M_Dn skew (read) tRMDQSQ -- -- Write command to first M_DQSn delay tWMDQSS time (rising edge) M_DQSn falling edge setup time to M_CLK rising edge (write) M_DQSn falling edge hold time to M_CLK rising edge (write) M_DQS high-level pulse width (write) M_DQS low-level pulse width (write) M_Dn and M_DQMn setup time to M_DQSn rising edge (write) M_Dn and M_DQMn hold time to M_DQSn rising edge (write) Note: tMCLK : One M_CLK cycle time tWDSS tWDSH tWMDQSH tWMDQSL tWDS tWDH 0.75 0.25 0.25 0.35 0.35 1.0 0.75 1.0 0.75 Max. 12 12 0.55 0.55 -- -- -- -- 1.0 0.8 0.7 0.6 1.2 -- -- -- -- -- -- -- -- ns 43.30 tMCLK tMCLK tMCLK tMCLK tMCLK ns 43.30 43.30 43.30 43.30 43.30 43.30 DDR200 DDR266 DDR200 DDR266 ns 43.29 ns ns tMCLK tMCLK ns 43.28 43.28 43.29, 43.30 43.29, 43.30 43.29 DDR200 DDR266 DDR200 DDR266 DDR200 DDR266 DDR200 DDR266 Unit ns Figure Remarks 43.28 DDR200 DDR266
Item M_CLK output cycle
Address and command signal hold time tADCTLH to M_CLK rising edge M_CLK-to-M_DQSn skew time (read)
tRMDQS-MCLK -1.0
Rev. 1.00 Oct. 01, 2007 Page 1858 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
tMCLK
M_CLK1
tMCLKH
M_CLK0 tMCLKL
Figure 43.28 DDRIF MCLK Output Timing
M_CLK1 M_CLK0 tADCTLS tADCTLH M_CKE, M_CS, M_WE, M_BAn, M_RAS, M_CAS, M_A13-M_A0 tRMDQS-MCLK (Min)
M_DQSn
M_D31-M_D0
D0
D1
D2
D3
tRMDQSQ tRMDQS-MCLK (Max)
M_DQSn
M_D31-M_D0
D0
D1
D2
D3
tRMDQSQ
Figure 43.29 Read Timing of DDR-SDRAM (2 Burst Read)
Rev. 1.00 Oct. 01, 2007 Page 1859 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
M_CLK1 M_CLK0 tADCTLS tADCTLH M_CKE, M_CS, M_WE, M_BAn, M_RAS, M_CAS, M_A13-M_A0 Write command tWMDQSS (Min) tWDSS tWDSH
M_DQSn tWMDQSH tWMDQSL
M_D31-M_D0, M_DQMn
D0 tWDS tWDH
D1
D2
D3
tWMDQSS (Max)
tWDSS tWDSH
M_DQSn tWMDQSH tWMDQSL
M_D31-M_D0, M_DQMn
D0 tWDS tWDH
D1
D2
D3
Figure 43.30 Write Timing of DDR-SDRAM (2 Burst Write)
Rev. 1.00 Oct. 01, 2007 Page 1860 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.5
INTC Module Signal Timing
Table 43.13 INTC Module Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tNMIH tNMIL Min. 5 5 8 3 8 3 15 8 -- Max. -- -- -- -- -- -- -- -- 13 Unit tcyc tcyc ns ns ns ns ns ns ns Figure Remarks 43.31 43.31 43.32 43.32 43.32 43.32 43.32 43.32 43.32 normal mode sleep mode NMI pulse width (Low) normal mode sleep mode IRQ7/IRL7 to IRQ0/IRL0 setup time tIRQS IRQ7/IRL7 to IRQ0/IRL0 hold time tIRQH tIRLH tGPIOS tGPIOH tIRQOD IRQ7/IRL7 to IRQ0/IRL0 setup time tIRLS IRQ7/IRL7 to IRQ0/IRL0 hold time PINTn interrupt setup PINTn interrupt hold time IRQOUT output delay time Note: tcyc: One CLKOUT cycle time IRQ input IRQ input IRL input IRL input GPIO interrupt input GPIO interrupt input IRQOUT output
Item NMI pulse width (High)
tNMIH
tNMIL
NMI
Figure 43.31 NMI Input Timing
Rev. 1.00 Oct. 01, 2007 Page 1861 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
CLKOUT
IRQn/IRLn, PINTn
tIRQS tIRLS tGPIOS
tIRQH tIRLH tGPIOH
IRQOUT
tIRQOD
Figure 43.32 IRQ/IRL, PINT Input and IRQOUT Output Timing
Rev. 1.00 Oct. 01, 2007 Page 1862 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.6
External CPU Interface Read/Write Access Timing
Table 43.14 External CPU Interface Access Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Item Symbol Min. 6 3 1 6 3 1 6 3 6 3 6 3 6 3 1 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- 13 -- -- 13 -- -- -- -- -- -- -- -- 13 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 43.33 43.33 43.33 43.33 43.33 43.33 43.33 43.33 43.33 43.33 43.33 43.33 43.33 43.33 43.33
External CPU bus release request (BREQ) tSEBRQ setup time External CPU bus release request (BREQ) tTMS hold time External CPU bus request acknowledge (BACK) delay time Address/write data setup time Address/write data hold time Read data delay time EX_CSn setup time EX_CSn hold time EX_BS setup time EX_BS hold time EX_FRAME setup time EX_FRAME hold time EX_RDWR setup time EX_RDWR hold time EX_RDY delay time tDEBAK tSEDA tHEDA tDED tSECS tHECS tSEBS tHEBS tSEFR tHEFR tSERW tHERW tDERY
Rev. 1.00 Oct. 01, 2007 Page 1863 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
CLKOUT
BREQ
tSEBRQ
tHEBRQ
BACK
tDEBAK
tDEBAK
EX_AD31-EX_AD0 (write) EX_AD31-EX_AD0 (read)
tSEDA tHEDA tSEDA
tHEDA
tSEDA tHEDA
tDED
tDED
EX_CSn
tSECS
tHECS
EX_BS
tSEBS tHEBS
EX_FRAME
tSEFR
tHEFR
EX_RDWR
tSERW
tHERW
EX_RDY
tDERY
tDERY tDERY
Figure 43.33 External CPU Interface Read/Write Access Timing
Rev. 1.00 Oct. 01, 2007 Page 1864 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.7
PCIC Module Signal Timing
Table 43.15 PCIC Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
33 MHz Pin PCICLK Item Clock cycle Clock pulse width (high) Clock pulse width (low) Clock rise time Clock fall time PCIRESET IDSEL AD31 to AD0 Output delay time Input setup time Input hold time Output data delay time Symbol tPCICYC tPCIHIGH tPCILOW tPCIr tPCIf tPCIRES tPCISU tPCIH tPCIVAL Min. 30 11 11 -- -- -- 4 0 -- -- -- 4 0 Max. -- -- -- 4 4 14 -- -- 10 10 12 -- -- 15 6 6 -- -- -- 4 0 -- -- -- 4 0 66 MHz Min. Max. 30 -- -- 1.5 1.5 14 -- -- 10 10 12 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 43.34 43.34 43.34 43.34 43.34 -- 43.36 43.36 43.35 43.35 43.35 43.36 43.36
CBE3 to CBE0 Tri-state drive delay time tPCION PAR Tri-state high-impedance tPCIOFF delay time PCIFRAME IRDY , TRDY STOP, LOCK DEVSEL PERR REQ0/ REQOUT Output data delay time tPCIVAL Input setup time Input hold time tPCISU tPCIH
-- -- -- 4 0 -- -- 4 0
10 10 12 -- -- 10 12 -- --
-- -- -- 4 0 -- -- 4 0
10 10 12 -- -- 10 12 -- --
ns ns ns ns ns ns ns ns ns
43.35 43.35 43.35 43.36 43.36 43.35 43.35 43.36 43.36
Tri-state drive delay time tPCION REQ3 to REQ1 Tri-state high-impedance tPCIOFF GNT0/GNTIN delay time GNT3 to GNT1 Input setup time tPCISU Input hold time SERR INTA to INTD Tri-state drive delay time tPCIH tPCION
Tri-state high-impedance tPCIOFF delay time Input setup time Input hold time tPCISU tPCIH
Note: When the ratio of the clocks (SHwy clock : PCICLK clock) is in the ranges of (2.1 : 1) to (3.3 : 1), the PCIC cannot be used.
Rev. 1.00 Oct. 01, 2007 Page 1865 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
tPCICYC
tPCIHIGH PCICLK VH VH VL tPCIf
tPCILOW VH 0.5VDDQ VL tPCIr
0.5VDDQ
Figure 43.34 PCI Clock Input Timing
PCICLK
0.4VDDQ
tPCIVAL Output delay 0.4VDDQ
Tri-state output
tPCION tPCIOFF
Figure 46.35 Output Signal Timing
PCICLK
0.4VDDQ tPCISU tPCIH 0.4VDDQ
Input
0.4VDDQ
Figure 43.36 Input Signal Timing
Rev. 1.00 Oct. 01, 2007 Page 1866 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.8
DMAC Module Signal Timing
Table 43.16 DMAC Module Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tDRQS tDRQH tTENDD tDACKD Min. 6 5 -- -- Max. -- -- 13 13 Unit ns ns ns ns Figure 43.37 43.37 43.37 43.37 Remarks
Item DREQn setup time DREQn hold time TENDn delay time DACKn delay time
CLKOUT
tDRQH
DREQ
tDRQH tDRQS
tDRQS
TEND, DACK
tTENDD tDACKD
Figure 43.37 DREQ, TEND, and DACK Timing
Rev. 1.00 Oct. 01, 2007 Page 1867 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.9
TMU Module Signal Timing
Table 43.17 TMU Module Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tTCLKWH tTCLKWL tTCLKr tTCLKf Min. 4 4 -- -- Max. -- -- 0.8 0.8 Unit tPcyc0 tPcyc0 tPcyc0 tPcyc0 Figure Remarks 43.38 43.38 43.38 43.38
Item Timer clock pulse width (High) Timer clock pulse width (Low) Timer clock rise time Timer clock fall time Note: tPcyc0: One Pck0 cycle time
TCLK tTCLKWH tTCLKWL tTCLKf tTCLKr
Figure 43.38 TCLK Input Timing
Rev. 1.00 Oct. 01, 2007 Page 1868 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.10 16-bit Timer Pulse Unit (TPU) Timing Table 43.18 16-bit Timer Pulse Unit Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tTOD tTCKS tTCKWH, tTCKWL tTCKWH, tTCKWL Min. -- 15 2 3 Max. 15 -- -- -- Unit Ns ns tPcyc0* tPcyc0* Figure Remarks 43.39 43.40 43.40 43.40
Item Timer output delay Timer clock input setup time Timer clock Count at rising or falling pulse width edge Count at both edge Note: *
tPcyc0 is a cycle time of a peripheral clock 0 (Pck0).
CLKOUT tTOD TPU_TO0, TPU_TO1, TPU_TO2, TPU_TO3
Figure 43.39 TPU Output Timing
CLKOUT tTCKS TPU_TI2A, TPU_TI2B, TPU_TI3A, TPU_TI3B tTCKWL tTCKWH tTCKS
Figure 43.40 TPU Clock Input Timing
Rev. 1.00 Oct. 01, 2007 Page 1869 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.11 GETHER Module Signal Timing (1) Ethernet Controller Signal Timing (MII)
Table 43.19 Ethernet Controller Signal Timing (MII) Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tTcyc tTEND tTEDD tRcyc tRDVS tRDVH tERDS tERDH tERRS tERRH tWOLD Min. 40 3 3 40 10 3 10 3 10 3 1 Typ. -- -- -- -- -- -- -- -- -- -- -- Max. -- 20 20 -- -- -- -- -- -- -- 18 Unit ns ns ns ns ns ns ns ns ns ns ns Figure 43.41 43.41 43.41 43.42 43.42 43.42 43.42 43.42 43.43 43.43 43.44
Item ETn_TX-CLK cycle time ETn_TX-EN output delay time ETn_ETXD[3:0] output delay time ETn_RX-CLK cycle time ETn_RX-DV setup time ETn_RX-DV hold time ETn_ERXD[3:0] setup time ETn_ERXD[3:0] hold time ETn_RX-ER setup time ETn_RX-ER hold time ETn_WOL output delay time
Rev. 1.00 Oct. 01, 2007 Page 1870 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
ETn_TX-CLK
tTEND
ETn_TX-EN tETDD ETn_ETXD3 to ETn_ETXD0
Preamble
SFD
DATA
CRC
ETn_TX-ER
ETn_CRS
ETn_COL
Figure 43.41 MII Transmit Timing (normal operation)
ETn_RX-CLK
tRDVS tRDVH
ETn_RX-DV
tERDS
tERDH
ETn_ERXD3 to ETn_ERXD0
ETn_RX-ER
Preamble
SFD
DATA
CRC
Figure 43.42 MII Receive Timing (normal operation)
Rev. 1.00 Oct. 01, 2007 Page 1871 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
ETn_RX-CLK ETn_RX-DV ETn_ERXD3 to ETn_ERXD0
Preamble
SFD
DATA
tRERS
tRERH
XXXX
ETn_RX-ER
Figure 43.43 MII Receive Timing (When an Error is Detected)
ETn_RX-CLK
tWOLD ETn_WOL
Figure 43.44 WOL Output Timing (2) Ethernet Controller Signal Timing (GMII)
Table 43.20 Ethernet Controller Signal Timing (GMII) Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol Min. tGtcyc tGTEND tGETDD tGRcyc tGRDVS tGRDVH tGERDS 8 0.5 0.5 8 2.5 0.5 2.5 Typ. -- -- -- -- -- -- -- Max. -- 5.5 5.5 -- -- -- -- Unit ns ns ns ns ns ns ns Figure 43.45 43.45 43.45 43.46 43.46 43.46 43.46
Item GETn_GTX-CLK cycle time Etn_TX-EN output delay time GETn_ETXD[7:4], ETn_ETXD[3:0] output delay time ETn_RX-CLK cycle time ETn_RX-DV setup time ETn_RX-DV hold time GETn_ERXD[7:4], ETn_ERXD[3:0] setup time
Rev. 1.00 Oct. 01, 2007 Page 1872 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Item GETn_ERXD[7:4], ETn_ERXD[3:0] hold time ETn_RX-ER setup time ETn_RX-ER hold time ETn_WOL output delay time
Symbol Min. tGERDH tGRERS tGRERH tGWOLD 0.5 2.5 0.5 0
Typ. -- -- -- --
Max. -- -- -- 18
Unit ns ns ns ns
Figure 43.46 43.47 43.47 43.48
GETn_GTX_CLK
tGTEND
ETn_TX-EN tGETDD GETn_ETXD7 to GETn_ETXD4, ETn_ETXD3 to ETn_ETXD0
Preamble
SFD
DATA
CRC
ETn_TX-ER
ETn_CRS
ETn_COL
Figure 43.45 GMII Transmit Timing (normal operation)
ETn_RX-CLK tGRDVS ETn_RX-DV tGERDS GETn_ERXD7 to GETn_ERXD4, ETn_ERXD3 to ETn_ERXD0 Preamble SFD DATA CRC tGRDVH
tGERDH
ETn_RX-ER
Figure 43.46 GMII Receive Timing (normal operation)
Rev. 1.00 Oct. 01, 2007 Page 1873 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
ETN_RX-CLK ETn_RX-DV GETn_ERXD7 to GETn_ERXD4, ETn_ERXD3 to ETn_ERXD0
Preamble
SFD
DATA tGRERS tGRERH
XXXX
ETn_RX-ER
Figure 43.47 GMII Receive Timing (When an Error is Detected)
ETn_RX-CLK
tGWOLD ETn_WOL
Figure 43.48 WOL Output Timing (3) Ethernet Controller Signal Timing (RMII)
Table 43.21 Ethernet Controller Signal Timing (RMII) Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol Min. tRtcyc tRTEND 20 2.5 2.5 Typ. -- -- -- Max. -- 10 10 Unit ns ns ns Figure 43.49 43.49 43.49
Item REF50CK cycle time RMIIn_TXD-EN, RMII1M_TXD-EN output delay time
RMIIn_TXD1, RMIIn_TXD0, tRETDD RMII1M_TXD1, RMII1M_TXD0 output delay time RMIIn_CRS_DV, RMII1M_CRS_DV setup time RMIIn_CRS_DV, RMII1M_CRS_DV hold time RMIIn_RXD1, RMIIn_RXD0, RMII1M_RXD1, RMII1M_RXD0 setup time tRRDVS tRRDVH tRERDS
4 2.5 4
-- -- --
-- -- --
ns ns ns
43.50 43.50 43.50
Rev. 1.00 Oct. 01, 2007 Page 1874 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Item RMIIn_RXD1, RMIIn_RXD0, RMII1M_RXD1, RMII1M_RXD0 hold time RMIIn_RX_ER setup time RMIIn_RX_ER hold time
Symbol Min. tRERDH tRRERS tRRERH 2.5 4 2.5
Typ. -- -- --
Max. -- -- --
Unit ns ns ns
Figure 43.50 43.51 43.51
REF50CK tRTEND RMIIn_TXD_EN RMII1M_TXD_EN tRETDD RMIIn_TXD1, RMIIn_TXD0 RMII1M_TXD1, RMII1M_TXD0
Preamble
SFD
DATA
CRC
Figure 43.49 RMII Transmit Timing
REF50CK
tRRDVS
RMIIn_CRS_DV, RMII1M_CRS_DV
tRRDVH
tRERDH
tRERDS
RMIIn_RXD1, RMIIn_RXD0 RMII1M_RXD1, RMII1M_RXD0 Preamble
SFD
DATA
CRC
RMIIn_RX_ER, RMII1M_RX_ER
Figure 43.50 RMII Receive Timing (normal operation)
Rev. 1.00 Oct. 01, 2007 Page 1875 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
REF50CK RMIIn_CRS_DV, RMII1M_CRS_DV RMIIn_RXD1, RMIIn_RXD0 RMII1M_RXD1, RMII1M_RXD0 Preamble SFD DATA tRRERS tRRERH XXXX
RMIIn_RX_ER, RMII1M_RX_ER
Figure 43.51 RMII Receive Timing (When an Error is Detected) 43.4.12 Stream Interface Module Timing (1) Clock Valid Reception
Table 43.22 STIF Clock Valid Reception Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tSTCYC tSTRQD tSTSTS tSTSTH tSTVLS tSTVLH tSTDS tSTDH Min. 30 4 7 4 7 4 7 4 Max. -- 21 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns Figure 43.52 43.52 43.52 43.52 43.52 43.52 43.52 43.52
Item ST_CLK cycle time ST_REQ delay time ST_START setup time ST_START hold time ST_VALID setup time ST_VALID hold time ST_DATA setup time ST_DATA hold time
Rev. 1.00 Oct. 01, 2007 Page 1876 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
tSTCYC
STn_CLK ST0M_CLKIO STn_REQ ST0M_REQ0 STn_START ST0M_STARTI STn_VALID ST0M_VALIDI
tSTDS tSTDH tSTRQD tSTSTS tSTSTH
tSTVLS
tSTVLH
STn_D7_STn_D0 ST0M_D7I_ST0M_D0I
Figure 43.52 STIF Clock Valid Receive Timing (2) Clock Valid Transmission
Table 43.23 STIF Clock Valid Transmission Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tSTCYC tSTRQS tSTRQH tSTSTD tSTVLD tSTDD Min. 30 7 5 3 3 3 Max. -- -- -- 21 21 21 Unit ns ns ns ns ns ns Figure 43.53 43.53 43.53 43.53 43.53 43.53
Item ST_CLK cycle time ST_REQ setup time ST_REQ hold time ST_START delay time ST_VALID delay time ST_DATA delay time
Rev. 1.00 Oct. 01, 2007 Page 1877 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
tSTCYC
STn_CLK
tSTRQS
tSTRQH
STn_REQ
tSTSTD
STn_START
tSTVLD
STn_VALID
tSTDD
STn_DC[7:0]
Figure 43.53 STIF Clock Valid Transmit Timing (3) Strobe Reception
Table 43.24 STIF Strobe Reception Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tSTSLW tSTSHW tSTRQD tSTDS tSTDH Min. 30 30 0 7 4 Max. -- -- -- -- -- Unit ns ns ns ns ns Figure 43.54 43.54 43.54 43.54 43.54
Item ST_STRB low level width ST_STRB high level width ST_REQ output delay time ST_DATA setup time ST_DATA hold time
tSTSHW
STn_STRB ST0M_STRBI STn_REQ ST0M_REQO
tSTSLW tSTDS tSTDH
tSTRQD
STn_D7_STn_D0 ST0M_D7I_ST0M_D0I
Figure 43.54 STIF Strobe Receive Timing
Rev. 1.00 Oct. 01, 2007 Page 1878 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
(4)
Strobe Transmission
Table 43.25 STIF Strobe Transmission Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tSTRQRDH tSTSRRQD tSTRQSRH tSTSTSRD tSTDSRD Min. 0 2 0 -2 -1 Max. -- 3 -- -- -- Unit ns tSTYCYC ns ns ns Figure 43.55 43.55 43.55 43.55 43.55
Item STn_REQ hold time to STn_VALID STn_STRB delay time from STn_REQ STn_STRB hold time from STn_REQ ST_START delay time from STn_STRB ST_DATA delay time from STn_STRB
STn_VALID
tSTRQRDH
STn_REQ
tSTSRRQD tSTRQSRH
STn_STRB
tSTSTSRD
STn_START
tSTDSRD
STn_D7_STn_D0
Figure 43.55 STIF Strobe Transmit Timing
Rev. 1.00 Oct. 01, 2007 Page 1879 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.13 I2C Bus Interface Timing Table 43.26 I2C Bus Interface Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tICYC tICF tICBF tICH tICS tICST tDAS tICDH Min. 0 1.3 0.6 0.6 0.6 100 0 Typ. Max. Unit 400 300 0.9 kHz ns ns ns ns ns ns ns Figure 43.56, 43.57 RP*CB = 257 x 10-9 to 275 x 10-9 [*pF] VPU = 3.3V
Item IICn_SCL frequency IICn_SCL, IICn_SDA fall time IICn_SDA input bus free time IICn_SCL start condition input hold time IICn_SCL retransmission start condition input setup time IICn_SDA stop condition input setup time IICn_SDA setup time IICn_SDA hold time
Rev. 1.00 Oct. 01, 2007 Page 1880 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
P
S tICBF
Sr
P
IICn_SDA
tICST
tICF
tICH
tICS
tDAS
IICn_SCL
tICDH
tICF
tICYC
* S, P, and Sr indicate as below. S: Start condition P: Stop condition Sr: Retransmission start condition 0
Figure 43.56 I2C Bus Interface Input/Output Timing
This LSI
VPU RP
IICn_SDA IICn_SCL
CB
Figure 43.57 AC Characteristic Load Condition
Rev. 1.00 Oct. 01, 2007 Page 1881 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.14 SCIF Module Signal Timing Table 43.27 SCIF Module Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tScyc tSCKW tSCKr tSCKf tTXD tRXS tRXH Min. 8 24 0.4 -- -- -- 4 x tPcyc0 4 x tPcyc0 Max. -- -- 0.6 0.8 0.8 6 x tPcyc0 + 50 -- -- Unit tPcyc0 tPcyc0 tPcyc0 tPcyc0 tPcyc0 ns ns ns Figure 43.58 43.58 43.58 43.58 43.58 43.59 43.59 43.59
Item Input clock cycle (asynchronous) Input clock cycle (synchronous) Input clock pulse width Input clock rise time Input clock fall time Transfer data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) Note: tPcyc0: One Pck0 cycle time
tSCKW SCIFn_SCK tScyc tSCKf tSCKr
Figure 43.58 SCIFn_SCK Input Clock Timing
Rev. 1.00 Oct. 01, 2007 Page 1882 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
tScyc SCIFn_SCK tTXD SCIFn_TXD tTXD
SCIFn_RXD tRXS tRXH
Figure 43.59 SCIFn I/O Synchronous Mode Clock Timing
Rev. 1.00 Oct. 01, 2007 Page 1883 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.15 SIOF Module Signal Timing Table 43.28 SIOF Module Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tMCYC tMWH tMWL tSICYC tSWHO tSWLO tFSD tSWHI tSWLI tFSS tFSH tSTDD tSRDS tSRDH Min. 2 x tPcyc0* 0.4 x tMCYC 0.4 x tMCYC 2 x tPcyc0* 0.4 x tMCYC 0.4 x tMCYC 0.4 x tSICYC 0.4 x tSICYC 20 20 20 20 Max. 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 43.60 43.60 43.60 43.61 to 43.65 43.61 to 43.64 43.61 to 43.64 43.61 to 43.64 43.65 43.65 43.65 43.65 43.61 to 43.65 43.61 to 43.65 43.61 to 43.65
Item SIOFn_MCK clock input cycle time SIOFn_MCK input high level width SIOFn_MCK input low level width SIOFn_SCK clock cycle time SIOFn_SCK output high level width SIOFn_SCK output low level width SIOFn_SYNC output delay time SIOFn_SCK input high level width SIOFn_SCK input low level width SIOFn_SYNC input setup time SIOFn_SYNC input hold time SIOFn_TXD output delay time SIOFn_RXD input setup time SIOFn_RXD input hold time Note: *
tPcyc0 is a cycle time of a peripheral clock 0(Pck0).
tMCYC
SIOF_MCLK
tMWH
tMWL
Figure 43.60 SIOF_MCLK Input Timing
Rev. 1.00 Oct. 01, 2007 Page 1884 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
tSICYC tSWHO
SIOF_SCK (output)
tSWLO
tFSD
SIOF_SYNC (output)
tFSD
tSTDD
SIOF_TXD
tSTDD
tSRDS
SIOF_RXD
tSRDH
Figure 43.61 SIOF Transmission/Reception Timing (Master Mode 1, Sampling at the Falling Edge)
tSICYC tSWLO
SIOF_SCK (output)
tSWHO
tFSD
SIOF_SYNC (output)
tFSD
tSTDD
SIOF_TXD
tSTDD
tSRDS
SIOF_RXD
tSRDH
Figure 43.62 SIOF Transmission/Reception Timing (Master Mode 1, Sampling at the Rising Edge)
Rev. 1.00 Oct. 01, 2007 Page 1885 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
tSICYC tSWHO
SIOF_SCK (output)
tSWLO
tFSD
SIOF_SYNC (output)
tFSD
tSTDD
SIOF_TXD
tSTDD
tSTDD
tSTDD
tSRDS
SIOF_RXD
tSRDH
Figure 43.63 SIOF Transmission/Reception Timing (Master Mode 2, Sampling at the Falling Edge)
tSICYC tSWLO
SIOF_SCK (output)
tSWHO
tFSD
SIOF_SYNC (output)
tFSD
tSTDD
SIOF_TXD
tSTDD
tSTDD
tSTDD
tSRDS
SIOF_RXD
tSRDH
Figure 43.64 SIOF Transmission/Reception Timing (Master Mode 2, Sampling at the Rising Edge)
Rev. 1.00 Oct. 01, 2007 Page 1886 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
tSICYC tSWHI
SIOF_SCK (input)
tSWLI
tFSS
SIOF_SYNC (input)
tFSH
tSTDD
SIOF_TXD
tSTDD
tSRDS
SIOF_RXD
tSRDH
Figure 43.65 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2)
Rev. 1.00 Oct. 01, 2007 Page 1887 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.16 SIM Module Signal Timing Table 43.29 SIM Module Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tSMCYC tSMCWH tSMCWL tSMRD Min. 2/tPcyc0 0.4 x tSMCYC 0.4 x tSMCYC Max. 16/tPcyc0 20 Unit ns ns ns ns Figure 43.66
Item SIM_CLK clock cycle SIM_CLK clock high level width SIM_CLK clock low level width SIM_RST reset output delay
Note: tPcyc0 is a cycle time of a peripheral clock (Pch0).
tSMCWH
SIM_CLK
tSMCYC
tSMCWL tSMRD
SIM_RST
tSMRD
Figure 43.66 SIM Module Signal Timing
Rev. 1.00 Oct. 01, 2007 Page 1888 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.17 MMCIF Module Signal Timing Table 43.30 MMCIF Module Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tMMCYC tMMWH tMMWL tMMCD tMMRCS tMMRCH tMMTDD tMMRDS tMMRDH Min. 60 0.4 x tMMCYC 0.4 x tMMcyc -- 10 10 -- 10 10 Max. -- -- -- 10 -- -- 10 -- -- Unit ns ns ns ns ns ns ns ns ns Figure 43.67 43.67 43.67 43.67 43.68 43.68 43.67 43.68 43.68
Item MMC_CLK clock cycle time MMC_CLK clock high level width MMC_CLK clock low level width MMC_CMD output data delay time MMC_CMD input data setup time MMC_CMD input data hold time MMC_DAT output data delay time MMC_DAT input data setup time MMC_DAT input data hold time
tMMCYC tMMWL
MMC_CLK
tMMWH
tMMCD
MMC_CMD (output)
tMMCD
tMMTDD
MMC_DAT (output)
tMMTDD
Figure 43.67 MMCIF Transmit Timing
Rev. 1.00 Oct. 01, 2007 Page 1889 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
MMC_CLK
tMMRCS
tMMRCH
MMC_CMD (input)
tMMRDS
MMC_DAT (input)
tMMRDH
Figure 43.68 MMCIF Receive Timing (Sampling at the Rising Edge)
Rev. 1.00 Oct. 01, 2007 Page 1890 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.18 HAC Interface Module Signal Timing Table 43.31 HAC Interface Module Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tRST_LOW tSYN_HIGH tSYNCD1 tSYNCD2 tSDOUTD tSDINS tSDINH tICL_HIGH tICL_LOW Min. 1000 1000 0 0 0 10 10 tPcyc0 tPcyc0 Max. -- -- 15 15 15 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns Figure 43.69 43.70 43.72 43.72 43.72 43.72 43.72 43.71 43.71
Item HAC_RES active low pulse width HAC_SYNC active high pulse width HAC_SYNC delay time 1 HAC_SYNC delay time 2 HAC_SD_OUT delay time HAC_SD_IN setup time HAC_SD_IN hold time HAC_BITCLK input high level width HAC_BITCLK input low level width Note: tPcyc0: One Pck0 cycle time
tRST_LOW
HAC_RES
Figure 43.69 HAC Cold Reset Timing
tSYN_HIGH
HAC_SYNC
Figure 43.70 HAC SYNC Output Timing
Rev. 1.00 Oct. 01, 2007 Page 1891 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
tICL_HIGH
HAC_BITCLK tICL_LOW
Figure 43.71 HAC Clock Input Timing
tSDINS
HAC_BITCLK
HAC_SD_IN
tSDINH
tSDOUTD
HAC_SD_OUT
tSYNCD1
HAC_SYNC
tSYNCD2
Figure 43.72 HAC Interface Module Signal Timing
Rev. 1.00 Oct. 01, 2007 Page 1892 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.19 SSI Interface Module Signal Timing Table 43.32 SSI Interface Module Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol Min. tOSCK tISCK tIHC/tOHC 60 60 15 15 -- -- 10 10 Max. 960 3300 -- -- 10 25 -- -- Unit ns ns ns ns ns ns ns ns Remarks output input Figure 43.73 43.73
Item Output cycle time Input cycle time Input high level width/Output high level width
input, output 43.73 input, output 43.73 output transmit receive receive 43.73 43.74, 43.75 43.76, 43.77 43.76, 43.77
Input low level width/Output low level tILC/tOLC width SSI_SCK output rise time SSI_SDATA/WS output delay time SSI_SDATA/WS input setup time SSI_SDATA/WS input hold time tRC tDTR tSR tHTR
tOHC tIHC VIH, VOH VIL, VOL VIH, VOH VIL, VOL tISCK, tOSCK tOLC tILC
tRC VIH, VOH VIL, VOL
SSI_SCK
Figure 43.73 SSI Clock Input/Output Timing
SSI_SCK tDTR SSI_WS, SSI_SDATA
Figure 43.74 SSI Transmit Timing (1)
Rev. 1.00 Oct. 01, 2007 Page 1893 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
SSI_SCK tDTR SSI_WS, SSI_SDATA
Figure 43.75 SSI Transmit Timing (2)
SSI_SCK tSR SSI_WS, SSI_SDATA tHTR
Figure 43.76 SSI Receive Timing (1)
SSI_SCK tHTR SSI_WS, SSI_SDATA tSR
Figure 43.77 SSI Receive Timing (2)
Rev. 1.00 Oct. 01, 2007 Page 1894 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.20 USB Module Signal Timing Table 43.33 USB Module Clock Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tFREQ tR48 tF48 tDUTY Min. 47.9 90 Max. 48.1 4 4 110 Unit MHz ns ns % Figure 43.78
Item USB_CLK external input clock frequency (48 MHz) Clock rise time Clock fall time Duty (tHIGH/tLOW)
tFREQ tHIGH
USB_CLK (input) 90% 10%
tLOW
tR48
tF48
Figure 43.78 USB Clock Timing Table 43.34 USB Electrical Characteristics (Full-Speed)
Item Transition time (rise)*2 Transition time (fall)*
2
Symbol tR tF tRFM
Min. 4 4 90 1.3
Max. 20 20 111 2.0
Unit ns ns % V
Condition*1 CL = 50 pF CL = 50 pF (TR/TF)
Rise/fall time matching
Output signal crossover power supply voltage VCRS
Notes: Measured with edge control CEDGE = 47 pF and connection of direct resister Rs = 22 . 1. Value when CL = 50 pF unless specified. 2. Value within 10% to 90% of the signal power supply voltage.
Rev. 1.00 Oct. 01, 2007 Page 1895 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
Table 43.35 USB Electrical Characteristics (Low-Speed)
Item Transition time (rise)* Symbol tR tF tRFM Min. 75 Transition time (fall)* 75 Rise/fall time matching 80 1.3 Output signal crossover power supply voltage VCRS Max. 300 300 125 2.0 Unit ns ns ns ns % V Condition CL = 200 pF CL = 600 pF CL = 200 pF CL = 600 pF (TR/TF)
Notes: Measured with edge control CEDGE = 47 pF and connection of direct resister Rs = 22 . * Value within 10% to 90% of the signal power supply voltage.
43.4.21 LCDC Module Signal Timing Table 43.36 LCDC Module Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tFREQ tr tf tDUTY tCC tCHW tCLW tCT tDDdo tIDdo tVDdo Min. 90 25 7 7 -3.5 -3.5 -3.5 -3.5 Max. 66 3 3 110 3 3 3 3 3 Unit MHz ns ns % ns ns ns ns ns ns ns ns 43.79 Figure
Item LCD_CLK input clock frequency LCD_CLK input clock rise time LCD_CLK input clock fall time LCD_CLK input clock duty Clock (LCD_CL2) cycle time Clock (LCD_CL2) high level pulse width Clock (LCD_CL2) low level pulse width Clock (LCD_CL2) transition time (rise/fall) Data (LCD_DATA) delay time Display enable (LCD_M_DISP) delay time
Horizontal synchronous signal (LCD_CL1) delay time tHDdo Vertical synchronous signal (LCD_FLM) delay time
Rev. 1.00 Oct. 01, 2007 Page 1896 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
tCHW
LCD_CL2
0.8Vcc 0.2Vcc
tCLW
tCT
tCT
tCC
tDD
LCD_DATA0 to LCD_DATA15
tDT
0.8Vcc 0.2Vcc
tDT
tID
LCD_M_DISP
tIT
0.8Vcc 0.2Vcc
tIT
tHD
LCD_CL1
tHT
0.8Vcc 0.2Vcc
tHT
tVD
LCD_FLM
tVT
0.8Vcc 0.2Vcc
tVT
Figure 43.79 LCDC Module Signal Timing 43.4.22 GPIO Signal Timing Table 43.37 GPIO Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tIOPD tIOPS tIOPH Min. 0 15 5 Max. 15 -- -- Unit ns ns ns Figure 43.80 43.80 43.80
Item GPIO output delay time GPIO input setup time GPIO input hold time
CLKOUT tIOPD GPIO output tIOPS GPIO input tIOPH
Figure 43.80 GPIO Timing
Rev. 1.00 Oct. 01, 2007 Page 1897 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.4.23 H-UDI Module Signal Timing Table 43.38 H-UDI Module Signal Timing Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Symbol tTCKcyc tTCKH tTCKL tTCKr tTCKf tASEBRKS tASEBRKH tTDIS tTDIH tTDO tPINBRK Min. 50 15 15 -- -- 10 10 15 15 0 2 Max. -- -- -- 10 10 -- -- -- -- 10 -- Unit ns ns ns ns ns tcyc tcyc ns ns ns tPcyc0 Figure 43.81, 43.83 43.81 43.81 43.81 43.81 43.82 43.82 43.83 43.83 43.83 43.84
Item Input clock cycle Input clock pulse width (High) Input clock pulse width (Low) Input clock rise time Input clock fall time ASEBRK setup time ASEBRK hold time TDI/TMS setup time TDI/TMS hold time TDO data delay time ASEBRK pin break pulse width Notes: 1. tcyc: One CLKOUT cycle time 2. tPcyc0: One Pck0 cycle time
tTCKcyc tTCKH tTCKL VIH 1/2VCCQ tTCKr
TCK
1/2VCCQ
VIH
VIH VIL tTCKf
VIL
Note: When clock is input from TCK pin.
Figure 43.81 TCK Input Timing
Rev. 1.00 Oct. 01, 2007 Page 1898 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
PRESET
tASEBRKS ASEBRK/ BRKACK
tASEBRKH
Figure 43.82 PRESET Hold Timing
tTCKcyc
TCK
TDI TMS
tTDIS
tTDIH
TDO
tTDO
Figure 43.83 H-UDI Data Transfer Timing
tPINBRK ASEBRK
Figure 43.84 ASEBRK Pin Break Timing
Rev. 1.00 Oct. 01, 2007 Page 1899 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.5
43.5.1
A/D, D/A Converter Characteristics
A/D Converter Characteristics
Table 43.39 A/D Converter Characteristics Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Min. 10 8.5 Typ. 10 Max. 10 20 3.5 4.0 Unit bits s pF k LSB
Item Resolution Conversion time Analog input capacitance
Permissible signal source (single source) impedance Absolute accuracy
43.5.2
D/A Converter Characteristics
Table 43.40 D/A Converter Characteristics Conditions: VCCQ = VDD_RTC = AVCC = 3.0 to 3.6 V, VCCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to 1.35 V, Ta = -20 to 75C
Min. 8 Typ. 8 Max. 8 10.0 4.0 Unit bits s LSB 20 pF capacitive load 2 M resistance load Test Conditions
Item Resolution Conversion time Absolute accuracy
Rev. 1.00 Oct. 01, 2007 Page 1900 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.6
AC Characteristic Test Conditions
The AC characteristic test conditions are as follows: * Input/output signal reference level: V*/2 * Input pulse level: VSSQ to V* * Input rise/fall time: 1 ns Note: V*: VCCQ, VCCQ -DDR (VDDQ = 3.0 to 3.6V, VCCQ_DDR = 2.3 to 2.7V) The output load circuit is shown in figure 43.85
IOL *3
VTT=DDR-VREF
(DDR pins only)
RT LSI output pin CL
DUT output
Reference level
IOH
Notes: 1. CL = 30pF (All pins). CL is the total value that includes the capacitance of measurement instruments. The capacitance of each pin is set to 30 pF. 2. RT = 50 (DDR pins only) 3. IOL = 7.6 mA (DDR pins), 4 mA (PCI pins), 2 mA (Other output pins) IOH = -7.6 mA (DDR pins), -4 mA (PCI pins), -2 mA (Other output pins)
Figure 43.85 Output Load Circuit
Rev. 1.00 Oct. 01, 2007 Page 1901 of 1956 REJ09B0256-0100
Section 43 Electrical Characteristics
43.7
Change in Delay Time Based on Load Capacitance
Figure 43.86 is a chart showing the changes in the delay time (reference data) when a load capacitance equal to or larger than the stipulated value (30 pF) is connected to the LSI pins. When connecting an external device with a load capacitance exceeding the regulation, use the chart in figure 43.86 as reference for system design. Note that if the load capacitance to be connected exceeds the range shown in figure 43.86 the graph will not be a straight line.
+4.0 ns
+3.0 ns
Delay time
+2.0 ns
+1.0 ns
+0.0 ns +0 pF
+25 pF Load capacitance
+50 pF
Figure 43.86 Load Capacitance - Delay Time
Rev. 1.00 Oct. 01, 2007 Page 1902 of 1956 REJ09B0256-0100
Appendix
Appendix
A. CPU Operation Mode Register (CPUOPM)
The CPUOPM is used to control the CPU operation mode. This register can be read from or written to the address H'FF2F0000 in P4 area or H'1F2F0000in area 7 as 32-bit size. The write value to the reserved bits should be the initial value. The operation is not guaranteed if the write value is not the initial value. The CPUOPM register should be updated by the CPU store instruction not the access from SuperHyway bus master except CPU. After the CPUOPM is updated, read CPUOPM once, and execute one of the following two methods. 1. Execute a branch using the RTE instruction. 2. Execute the ICBI instruction for any address (including non-cacheable area). After one of these methods are executed, it is guaranteed that the CPU runs under the updated CPUOPM value.
Bit: Initial value: R/W: Bit: Initial value: R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
RABD
0 R 4
0 R 3
INTMU
0 R 2
0 R 1
0 R 0
0 R
0 R
0 R
0 R
0 R
0 R
1 R
1 R
1 R
1 R
1 R/W
0 R
0 R/W
0 R
0 R
0 R
Rev. 1.00 Oct. 01, 2007 Page 1903 of 1956 REJ09B0256-0100
Appendix
Bit 31 to 6 5
Bit Name RABD
Initial Value
R/W
Description Reserved The write value must be the initial value. Speculative execution bit for subroutine return 0: Instruction fetch for subroutine return is issued speculatively. When this bit is set to 0, refer to appendix C, Speculative Execution for Subroutine Return. 1: Instruction fetch for subroutine return is not issued speculatively.
H'000000F R 1 R/W
4 3
INTMU
0 0
R R/W
Reserved The write value must be the initial value. Interrupt mode switch bit 0: SR.IMASK is not changed when an interrupt is accepted. 1: SR.IMASK is changed to the accepted interrupt level.
2 to 0
All 0
R
Reserved The write value must be the initial value.
Rev. 1.00 Oct. 01, 2007 Page 1904 of 1956 REJ09B0256-0100
Appendix
B.
Instruction Prefetching and Its Side Effects
This LSI is provided with an internal buffer for holding pre-read instructions, and always performs pre-reading. Therefore, program code must not be located in the last 64-byte area of any memory space. If program code is located in these areas, a bus access for instruction prefetch may occur exceeding the memory areas boundary. A case in which this is a problem is shown below.
Address : H'03FF FFF8 H'03FF FFFA H'03FF FFFC H'03FF FFFE H'4000 0000 H'4000 0002 Instruction : ADD R1,R4 JMP @R2 NOP NOP
PC (Program Counter)
Area 0 Area 1
Instruction prefetch address
Figure B.1 Instruction Prefetch Figure B.1 presupposes a case in which the instruction (ADD) indicated by the program counter (PC) and the address H'04000002 instruction prefetch are executed simultaneously. It is also assumed that the program branches to an area other than area 1 after executing the following JMP instruction and delay slot instruction. In this case, a bus access (instruction prefetch) to area 1 may unintentionally occur from the programming flow. Instruction Prefetch Side Effects: 1. It is possible that an external bus access caused by an instruction prefetch may result in misoperation of an external device, such as a FIFO, connected to the area concerned. 2. If there is no device to reply to an external bus request caused by an instruction prefetch, hangup will occur. Remedies: 1. These illegal instruction fetches can be avoided by using the MMU. 2. The problem can be avoided by not locating program code in the last 64 bytes of any area.
Rev. 1.00 Oct. 01, 2007 Page 1905 of 1956 REJ09B0256-0100
Appendix
C.
Speculative Execution for Subroutine Return
The SH-4A has the mechanism to issue an instruction fetch speculatively when returning from subroutine. By issueing an instruction fetch speculatively, the execution cycles to return from subroutine may be shortened. This function is enabled by setting 0 to the bit 5 (RABD) of CPU Operation Mode register (CPUOPM). But this speculative instruction fetch may issue the access to the address that should not be accessed from the program. Therefore a bus access to an unexpected area or an internal instruction address error may cause a problem. As for the effect of this bus access to unexpected memory area, refer to appendix B, Instruction Prefetching and Its Side Effects. Usage Condition: When the speculative execution for subroutine return is enabled, the RTS instruction should be used to return to the address set in PR by the JSR, BSR or BSRF instructions. It can prevent the access to unexpected address and avoid the problem.
Rev. 1.00 Oct. 01, 2007 Page 1906 of 1956 REJ09B0256-0100
Appendix
D.
List of Mode Control Pins and Schematic Diagram of External Cicuits
Table D.1 shows the list of mode control pins of this LSI. Table D.1 Mode Control Pins
Pin Name MD0, MD1, and MD2 MD3 and MD4 MD5 MD6 MD8 MD10 MPMD Function Mode control pins 0,1 and 2 Mode control pins 3 and 4 I/O Input Input Description Selects the clock-operating mode at a power-on reset. Selects the bus width and MPX interface of area 0 at a power-on reset Selects the endian at a power-on reset Selects the PCI operating mode at a poweron reset. Selects whether to use the crystal resonator at a power-on reset. Selects the external CPU at a power-on reset Selects either emulation support mode or LSI operation mode at a power-on reset.
Mode control pin Input 5 Mode control pin Input 6 Mode control pin Input 8 Mode control pin Input 10 Chip mode control pin Input
The state of the mode control pins of this LSI is sampled white a power-on reset is applied. Therefore, these pins can serve as other functions in the other periods. The method for switching between the control functions and other functions should be examined referring to figure D.1. See section 40, General Purpose I/O (GPIO), or the relevant sections of the applicable modules for whether the pins of the other functions are the input, output, or input/output pins.
Rev. 1.00 Oct. 01, 2007 Page 1907 of 1956 REJ09B0256-0100
Appendix
When the device to e connected is supplied with input
MDn This LSI PRESET Mode settings (high or low level) Power-on reset from system
Device to be connected
When the device to be connected supplies outputs
MDn This LSI PRESET Mode settings (high or low level)
Devicce to be connected
Power-on reset from system
When the device to be connected is supplied with inputs or supplies outputs
MDn This LSI PRESET Mode settings (high or low level)
Device to be connected
I/O control signal
Power-on reset from system
Figure D.1 Schematic Diagram of External Circuits
Rev. 1.00 Oct. 01, 2007 Page 1908 of 1956 REJ09B0256-0100
Appendix
E.
Notes on Board Design
A multi-layer ceramic capacitor should be used as a bypass capacitor for each pair of a Vss or a Vdd power supply pin and a Vcc pin. The following table shows the pairs of a Vss or Vdd power supply pin and a Vcc pin in terms of the specific pin numbers.
Power Supply Pin Pair for Internal circuits: 1.25V (Vdd - V CC) Vss/Vdd Pin Number V1 V2 V3 V4 V5 W5 AA9 AA10 AA11 W21 U21 N21 K21 G21 D20 E16 E8 DDR-SDRAM I/O: 2.5V (VCCQ-DDR - VSSQ-DDR B1 C2 E4 E5 G4 G5 K4 K5 N4 Vcc Pin Number K10 L10 M10 N10 P10 Y5 R10 T10 T11 V21 T21 M21 J21 F21 E20 E17 E9 B2 C3 F4 F5 H4 H5 J4 J5 P4
Rev. 1.00 Oct. 01, 2007 Page 1909 of 1956 REJ09B0256-0100
Appendix
Power Supply Pin Pair for DDR-SDRAM I/O: 2.5V (VCCQ-DDR - VSSQ-DDR
Vss/Vdd Pin Number N5 R4 R5 T4 T5 D11 E11 D8 D7 E7 C4 D3 A2
Vcc Pin Number P5 T3 U3 U4 U5 D10 E10 D9 D6 E6 D5 D4 A1 AE1 AD2 AC3 AB4 AA5 AA7 AA14 AB14 AA16 AA17 AA19 AA21 AB22 AA22 P21 B23 A24 A25
I/O: 3.3V (VCCQ - VSSQ
AE2 AD3 AC4 AB5 AA6 AA8 AA12 AA13 AA15 AB15 AA18 AA20 Y21 AB23 R21 L21 H21 E21
Rev. 1.00 Oct. 01, 2007 Page 1910 of 1956 REJ09B0256-0100
Appendix
Power Supply Pin Pair for I/O: 3.3V (VCCQ - VSSQ
Vss/Vdd Pin Number C21 D22 E18 D16 E14 AD23 C13
Vcc Pin Number C22 D21 E19 E15 D14 AE25 D13 AC23/T16* L4 L5 AD24 AD21 AD20 E12
Analog circuits: 3.3V (AVcc-AVss DLL: 1.25V (Vcc-DLL - Vss-DLL) PLL: 1.25V (Vcc-PLL - Vss-PLL)
AD25/AA25/AA24* M4 M5 AE24 AE21 AE20
RTC: 3.3V (VDD-RTC - VSS-RTC) Note *
D12
See figure E.1, Connection Exmple of Bypass Capacitors for Analog Power Supply.
This LSI AD25 (AVcc)
AVcc
0.1F 0.1F 0.1F
AA25 (AVcc) AA24 (AVcc)
AC23 (AVss)
T16 (AVss)
Figure E.1 Connection Example of Bypass Capacitors for Analog Power Supply
Rev. 1.00 Oct. 01, 2007 Page 1911 of 1956 REJ09B0256-0100
Appendix
F.
0.30 C B
Package Dimensions
21.00
Unit : mm
0.30 C A
25 23 21 19 17 15 13 11 9 7 5 3 1 24 22 20 18 16 14 12 10 8 6 4 2
0.80
A B D F H C E G J L N R U
(Index)
21.00
B
K M P T V
0.90
W Y AA AB AC AD AE
4x
0.35 C
0.20
0.80
0.90
A
449 x 0.50 0.05 C 0.08 M C AB
0.15
C
Figure F.1 Package Dimensions (449-Pin)
Rev. 1.00 Oct. 01, 2007 Page 1912 of 1956 REJ09B0256-0100
2.0 Max
0.4 0.05
Appendix
G.
Pin States
Pin States
Power-On Reset Pin Name M_CLK0 M_CLK1 M_WE M_RAS M_BA0 M_A10 M_A1 M_A3 XTAL2 USBM I/O O O O O O O O O O IO MD6 = 0 O O H H L L L L O I I MD6 = 1 O O H H L L L L O I I Manual Reset O O H H L L L L O I I/I/IO/I/I/I Bus Release O O O O O O O O O I I/I/IO/I/I/I
Table G.1
Pin No. A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
Standby O O O O O O O O O I I
PTI2/ I/I/IO/I/I/I ST0M_STARTI/ IIC0_SCL/ SIOF1_RXD/ USB_OVRCRT/ USBF_VBUS PTI0/STATUS0/ IO/O/IO/O ST1_CLK/ RMII0_MDC
A15
H
H
P/O/O/O
Z/O/Z/O
P/O/IO/O
A16
PTK4/ST1_D4/ IO/IO/I/O/O M GET0_ERXD4/ SIOF2_TXD/ LCD_D6 PTI6/IRQ2/ IRL2/ ST0M_D6I/ IIC1_SCL PTJ5/ ST0M_D3I/ ET0_ERXD3/ RMII1_RXD0/ LCD_DON I/I/I/I/IO I
M
P/IV/I/O/O Z/Z/Z/Z/O
P/IO/I/O/O
A17
I
I/I/I/I/IO
I
I/I/I/I/IO
A18
IO/I/I/I/O
M
M
P/IV/I/I/O
Z/Z/Z/Z/O
P/I/I/I/O
Rev. 1.00 Oct. 01, 2007 Page 1913 of 1956 REJ09B0256-0100
Appendix
Pin No. A19
Power-On Reset Pin Name I/O MD6 = 0 M MD6 = 1 M
Manual Reset P/O/I/I
Standby Z/Z/Z/I
Bus Release P/IO/I/I
PTJ1/ IO/IO/I/I ST0M_CLKIO/ RMII1_RX_ER/ LCK_CLK CS5/CE1A PTM6/D30/ EX_AD30/ ST0_D6/ ET0_RX-CLK/ RMII0_TXD1/ PINT6 PTM4/D28/ EX_AD28/ ST0_D4/ ET0_PHY-INT/ RMII0_RXD0/ PINT4 CS0 M_BKPRST M_CKE M_A13 M_CAS M_CS M_BA1 M_A0 M_A2 M_A4 EXTAL2 USBP PTI3/ ST0M_VALIDI/ IIC0_SDA/ SIOF1_MCLK/ USB_CLK O/O IO/IO/IO/ IO/IO/I
A20 A21
H Z
H Z
H P/Z/Z/IV/I/ O/IV
Z Z
ZV P/Z/Z/IO/I/ O/I
A22
IO/IO/IO/ IO/I/I/I
Z
Z
P/Z/Z/IV/I/I/ Z IV
P/Z/Z/IO/I/ I/I
A23 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14
O I O O O O O O O O I IO I/I/IO/I/I
H M O L H H L L L L I I I
H M O L H H L L L L I I I
H M O L H H L L L L I I I/I/IO/I/I
Z M O O O O O O O O I I I
ZV I O O O O O O O O I I I/I/IO/I/I
Rev. 1.00 Oct. 01, 2007 Page 1914 of 1956 REJ09B0256-0100
Appendix
Pin No. B15
Power-On Reset Pin Name I/O MD6 = 0 MD6 = 1 M
Manual Reset
Standby
Bus Release P/IO/I/I/O
PTK7/ST1_D7/ IO/IO/I/I/O M GET0_ERXD7/ SIOF2_MXLK/ LCD_VCPWC PTI5/MD10/ ST1_VALID/ LCD_D1 PTI7/IRQ3/ IRL3/ ST0M_D7I/ IIC1_SDA PTJ4/ ST0M_D2I/ ET0_ERXD2/ RMII1_RXD1/ LCD_CL2 RDY/EX_RDY/ PCC_WAIT CS2/EX_CS1 PTM7/D31/ EX_AD31/ ST0_D7/ ET0_RX-DV/ RMII0_TXD0/ PINT7 IO/I/IO/O I
P/IV/I/IV/O Z/Z/Z/Z/O
B16
I
P/-/I/O
Z/-/Z/O
P/-/IO/O
B17
I/I/I/I/IO
I
I
I/I/I/I/IO
I
I/I/I/I/IO
B18
IO/I/I/I/O
M
M
P/IV/I/I/O
Z/Z/Z/Z/O
P/I/I/I/O
B19 B20 B21
I/O/I O/I IO/IO/IO/ IO/I/O/I
M H Z
M H Z
IV/O/IV H/I P/Z/Z/IV/I/ O/IV
IV/O/IV Z Z
IV/O/IV ZV P/Z/Z/IO/I/ O/I
B22
PTM5/D29/ IO/IO/IO/ EX_AD29/ IO/I/O/I ST0_D5/ ET0/RX-ER/ RMII0_TXD_EN /PINT5 PTM3/D27/ IO/IO/IO/ EX_AD27/ IO/I/I/I ST0_D3/ ET0_LINKSTA/ RMII0_RXD1/ PINT3
Z
Z
P/Z/Z/IV/I/ O/IV
Z
P/Z/Z/IO/I/ O/I
B24
Z
Z
P/Z/Z/IV/I/I/ Z IV
P/Z/Z/IO/I/ I/I
Rev. 1.00 Oct. 01, 2007 Page 1915 of 1956 REJ09B0256-0100
Appendix
Pin No. B25
Power-On Reset Pin Name REF125CK/ SSI_CLK/ HAC_BITCLK M_D0 M_A12 M_A11 M_A9 M_A8 M_A7 M_A6 M_A5 XRTCSTBI I/O I/I/I MD6 = 0 I MD6 = 1 I
Manual Reset I/I/I
Standby I
Bus Release I/I/I
C1 C5 C6 C7 C8 C9 C10 C11 C12 C14
IO O O O O O O O I
Z L L L L L L L I
Z L L L L L L L I H
Z L L L L L L L I P/O/O/I
Z O O O O O O O I Z/O/Z/Z
IO O O O O O O O I P/O/IO/IO
PTI1/STATUS1/ IO/O/IO/IO H ST1_REQ/ RMII0_MDIO PTK6/ST1_D6/ IO/IO/I/IO/ M GET0_ERXD6/ O SIOF2_SCK/ LCD_VEPWC PTI4/MD8/ IO/I/IO/I/O/ I ST1_START/ O/O ET1_PHY-INT/ RMII0M0_MDC/ USB_PWREN/ USBF_UPLUP PTJ7/INTB/ ST0M_D5I/ IRQOUT/ IRMII1_TXD0/ LCD_D0 PTJ3/ ST0M_D1I/ ET0_ERXD1/ RMII1_CRS_ DV/LCD_CL1 CS6/CE1B IO/I/I/O/O/ M O
C15
M
P/IV/I/O/O Z/Z/Z/Z/O
P/IO/I/IO/O
C16
I
P/-/I/I/O/ O/O
Z/-/Z/Z/O/ O/O
P/-/IO/I/O/ O/O
C17
M
IO/IV/IV/O/ Z/Z/Z/Z/O/ P/I/I/O/O/O O/O O
C18
IO/I/I/I/O
M
M
P/IV/I/I/O
Z/Z/Z/Z/O
P/I/I/I/O
C19
O/O
H
H
H
Z
ZV
Rev. 1.00 Oct. 01, 2007 Page 1916 of 1956 REJ09B0256-0100
Appendix
Pin No. C20 C23 C24
Power-On Reset Pin Name CS1/EX_CS0 BS/EX_BS PTM2/D26/ EX_AD26/ ST0_D2/ ET0_WOL/ RMII0_CRS_ DV/PINT2 I/O O/I O/I IO/IO/IO/ IO/O/I/I MD6 = 0 H H Z MD6 = 1 H H Z
Manual Reset H/I H/I
Standby Z Z
Bus Release ZV ZV P/Z/Z/IO/ O/I/I
P/Z/Z/IV/O/ Z I/IV
C25
PTM1/D25/ IO/IO/IO/ EX_AD25/ IO/I/I/I ST0_D1/ ET0_TX-CLK/ RMII0_RX_ER/ PINT1 M_D1 M_D16 IO IO
Z
Z
P/Z/Z/IV/I/I/ Z IV
P/Z/Z/IO/I/ I/I
D1 D2 D15
Z Z
Z Z M
Z Z
Z Z
IO IO P/IO/I/I/O
PTK5/ST1_D5/ IO/IO/I/I/O M GET0_ERXD5/ SIOF2_RXD/ LCD_D7 PTJ6/ IO/I/I/O/O ST0M_D4I/ ET0_CRS/ RMII1_TXD_EN /LCD_FLM PTJ2/ ST0M_D0I/ ET0_ERXD0/ RMII1_TXD1/ LCD_M_DISP CS4 PDWR/ EX_RDWR IO/I/I/O/O M
P/IV/I/IV/O Z/Z/Z/Z/O
D17
M
P/IV/I/O/O Z/Z/Z/O/O
P/I/I/O/O
D18
M
M
P/IV/I/O/O Z/Z/Z/O/O
P/I/I/O/O
D19 D23
O O/I
H H
H H
H H/I
Z Z
ZV ZV
Rev. 1.00 Oct. 01, 2007 Page 1917 of 1956 REJ09B0256-0100
Appendix
Pin No. D24
Power-On Reset Pin Name I/O MD6 = 0 Z MD6 = 1 Z
Manual Reset
Standby
Bus Release
PTM0/D24/ IO/IO/IO/ EX_AD24/ IO/O/I/IO ST0_D0/ ET0_TX-ER/ PINT0/ RMII0M0_MDIO PTL7/D23/ EX_AD23/ ST0_VALID/ ET0_TX-EN/ TEND1/ LCD_D15 M_D2 M_D17 M_D18 IO/IO/IO/ IO/O/O/O
P/Z/Z/IV/O/ Z/Z/Z/Z/O/ P/Z/Z/IO/ IV/IV Z/Z O/I/IO
D25
Z
Z
P/Z/Z/IV/O/ Z/Z/Z/Z/O/ P/Z/Z/IO/ O/O O/O O/O/O
E1 E2 E3 E22
IO IO IO
Z Z Z
Z Z Z M
Z Z Z
Z Z Z
IO IO IO P/IO/O/IO/ O
PTK3/ST1_D3/ IO/IO/O/IO/ M GET0_ETXD7/ O SIOF2_SYNC/ LCD_D5 PTK2/ST1_D2/ IO/IO/O/IO/ M GET0_ETXD6/ O SIOF1_SCK/ LCD_D4 PTL6/D22/ EX_AD22/ ST0_START/ ET0_ETXD2/ DACK1/ LCD_D14 PTL5/D21/ EX_AD21/ ST0_CLK/ ET0_ETXD1/ DREQ1/ LCD_D13 M_D3 M_D19 IO/IO/IO/ IO/O/O/O Z
P/IV/O/O/O Z/Z/O/Z/O
E23
M
P/IV/O/O/O Z/Z/O/Z/O
P/IO/O/IO/ O
E24
Z
P/Z/Z/IV/O/ Z/Z/Z/Z/O/ P/Z/Z/IO/ O/O O/O O/O/O
E25
IO/IO/IO/ IO/O/I/O
Z
Z
P/Z/Z/O/O/ Z/Z/Z/Z/O/ P/Z/Z/IO/ IV/O Z/O O/I/O
F1 F2
IO IO
Z Z
Z Z
Z Z
Z Z
IO IO
Rev. 1.00 Oct. 01, 2007 Page 1918 of 1956 REJ09B0256-0100
Appendix
Pin No. F3 F22
Power-On Reset Pin Name M_D20 I/O IO MD6 = 0 Z MD6 = 1 Z M
Manual Reset Z
Standby Z
Bus Release IO P/IO/O/O/ O
PTK1/ST1_D1/ IO/IO/O/O/ M GET0_ETXD5/ O SIOF1_TXD/ LCD_D3 PTK0/ST1_D0/ IO/IO/O/I/ GET0_ETXD4/ O/O SIOF1_SYNC/ LCD_D2 PTL4/D20/ IO/IO/IO/ EX_AD20/ IO/O/I/O ST0_REQ/ ET0_ETXD0/ INTD/LCD_D12 PTJ0/ ST0M_REQO/ GET0_ GTX-CLK/ REF50CK M_D4 M_D21 M_D22 IO/O/O/I M
P/IV/O/O/O Z/Z/O/Z/O
F23
M
P/IV/O/O/O Z/Z/O/Z/O
P/IO/O/IO/ O
F24
Z
Z
P/Z/Z/O/O/ Z/Z/Z/Z/O/ P/Z/Z/IO/ IV/O IV/O O/I/O
F25
M
M
P/O/O/I
Z/Z/O/Z
P/O/O/I
G1 G2 G3 G22
IO IO IO
Z Z Z
Z Z Z Z
Z Z Z P/Z/Z/IV/ IV/I/IV/O
Z Z Z Z/Z/Z/IV/ IV/Z/IV/O
IO IO IO P/Z/Z/I/I/ IO/I/O
PTL3/D19/ IO/IO/IO/I/ Z EX_AD19/ I/IO/I/O IRQ7/IRL7/ ET0_MDIO/ INTC/LCD_D11 PTL2/D18/ EX_AD18/ IRQ6/IRL6/ ET0_ETXD3/ TEND0/ LCD_D10 WE3/IOWR WE2/IORD M_D5 M_D23 IO/IO/IO/I/ Z I/O/O/O
G23
Z
P/Z/Z/IV/ IV/O/O/O
Z/Z/Z/IV/ IV/O/O/O
P/Z/Z/I/I/O/ O/O
G24 G25 H1 H2
O/O O/O IO IO
H H Z Z
H H Z Z
H H Z Z
Z Z Z Z
ZV ZV IO IO
Rev. 1.00 Oct. 01, 2007 Page 1919 of 1956 REJ09B0256-0100
Appendix
Pin No. H3 H22
Power-On Reset Pin Name M_DQS2 PTL0/D16/ EX_AD16/ IRQ4/IRL4/ ET0_COL/ DREQ0/ LCD_D8 PTL1/D17/ EX_AD17/ IRQ5/IRL5/ ET0_MDC/ DACK0/ LCD_D9 D15/EX_AD15 D14/EX_AD14 M_D7 M_D6 M_DQM2 D7/EX_AD7 D6/EX_AD6 D13/EX_AD13 D12/EX_AD12 M_DQM0 M_DQS0 M_DQS3 D5/EX_AD5 D4/EX_AD4 D11/EX_AD11 D10/EX_AD10 M_DQS1 M_DQM1 M_DQM3 D3/EX_AD3 I/O IO MD6 = 0 Z MD6 = 1 Z Z
Manual Reset Z P/Z/Z/IV/ IV/I/IV/O
Standby Z Z/Z/Z/IV/ IV/Z/Z/O
Bus Release IO P/Z/Z/I/I/I/I/ O
IO/IO/IO/I/ Z I/I/I/O
H23
IO/IO/IO/I/ Z I/O/O/O
Z
P/Z/Z/IV/ IV/O/O/O
Z/Z/Z/IV/ IV/O/O/O
P/Z/Z/I/I/O/ O/O
H24 H25 J1 J2 J3 J22 J23 J24 J25 K1 K2 K3 K22 K23 K24 K25 L1 L2 L3 L22
IO/IO IO/IO IO IO O IO/IO IO/IO IO/IO IO/IO O IO IO IO/IO IO/IO IO/IO IO/IO IO O O IO/IO
Z Z Z Z H Z Z Z Z H Z Z Z Z Z Z Z H H Z
Z Z Z Z H Z Z Z Z H Z Z Z Z Z Z Z H H Z
Z Z Z Z H Z Z Z Z H Z Z Z Z Z Z Z H H Z
ZV ZV Z Z O ZV ZV ZV ZV O Z Z ZV ZV ZV ZV Z O O ZV
Z Z IO IO O Z Z Z Z O IO IO Z Z Z Z IO O O Z
Rev. 1.00 Oct. 01, 2007 Page 1920 of 1956 REJ09B0256-0100
Appendix
Pin No. L23 L24 L25 M1 M2 M3 M22 M23 M24 M25 N1 N2 N3 N22 N23 N24 N25 P1 P2 P3 P22 P23 P24 P25 R1 R2 R3 R22 R23
Power-On Reset Pin Name D2/EX_AD2 D9/EX_AD9 D8/EX_AD8 M_D8 M_D24 M_D25 D1/EX_AD1 D0/EX_AD0 WE1/WE CLKOUT M_D9 M_D26 M_D27 RD/FRAME/ EX_FRAME WE0/ PCC_REG A1 A0 M_D10 M_D28 M_D29 A9 A8 A3 A2 M_D11 M_D30 M_D31 A11 A10 I/O IO/IO IO/IO IO/IO IO IO IO IO/IO IO/IO O/O O IO IO IO O/O/I O/O O O IO IO IO O O O O IO IO IO O O MD6 = 0 Z Z Z Z Z Z Z Z H O Z Z Z H H O(V*1) O(V* ) Z Z Z O(V* ) O(V* ) O(V* ) O(V*1) Z Z Z O(V* ) O(V* )
1 1 1 1 1 1
MD6 = 1 Z Z Z Z Z Z Z Z H O Z Z Z H H O(V*1) O(V* ) Z Z Z O(V* ) O(V* ) O(V* ) O(V*1) Z Z Z O(V* ) O(V* )
1 1 1 1 1 1
Manual Reset Z Z Z Z Z Z Z Z H O Z Z Z H/H/I H/O O O Z Z Z O O O O Z Z Z O O
Standby ZV ZV ZV Z Z Z ZV ZV Z O Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Bus Release Z Z Z IO IO IO Z Z ZV O IO IO IO ZV ZV ZV ZV IO IO IO ZV ZV ZV ZV IO IO IO ZV ZV
Rev. 1.00 Oct. 01, 2007 Page 1921 of 1956 REJ09B0256-0100
Appendix
Pin No. R24 R25 T1 T2 T22 T23 T24 T25 U1 U2 U22 U23 U24 U25 V22 V23 V24 V25 W1 W2 W3 W4
Power-On Reset Pin Name A5 A4 M_D13 M_D12 A17 A16 A7 A6 M_D15 M_D14 A19 A18 A13 A12 A21 A20 A15 A14 PTG1/GNT2/ ET1_ETXD0 PTG2/REQ1/ ET1_ETXD1 PTG3/REQ3/ ET1_ETXD2 I/O O O IO IO O O O O IO IO O O O O O O O O IO/O/O IO/I/O IO/I/O MD6 = 0 O(V*1) O(V* ) Z Z O(V* ) O(V* ) O(V* ) O(V* ) Z Z O(V* ) O(V*1) O(V* ) O(V* ) O(V* ) O(V* ) O(V* ) O(V* ) Z I I
1 1 1 1 1 1 1 1 1 1 1 1
MD6 = 1 O(V*1) O(V* ) Z Z O(V* ) O(V* ) O(V* ) O(V* ) Z Z O(V* ) O(V*1) O(V* ) O(V* ) O(V* ) O(V* ) O(V* ) O(V* ) Z I I I
1 1 1 1 1 1 1 1 1 1 1 1
Manual Reset O O Z Z O O O O Z Z O O O O O O O O IO/Z/O IO/I/O IO/I/O
Standby Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z/Z/O Z/Z/O Z/Z/O
Bus Release ZV ZV IO IO ZV ZV ZV ZV IO IO ZV ZV ZV ZV ZV ZV ZV ZV IO/O/O IO/I/O IO/I/O
PTF0/GNT0/ IO/IO/I/IO/ I GNTIN/SIM_D/ O/I ET1_ETXD3/ DREQ3 A25/EX_SIZE2 O/I A24/EX_SIZE1 O/I A23/EX_SIZE0 O/I A22 O O(M*1) O(M*1) O(M* ) O(V* )
1 1
IO/I(IO*2)/I/ Z/Z/Z/Z/O/ IO/IO/I/IO/ I/O/I Z O/I
W22 W23 W24 W25
O(M*1) O(M*1) O(M* ) O(V* )
1 1
O/I O/I O/I O
Z Z Z Z
ZV ZV ZV ZV
Rev. 1.00 Oct. 01, 2007 Page 1922 of 1956 REJ09B0256-0100
Appendix
Pin No. Y1
Power-On Reset Pin Name PTE1/PCICLK/ GET1_ETXD4/ DACK2 I/O IO/I/O/O MD6 = 0 I MD6 = 1 I
Manual Reset IO/I/O/O
Standby I/I/O/O
Bus Release IO/I/O/O
Y2
PTD6/REQ2/ IO/I/I/O/IO/ I PCC_BVD1/ O GET1_ETXD5/ SSI1_SCK/ LCDM_VCPWC PTE0/INTA/ PCC_DRV/ GET1_ETXD6/ DREQ2 IO/IO/O/O/I I
I
IO/I/I/O/I/O Z/Z/Z/O/Z/ IO/I/I/O/IO/ O O
Y3
I
IO/I/O/O/I
Z/Z/O/O/Z
IO/IO/O/O/I
Y4
PTD7/ O/O/O/O/O O PCIRESET/ PCC_RESET/ GET1_ETXD7/ LCDM_VEPWC CE2A CE2B DA1 DA0 PTF1/REQ0/ REQOUT/ SIM_CLK/ ET1_MDC/ DACK3 PTF2/AD31/ SIM_RST/ ET1_MDIO/ TEND3 PTG0/GNT1/ ET1_WOL PTG4/AD30/ ET1_LINKSTA O O O O V V O O
O
O/O/O/O/O O
O/O/O/O/O
Y22 Y23 Y24 Y25 AA1
V V O O I
O O O O IO/IO(I* )/ O/O/O/O
1
ZV ZV O O
ZV ZV O O
IO/IO/O/O/ I O/O
Z/Z/Z/Z/O/ IO/IO/O/O/ O O/O
AA2
IO/IO/O/IO/ I O
O
IO/I(IO*2)/ O/I/O
Z/Z/Z/Z/O
IO/IO/O/IO/ O
AA3 AA4
IO/O/O IO/IO/I I/I
Z I M(V*1)
Z O M(V*1)
IO/Z/O
Z/Z/O
IO/O/O IO/IO/I IV/I
IO/I(IO*2)/I Z IV ZV
AA23 IOIS16/ TMU_TCLK
Rev. 1.00 Oct. 01, 2007 Page 1923 of 1956 REJ09B0256-0100
Appendix
Pin No. AB1
Power-On Reset Pin Name PTE5/AD29/ SCIF2_TXD/ GET1_ GTX-CLK/ SSI0_SCK PTG7/AD28/ ET1_TX-EN PTG6/AD26/ ET1_TX-ER I/O MD6 = 0 MD6 = 1 O
Manual Reset IO/I(IO*2)/ O/O/I
Standby Z/Z/Z/O/Z
Bus Release IO/IO/O/O/ IO
IO/IO/O/O/ I IO
AB2 AB3 AB6
IO/IO/O IO/IO/O
I I
O O O
IO/I(IO*2)/ O IO/I(IO*2)/ O
Z/Z/O Z/Z/O
IO/IO/O IO/IO/O IO/IO/I/I/IO
PTE4/AD22/ IO/IO/I/I/IO I SCIF2_RXD/ GET1_ERXD4/ SSI0_SDATA PTD5/AD18/ IO/IO/I/I/ PCC_CD2/ IO/O GET1_ERXD6/ SSI1_SDATA/ LCDM_D14 PTD3/ PCIFRAME/ PCC_BVD2/ SIOF0_SCK/ HAC_RES/ LCDM_D12 PTD4/STOP/ PCC_CD1/ SIOF0_MCLK/ SSI1_WS/ LCDM_DON I
IO/I(IO*2)I/I Z /I
AB7
O
IO/I(IO*2)/I/ Z/Z/Z/Z/Z/ I/I/O O
IO/IO/I/I/ IO/O
AB8
IO/IO/I/IO/ I O/O
I
IO/I/I/O/O/ Z/Z/Z/Z/O/ IO/IO/I/IO/ O O O/O
AB9
IO/IO/I/I/ IO/O
I
I
IO/I/I/I/I/O
Z/Z/Z/Z/Z/ O
IO/IO/I/I/ IO/O
AB10 PTA3/AD15/ SCIF1_CTS AB11 PTB2/AD11/ PINT10/ LCDM_D7 AB12 PTB6/CBE0/ PINT14/ LCDM_D3 AB13 PTC1/AD4/ LCDM_D1
IO/IO/IO IO/IO/I/O
I I
O O
IO/I(IO*2)/I Z IO/I(IO*2)/I/ Z/Z/Z/O O IO/I(IO*2)/I/ Z/Z/Z/O O IO/I(IO*2)/ O Z/Z/O
IO/IO/IO IO/IO/I/O
IO/IO/I/O
I
O
IO/IO/I/O
IO/IO/O
I
O
IO/IO/O
Rev. 1.00 Oct. 01, 2007 Page 1924 of 1956 REJ09B0256-0100
Appendix
Pin No.
Power-On Reset Pin Name I/O I MD6 = 0 M I MD6 = 1 M I
Manual Reset M P/I/I/O/-
Standby M Z/I/I/O/-
Bus Release M P/I/I/O/-
AB16 MPMD
AB17 PTO6/IRQ0/ IO/I/I/O/I IRL0/DACK1M/ MD5 AB18 PTO2/ IO/O/O AUDATA1/ RMII0M1_MDC AB20 TDO AB24 AN3 AB25 AN2 AC1 PTH6/AD27/ TPU_TO2/ ET1_CRS/ RMII1M_TXD_ EN PTH0/AD25/ TPU_TI3A/ ET1_COL/ RMII1M_RX_ ER O I I
M
M
P/O/O
Z/O/O
P/O/O
Z Z Z
Z Z Z O
O I I IO/I(IO* )/ O/I/O
2
Z I I Z/Z/O/Z/O
O I I IO/IO/O/I/O
IO/IO/O/I/O I
AC2
IO/IO/I/I/I
I
O
IO/I(IO*2)/I/ Z I/I
IO/IO/I/I/I
AC5
PTH1/IDSEL/ IO/I/I/I/I TPU_TI3B/ ET1_RX-ER/ RMII1M_CRS_ DV
I
I
IO/I/I/I/I
Z
IO/I/I/I/I
AC6
PTE3/AD20/ IO/IO/IO/I/ I SCIF2_SCK/ IO GET1_ERXD5/ SSI0_WS PTE2/AD16/ IO/IO/I/I/O I PCC_IOIS16/ GET1_ERXD7/ TEND2 PTD2/TRDY/ PCC_RDY/ SIOF0_RXD/ HAC_SYNC/ LCDM_D11 IO/IO/I/I/O/ I O
O
IO/I(IO*2)/I/ Z I/I
IO/IO/IO/I/ IO
AC7
O
IO/I(IO*2)/I/ Z/Z/Z/Z/O I/O
IO/IO/I/I/O
AC8
I
IO/I/I/I/O/O Z/Z/Z/Z/O/ IO/IO/I/I/O/ O O
Rev. 1.00 Oct. 01, 2007 Page 1925 of 1956 REJ09B0256-0100
Appendix
Pin No. AC9
Power-On Reset Pin Name PTA0/PAR/ SCIF1_SCK I/O IO/IO/IO IO/IO/IO IO/IO/I/O MD6 = 0 I I I MD6 = 1 O O O
Manual Reset
Standby
Bus Release IO/IO/IO IO/IO/IO IO/IO/I/O
IO/I(IO*2)/I Z IO/I(IO*2)/ O Z
AC10 PTA4/AD13/ SCIF1_RTS AC11 PTB3/AD9/ PINT11/ LCDM_D6 AC12 PTB7/AD6/ PINT15/ LCDM_D2 AC13 PTC2/AD2/ LCDM_D0 AC14 PTC5/AD0/ MMC_CD/ LCDM_FLM AC15 PTN2/ SCIF0_TXD/ MD1 AC16 MRESET
IO/I(IO*2)/I/ Z/Z/Z/O O IO/I(IO*2)/I/ Z/Z/Z/O O IO/I(IO*2)/ O Z/Z/O
IO/IO/I/O
I
O
IO/IO/I/O
IO/IO/O IO/IO/I/O
I I
O O
IO/IO/O IO/IO/I/O
IO/I(IO*2)/I/ Z/Z/Z/O O IO/O/Z/Z/-
IO/O/I
I
I
IO/O/-
I
I
I I
I P/I/I/O/I/-
I Z/I/I/O/Z/-
I P/I/I/O/IO/-
AC17 PTO7/IRQ1/ IO/I/I/O/IO/ I IRL1/TEND1M/ I SSI3_SCK/MD6 AC18 PTO3/ IO/O/IO/IO M AUDATA2/ RMII0M1_MDIO /SSI2_SCK AC19 TRST AC20 TDI AC21 TMS AC22 BACK AC24 AN1 AC25 AN0 AD1 PTF3/CBE3/ ET1_TX-CLK I I I O I I IO/IO/I M M M O Z Z I
M
P/O/I/IV
Z/O/Z/Z
P/O/IO/IO
M M M O Z Z O
M M M O I I
2
M M M O I I
M M M O I I IO/IO/I
IO/I(IO* )/I Z
Rev. 1.00 Oct. 01, 2007 Page 1926 of 1956 REJ09B0256-0100
Appendix
Pin No. AD4
Power-On Reset Pin Name PTH2/AD24/ TPU_TI2A/ ET1_ERXD0/ RMII1M_TXD1 I/O MD6 = 0 MD6 = 1 O
Manual Reset
Standby
Bus Release IO/IO/I/I/O
IO/IO/I/I/O I
IO/I(IO*2)/I/ Z/Z/Z/Z/O I/O
AD5
PTH3/AD21/ IO/IO/I/I/I TPU_TI2B/ ET1_ERXD2/ RMII1M_RXD1 PTH7/AD17/ TPU_TO3/ ET1_RX-DV PTD0/IRDY/ PCC_VS1/ SIOF0_SYNC/ HAC_SD_IN/ LCDM_D13 PTA2/LOCK/ SCIF1_TXD PTB1/SERR/ PINT9/ LCDM_D9 IO/IO/O/I
I
O
IO/I(IO*2)/I/ Z I/I
IO/IO/I/I/I
AD6
I
O
IO/I(IO*2)/ O/I
Z/Z/O/Z
IO/IO/O/I
AD7
IO/IO/I/IO/ I I/O
I
IO/I/I/O/I/O Z/Z/Z/Z/Z/ O
IO/IO/I/IO/ I/O
AD8 AD9
IO/IO/O IO/IO/I/O
I I
I I
IO/I/O IO/I/I/O
Z Z/Z/Z/O
IO/IO/O IO/IO/I/O
AD10 PTB5/AD14/ IO/IO/I/O PINT13/ LCDM_M_DISP AD11 PTC0/AD10/ MMC_DAT/ LCDM_D5 AD12 PTC4/AD7/ MMC_CMD/ LCDM_CL2 AD13 PTC7/AD3/ MMC_CLK AD14 PTN0/ SCIF0_SCK/ MD0 AD15 PTN3/ SCIF0_CTS/ MD4
I
O
IO/I(IO*2)/I/ Z/Z/Z/O O IO/I(IO*2)/ IO/O IO/I(IO*2)/ IO/O IO/I(IO*2)/ O IO/I/Z/Z/Z/O
IO/IO/I/O
IO/IO/IO/O I
O
IO/IO/IO/O
IO/IO/IO/O I
O
Z/Z/Z/O
IO/IO/IO/O
IO/IO/O IO/IO/I
I I
O I
Z Z/Z/-
IO/IO/O IO/IO/-
IO/IO/I
I
I
IO/I/-
Z/Z/-
IO/IO/-
Rev. 1.00 Oct. 01, 2007 Page 1927 of 1956 REJ09B0256-0100
Appendix
Pin No.
Power-On Reset Pin Name I/O IO/I IO/O/O/IO MD6 = 0 M M MD6 = 1 M M
Manual Reset P/IV P/O/O/IV
Standby Z/IV Z/O/O/Z
Bus Release P/I P/O/O/IO
AD16 PTN5/NMI AD17 PTO0/ AUDSYNC/ RMII1_MDC/ SSI2_WS AD18 PTO4/ AUDATA3/ EX_INT/ SSI3_WS AD19 ASEBRK/ BRKACK AD22 BREQ AE3 AE4 PTG5/GNT3/ ET1_RX-CLK PTH5/AD23/ TPU_TO1/ ET1_ERXD1/ RMII1M_TXD0
IO/O/O/IO
M
M
P/O/O/IV
Z/O/O/Z
P/O/O/IO
IO I IO/O/I
M M Z
M M Z O
M/O IV IO/Z/I IO/I(IO*2)/ O/I/O
M IV Z Z/Z/O/Z/O
M/O IV IO/O/I IO/IO/O/I/O
IO/IO/O/I/O I
AE5
PTH4/AD19/ IO/IO/O/I/I I TPU_TO0/ ET1_ERXD3/ RMII1M_RXD0 PTD1/CBE2/ IO/IO/I/O/ PCC_VS2/ O/O SIOF0_TXD/ HAC_SD_OUT/ LCDM_D15 PTA1/DEVSEL/ IO/IO/I SCIF1_RXD PTB0/PERR/ PINT8/ LCDM_D10 PTB4/CBE1/ PINT12/ LCDM_D8 IO/IO/I/O I
O
IO/I(IO*2)/ O/I/I
Z/Z/O/Z/Z
IO/IO/O/I/I
AE6
O
IO/I(IO*2)/I/ Z/Z/Z/Z/O/ IO/IO/I/O/ O/O/O O O/O
AE7 AE8
I I
I I
IO/I/I IO/I/I/O
Z Z/Z/Z/O
IO/IO/I IO/IO/I/O
AE9
IO/IO/I/O
I
O
IO/I(IO*2)/I/ Z/Z/Z/O O IO/I(IO*2) Z
IO/IO/I/O
AE10 PTA5/AD12
IO/IO
I
O
IO/IO
Rev. 1.00 Oct. 01, 2007 Page 1928 of 1956 REJ09B0256-0100
Appendix
Pin No.
Power-On Reset Pin Name I/O MD6 = 0 I MD6 = 1 O
Manual Reset IO/I(IO*2)/ O/O IO/I(IO*2)/ O IO/I(IO*2)/ O IO/Z/-
Standby Z/Z/Z/O
Bus Release IO/IO/O/O
AE11 PTC3/AD8/ IO/IO/O/O MMC_ODMOD/ LCDM_D4 AE12 PTC6/AD5/ LCDM_CL1 AE13 PTA6/AD1/ MMC_VDDON AE14 PTN1/ SCIF0_RXD/ MD3 AE15 PTN4/ SCIF0_RTS/ MD2 AE16 PRESET AE17 PTO1/ AUDATA0/ RMII1_MDIO/ SSI2_SDATA AE18 PTO5/AUDCK/ DREQ1M/ SSI3_SDATA AE19 TCK AE22 EXTAL IO/IO/O IO/IO/O IO/I/I
I I I
O O I
Z/Z/Z/O Z Z/Z/-
IO/IO/O IO/IO/O IO/I/-
IO/IO/I
I
I
IO/O/-
Z/Z/-
IO/IO/-
I
I
I M
I P/O/I/IV
I Z/O/Z/Z
I P/O/IO/IO
IO/O/IO/IO M
IO/O/I/IO
M
M
P/O/IV/IV
Z/O/Z/Z
P/O/I/IO
I I
M I
M I
M I
M I
M I
Rev. 1.00 Oct. 01, 2007 Page 1929 of 1956 REJ09B0256-0100
Appendix
Pin No.
Power-On Reset Pin Name I/O O MD6 = 0 O MD6 = 1 O
Manual Reset O
Standby O
Bus Release O
AE23 XTAL [Legend] I: O: IO: H: V: M: IV:
Input Output Input or output High level output (input buffer: off, output buffer: on) Input buffer: off, output buffer: off, pulled-up Input buffer: on, output buffer: off, pulled-up Input buffer: on, output buffer: off, pulled-up or not according to the GPIO register settings Z: High impedance state (input buffer: off, output buffer: off) ZV: High impedance or pulled up according to the LBSC, GPIO register settings P: Input buffer on or off, output buffer on or off, pulled-up or not according to register settings -: Invalid Notes: 1. Pin states until the internal status is determined. 2. When MD6 = 1.
Rev. 1.00 Oct. 01, 2007 Page 1930 of 1956 REJ09B0256-0100
Appendix
H.
Handling of Unused Pins
Handling of Unused Pins
I/O O O O O O O O O O IO Handling of Unused Pins Open Open Open Open Open Open Open Open Always used Pulled-down Pulled-up Open Open Pulled-up Pulled-up Open Pulled-up Open Pulled-up Open
Table H.1
Pin No. Pin Name A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 M_CLK0 M_CLK1 M_WE M_RAS M_BA0 M_A10 M_A1 M_A3 XTAL2 USBM
PTI2/ST0M_STARTI/IIC0_SCL/SIOF1_RXD/ I/I/IO/I/I/I USB_OVRCRT/USBF_VBUS PTI0_STATUS0/ST1_CLK/RMII0_MDC PTK4/ST1_D4/SIOF2_TXD/LCD_D6 GET0_ERXD4 IO/O/IO/O IO/IO/O/O I I/I/I/I/IO IO/O I/I/I IO/IO I/I O/O
A17 A18
PTI6/IRQ2/IRL2/ST0M_D6I/IIC1_SCL PTJ5/LCD_DON ST0M_D3I/ET0_ERXD3/RMII1_RXD0
A19
PTJ1/ST0M_CLKIO RMII1_RX_ER/LCK_CLK CS5/CE1A PTM6/D30/EX_AD30/ST0_D6/RMII0_TXD1 ET0_RX-CLK/PINT6
A20 A21
IO/IO/IO/IO Open /O I/I Pulled-up
A22
PTM4/D28/EX_AD28/ST0_D4 ET0_PHY-INT/RMII0_RXD0/PINT4 CS0 M_BKPRST M_CKE
IO/IO/IO/IO Open I/I/I O I O Pulled-up Open Pulled-up Open
A23 B3 B4
Rev. 1.00 Oct. 01, 2007 Page 1931 of 1956 REJ09B0256-0100
Appendix
Pin No. Pin Name B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 M_A13 M_CAS M_CS M_BA1 M_A0 M_A2 M_A4 EXTAL2 USBP
I/O O O O O O O O I IO
Handling of Unused Pins Open Open Open Open Open Open Open Always used Pulled-up Pulled-up Open Pulled-up Always used Pulled-up Open Pulled-up Pulled-down Open Pulled-up Open Pulled-up
PTI3/ST0M_VALIDI/IIC0_SDA/SIOF1_MCLK I/I/IO/I/I /USB_CLK PTK7/ST1_D7/LCD_VCPWC GET0_ERXD7/SIOF2_MCLK IO/IO/O I/I IO/I/IO/O I/I/I/I/IO IO/O I/I/I I O I O I
B16 B17 B18
PTI5/MD10/ST1_VALID/LCD_D1 PTI7/IRQ3/IRL3/ST0M_D7I/IIC1_SDA PTJ4/LCD_CL2 ST0M_D2I/ET0_ERXD2/RMII1_RXD1 RDY EX_RDY PCC_WAIT CS2 EX_CS1
B19
B20
B21
PTM7/D31/EX_AD31/ST0_D7/RMII0_TXD0 ET0_RX-DV/PINT7
IO/IO/IO/IO Open /O I/I Pulled-up
B22
PTM5/D29/EX_AD29/ST0_D5/ RMII0_TXD_EN ET0_RX-ER/PINT5
IO/IO/IO/IO Open /O I/I Pulled-up
B24
PTM3/D27/EX_AD27/ST0_D3 ET0_LINKSTA/RMII0_RXD1/PINT3
IO/IO/IO/IO Open I/I/I I/I/I IO Pulled-up Pulled-up Open
B25 C1
REF125CK/SSI_CLK/HAC_BITCLK M_D0
Rev. 1.00 Oct. 01, 2007 Page 1932 of 1956 REJ09B0256-0100
Appendix
Pin No. Pin Name C5 C6 C7 C8 C9 C10 C11 C12 C14 C15 M_A12 M_A11 M_A9 M_A8 M_A7 M_A6 M_A5 XRTCSTBI PTI1/STATUS1/ST1_REQ/RMII0_MDIO PTK6/ST1_D6/SIOF2_SCK/LCD_VEPWC GET0_ERXD6 C16 PTI4/MD8/ST1_START/ET1_PHY-INT/ RMII0M0_MDC/USB_PWREN/ USBF_UPLUP PTJ7/IRQOUT/IRMII1_TXD0/LCD_D0 INTB/ST0M_D5I C18 PTJ3/LCD_CL1 ST0M_D1I/ET0_ERXD1/RMII1_CRS_DV C19 C20 CS6/CE1B CS1 EX_CS0 C23 BS EX_BS C24 PTM2/D26/EX_AD26/ST0_D2/ET0_WOL RMII0_CRS_DV/PINT2 C25 PTM1/D25/EX_AD25/ST0_D1/ ET0_TX-CLK/RMII0_RX_ER/PINT1 D1 D2 D15 M_D1 M_D16 PTK5/ST1_D5/LCD_D7 GET0_ERXD5/SIOF2_RXD
I/O O O O O O O O I
Handling of Unused Pins Open Open Open Open Open Open Open Pulled-up
IO/O/IO/IO Open IO/IO/IO/O Open I Pulled-up
IO/I/IO/I/O/ Always used O/O IO/O/O/O I/I IO/O I/I/I O/O O I O I Open Pulled-up Open Pulled-up Open Open Pulled-up Open Pulled-up
C17
IO/IO/IO/IO Open /O I/I Pulled-up
IO/IO/IO/IO Open I/I/I IO IO IO/IO/O I/I Pulled-up Open Open Open Pulled-up
Rev. 1.00 Oct. 01, 2007 Page 1933 of 1956 REJ09B0256-0100
Appendix
Pin No. Pin Name D17 PTJ6/RMII1_TXD_EN/LCD_FLM ST0M_D4I/ET0_CRS D18 PTJ2/RMII1_TXD1/LCD_M_DISP ST0M_D0I/ET0_ERXD0 D19 D23 CS4 PDWR EX_RDWR D24 PTM0/D24/EX_AD24/ST0_D0/ET0_TX-ER/ RMII0M0_MDIO PINT0 D25 E1 E2 E3 E22 E23 E24 E25 PTL7/D23/EX_AD23/ST0_VALID/ ET0_TX-EN/TEND1/LCD_D15 M_D2 M_D17 M_D18
I/O IO/O/O I/I IO/O/O I/I O O I
Handling of Unused Pins Open Pulled-up Open Pulled-up Open Open Pulled-up
IO/IO/IO/IO Open /O/IO I Pulled-up
IO/IO/IO/IO Open /O/O/O IO IO IO Open Open Open
PTK3/ST1_D3/GET0_ETXD7/SIOF2_SYNC/ IO/IO/O/IO/ Open LCD_D5 O PTK2/ST1_D2/GET0_ETXD6/SIOF1_SCK/ LCD_D4 PTL6/D22/EX_AD22/ST0_START/ ET0_ETXD2/DACK1/LCD_D14 IO/IO/O/IO/ Open O IO/IO/IO/IO Open /O/O/O
PTL5/D21/EX_AD21/ST0_CLK/ET0_ETXD1/ IO/IO/IO/IO Open LCD_D13 /O/O DREQ1 I IO IO IO Pulled-up Open Open Open
F1 F2 F3 F22 F23 F24
M_D3 M_D19 M_D20 PTK1/ST1_D1/GET0_ETXD5/SIOF1_TXD/ LCD_D3
IO/IO/O/O/ Open O
PTK0/ST1_D0/GET0_ETXD4/SIOF1_SYNC/ IO/IO/O/IO/ Open LCD_D2 O PTL4/D20/EX_AD20/ST0_REQ/ET0_ETXD0 IO/IO/IO/IO Open /LCD_D12 /O/O INTD I Pulled-up
Rev. 1.00 Oct. 01, 2007 Page 1934 of 1956 REJ09B0256-0100
Appendix
Pin No. Pin Name F25 PTJ0/ST0M_REQO/GET0_GTX-CLK REF50CK G1 G2 G3 G22 M_D4 M_D21 M_D22 PTL3/D19/EX_AD19/ET0_MDIO/LCD_D11 IRQ7/IRL7/INTC G23 PTL2/D18/EX_AD18/ET0_ETXD3/TEND0/ LCD_D10 IRQ6/IRL6 G24 G25 H1 H2 H3 H22 WE3/IOWR WE2/IORD M_D5 M_D23 M_DQS2 PTL0/D16/EX_AD16/LCD_D8 IRQ4/IRL4/ET0_COL/DREQ0 H23 PTL1/D17/EX_AD17/ET0_MDC/DACK0/ LCD_D9 IRQ5/IRL5 H24 H25 J1 J2 J3 J22 J23 J24 J25 K1 K2 D15/EX_AD15 D14/EX_AD14 M_D7 M_D6 M_DQM2 D7/EX_AD7 D6/EX_AD6 D13/EX_AD13 D12/EX_AD12 M_DQM0 M_DQS0
I/O IO/O/O I IO IO IO
Handling of Unused Pins Open Pulled-up Open Open Open
IO/IO/IO/IO Open /O I/I/I Pulled-up
IO/IO/IO/O/ Open O/O I/I O/O O/O IO IO IO Pulled-up Open Open Open Open Open
IO/IO/IO/O Open I/I/I/I Pulled-up
IO/IO/IO/O/ Open O/O I/I IO/IO IO/IO IO IO O IO/IO IO/IO IO/IO IO/IO O IO Pulled-up Open Open Open Open Open Open Open Open Open Open Open
Rev. 1.00 Oct. 01, 2007 Page 1935 of 1956 REJ09B0256-0100
Appendix
Pin No. Pin Name K3 K22 K23 K24 K25 L1 L2 L3 L22 L23 L24 L25 M1 M2 M3 M22 M23 M24 M25 N1 N2 N3 N22 M_DQS3 D5/EX_AD5 D4/EX_AD4 D11/EX_AD11 D10/EX_AD10 M_DQS1 M_DQM1 M_DQM3 D3/EX_AD3 D2/EX_AD2 D9/EX_AD9 D8/EX_AD8 M_D8 M_D24 M_D25 D1/EX_AD1 D0/EX_AD0 WE1/WE CLKOUT M_D9 M_D26 M_D27 RD/FRAME EX_FRAME N23 N24 N25 P1 P2 P3 P22 WE0/PCC_REG A1 A0 M_D10 M_D28 M_D29 A9
I/O IO IO/IO IO/IO IO/IO IO/IO IO O O IO/IO IO/IO IO/IO IO/IO IO IO IO IO/IO IO/IO O/O O IO IO IO O/O I O/O O O IO IO IO O
Handling of Unused Pins Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Pulled-up Open Open Open Open Open Open Open
Rev. 1.00 Oct. 01, 2007 Page 1936 of 1956 REJ09B0256-0100
Appendix
Pin No. Pin Name P23 P24 P25 R1 R2 R3 R22 R23 R24 R25 T1 T2 T22 T23 T24 T25 U1 U2 U22 U23 U24 U25 V22 V23 V24 V25 W1 W2 A8 A3 A2 M_D11 M_D30 M_D31 A11 A10 A5 A4 M_D13 M_D12 A17 A16 A7 A6 M_D15 M_D14 A19 A18 A13 A12 A21 A20 A15 A14 PTG1/GNT2/ET1_ETXD0 PTG2/ET1_ETXD1 REQ1 W3 PTG3/ET1_ETXD2 REQ3
I/O O O O IO IO IO O O O O IO IO O O O O IO IO O O O O O O O O IO/O/O IO/O I IO/O I
Handling of Unused Pins Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Pulled-up Open Pulled-up
Rev. 1.00 Oct. 01, 2007 Page 1937 of 1956 REJ09B0256-0100
Appendix
Pin No. Pin Name W4 PTF0/SIM_D/ET1_ETXD3 GNT0/GNTIN/DREQ3 W22 A25 EX_SIZE2 W23 A24 EX_SIZE1 W24 A23 EX_SIZE0 W25 Y1 A22 PTE1/GET1_ETXD4/DACK2 PCICLK Y2 PTD6/GET1_ETXD5/SSI1_SCK/ LCDM_VCPWC REQ2/PCC_BVD1 Y3 PTE0/PCC_DRV/GET1_ETXD6 INTA/DREQ2 Y4 Y22 Y23 Y24 Y25 AA1 PTD7/PCIRESET/PCC_RESET/ GET1_ETXD7/LCDM_VEPWC CE2A CE2B DA1 DA0
I/O IO/IO/O IO/I/I O I O I O I O IO/O/O I IO/O/IO/O I/I IO/O/O IO/I
Handling of Unused Pins Open Pulled-up Open Pulled-up Open Pulled-up Open Pulled-up Open Open Pulled-up Open Pulled-up Open Pulled-up
O/O/O/O/O Open O O O O Open Open Open Open Open Pulled-up
PTF1/REQOUT/SIM_CLK/ET1_MDC/DACK3 IO/O/O/O/ O REQ0 IO
AA2 AA3 AA4
PTF2/AD31/SIM_RST/ET1_MDIO/TEND3 PTG0/GNT1/ET1_WOL PTG4/AD30 ET1_LINKSTA IOIS16/TMU_TCLK PTE5/AD29/SCIF2_TXD/GET1_GTX-CLK/ SSI0_SCK
IO/IO/O/IO/ Open O IO/O/O IO/IO I I/I Open Open Pulled-up Pulled-up
AA23 AB1
IO/IO/O/O/ Open IO
Rev. 1.00 Oct. 01, 2007 Page 1938 of 1956 REJ09B0256-0100
Appendix
Pin No. Pin Name AB2 AB3 AB6 PTG7/AD28/ET1_TX-EN PTG6/AD26/ET1_TX-ER PTE4/AD22/SSI0_SDATA SCIF2_RXD/GET1_ERXD4 AB7 PTD5/AD18/GET1_ERXD6/SSI1_SDATA/ LCDM_D14 PCC_CD2 AB8 PTD3/SIOF0_SCK/HAC_RES/LCDM_D12 PCIFRAME/PCC_BVD2 AB9 PTD4/SSI1_WS/LCDM_DON STOP/PCC_CD1/SIOF0_MCLK AB10 AB11 PTA3/AD15/SCIF1_CTS PTB2/AD11/LCDM_D7 PINT10 AB12 PTB6/CBE0/LCDM_D3 PINT14 AB13 AB16 AB17 AB18 AB20 AB24 AB25 AC1 PTC1/AD4/LCDM_D1 MPMD PTO6/IRQ0/IRL0/DACK1M/MD5 PTO2/AUDATA1/RMII0M1_MDC TDO AN3 AN2 PTH6/AD27/TPU_TO2/RMII1M_TXD_EN ET1_CRS AC2 PTH0/AD25 TPU_TI3A/ET1_COL/RMII1M_RX_ER AC5 PTH1 IDSEL TPU_TI3B/ET1_RX-ER/RMII1M_CRS_DV AC6 PTE3/AD20/SCIF2_SCK/SSI0_WS GET1_ERXD5
I/O IO/IO/O IO/IO/O IO/IO/IO I/I
Handling of Unused Pins Open Open Open Pulled-up
IO/IO/I/IO/ Open O I IO/IO/O/O IO/I IO/IO/O IO/I/I IO/IO/IO IO/IO/O I IO/IO/O I IO/IO/O I IO/I/I/O/I IO/O/O O I I IO/IO/O/O I IO/IO I/I/I IO I I/I/I Pulled-up Open Pulled-up Open Pulled-up Open Open Pulled-up Open Pulled-up Open Always used Always used Open Open Open Open Open Pulled-up Open Pulled-up Open Pulled-down Pulled-up
IO/IO/IO/IO Open I Pulled-up
Rev. 1.00 Oct. 01, 2007 Page 1939 of 1956 REJ09B0256-0100
Appendix
Pin No. Pin Name AC7 PTE2/AD16/TEND2 PCC-IOIS16/GET1_ERXD7 AC8 PTD2/HAC_SYNC/LCDM_D11 TRDY/PCC_RDY/SIOF0_RXD AC9 AC10 AC11 PTA0/PAR/SCIF1_SCK PTA4/AD13/SCIF1_RTS PTB3/AD9/LCDM_D6 PINT11 AC12 PTB7/AD6/LCDM_D2 PINT15 AC13 AC14 PTC2/AD2/LCDM_D0 PTC5/AD0/LCDM_FLM MMC_CD AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC24 AC25 AD1 PTN2/SCIF0_TXD/MD1 MRESET PTO7/IRQ1/IRL1/TEND1M/SSI3_SCK/MD6 TRST TDI TMS BACK AN1 AN0 PTF3/CBE3 ET1_TX-CLK AD4 PTH2/AD24/RMII1M_TXD1 TPU_TI2A/ET1_ERXD0 AD5 PTH3/AD21 TPU_TI2B/ET1_ERXD2/RMII1M_RXD1 AD6 PTH7/AD17/TPU_TO3 ET1_RX-DV
I/O IO/IO/O I/I IO/O/O IO/I/I IO/IO/IO IO/IO/IO IO/IO/O I IO/IO/O I IO/IO/O IO/IO/O I IO/O/I I
Handling of Unused Pins Open Pulled-up Open Pulled-up Open Open Open Pulled-up Open Pulled-up Open Open Pulled-up Always used Always used
IO/I/I/O/IO/I Always used
PTO3/AUDATA2/RMII0M1_MDIO/SSI2_SCK IO/O/IO/IO Open I I I O I I IO/IO I IO/IO/O I/I IO/IO I/I/I IO/IO/O I Always used Open Open Open Open Open Open Pulled-up Open Pulled-up Open Pulled-up Open Pulled-up
Rev. 1.00 Oct. 01, 2007 Page 1940 of 1956 REJ09B0256-0100
Appendix
Pin No. Pin Name AD7 PTD0/SIOF0_SYNC/LCDM_D13 IRDY/PCC_VS1/HAC_SD_IN AD8 PTA2/SCIF1_TXD LOCK AD9 PTB1/LCDM_D9 SERR/PINT9 AD10 PTB5/AD14/LCDM_M_DISP PINT13 AD11 AD12 AD13 AD14 AD15 AD16 PTC0/AD10/MMC_DAT/LCDM_D5 PTC4/AD7/MMC_CMD/LCDM_CL2 PTC7/AD3/MMC_CLK PTN0/SCIF0_SCK/MD0 PTN3/SCIF0_CTS/MD4 PTN5 NMI AD17 AD18 AD19 AD22 AE3 PTO0/AUDSYNC/RMII1_MDC/SSI2_WS PTO4/AUDATA3/EX_INT/SSI3_WS ASEBRK/BRKACK BREQ PTG5/GNT3 ET1_RX-CLK AE4 PTH5/AD23/TPU_TO1/RMII1M_TXD0 ET1_ERXD1 AE5 PTH4/AD19/TPU_TO0 ET1_ERXD3/RMII1M_RXD0 AE6 PTD1/CBE2/SIOF0_TXD/HAC_SD_OUT/ LCDM_D15 PCC_VS2 AE7 PTA1 DEVSEL/SCIF1_RXD AE8 PTB0/LCDM_D10 PERR/PINT8
I/O IO/IO/O IO/I/I IO/O IO IO/O IO/I IO/IO/O I
Handling of Unused Pins Open Pulled-up Open Pulled-up Open Pulled-up Open Pulled-up
IO/IO/IO/O Open IO/IO/IO/O Open IO/IO/O IO/IO/I IO/IO/I IO I IO/O/O/IO IO/O/O/IO IO I IO/O I IO/IO/O/O I IO/IO/O I/I Open Always used Always used Open Pulled-up Open Open Open Pulled-up Open Pulled-up Open Pulled-up Open Pulled-up
IO/IO/O/O/ Open O I IO IO/I IO/O IO/I Pulled-up Open Pulled-up Open Pulled-up
Rev. 1.00 Oct. 01, 2007 Page 1941 of 1956 REJ09B0256-0100
Appendix
Pin No. Pin Name AE9 PTB4/CBE1/LCDM_D8 PINT12 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 PTA5/AD12 PTC3/AD8/MMC_ODMOD/LCDM_D4 PTC6/AD5/LCDM_CL1 PTA6/AD1/MMC_VDDON PTN1/SCIF0_RXD/MD3 PTN4/SCIF0_RTS/MD2 PRESET
I/O IO/IO/O I IO/IO IO/IO/O/O IO/IO/O IO/IO/O IO/I/I IO/IO/I I
Handling of Unused Pins Open Pulled-up Pulled-up Pulled-up Open Open Always used Always used Always used
PTO1/AUDATA0/RMII1_MDIO/SSI2_SDATA IO/O/IO/IO Open PTO5/AUDCK/SSI3_SDATA DREQ1M IO/O/IO I I I O Open Pulled-up Open Always used Always use
AE19 AE22 AE23
TCK EXTAL XTAL
Rev. 1.00 Oct. 01, 2007 Page 1942 of 1956 REJ09B0256-0100
Appendix
I.
Version Registers
The registers related to the version registers are shown below. Table I.1
Name Processor version register Product register [Legend] x: Undefined
Register Configuration
Abbrev. PVR PRR R/W Initial Value P4 Address Area 7 Address R R H'1020 0Axx H'FF00 0030 H'1F00 0030 H'0000 092x H'FF00 0044 H'1F00 0044 Size 32 32
(1)
Processor Version Register (PVR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Version information Initial value: R/W: 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0 R 0 R
Bit: 15
14
13
12
11
10
9
8
7

6
5
4
3

2
1
0
Version information
Initial value: R/W:
0
0
R
0
R
0
R
1
0
R
1
R
0

R
R
R
(2)
Product Register (PRR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Version information Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Version information
Initial value: R/W:
0 R
0 R
0 R
0 R
1 R
0 R
0 R
1 R
0 R
0 R
1 R
0 R

Rev. 1.00 Oct. 01, 2007 Page 1943 of 1956 REJ09B0256-0100
Appendix
J.
Heat Radiation
This LSI is assumed to be used under the condition of Tj (junction temperature) 125C. Accordingly, if Tj can possibly exceed 125C, some heat radiation measures should be taken. For reference, the following sections show the heat resistance simulation results of this LSI; determine the measures to be taken so that a condition of Tj 125C should be satisfied. Here, note that the following sections only show the simulation results, not the guaranteed values or measures. J.1 Heat Resistance Simulation Conditions
(1) Circuit Board Model on which this LSI is Mounted: JEDEC Standard Board (PCB) * Structure: Four-layer board of 101.5 mm x 114.5 mm x t1.6 mm (2S2P) * Routing rate: 20% - 100% - 100% - 20% (2) Heat Resistance Simulation Environment * Heat resistance simulation environment: JEDEC standard environment (300-mm cubic casing); Ta (ambient temperature) = 75C or 60C; windless. * Casing: Acrylic (300 mm x 300 mm x 300 mm in size) Figure J.1 shows the overall view of the simulation model. (3) Power Consumption * Power consumption: 2.4 W (maximum value when this LSI is operating in normal operating mode) (4) Heat Sink Model * Heat sink: Aluminum * Thermal conductivity: 215.9 W/mK Figure J.2 shows the heat sink model.
Rev. 1.00 Oct. 01, 2007 Page 1944 of 1956 REJ09B0256-0100
Appendix
J.2
Analysis Results of Heat Resistance Simulation
Table J.1 shows the analysis results of heat resistance simulation. As shown, Tj exceeds 125C when TA = 60C and a heat sink is not provided. Therefore, if Ta possibly exceeds 60C, heat radiation measures are indispensable. Table J.1 Heat Resistance Simulation Results
Ta (C) 75 75 60 Tj (C) 136.9 116.9 122.9 ja (C/W) 25.8 17.4 26.2
Power Consumption (W) Heat Sink 2.4 2.4 2.4 Not provided Provided Not provided
Note: Tj and ja vary depending on the PCB, casing, heat source, and other environmental factors.
Heat sink This LSI
Casing
PCB
Figure J.1 Overall View of Simulation Model (with heat sink)
Rev. 1.00 Oct. 01, 2007 Page 1945 of 1956 REJ09B0256-0100
Appendix
Top view (perspective)
25.4 mm
25.4 mm Side view (perspective)
10.0 mm
This LSI
Note: A heat sink is attached to this LSI using adhesive (0.125 mm thick and 0.6 W/mK).
Figure J.2 Heat Sink Model
Rev. 1.00 Oct. 01, 2007 Page 1946 of 1956 REJ09B0256-0100
Index
Numerics
0-Time PAUSE frame control ................ 981 10-Bit address format ........................... 1048 16-Bit timer pulse unit (TPU)................. 707 32-Bit address extended mode................ 177 7-Bit address format ............................. 1047 Buffer operation ...................................... 734 Burst mode.............................................. 602 Bus Arbitration........................................ 405
C
Cacheability bit ....................................... 158 Caches..................................................... 187 CAM function ......................................... 969 Clock pulse generator (CPG) .................. 633 Clock valid reception ............................ 1017 Clock valid transmission....................... 1021 Clocked Synchronous Mode ................. 1152 Clocked synchronous serial communication mode............................ 1059 Compare match timer (CMT) ................. 747 Control registers........................................ 39 Crystal Oscillator Circuit ........................ 781 CUI ......................................................... 781 Cycle-steal mode..................................... 600
A
A/D converter ....................................... 1655 AC 97 Frame Slot Structure ................. 1409 Address space identifier (ASID)............. 145 Address translation ................................. 145 Addressing modes..................................... 59 Alarm function........................................ 780 Arithmetic operation instructions ............. 68 ASID....................................................... 156 Asynchronous Mode............................. 1151 Asynchronous serial communication mode ..................................................... 1059 ATI ......................................................... 781 Audio Codec Interface (HAC).............. 1391 Automatic PAUSE frame transmission ............................................ 980 Auto-Reload Count Operation ................ 701 Auto-Request mode ................................ 591
D
D/A converter (DAC) ........................... 1673 Data address error ................................... 123 Data alignment ........................................ 412 Data TLB miss exception................ 118, 169 Data TLB multiple hit exception ............ 169 Data TLB multiple-hit exception ............ 117 Data TLB protection violation exception......................................... 121, 170 DDR-SDRAM commands ...................... 432 DDR-SDRAM interface (DDRIF) .......... 409 Delay slot .................................................. 57 Delayed branches ...................................... 57 Descriptor and Transmit/Receive Buffer ...................................................... 952
Rev. 1.00 Oct. 01, 2007 Page 1947 of 1956 REJ09B0256-0100
B
Baud rate generator............................... 1217 Baud Rate Generator for External Clock (BRG)......................................... 1181 Big endian................................................. 52 Block diagram........................................... 13 Branch instructions ................................... 72 Break........................................... 1115, 1176 BRI ............................................. 1114, 1175
Descriptor Pointer................................... 954 Direct memory access controller (DMAC) ................................................. 565 Dirty bit .................................................. 158 Double-precision floating-point extended registers ..................................... 43 Double-precision floating-point registers .................................................... 43 Dual address mode.................................. 598
G
GEINT0 .................................................. 974 GEINT1 .................................................. 974 GEINT2 .................................................. 974 General FPU disable exception............... 128 General illegal instruction exception ...... 126 General interrupt request......................... 133 General Purpose I/O (GPIO)................. 1679 General registers ....................................... 38 Gigabit Ethernet controller (GETHER).............................................. 783 GMII/MII frame...................................... 986
E
effective address ....................................... 59 ERI.............................................. 1114, 1175 Ethernet reception................................... 962 Ethernet relay.......................................... 968 Ethernet transmission ............................. 956 Exception flow........................................ 112 Exception handling ................................. 105 Exception/interrupt codes ....................... 110 Execution cycles ....................................... 94 External CPU interface (EXCPU) .......... 621 External request mode ............................ 591
H
Hardware ITLB miss handling................ 164 H-UDI reset ............................................ 116
I
I2C bus data format ............................... 1046 I2C bus interface (IIC)........................... 1025 Infrared Data Communication Interface ................................................ 1179 Initial page write exception............. 120, 171 Input Capture Function ........................... 703 Instruction address error ......................... 124 Instruction execution state ........................ 53 Instruction fetch cycle break................. 1784 Instruction set............................................ 57 Instruction TLB miss exception...... 119, 167 Instruction TLB multiple hit exception................................................. 166 Instruction TLB multiple-hit exception................................................. 117 Instruction TLB protection violation exception.......................... 122, 168 Intermittent mode.................................... 601 Interrupt controller (INTC) ..................... 233 Interrupt response time ........................... 308
F
Fixed mode ............................................. 595 Fixed-point transfer instructions............... 66 Floating-point control instructions ........... 76 Floating-point double-precision instructions ............................................... 76 Floating-point graphics acceleration instructions ............................................... 77 Floating-point registers....................... 39, 43 Floating-point single-precision instructions ............................................... 75 FPU exception ........................................ 131 Free-running operation ........................... 755
Rev. 1.00 Oct. 01, 2007 Page 1948 of 1956 REJ09B0256-0100
IP Security Accelerator (SECURITY).... 995 IRL interrupts ......................................... 293 IRQ interrupts ......................................... 292 Issue rates ................................................. 94 ITLB ....................................................... 159 ITLB address array ................................. 173 ITLB data array ...................................... 174
Notes on display-off mode (LCDC stopped).................................... 1638
O
On-chip module interrupts ...................... 295 On-Chip peripheral module request mode ....................................................... 592 One-shot operation.................................. 755 Operand access cycle break .................. 1785
L
L memory ............................................... 217 LCD controller (LCDC) ....................... 1585 LCD module power-supply states......... 1637 List processor........................................ 1491 Little endian.............................................. 52 Load-store architecture ............................. 57 Logic operation instructions ..................... 70
P
P0, P3, and U0 areas ............................... 142 P1 area..................................................... 142 P2 area..................................................... 142 P4 area..................................................... 142 Padding insertion .................................... 973 Page size bits........................................... 157 PAUSE frame reception.......................... 981 PC card controller (PCC) ...................... 1359 PECR .................................................... 1700 Phase counting mode .............................. 740 PHY-LSI ................................................. 984 Pipelining .................................................. 79 Power-Down mode ......................... 434, 667 Power-down state...................................... 53 Power-on reset ........................................ 116 Power-supply control sequences ........... 1633 PPN ......................................................... 157 Pre-execution user break/ post-execution user break........................ 130 Prefetch instruction ................................. 229 PRI .......................................................... 781 Privileged mode ........................................ 38 Processing modes...................................... 38 Programming model.................................. 37 Protection key data.................................. 157 PWM modes ........................................... 737
M
Magic packet detection ........................... 981 Manual PAUSE frame transmission ....... 980 Manual reset ........................................... 116 Master Mode........................................... 407 Master Mode 1...................................... 1226 Memory management unit.............. 137, 324 Memory-mapped registers ........................ 51 MII frame................................................ 984 MII registers ................................... 989, 990 MII-RMII conversion circuit .................. 991 MMC Mode .......................................... 1326 Module standby mode............................. 680 Multi-Buffer frame ................................. 971 Multiple interrupts .................................. 307 Multiple virtual memory mode ............... 145
N
NMI (nonmaskable interrupt) ................. 132 NMI interrupt.......................................... 292
Rev. 1.00 Oct. 01, 2007 Page 1949 of 1956 REJ09B0256-0100
Q
Qtag ........................................................ 982
R
Realtime clock (RTC)............................. 759 Receive Descriptor ................................. 945 Reception in Master Mode ................... 1230 Reception in Slave Mode...................... 1232 Registers ADCSR............................................. 1660 ADDR............................................... 1658 APR .................................................... 834 ARSTR ............................................... 807 BCULR............................................... 840 BRGCKS2 ........................................ 1149 BRGDL2........................................... 1148 CAMR0 ............................................ 1774 CAMR1 ............................................ 1774 CAR0................................................ 1772 CAR1................................................ 1772 CBCR ............................................... 1780 CBR0 ................................................ 1763 CBR1 ................................................ 1763 CCMFR ............................................ 1779 CCR .................................................... 191 CDCR ................................................. 824 CDMR1 ............................................ 1777 CDR1................................................ 1776 CEECR ............................................... 832 CEFCR ............................................... 826 CERCR ............................................... 831 CETR1.............................................. 1778 CHATR ............................................ 1324 CHCR ................................................. 576 CLKON ............................................ 1316 CMCNT.............................................. 754 CMCOR.............................................. 754 CMCSR .............................................. 752 CMDR .............................................. 1298
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CMDSTRT ....................................... 1302 CMDTYR ......................................... 1292 CMSTR............................................... 751 CPUOPM.......................................... 1903 CRR0 ................................................ 1770 CRR1 ................................................ 1770 CSTR ................................................ 1308 CSWR ............................................... 1322 CTLR0 .............................................. 1546 CTLR1 .............................................. 1548 CTOCR ............................................. 1306 CVR .................................................. 1543 DACR ............................................... 1676 DADR ............................................... 1675 DAR.................................................... 573 DARB ................................................. 574 DASTS.............................................. 1537 DBK.................................................... 429 DBR ...................................................... 47 DMA ................................................. 1540 DMACR............................................ 1319 DMAOR ............................................. 584 DMARS .............................................. 587 DR..................................................... 1318 DTOUTR .......................................... 1307 ECMR ................................................. 808 ECSIPR............................................... 816 ECSR .................................................. 814 EDMR................................................. 904 EDRRR ............................................... 907 EDSR .................................................. 903 EDTRR ............................................... 906 EESIPR ............................................... 916 EESR................................................... 910 EPDR0i ............................................. 1525 EPDR0o ............................................ 1526 EPDR0s............................................. 1527 EPDR1 .............................................. 1528 EPDR2 .............................................. 1529 EPDR3 .............................................. 1530
EPDR4.............................................. 1531 EPDR5.............................................. 1532 EPIR ................................................. 1549 EPSTL0 ............................................ 1541 EPSTL1 ............................................ 1542 EPSZ0o............................................. 1533 EPSZ1............................................... 1534 EPSZ4............................................... 1535 EXCCTRL .......................................... 624 EXCINOR .......................................... 626 EXCMSETR....................................... 625 EXPEVT............................................. 107 FCFTR................................................ 933 FCLR0 .............................................. 1538 FCLR1 .............................................. 1539 FDR .................................................... 925 FIFOCLR.......................................... 1318 FPSCR .................................................. 48 FRECR ............................................... 827 FRQCR ............................................... 639 FWALCR0.......................................... 896 FWALCR1.......................................... 902 FWNLCR0.......................................... 895 FWNLCR1.......................................... 901 GBR...................................................... 47 GECMR.............................................. 839 HACACR.......................................... 1407 HACCR ............................................ 1394 HACCSAR ....................................... 1396 HACCSDR ....................................... 1398 HACPCML....................................... 1399 HACPCMR....................................... 1401 HACRIER......................................... 1405 HACRSR .......................................... 1406 HACTIER......................................... 1402 HACTSR .......................................... 1403 ICCCR .............................................. 1041 ICMAR ............................................. 1041 ICMCR ............................................. 1036 ICMIER ............................................ 1040
ICMSR .............................................. 1038 ICR0.................................................... 246 ICR1.................................................... 248 ICRXD .............................................. 1043 ICSAR............................................... 1035 ICSCR............................................... 1029 ICSIER.............................................. 1034 ICSSR ............................................... 1031 ICTXD .............................................. 1043 IER0 .................................................. 1520 IFR0 .................................................. 1504 INT2A0............................................... 268 INT2A01............................................. 269 INT2A1............................................... 272 INT2A11............................................. 274 INT2B ................................................. 283 INT2GPIC........................................... 289 INT2MSKCR...................................... 279 INT2MSKCR1.................................... 281 INT2MSKR ........................................ 276 INT2MSKR1 ...................................... 277 INT2PRI.............................................. 266 INTCR .............................................. 1310 INTCR2 ............................................ 1320 INTEVT .............................................. 108 INTMSK0 ........................................... 251 INTMSK1 ........................................... 253 INTMSK2 ........................................... 254 INTMSKCLR0 ................................... 257 INTMSKCLR1 ................................... 259 INTMSKCLR2 ................................... 260 INTPRI................................................ 249 INTREQ.............................................. 250 INTSTR ............................................ 1312 INTSTR2 .......................................... 1321 IRMCR................................................ 153 ISR0 .................................................. 1515 LCCR .................................................. 825 LDA0 .................................................. 225 LDA1 .................................................. 227
Rev. 1.00 Oct. 01, 2007 Page 1951 of 1956 REJ09B0256-0100
LDACLNR ....................................... 1610 LDCNTR .......................................... 1618 LDDFR............................................. 1596 LDHCNR.......................................... 1605 LDHSYNR ....................................... 1606 LDICKR ........................................... 1591 LDINTR ........................................... 1611 LDLAOR.......................................... 1602 LDLIRNR......................................... 1622 LDMTR ............................................ 1593 LDPALCR........................................ 1603 LDPMMR......................................... 1614 LDPR................................................ 1604 LDPSPR ........................................... 1616 LDSARL........................................... 1601 LDSARU .......................................... 1599 LDSMR ............................................ 1598 LDUINTLNR ................................... 1621 LDUINTR......................................... 1619 LDVDLNR ....................................... 1607 LDVSYNR ....................................... 1609 LDVTLNR ....................................... 1608 LSA0 .................................................. 221 LSA1 .................................................. 223 MACH .................................................. 47 MACL .................................................. 47 MAFCR .............................................. 833 MAHR ................................................ 818 MALR ................................................ 819 MIM.................................................... 417 MMUCR............................................. 149 MPR.................................................... 835 MSTPCR0 .......................................... 672 MSTPCR1 .......................................... 673 NMIFCR............................................. 263 OPCR................................................ 1304 PACR................................................ 1693 PADR ............................................... 1721 PASCR ............................................... 152 PBCR................................................ 1695
Rev. 1.00 Oct. 01, 2007 Page 1952 of 1956 REJ09B0256-0100
PBDR................................................ 1722 PC ......................................................... 47 PCC0CSCIER................................... 1376 PCC0CSCR....................................... 1372 PCC0GCR......................................... 1369 PCC0ISR........................................... 1366 PCCR ................................................ 1696 PCDR................................................ 1723 PDCR................................................ 1698 PDDR................................................ 1724 PEDR ................................................ 1725 PFCR................................................. 1701 PFDR ................................................ 1726 PFRCR................................................ 838 PFTCR ................................................ 837 PGCR................................................ 1703 PGDR................................................ 1727 PHCR................................................ 1705 PHDR................................................ 1728 PICR ................................................. 1707 PIDR ................................................. 1729 PIPR.................................................... 822 PIPUPR............................................. 1736 PIR ...................................................... 817 PJCR ................................................. 1709 PJDR ................................................. 1730 PJPUPR............................................. 1737 PKCR................................................ 1711 PKDR................................................ 1731 PKPUPR ........................................... 1738 PLCR ...................................... 1713, 1719 PLDR ................................................ 1732 PLLCR................................................ 641 PLPUPR............................................ 1739 PMDR ............................................... 1733 PMPUPR........................................... 1740 PNCR................................................ 1717 PNDR................................................ 1734 PNPUPR ........................................... 1742 PODR................................................ 1735
POPUPR ........................................... 1743 PPUPR.............................................. 1744 PR ......................................................... 47 PRPRICR............................................ 316 PSEL0............................................... 1745 PSEL1............................................... 1746 PSEL2............................................... 1749 PSEL3............................................... 1752 PSEL4............................................... 1755 PSR ..................................................... 821 PTEH .................................................. 147 PTEL................................................... 148 QACR0 ............................................... 193 QACR1 ............................................... 194 R64CNT ............................................. 764 RAMCR...................................... 195, 220 RCR1 .................................................. 772 RCR2 .................................................. 774 RCR3 .................................................. 777 RDAYAR ........................................... 771 RDAYCNT......................................... 767 RDFAR............................................... 927 RDFFR ............................................... 929 RDFXR............................................... 928 RDLAR............................................... 909 RFCR.................................................. 830 RFLR .................................................. 820 RHRAR .............................................. 770 RHRCNT ............................................ 765 RMCR................................................. 926 RMFCR .............................................. 923 RMINAR ............................................ 769 RMINCNT.......................................... 765 RMONAR........................................... 772 RMONCNT ........................................ 768 RPADIR ............................................. 935 RSECAR............................................. 769 RSECCNT .......................................... 764 RSPR ................................................ 1300 RSPTYR ........................................... 1293
RWKAR.............................................. 770 RWKCNT ........................................... 766 RXALCR0 .......................................... 894 RXALCR1 .......................................... 900 RXNLCR0 .......................................... 893 RXNLCR1 .......................................... 899 RYRAR............................................... 777 RYRCNT ............................................ 768 SAR..................................................... 572 SARB .................................................. 573 SBRIVCLV......................................... 315 SCBRR.......................... 1083, 1141, 1247 SCFCR .................................... 1084, 1142 SCFDR.............................................. 1144 SCFRDR ................................. 1068, 1126 SCFSR .................................... 1077, 1135 SCFTDR ................................. 1069, 1127 SCGRD ............................................. 1262 SCLSR .................................... 1090, 1147 SCR..................................................... 421 SCRDR ............................................. 1258 SCRER.............................................. 1091 SCRFDR ........................................... 1086 SCRSR .......................... 1068, 1126, 1258 SCSC2R ............................................ 1261 SCSCMR .......................................... 1259 SCSCR .......................... 1073, 1131, 1248 SCSMPL ........................................... 1264 SCSMR ......................... 1070, 1128, 1246 SCSMRIR ......................................... 1150 SCSPTR .................................. 1087, 1145 SCSSR .............................................. 1252 SCTDR.............................................. 1251 SCTFDR ........................................... 1086 SCTSR .......................... 1069, 1127, 1250 SCWAIT ........................................... 1263 SDBSR.............................................. 1805 SDINT............................................... 1804 SDIR ................................................. 1803 SDMR ................................................. 427
Rev. 1.00 Oct. 01, 2007 Page 1953 of 1956 REJ09B0256-0100
SDR .................................................... 426 SGR ...................................................... 47 SICDAR ........................................... 1215 SICTR............................................... 1196 SIFCTR ............................................ 1211 SIIER ................................................ 1209 SIMDR ............................................. 1192 SIRCR .............................................. 1202 SIRDAR ........................................... 1214 SIRDR .............................................. 1200 SISCR............................................... 1194 SISTR ............................................... 1203 SITCR............................................... 1201 SITDAR............................................ 1213 SITDR .............................................. 1199 SPC....................................................... 47 SR ......................................................... 45 SSICR............................................... 1424 SSIRDR ............................................ 1436 SSISR ............................................... 1431 SSITDR ............................................ 1436 SSR....................................................... 47 STBCR ............................................... 671 STICR............................................... 1006 STIFIFO ........................................... 1014 STIIER.............................................. 1009 STIISR.............................................. 1007 STIMDR ........................................... 1002 STIPCR ............................................ 1013 STIPNR ............................................ 1012 STITSC............................................. 1011 STR..................................................... 423 SWSR ............................................... 1323 TBCR................................................ 1297 TBNCR............................................. 1298 TCNT.................................................. 695 TCOR ................................................. 695 TCPR2 ................................................ 698 TCR ............................................ 574, 696 TCRB.................................................. 575
Rev. 1.00 Oct. 01, 2007 Page 1954 of 1956 REJ09B0256-0100
TDFAR ............................................... 930 TDFFR................................................ 932 TDFXR ............................................... 931 TDLAR ............................................... 908 TFTR................................................... 924 TGR .................................................... 727 TIER ................................................... 723 TIOR ................................................... 721 TLFRCR ............................................. 829 TMDR................................................. 719 TOCR.................................................. 692 TPAUSER........................................... 836 TRA .................................................... 106 TRG .................................................. 1536 TROCR ............................................... 823 TRSCER ............................................. 920 TSFRCR ............................................. 828 TSR ..................................................... 725 TSTR................................................... 693 TSU_ADQT0...................................... 867 TSU_ADQT1...................................... 868 TSU_ADRH........................................ 889 TSU_ADRL ........................................ 890 TSU_ADSBSY ................................... 871 TSU_BSYSL0 .................................... 845 TSU_BSYSL1 .................................... 847 TSU_CTRST ...................................... 841 TSU_FCM .......................................... 844 TSU_FWEN0...................................... 842 TSU_FWEN1...................................... 843 TSU_FWINMK .................................. 864 TSU_FWSL0 ...................................... 853 TSU_FWSL1 ...................................... 855 TSU_FWSLC...................................... 857 TSU_FWSR........................................ 861 TSU_POST1 ....................................... 877 TSU_POST2 ....................................... 880 TSU_POST3 ....................................... 883 TSU_POST4 ....................................... 886 TSU_PRISL0 ...................................... 849
TSU_PRISL1...................................... 851 TSU_QTAG0...................................... 859 TSU_QTAG1...................................... 860 TSU_TEN........................................... 872 TSU_VTAG0...................................... 869 TSU_VTAG1...................................... 870 TTB..................................................... 149 TXALCR0 .......................................... 892 TXALCR1 .......................................... 898 TXNLCR0 .......................................... 891 TXNLCR1 .......................................... 897 USBHBCED..................................... 1473 USBHBHED..................................... 1473 USBHC............................................. 1463 USBHCCED..................................... 1472 USBHCHED..................................... 1472 USBHCS........................................... 1465 USBHDHED .................................... 1474 USBHFI............................................ 1475 USBHFN .......................................... 1477 USBHFR........................................... 1476 USBHHCCA .................................... 1471 USBHID ........................................... 1469 USBHIE............................................ 1468 USBHIS............................................ 1466 USBHLST ........................................ 1479 USBHPCED ..................................... 1471 USBHPS ........................................... 1478 USBHR............................................. 1462 USBHRDA ....................................... 1480 USBHRDB ....................................... 1482 USBHRPS2 ...................................... 1486 USBHRS........................................... 1484 USBHSC........................................... 1489 USERIMASK ..................................... 264 VBR...................................................... 47 VDCNT ............................................ 1317 WDTBST............................................ 652 WDTCNT ........................................... 653 WDTCSR............................................ 650
WDTST............................................... 649 Relative priorities.................................... 110 Reset state ................................................. 53 RMII frame ............................................. 988 Root hub................................................ 1492 Round-robin mode .................................. 595 RTC power supply backup...................... 684 RXI ............................................. 1114, 1175
S
SCIF Interrupt Sources ......................... 1175 Self-Refresh and initialization ................ 681 Self-Refresh mode .................................. 433 Sequential break.................................... 1787 Serial communication interface with FIFO...................................................... 1059 Serial communication interface with FIFO/IrDA interface (SCIF/IrDA)........ 1119 Serial I/O with FIFO (SIOF)................. 1185 Serial interface engine (SIE) ................. 1491 Serial Sound Interface (SSI) ................. 1419 Setting the display resolution................ 1633 Share status bit ........................................ 157 Shift instructions ....................................... 71 Sign-extended ........................................... 52 SIM Card Module (SIM)....................... 1241 Single virtual memory mode................... 145 Single-precision floating-point extended register matrix............................ 44 Single-precision floating-point extended registers...................................... 43 single-precision floating-point registers..................................................... 43 Single-precision floating-point registers..................................................... 43 Single-precision floating-point vector registers..................................................... 43 Slave Mode 1 ........................................ 1226 Slave Mode 2 ........................................ 1226
Rev. 1.00 Oct. 01, 2007 Page 1955 of 1956 REJ09B0256-0100
Sleep mode ............................................. 678 Slot FPU disable exception..................... 129 Slot illegal instruction exception ............ 127 Smart card interface.............................. 1266 Software standby mode .......................... 679 Stall operations ..................................... 1577 Stream interface (STIF) .......................... 997 Strobe reception.................................... 1019 Strobe transmission .............................. 1023 SuperHyway bus bridge (SBR) .............. 313 System control instructions ...................... 72 System registers........................................ 39 System registers related to FPU................ 39
Types of exceptions ................................ 110
U
Unconditional trap .................................. 125 USB function controller (USBF) .......... 1495 User break controller ............................ 1759 User break operation............................. 1782 User debugging interface ...................... 1797 User mode................................................. 38 UTLB...................................................... 156 UTLB address array................................ 175 UTLB data array ..................................... 176
T
T bit .......................................................... 58 TAP control .......................................... 1823 TCNT Count Timing .............................. 701 TICPI ...................................................... 704 Time setting ............................................ 778 Timer Unit .............................................. 687 Transmission in Master Mode .............. 1229 Transmission in Slave Mode ................ 1231 Transmit Descriptor................................ 939 Transmit/Receive Reset........................ 1233 TUNI ...................................................... 704 TXI ............................................. 1114, 1175
V
Validity bit .............................................. 157 Vector addresses ..................................... 110 Virtual address space .............................. 140 VPN ........................................................ 156
W
Watchdog timer and reset ....................... 645 Write-back instruction ............................ 229 Write-through bit .................................... 158
Rev. 1.00 Oct. 01, 2007 Page 1956 of 1956 REJ09B0256-0100
Renesas 32-Bit RISC Microcomputer Hardware Manual SH7763
Publication Date: Rev.1.00, Oct. 01, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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